1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel AT32 and AT91 SPI Controllers
5 * Copyright (C) 2006 Atmel Corporation
8 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/spi/spi.h>
18 #include <linux/slab.h>
19 #include <linux/platform_data/dma-atmel.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/pm_runtime.h>
26 #include <trace/events/spi.h>
28 /* SPI register offsets */
31 #define SPI_RDR 0x0008
32 #define SPI_TDR 0x000c
34 #define SPI_IER 0x0014
35 #define SPI_IDR 0x0018
36 #define SPI_IMR 0x001c
37 #define SPI_CSR0 0x0030
38 #define SPI_CSR1 0x0034
39 #define SPI_CSR2 0x0038
40 #define SPI_CSR3 0x003c
41 #define SPI_FMR 0x0040
42 #define SPI_FLR 0x0044
43 #define SPI_VERSION 0x00fc
44 #define SPI_RPR 0x0100
45 #define SPI_RCR 0x0104
46 #define SPI_TPR 0x0108
47 #define SPI_TCR 0x010c
48 #define SPI_RNPR 0x0110
49 #define SPI_RNCR 0x0114
50 #define SPI_TNPR 0x0118
51 #define SPI_TNCR 0x011c
52 #define SPI_PTCR 0x0120
53 #define SPI_PTSR 0x0124
56 #define SPI_SPIEN_OFFSET 0
57 #define SPI_SPIEN_SIZE 1
58 #define SPI_SPIDIS_OFFSET 1
59 #define SPI_SPIDIS_SIZE 1
60 #define SPI_SWRST_OFFSET 7
61 #define SPI_SWRST_SIZE 1
62 #define SPI_LASTXFER_OFFSET 24
63 #define SPI_LASTXFER_SIZE 1
64 #define SPI_TXFCLR_OFFSET 16
65 #define SPI_TXFCLR_SIZE 1
66 #define SPI_RXFCLR_OFFSET 17
67 #define SPI_RXFCLR_SIZE 1
68 #define SPI_FIFOEN_OFFSET 30
69 #define SPI_FIFOEN_SIZE 1
70 #define SPI_FIFODIS_OFFSET 31
71 #define SPI_FIFODIS_SIZE 1
74 #define SPI_MSTR_OFFSET 0
75 #define SPI_MSTR_SIZE 1
76 #define SPI_PS_OFFSET 1
78 #define SPI_PCSDEC_OFFSET 2
79 #define SPI_PCSDEC_SIZE 1
80 #define SPI_FDIV_OFFSET 3
81 #define SPI_FDIV_SIZE 1
82 #define SPI_MODFDIS_OFFSET 4
83 #define SPI_MODFDIS_SIZE 1
84 #define SPI_WDRBT_OFFSET 5
85 #define SPI_WDRBT_SIZE 1
86 #define SPI_LLB_OFFSET 7
87 #define SPI_LLB_SIZE 1
88 #define SPI_PCS_OFFSET 16
89 #define SPI_PCS_SIZE 4
90 #define SPI_DLYBCS_OFFSET 24
91 #define SPI_DLYBCS_SIZE 8
93 /* Bitfields in RDR */
94 #define SPI_RD_OFFSET 0
95 #define SPI_RD_SIZE 16
97 /* Bitfields in TDR */
98 #define SPI_TD_OFFSET 0
99 #define SPI_TD_SIZE 16
101 /* Bitfields in SR */
102 #define SPI_RDRF_OFFSET 0
103 #define SPI_RDRF_SIZE 1
104 #define SPI_TDRE_OFFSET 1
105 #define SPI_TDRE_SIZE 1
106 #define SPI_MODF_OFFSET 2
107 #define SPI_MODF_SIZE 1
108 #define SPI_OVRES_OFFSET 3
109 #define SPI_OVRES_SIZE 1
110 #define SPI_ENDRX_OFFSET 4
111 #define SPI_ENDRX_SIZE 1
112 #define SPI_ENDTX_OFFSET 5
113 #define SPI_ENDTX_SIZE 1
114 #define SPI_RXBUFF_OFFSET 6
115 #define SPI_RXBUFF_SIZE 1
116 #define SPI_TXBUFE_OFFSET 7
117 #define SPI_TXBUFE_SIZE 1
118 #define SPI_NSSR_OFFSET 8
119 #define SPI_NSSR_SIZE 1
120 #define SPI_TXEMPTY_OFFSET 9
121 #define SPI_TXEMPTY_SIZE 1
122 #define SPI_SPIENS_OFFSET 16
123 #define SPI_SPIENS_SIZE 1
124 #define SPI_TXFEF_OFFSET 24
125 #define SPI_TXFEF_SIZE 1
126 #define SPI_TXFFF_OFFSET 25
127 #define SPI_TXFFF_SIZE 1
128 #define SPI_TXFTHF_OFFSET 26
129 #define SPI_TXFTHF_SIZE 1
130 #define SPI_RXFEF_OFFSET 27
131 #define SPI_RXFEF_SIZE 1
132 #define SPI_RXFFF_OFFSET 28
133 #define SPI_RXFFF_SIZE 1
134 #define SPI_RXFTHF_OFFSET 29
135 #define SPI_RXFTHF_SIZE 1
136 #define SPI_TXFPTEF_OFFSET 30
137 #define SPI_TXFPTEF_SIZE 1
138 #define SPI_RXFPTEF_OFFSET 31
139 #define SPI_RXFPTEF_SIZE 1
141 /* Bitfields in CSR0 */
142 #define SPI_CPOL_OFFSET 0
143 #define SPI_CPOL_SIZE 1
144 #define SPI_NCPHA_OFFSET 1
145 #define SPI_NCPHA_SIZE 1
146 #define SPI_CSAAT_OFFSET 3
147 #define SPI_CSAAT_SIZE 1
148 #define SPI_BITS_OFFSET 4
149 #define SPI_BITS_SIZE 4
150 #define SPI_SCBR_OFFSET 8
151 #define SPI_SCBR_SIZE 8
152 #define SPI_DLYBS_OFFSET 16
153 #define SPI_DLYBS_SIZE 8
154 #define SPI_DLYBCT_OFFSET 24
155 #define SPI_DLYBCT_SIZE 8
157 /* Bitfields in RCR */
158 #define SPI_RXCTR_OFFSET 0
159 #define SPI_RXCTR_SIZE 16
161 /* Bitfields in TCR */
162 #define SPI_TXCTR_OFFSET 0
163 #define SPI_TXCTR_SIZE 16
165 /* Bitfields in RNCR */
166 #define SPI_RXNCR_OFFSET 0
167 #define SPI_RXNCR_SIZE 16
169 /* Bitfields in TNCR */
170 #define SPI_TXNCR_OFFSET 0
171 #define SPI_TXNCR_SIZE 16
173 /* Bitfields in PTCR */
174 #define SPI_RXTEN_OFFSET 0
175 #define SPI_RXTEN_SIZE 1
176 #define SPI_RXTDIS_OFFSET 1
177 #define SPI_RXTDIS_SIZE 1
178 #define SPI_TXTEN_OFFSET 8
179 #define SPI_TXTEN_SIZE 1
180 #define SPI_TXTDIS_OFFSET 9
181 #define SPI_TXTDIS_SIZE 1
183 /* Bitfields in FMR */
184 #define SPI_TXRDYM_OFFSET 0
185 #define SPI_TXRDYM_SIZE 2
186 #define SPI_RXRDYM_OFFSET 4
187 #define SPI_RXRDYM_SIZE 2
188 #define SPI_TXFTHRES_OFFSET 16
189 #define SPI_TXFTHRES_SIZE 6
190 #define SPI_RXFTHRES_OFFSET 24
191 #define SPI_RXFTHRES_SIZE 6
193 /* Bitfields in FLR */
194 #define SPI_TXFL_OFFSET 0
195 #define SPI_TXFL_SIZE 6
196 #define SPI_RXFL_OFFSET 16
197 #define SPI_RXFL_SIZE 6
199 /* Constants for BITS */
200 #define SPI_BITS_8_BPT 0
201 #define SPI_BITS_9_BPT 1
202 #define SPI_BITS_10_BPT 2
203 #define SPI_BITS_11_BPT 3
204 #define SPI_BITS_12_BPT 4
205 #define SPI_BITS_13_BPT 5
206 #define SPI_BITS_14_BPT 6
207 #define SPI_BITS_15_BPT 7
208 #define SPI_BITS_16_BPT 8
209 #define SPI_ONE_DATA 0
210 #define SPI_TWO_DATA 1
211 #define SPI_FOUR_DATA 2
213 /* Bit manipulation macros */
214 #define SPI_BIT(name) \
215 (1 << SPI_##name##_OFFSET)
216 #define SPI_BF(name, value) \
217 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
218 #define SPI_BFEXT(name, value) \
219 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
220 #define SPI_BFINS(name, value, old) \
221 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
222 | SPI_BF(name, value))
224 /* Register access macros */
225 #define spi_readl(port, reg) \
226 readl_relaxed((port)->regs + SPI_##reg)
227 #define spi_writel(port, reg, value) \
228 writel_relaxed((value), (port)->regs + SPI_##reg)
229 #define spi_writew(port, reg, value) \
230 writew_relaxed((value), (port)->regs + SPI_##reg)
232 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
233 * cache operations; better heuristics consider wordsize and bitrate.
235 #define DMA_MIN_BYTES 16
237 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
239 #define AUTOSUSPEND_TIMEOUT 2000
241 struct atmel_spi_caps
{
244 bool has_dma_support
;
245 bool has_pdc_support
;
249 * The core SPI transfer engine just talks to a register bank to set up
250 * DMA transfers; transfer queue progress is driven by IRQs. The clock
251 * framework provides the base clock, subdivided for each spi_device.
261 struct platform_device
*pdev
;
262 unsigned long spi_clk
;
264 struct spi_transfer
*current_transfer
;
265 int current_remaining_bytes
;
267 dma_addr_t dma_addr_rx_bbuf
;
268 dma_addr_t dma_addr_tx_bbuf
;
272 struct completion xfer_completion
;
274 struct atmel_spi_caps caps
;
283 u8 native_cs_for_gpio
;
286 /* Controller-specific per-slave state */
287 struct atmel_spi_device
{
291 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
292 #define INVALID_DMA_ADDRESS 0xffffffff
295 * Version 2 of the SPI controller has
297 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
298 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
300 * - SPI_CSRx.SBCR allows faster clocking
302 static bool atmel_spi_is_v2(struct atmel_spi
*as
)
304 return as
->caps
.is_spi2
;
308 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
309 * they assume that spi slave device state will not change on deselect, so
310 * that automagic deselection is OK. ("NPCSx rises if no data is to be
311 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
312 * controllers have CSAAT and friends.
314 * Even controller newer than ar91rm9200, using GPIOs can make sens as
315 * it lets us support active-high chipselects despite the controller's
316 * belief that only active-low devices/systems exists.
318 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
319 * right when driven with GPIO. ("Mode Fault does not allow more than one
320 * Master on Chip Select 0.") No workaround exists for that ... so for
321 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
322 * and (c) will trigger that first erratum in some cases.
325 static void cs_activate(struct atmel_spi
*as
, struct spi_device
*spi
)
327 struct atmel_spi_device
*asd
= spi
->controller_state
;
332 chip_select
= as
->native_cs_for_gpio
;
334 chip_select
= spi
->chip_select
;
336 if (atmel_spi_is_v2(as
)) {
337 spi_writel(as
, CSR0
+ 4 * chip_select
, asd
->csr
);
338 /* For the low SPI version, there is a issue that PDC transfer
339 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
341 spi_writel(as
, CSR0
, asd
->csr
);
342 if (as
->caps
.has_wdrbt
) {
344 SPI_BF(PCS
, ~(0x01 << chip_select
))
350 SPI_BF(PCS
, ~(0x01 << chip_select
))
355 mr
= spi_readl(as
, MR
);
357 gpiod_set_value(spi
->cs_gpiod
, 1);
359 u32 cpol
= (spi
->mode
& SPI_CPOL
) ? SPI_BIT(CPOL
) : 0;
363 /* Make sure clock polarity is correct */
364 for (i
= 0; i
< spi
->master
->num_chipselect
; i
++) {
365 csr
= spi_readl(as
, CSR0
+ 4 * i
);
366 if ((csr
^ cpol
) & SPI_BIT(CPOL
))
367 spi_writel(as
, CSR0
+ 4 * i
,
368 csr
^ SPI_BIT(CPOL
));
371 mr
= spi_readl(as
, MR
);
372 mr
= SPI_BFINS(PCS
, ~(1 << chip_select
), mr
);
374 gpiod_set_value(spi
->cs_gpiod
, 1);
375 spi_writel(as
, MR
, mr
);
378 dev_dbg(&spi
->dev
, "activate NPCS, mr %08x\n", mr
);
381 static void cs_deactivate(struct atmel_spi
*as
, struct spi_device
*spi
)
387 chip_select
= as
->native_cs_for_gpio
;
389 chip_select
= spi
->chip_select
;
391 /* only deactivate *this* device; sometimes transfers to
392 * another device may be active when this routine is called.
394 mr
= spi_readl(as
, MR
);
395 if (~SPI_BFEXT(PCS
, mr
) & (1 << chip_select
)) {
396 mr
= SPI_BFINS(PCS
, 0xf, mr
);
397 spi_writel(as
, MR
, mr
);
400 dev_dbg(&spi
->dev
, "DEactivate NPCS, mr %08x\n", mr
);
403 spi_writel(as
, CR
, SPI_BIT(LASTXFER
));
405 gpiod_set_value(spi
->cs_gpiod
, 0);
408 static void atmel_spi_lock(struct atmel_spi
*as
) __acquires(&as
->lock
)
410 spin_lock_irqsave(&as
->lock
, as
->flags
);
413 static void atmel_spi_unlock(struct atmel_spi
*as
) __releases(&as
->lock
)
415 spin_unlock_irqrestore(&as
->lock
, as
->flags
);
418 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer
*xfer
)
420 return is_vmalloc_addr(xfer
->tx_buf
) || is_vmalloc_addr(xfer
->rx_buf
);
423 static inline bool atmel_spi_use_dma(struct atmel_spi
*as
,
424 struct spi_transfer
*xfer
)
426 return as
->use_dma
&& xfer
->len
>= DMA_MIN_BYTES
;
429 static bool atmel_spi_can_dma(struct spi_master
*master
,
430 struct spi_device
*spi
,
431 struct spi_transfer
*xfer
)
433 struct atmel_spi
*as
= spi_master_get_devdata(master
);
435 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5
))
436 return atmel_spi_use_dma(as
, xfer
) &&
437 !atmel_spi_is_vmalloc_xfer(xfer
);
439 return atmel_spi_use_dma(as
, xfer
);
443 static int atmel_spi_dma_slave_config(struct atmel_spi
*as
,
444 struct dma_slave_config
*slave_config
,
447 struct spi_master
*master
= platform_get_drvdata(as
->pdev
);
450 if (bits_per_word
> 8) {
451 slave_config
->dst_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
452 slave_config
->src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
454 slave_config
->dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
455 slave_config
->src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
458 slave_config
->dst_addr
= (dma_addr_t
)as
->phybase
+ SPI_TDR
;
459 slave_config
->src_addr
= (dma_addr_t
)as
->phybase
+ SPI_RDR
;
460 slave_config
->src_maxburst
= 1;
461 slave_config
->dst_maxburst
= 1;
462 slave_config
->device_fc
= false;
465 * This driver uses fixed peripheral select mode (PS bit set to '0' in
466 * the Mode Register).
467 * So according to the datasheet, when FIFOs are available (and
468 * enabled), the Transmit FIFO operates in Multiple Data Mode.
469 * In this mode, up to 2 data, not 4, can be written into the Transmit
470 * Data Register in a single access.
471 * However, the first data has to be written into the lowest 16 bits and
472 * the second data into the highest 16 bits of the Transmit
473 * Data Register. For 8bit data (the most frequent case), it would
474 * require to rework tx_buf so each data would actualy fit 16 bits.
475 * So we'd rather write only one data at the time. Hence the transmit
476 * path works the same whether FIFOs are available (and enabled) or not.
478 slave_config
->direction
= DMA_MEM_TO_DEV
;
479 if (dmaengine_slave_config(master
->dma_tx
, slave_config
)) {
480 dev_err(&as
->pdev
->dev
,
481 "failed to configure tx dma channel\n");
486 * This driver configures the spi controller for master mode (MSTR bit
487 * set to '1' in the Mode Register).
488 * So according to the datasheet, when FIFOs are available (and
489 * enabled), the Receive FIFO operates in Single Data Mode.
490 * So the receive path works the same whether FIFOs are available (and
493 slave_config
->direction
= DMA_DEV_TO_MEM
;
494 if (dmaengine_slave_config(master
->dma_rx
, slave_config
)) {
495 dev_err(&as
->pdev
->dev
,
496 "failed to configure rx dma channel\n");
503 static int atmel_spi_configure_dma(struct spi_master
*master
,
504 struct atmel_spi
*as
)
506 struct dma_slave_config slave_config
;
507 struct device
*dev
= &as
->pdev
->dev
;
512 dma_cap_set(DMA_SLAVE
, mask
);
514 master
->dma_tx
= dma_request_chan(dev
, "tx");
515 if (IS_ERR(master
->dma_tx
)) {
516 err
= PTR_ERR(master
->dma_tx
);
517 if (err
!= -EPROBE_DEFER
)
518 dev_err(dev
, "No TX DMA channel, DMA is disabled\n");
522 master
->dma_rx
= dma_request_chan(dev
, "rx");
523 if (IS_ERR(master
->dma_rx
)) {
524 err
= PTR_ERR(master
->dma_rx
);
526 * No reason to check EPROBE_DEFER here since we have already
527 * requested tx channel.
529 dev_err(dev
, "No RX DMA channel, DMA is disabled\n");
533 err
= atmel_spi_dma_slave_config(as
, &slave_config
, 8);
537 dev_info(&as
->pdev
->dev
,
538 "Using %s (tx) and %s (rx) for DMA transfers\n",
539 dma_chan_name(master
->dma_tx
),
540 dma_chan_name(master
->dma_rx
));
544 if (!IS_ERR(master
->dma_rx
))
545 dma_release_channel(master
->dma_rx
);
546 if (!IS_ERR(master
->dma_tx
))
547 dma_release_channel(master
->dma_tx
);
549 master
->dma_tx
= master
->dma_rx
= NULL
;
553 static void atmel_spi_stop_dma(struct spi_master
*master
)
556 dmaengine_terminate_all(master
->dma_rx
);
558 dmaengine_terminate_all(master
->dma_tx
);
561 static void atmel_spi_release_dma(struct spi_master
*master
)
563 if (master
->dma_rx
) {
564 dma_release_channel(master
->dma_rx
);
565 master
->dma_rx
= NULL
;
567 if (master
->dma_tx
) {
568 dma_release_channel(master
->dma_tx
);
569 master
->dma_tx
= NULL
;
573 /* This function is called by the DMA driver from tasklet context */
574 static void dma_callback(void *data
)
576 struct spi_master
*master
= data
;
577 struct atmel_spi
*as
= spi_master_get_devdata(master
);
579 if (is_vmalloc_addr(as
->current_transfer
->rx_buf
) &&
580 IS_ENABLED(CONFIG_SOC_SAM_V4_V5
)) {
581 memcpy(as
->current_transfer
->rx_buf
, as
->addr_rx_bbuf
,
582 as
->current_transfer
->len
);
584 complete(&as
->xfer_completion
);
588 * Next transfer using PIO without FIFO.
590 static void atmel_spi_next_xfer_single(struct spi_master
*master
,
591 struct spi_transfer
*xfer
)
593 struct atmel_spi
*as
= spi_master_get_devdata(master
);
594 unsigned long xfer_pos
= xfer
->len
- as
->current_remaining_bytes
;
596 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_pio\n");
598 /* Make sure data is not remaining in RDR */
600 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
)) {
605 if (xfer
->bits_per_word
> 8)
606 spi_writel(as
, TDR
, *(u16
*)(xfer
->tx_buf
+ xfer_pos
));
608 spi_writel(as
, TDR
, *(u8
*)(xfer
->tx_buf
+ xfer_pos
));
610 dev_dbg(master
->dev
.parent
,
611 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
612 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->rx_buf
,
613 xfer
->bits_per_word
);
615 /* Enable relevant interrupts */
616 spi_writel(as
, IER
, SPI_BIT(RDRF
) | SPI_BIT(OVRES
));
620 * Next transfer using PIO with FIFO.
622 static void atmel_spi_next_xfer_fifo(struct spi_master
*master
,
623 struct spi_transfer
*xfer
)
625 struct atmel_spi
*as
= spi_master_get_devdata(master
);
626 u32 current_remaining_data
, num_data
;
627 u32 offset
= xfer
->len
- as
->current_remaining_bytes
;
628 const u16
*words
= (const u16
*)((u8
*)xfer
->tx_buf
+ offset
);
629 const u8
*bytes
= (const u8
*)((u8
*)xfer
->tx_buf
+ offset
);
633 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_fifo\n");
635 /* Compute the number of data to transfer in the current iteration */
636 current_remaining_data
= ((xfer
->bits_per_word
> 8) ?
637 ((u32
)as
->current_remaining_bytes
>> 1) :
638 (u32
)as
->current_remaining_bytes
);
639 num_data
= min(current_remaining_data
, as
->fifo_size
);
641 /* Flush RX and TX FIFOs */
642 spi_writel(as
, CR
, SPI_BIT(RXFCLR
) | SPI_BIT(TXFCLR
));
643 while (spi_readl(as
, FLR
))
646 /* Set RX FIFO Threshold to the number of data to transfer */
647 fifomr
= spi_readl(as
, FMR
);
648 spi_writel(as
, FMR
, SPI_BFINS(RXFTHRES
, num_data
, fifomr
));
650 /* Clear FIFO flags in the Status Register, especially RXFTHF */
651 (void)spi_readl(as
, SR
);
654 while (num_data
>= 2) {
655 if (xfer
->bits_per_word
> 8) {
663 spi_writel(as
, TDR
, (td1
<< 16) | td0
);
668 if (xfer
->bits_per_word
> 8)
673 spi_writew(as
, TDR
, td0
);
677 dev_dbg(master
->dev
.parent
,
678 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
679 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->rx_buf
,
680 xfer
->bits_per_word
);
683 * Enable RX FIFO Threshold Flag interrupt to be notified about
684 * transfer completion.
686 spi_writel(as
, IER
, SPI_BIT(RXFTHF
) | SPI_BIT(OVRES
));
690 * Next transfer using PIO.
692 static void atmel_spi_next_xfer_pio(struct spi_master
*master
,
693 struct spi_transfer
*xfer
)
695 struct atmel_spi
*as
= spi_master_get_devdata(master
);
698 atmel_spi_next_xfer_fifo(master
, xfer
);
700 atmel_spi_next_xfer_single(master
, xfer
);
704 * Submit next transfer for DMA.
706 static int atmel_spi_next_xfer_dma_submit(struct spi_master
*master
,
707 struct spi_transfer
*xfer
,
709 __must_hold(&as
->lock
)
711 struct atmel_spi
*as
= spi_master_get_devdata(master
);
712 struct dma_chan
*rxchan
= master
->dma_rx
;
713 struct dma_chan
*txchan
= master
->dma_tx
;
714 struct dma_async_tx_descriptor
*rxdesc
;
715 struct dma_async_tx_descriptor
*txdesc
;
716 struct dma_slave_config slave_config
;
719 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_dma_submit\n");
721 /* Check that the channels are available */
722 if (!rxchan
|| !txchan
)
725 /* release lock for DMA operations */
726 atmel_spi_unlock(as
);
730 if (atmel_spi_dma_slave_config(as
, &slave_config
,
731 xfer
->bits_per_word
))
734 /* Send both scatterlists */
735 if (atmel_spi_is_vmalloc_xfer(xfer
) &&
736 IS_ENABLED(CONFIG_SOC_SAM_V4_V5
)) {
737 rxdesc
= dmaengine_prep_slave_single(rxchan
,
738 as
->dma_addr_rx_bbuf
,
744 rxdesc
= dmaengine_prep_slave_sg(rxchan
,
754 if (atmel_spi_is_vmalloc_xfer(xfer
) &&
755 IS_ENABLED(CONFIG_SOC_SAM_V4_V5
)) {
756 memcpy(as
->addr_tx_bbuf
, xfer
->tx_buf
, xfer
->len
);
757 txdesc
= dmaengine_prep_slave_single(txchan
,
758 as
->dma_addr_tx_bbuf
,
759 xfer
->len
, DMA_MEM_TO_DEV
,
763 txdesc
= dmaengine_prep_slave_sg(txchan
,
773 dev_dbg(master
->dev
.parent
,
774 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
775 xfer
, xfer
->len
, xfer
->tx_buf
, (unsigned long long)xfer
->tx_dma
,
776 xfer
->rx_buf
, (unsigned long long)xfer
->rx_dma
);
778 /* Enable relevant interrupts */
779 spi_writel(as
, IER
, SPI_BIT(OVRES
));
781 /* Put the callback on the RX transfer only, that should finish last */
782 rxdesc
->callback
= dma_callback
;
783 rxdesc
->callback_param
= master
;
785 /* Submit and fire RX and TX with TX last so we're ready to read! */
786 cookie
= rxdesc
->tx_submit(rxdesc
);
787 if (dma_submit_error(cookie
))
789 cookie
= txdesc
->tx_submit(txdesc
);
790 if (dma_submit_error(cookie
))
792 rxchan
->device
->device_issue_pending(rxchan
);
793 txchan
->device
->device_issue_pending(txchan
);
800 spi_writel(as
, IDR
, SPI_BIT(OVRES
));
801 atmel_spi_stop_dma(master
);
807 static void atmel_spi_next_xfer_data(struct spi_master
*master
,
808 struct spi_transfer
*xfer
,
813 *rx_dma
= xfer
->rx_dma
+ xfer
->len
- *plen
;
814 *tx_dma
= xfer
->tx_dma
+ xfer
->len
- *plen
;
815 if (*plen
> master
->max_dma_len
)
816 *plen
= master
->max_dma_len
;
819 static int atmel_spi_set_xfer_speed(struct atmel_spi
*as
,
820 struct spi_device
*spi
,
821 struct spi_transfer
*xfer
)
824 unsigned long bus_hz
;
828 chip_select
= as
->native_cs_for_gpio
;
830 chip_select
= spi
->chip_select
;
832 /* v1 chips start out at half the peripheral bus speed. */
833 bus_hz
= as
->spi_clk
;
834 if (!atmel_spi_is_v2(as
))
838 * Calculate the lowest divider that satisfies the
839 * constraint, assuming div32/fdiv/mbz == 0.
841 scbr
= DIV_ROUND_UP(bus_hz
, xfer
->speed_hz
);
844 * If the resulting divider doesn't fit into the
845 * register bitfield, we can't satisfy the constraint.
847 if (scbr
>= (1 << SPI_SCBR_SIZE
)) {
849 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
850 xfer
->speed_hz
, scbr
, bus_hz
/255);
855 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
856 xfer
->speed_hz
, scbr
, bus_hz
);
859 csr
= spi_readl(as
, CSR0
+ 4 * chip_select
);
860 csr
= SPI_BFINS(SCBR
, scbr
, csr
);
861 spi_writel(as
, CSR0
+ 4 * chip_select
, csr
);
867 * Submit next transfer for PDC.
868 * lock is held, spi irq is blocked
870 static void atmel_spi_pdc_next_xfer(struct spi_master
*master
,
871 struct spi_message
*msg
,
872 struct spi_transfer
*xfer
)
874 struct atmel_spi
*as
= spi_master_get_devdata(master
);
876 dma_addr_t tx_dma
, rx_dma
;
878 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
880 len
= as
->current_remaining_bytes
;
881 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
882 as
->current_remaining_bytes
-= len
;
884 spi_writel(as
, RPR
, rx_dma
);
885 spi_writel(as
, TPR
, tx_dma
);
887 if (msg
->spi
->bits_per_word
> 8)
889 spi_writel(as
, RCR
, len
);
890 spi_writel(as
, TCR
, len
);
892 dev_dbg(&msg
->spi
->dev
,
893 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
894 xfer
, xfer
->len
, xfer
->tx_buf
,
895 (unsigned long long)xfer
->tx_dma
, xfer
->rx_buf
,
896 (unsigned long long)xfer
->rx_dma
);
898 if (as
->current_remaining_bytes
) {
899 len
= as
->current_remaining_bytes
;
900 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
901 as
->current_remaining_bytes
-= len
;
903 spi_writel(as
, RNPR
, rx_dma
);
904 spi_writel(as
, TNPR
, tx_dma
);
906 if (msg
->spi
->bits_per_word
> 8)
908 spi_writel(as
, RNCR
, len
);
909 spi_writel(as
, TNCR
, len
);
911 dev_dbg(&msg
->spi
->dev
,
912 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
913 xfer
, xfer
->len
, xfer
->tx_buf
,
914 (unsigned long long)xfer
->tx_dma
, xfer
->rx_buf
,
915 (unsigned long long)xfer
->rx_dma
);
918 /* REVISIT: We're waiting for RXBUFF before we start the next
919 * transfer because we need to handle some difficult timing
920 * issues otherwise. If we wait for TXBUFE in one transfer and
921 * then starts waiting for RXBUFF in the next, it's difficult
922 * to tell the difference between the RXBUFF interrupt we're
923 * actually waiting for and the RXBUFF interrupt of the
926 * It should be doable, though. Just not now...
928 spi_writel(as
, IER
, SPI_BIT(RXBUFF
) | SPI_BIT(OVRES
));
929 spi_writel(as
, PTCR
, SPI_BIT(TXTEN
) | SPI_BIT(RXTEN
));
933 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
934 * - The buffer is either valid for CPU access, else NULL
935 * - If the buffer is valid, so is its DMA address
937 * This driver manages the dma address unless message->is_dma_mapped.
940 atmel_spi_dma_map_xfer(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
942 struct device
*dev
= &as
->pdev
->dev
;
944 xfer
->tx_dma
= xfer
->rx_dma
= INVALID_DMA_ADDRESS
;
946 /* tx_buf is a const void* where we need a void * for the dma
948 void *nonconst_tx
= (void *)xfer
->tx_buf
;
950 xfer
->tx_dma
= dma_map_single(dev
,
951 nonconst_tx
, xfer
->len
,
953 if (dma_mapping_error(dev
, xfer
->tx_dma
))
957 xfer
->rx_dma
= dma_map_single(dev
,
958 xfer
->rx_buf
, xfer
->len
,
960 if (dma_mapping_error(dev
, xfer
->rx_dma
)) {
962 dma_unmap_single(dev
,
963 xfer
->tx_dma
, xfer
->len
,
971 static void atmel_spi_dma_unmap_xfer(struct spi_master
*master
,
972 struct spi_transfer
*xfer
)
974 if (xfer
->tx_dma
!= INVALID_DMA_ADDRESS
)
975 dma_unmap_single(master
->dev
.parent
, xfer
->tx_dma
,
976 xfer
->len
, DMA_TO_DEVICE
);
977 if (xfer
->rx_dma
!= INVALID_DMA_ADDRESS
)
978 dma_unmap_single(master
->dev
.parent
, xfer
->rx_dma
,
979 xfer
->len
, DMA_FROM_DEVICE
);
982 static void atmel_spi_disable_pdc_transfer(struct atmel_spi
*as
)
984 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
988 atmel_spi_pump_single_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
992 unsigned long xfer_pos
= xfer
->len
- as
->current_remaining_bytes
;
994 if (xfer
->bits_per_word
> 8) {
995 rxp16
= (u16
*)(((u8
*)xfer
->rx_buf
) + xfer_pos
);
996 *rxp16
= spi_readl(as
, RDR
);
998 rxp
= ((u8
*)xfer
->rx_buf
) + xfer_pos
;
999 *rxp
= spi_readl(as
, RDR
);
1001 if (xfer
->bits_per_word
> 8) {
1002 if (as
->current_remaining_bytes
> 2)
1003 as
->current_remaining_bytes
-= 2;
1005 as
->current_remaining_bytes
= 0;
1007 as
->current_remaining_bytes
--;
1012 atmel_spi_pump_fifo_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
1014 u32 fifolr
= spi_readl(as
, FLR
);
1015 u32 num_bytes
, num_data
= SPI_BFEXT(RXFL
, fifolr
);
1016 u32 offset
= xfer
->len
- as
->current_remaining_bytes
;
1017 u16
*words
= (u16
*)((u8
*)xfer
->rx_buf
+ offset
);
1018 u8
*bytes
= (u8
*)((u8
*)xfer
->rx_buf
+ offset
);
1019 u16 rd
; /* RD field is the lowest 16 bits of RDR */
1021 /* Update the number of remaining bytes to transfer */
1022 num_bytes
= ((xfer
->bits_per_word
> 8) ?
1026 if (as
->current_remaining_bytes
> num_bytes
)
1027 as
->current_remaining_bytes
-= num_bytes
;
1029 as
->current_remaining_bytes
= 0;
1031 /* Handle odd number of bytes when data are more than 8bit width */
1032 if (xfer
->bits_per_word
> 8)
1033 as
->current_remaining_bytes
&= ~0x1;
1037 rd
= spi_readl(as
, RDR
);
1038 if (xfer
->bits_per_word
> 8)
1048 * Must update "current_remaining_bytes" to keep track of data
1052 atmel_spi_pump_pio_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
1055 atmel_spi_pump_fifo_data(as
, xfer
);
1057 atmel_spi_pump_single_data(as
, xfer
);
1062 * No need for locking in this Interrupt handler: done_status is the
1063 * only information modified.
1066 atmel_spi_pio_interrupt(int irq
, void *dev_id
)
1068 struct spi_master
*master
= dev_id
;
1069 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1070 u32 status
, pending
, imr
;
1071 struct spi_transfer
*xfer
;
1074 imr
= spi_readl(as
, IMR
);
1075 status
= spi_readl(as
, SR
);
1076 pending
= status
& imr
;
1078 if (pending
& SPI_BIT(OVRES
)) {
1080 spi_writel(as
, IDR
, SPI_BIT(OVRES
));
1081 dev_warn(master
->dev
.parent
, "overrun\n");
1084 * When we get an overrun, we disregard the current
1085 * transfer. Data will not be copied back from any
1086 * bounce buffer and msg->actual_len will not be
1087 * updated with the last xfer.
1089 * We will also not process any remaning transfers in
1092 as
->done_status
= -EIO
;
1095 /* Clear any overrun happening while cleaning up */
1098 complete(&as
->xfer_completion
);
1100 } else if (pending
& (SPI_BIT(RDRF
) | SPI_BIT(RXFTHF
))) {
1103 if (as
->current_remaining_bytes
) {
1105 xfer
= as
->current_transfer
;
1106 atmel_spi_pump_pio_data(as
, xfer
);
1107 if (!as
->current_remaining_bytes
)
1108 spi_writel(as
, IDR
, pending
);
1110 complete(&as
->xfer_completion
);
1113 atmel_spi_unlock(as
);
1115 WARN_ONCE(pending
, "IRQ not handled, pending = %x\n", pending
);
1117 spi_writel(as
, IDR
, pending
);
1124 atmel_spi_pdc_interrupt(int irq
, void *dev_id
)
1126 struct spi_master
*master
= dev_id
;
1127 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1128 u32 status
, pending
, imr
;
1131 imr
= spi_readl(as
, IMR
);
1132 status
= spi_readl(as
, SR
);
1133 pending
= status
& imr
;
1135 if (pending
& SPI_BIT(OVRES
)) {
1139 spi_writel(as
, IDR
, (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
)
1142 /* Clear any overrun happening while cleaning up */
1145 as
->done_status
= -EIO
;
1147 complete(&as
->xfer_completion
);
1149 } else if (pending
& (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
))) {
1152 spi_writel(as
, IDR
, pending
);
1154 complete(&as
->xfer_completion
);
1160 static int atmel_word_delay_csr(struct spi_device
*spi
, struct atmel_spi
*as
)
1162 struct spi_delay
*delay
= &spi
->word_delay
;
1163 u32 value
= delay
->value
;
1165 switch (delay
->unit
) {
1166 case SPI_DELAY_UNIT_NSECS
:
1169 case SPI_DELAY_UNIT_USECS
:
1175 return (as
->spi_clk
/ 1000000 * value
) >> 5;
1178 static void initialize_native_cs_for_gpio(struct atmel_spi
*as
)
1181 struct spi_master
*master
= platform_get_drvdata(as
->pdev
);
1183 if (!as
->native_cs_free
)
1184 return; /* already initialized */
1186 if (!master
->cs_gpiods
)
1187 return; /* No CS GPIO */
1190 * On the first version of the controller (AT91RM9200), CS0
1191 * can't be used associated with GPIO
1193 if (atmel_spi_is_v2(as
))
1199 if (master
->cs_gpiods
[i
])
1200 as
->native_cs_free
|= BIT(i
);
1202 if (as
->native_cs_free
)
1203 as
->native_cs_for_gpio
= ffs(as
->native_cs_free
);
1206 static int atmel_spi_setup(struct spi_device
*spi
)
1208 struct atmel_spi
*as
;
1209 struct atmel_spi_device
*asd
;
1211 unsigned int bits
= spi
->bits_per_word
;
1215 as
= spi_master_get_devdata(spi
->master
);
1217 /* see notes above re chipselect */
1218 if (!spi
->cs_gpiod
&& (spi
->mode
& SPI_CS_HIGH
)) {
1219 dev_warn(&spi
->dev
, "setup: non GPIO CS can't be active-high\n");
1223 /* Setup() is called during spi_register_controller(aka
1224 * spi_register_master) but after all membmers of the cs_gpiod
1225 * array have been filled, so we can looked for which native
1226 * CS will be free for using with GPIO
1228 initialize_native_cs_for_gpio(as
);
1230 if (spi
->cs_gpiod
&& as
->native_cs_free
) {
1232 "No native CS available to support this GPIO CS\n");
1237 chip_select
= as
->native_cs_for_gpio
;
1239 chip_select
= spi
->chip_select
;
1241 csr
= SPI_BF(BITS
, bits
- 8);
1242 if (spi
->mode
& SPI_CPOL
)
1243 csr
|= SPI_BIT(CPOL
);
1244 if (!(spi
->mode
& SPI_CPHA
))
1245 csr
|= SPI_BIT(NCPHA
);
1248 csr
|= SPI_BIT(CSAAT
);
1249 csr
|= SPI_BF(DLYBS
, 0);
1251 word_delay_csr
= atmel_word_delay_csr(spi
, as
);
1252 if (word_delay_csr
< 0)
1253 return word_delay_csr
;
1255 /* DLYBCT adds delays between words. This is useful for slow devices
1256 * that need a bit of time to setup the next transfer.
1258 csr
|= SPI_BF(DLYBCT
, word_delay_csr
);
1260 asd
= spi
->controller_state
;
1262 asd
= kzalloc(sizeof(struct atmel_spi_device
), GFP_KERNEL
);
1266 spi
->controller_state
= asd
;
1272 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1273 bits
, spi
->mode
, spi
->chip_select
, csr
);
1275 if (!atmel_spi_is_v2(as
))
1276 spi_writel(as
, CSR0
+ 4 * chip_select
, csr
);
1281 static int atmel_spi_one_transfer(struct spi_master
*master
,
1282 struct spi_message
*msg
,
1283 struct spi_transfer
*xfer
)
1285 struct atmel_spi
*as
;
1286 struct spi_device
*spi
= msg
->spi
;
1289 struct atmel_spi_device
*asd
;
1292 unsigned long dma_timeout
;
1294 as
= spi_master_get_devdata(master
);
1296 if (!(xfer
->tx_buf
|| xfer
->rx_buf
) && xfer
->len
) {
1297 dev_dbg(&spi
->dev
, "missing rx or tx buf\n");
1301 asd
= spi
->controller_state
;
1302 bits
= (asd
->csr
>> 4) & 0xf;
1303 if (bits
!= xfer
->bits_per_word
- 8) {
1305 "you can't yet change bits_per_word in transfers\n");
1306 return -ENOPROTOOPT
;
1310 * DMA map early, for performance (empties dcache ASAP) and
1311 * better fault reporting.
1313 if ((!msg
->is_dma_mapped
)
1315 if (atmel_spi_dma_map_xfer(as
, xfer
) < 0)
1319 atmel_spi_set_xfer_speed(as
, msg
->spi
, xfer
);
1321 as
->done_status
= 0;
1322 as
->current_transfer
= xfer
;
1323 as
->current_remaining_bytes
= xfer
->len
;
1324 while (as
->current_remaining_bytes
) {
1325 reinit_completion(&as
->xfer_completion
);
1328 atmel_spi_pdc_next_xfer(master
, msg
, xfer
);
1329 } else if (atmel_spi_use_dma(as
, xfer
)) {
1330 len
= as
->current_remaining_bytes
;
1331 ret
= atmel_spi_next_xfer_dma_submit(master
,
1335 "unable to use DMA, fallback to PIO\n");
1336 atmel_spi_next_xfer_pio(master
, xfer
);
1338 as
->current_remaining_bytes
-= len
;
1339 if (as
->current_remaining_bytes
< 0)
1340 as
->current_remaining_bytes
= 0;
1343 atmel_spi_next_xfer_pio(master
, xfer
);
1346 /* interrupts are disabled, so free the lock for schedule */
1347 atmel_spi_unlock(as
);
1348 dma_timeout
= wait_for_completion_timeout(&as
->xfer_completion
,
1351 if (WARN_ON(dma_timeout
== 0)) {
1352 dev_err(&spi
->dev
, "spi transfer timeout\n");
1353 as
->done_status
= -EIO
;
1356 if (as
->done_status
)
1360 if (as
->done_status
) {
1362 dev_warn(master
->dev
.parent
,
1363 "overrun (%u/%u remaining)\n",
1364 spi_readl(as
, TCR
), spi_readl(as
, RCR
));
1367 * Clean up DMA registers and make sure the data
1368 * registers are empty.
1370 spi_writel(as
, RNCR
, 0);
1371 spi_writel(as
, TNCR
, 0);
1372 spi_writel(as
, RCR
, 0);
1373 spi_writel(as
, TCR
, 0);
1374 for (timeout
= 1000; timeout
; timeout
--)
1375 if (spi_readl(as
, SR
) & SPI_BIT(TXEMPTY
))
1378 dev_warn(master
->dev
.parent
,
1379 "timeout waiting for TXEMPTY");
1380 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
))
1383 /* Clear any overrun happening while cleaning up */
1386 } else if (atmel_spi_use_dma(as
, xfer
)) {
1387 atmel_spi_stop_dma(master
);
1390 if (!msg
->is_dma_mapped
1392 atmel_spi_dma_unmap_xfer(master
, xfer
);
1397 /* only update length if no error */
1398 msg
->actual_length
+= xfer
->len
;
1401 if (!msg
->is_dma_mapped
1403 atmel_spi_dma_unmap_xfer(master
, xfer
);
1405 spi_transfer_delay_exec(xfer
);
1407 if (xfer
->cs_change
) {
1408 if (list_is_last(&xfer
->transfer_list
,
1412 cs_deactivate(as
, msg
->spi
);
1414 cs_activate(as
, msg
->spi
);
1421 static int atmel_spi_transfer_one_message(struct spi_master
*master
,
1422 struct spi_message
*msg
)
1424 struct atmel_spi
*as
;
1425 struct spi_transfer
*xfer
;
1426 struct spi_device
*spi
= msg
->spi
;
1429 as
= spi_master_get_devdata(master
);
1431 dev_dbg(&spi
->dev
, "new message %p submitted for %s\n",
1432 msg
, dev_name(&spi
->dev
));
1435 cs_activate(as
, spi
);
1437 as
->keep_cs
= false;
1440 msg
->actual_length
= 0;
1442 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
1443 trace_spi_transfer_start(msg
, xfer
);
1445 ret
= atmel_spi_one_transfer(master
, msg
, xfer
);
1449 trace_spi_transfer_stop(msg
, xfer
);
1453 atmel_spi_disable_pdc_transfer(as
);
1455 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
1457 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1459 xfer
->tx_buf
, &xfer
->tx_dma
,
1460 xfer
->rx_buf
, &xfer
->rx_dma
);
1465 cs_deactivate(as
, msg
->spi
);
1467 atmel_spi_unlock(as
);
1469 msg
->status
= as
->done_status
;
1470 spi_finalize_current_message(spi
->master
);
1475 static void atmel_spi_cleanup(struct spi_device
*spi
)
1477 struct atmel_spi_device
*asd
= spi
->controller_state
;
1482 spi
->controller_state
= NULL
;
1486 static inline unsigned int atmel_get_version(struct atmel_spi
*as
)
1488 return spi_readl(as
, VERSION
) & 0x00000fff;
1491 static void atmel_get_caps(struct atmel_spi
*as
)
1493 unsigned int version
;
1495 version
= atmel_get_version(as
);
1497 as
->caps
.is_spi2
= version
> 0x121;
1498 as
->caps
.has_wdrbt
= version
>= 0x210;
1499 as
->caps
.has_dma_support
= version
>= 0x212;
1500 as
->caps
.has_pdc_support
= version
< 0x212;
1503 static void atmel_spi_init(struct atmel_spi
*as
)
1505 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1506 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1508 /* It is recommended to enable FIFOs first thing after reset */
1510 spi_writel(as
, CR
, SPI_BIT(FIFOEN
));
1512 if (as
->caps
.has_wdrbt
) {
1513 spi_writel(as
, MR
, SPI_BIT(WDRBT
) | SPI_BIT(MODFDIS
)
1516 spi_writel(as
, MR
, SPI_BIT(MSTR
) | SPI_BIT(MODFDIS
));
1520 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
1521 spi_writel(as
, CR
, SPI_BIT(SPIEN
));
1524 static int atmel_spi_probe(struct platform_device
*pdev
)
1526 struct resource
*regs
;
1530 struct spi_master
*master
;
1531 struct atmel_spi
*as
;
1533 /* Select default pin state */
1534 pinctrl_pm_select_default_state(&pdev
->dev
);
1536 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1540 irq
= platform_get_irq(pdev
, 0);
1544 clk
= devm_clk_get(&pdev
->dev
, "spi_clk");
1546 return PTR_ERR(clk
);
1548 /* setup spi core then atmel-specific driver state */
1550 master
= spi_alloc_master(&pdev
->dev
, sizeof(*as
));
1554 /* the spi->mode bits understood by this driver: */
1555 master
->use_gpio_descriptors
= true;
1556 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1557 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(8, 16);
1558 master
->dev
.of_node
= pdev
->dev
.of_node
;
1559 master
->bus_num
= pdev
->id
;
1560 master
->num_chipselect
= 4;
1561 master
->setup
= atmel_spi_setup
;
1562 master
->flags
= (SPI_MASTER_MUST_RX
| SPI_MASTER_MUST_TX
);
1563 master
->transfer_one_message
= atmel_spi_transfer_one_message
;
1564 master
->cleanup
= atmel_spi_cleanup
;
1565 master
->auto_runtime_pm
= true;
1566 master
->max_dma_len
= SPI_MAX_DMA_XFER
;
1567 master
->can_dma
= atmel_spi_can_dma
;
1568 platform_set_drvdata(pdev
, master
);
1570 as
= spi_master_get_devdata(master
);
1572 spin_lock_init(&as
->lock
);
1575 as
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1576 if (IS_ERR(as
->regs
)) {
1577 ret
= PTR_ERR(as
->regs
);
1578 goto out_unmap_regs
;
1580 as
->phybase
= regs
->start
;
1584 init_completion(&as
->xfer_completion
);
1588 as
->use_dma
= false;
1589 as
->use_pdc
= false;
1590 if (as
->caps
.has_dma_support
) {
1591 ret
= atmel_spi_configure_dma(master
, as
);
1594 } else if (ret
== -EPROBE_DEFER
) {
1597 } else if (as
->caps
.has_pdc_support
) {
1601 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5
)) {
1602 as
->addr_rx_bbuf
= dma_alloc_coherent(&pdev
->dev
,
1604 &as
->dma_addr_rx_bbuf
,
1605 GFP_KERNEL
| GFP_DMA
);
1606 if (!as
->addr_rx_bbuf
) {
1607 as
->use_dma
= false;
1609 as
->addr_tx_bbuf
= dma_alloc_coherent(&pdev
->dev
,
1611 &as
->dma_addr_tx_bbuf
,
1612 GFP_KERNEL
| GFP_DMA
);
1613 if (!as
->addr_tx_bbuf
) {
1614 as
->use_dma
= false;
1615 dma_free_coherent(&pdev
->dev
, SPI_MAX_DMA_XFER
,
1617 as
->dma_addr_rx_bbuf
);
1621 dev_info(master
->dev
.parent
,
1622 " can not allocate dma coherent memory\n");
1625 if (as
->caps
.has_dma_support
&& !as
->use_dma
)
1626 dev_info(&pdev
->dev
, "Atmel SPI Controller using PIO only\n");
1629 ret
= devm_request_irq(&pdev
->dev
, irq
, atmel_spi_pdc_interrupt
,
1630 0, dev_name(&pdev
->dev
), master
);
1632 ret
= devm_request_irq(&pdev
->dev
, irq
, atmel_spi_pio_interrupt
,
1633 0, dev_name(&pdev
->dev
), master
);
1636 goto out_unmap_regs
;
1638 /* Initialize the hardware */
1639 ret
= clk_prepare_enable(clk
);
1643 as
->spi_clk
= clk_get_rate(clk
);
1646 if (!of_property_read_u32(pdev
->dev
.of_node
, "atmel,fifo-size",
1648 dev_info(&pdev
->dev
, "Using FIFO (%u data)\n", as
->fifo_size
);
1653 pm_runtime_set_autosuspend_delay(&pdev
->dev
, AUTOSUSPEND_TIMEOUT
);
1654 pm_runtime_use_autosuspend(&pdev
->dev
);
1655 pm_runtime_set_active(&pdev
->dev
);
1656 pm_runtime_enable(&pdev
->dev
);
1658 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1663 dev_info(&pdev
->dev
, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
1664 atmel_get_version(as
), (unsigned long)regs
->start
,
1670 pm_runtime_disable(&pdev
->dev
);
1671 pm_runtime_set_suspended(&pdev
->dev
);
1674 atmel_spi_release_dma(master
);
1676 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1677 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1678 clk_disable_unprepare(clk
);
1682 spi_master_put(master
);
1686 static int atmel_spi_remove(struct platform_device
*pdev
)
1688 struct spi_master
*master
= platform_get_drvdata(pdev
);
1689 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1691 pm_runtime_get_sync(&pdev
->dev
);
1693 /* reset the hardware and block queue progress */
1695 atmel_spi_stop_dma(master
);
1696 atmel_spi_release_dma(master
);
1697 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5
)) {
1698 dma_free_coherent(&pdev
->dev
, SPI_MAX_DMA_XFER
,
1700 as
->dma_addr_tx_bbuf
);
1701 dma_free_coherent(&pdev
->dev
, SPI_MAX_DMA_XFER
,
1703 as
->dma_addr_rx_bbuf
);
1707 spin_lock_irq(&as
->lock
);
1708 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1709 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1711 spin_unlock_irq(&as
->lock
);
1713 clk_disable_unprepare(as
->clk
);
1715 pm_runtime_put_noidle(&pdev
->dev
);
1716 pm_runtime_disable(&pdev
->dev
);
1722 static int atmel_spi_runtime_suspend(struct device
*dev
)
1724 struct spi_master
*master
= dev_get_drvdata(dev
);
1725 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1727 clk_disable_unprepare(as
->clk
);
1728 pinctrl_pm_select_sleep_state(dev
);
1733 static int atmel_spi_runtime_resume(struct device
*dev
)
1735 struct spi_master
*master
= dev_get_drvdata(dev
);
1736 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1738 pinctrl_pm_select_default_state(dev
);
1740 return clk_prepare_enable(as
->clk
);
1743 #ifdef CONFIG_PM_SLEEP
1744 static int atmel_spi_suspend(struct device
*dev
)
1746 struct spi_master
*master
= dev_get_drvdata(dev
);
1749 /* Stop the queue running */
1750 ret
= spi_master_suspend(master
);
1754 if (!pm_runtime_suspended(dev
))
1755 atmel_spi_runtime_suspend(dev
);
1760 static int atmel_spi_resume(struct device
*dev
)
1762 struct spi_master
*master
= dev_get_drvdata(dev
);
1763 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1766 ret
= clk_prepare_enable(as
->clk
);
1772 clk_disable_unprepare(as
->clk
);
1774 if (!pm_runtime_suspended(dev
)) {
1775 ret
= atmel_spi_runtime_resume(dev
);
1780 /* Start the queue running */
1781 return spi_master_resume(master
);
1785 static const struct dev_pm_ops atmel_spi_pm_ops
= {
1786 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend
, atmel_spi_resume
)
1787 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend
,
1788 atmel_spi_runtime_resume
, NULL
)
1790 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1792 #define ATMEL_SPI_PM_OPS NULL
1795 static const struct of_device_id atmel_spi_dt_ids
[] = {
1796 { .compatible
= "atmel,at91rm9200-spi" },
1800 MODULE_DEVICE_TABLE(of
, atmel_spi_dt_ids
);
1802 static struct platform_driver atmel_spi_driver
= {
1804 .name
= "atmel_spi",
1805 .pm
= ATMEL_SPI_PM_OPS
,
1806 .of_match_table
= atmel_spi_dt_ids
,
1808 .probe
= atmel_spi_probe
,
1809 .remove
= atmel_spi_remove
,
1811 module_platform_driver(atmel_spi_driver
);
1813 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1814 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1815 MODULE_LICENSE("GPL");
1816 MODULE_ALIAS("platform:atmel_spi");