1 // SPDX-License-Identifier: GPL-2.0-only
3 // Driver for Cadence QSPI Controller
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
17 #include <linux/interrupt.h>
19 #include <linux/iopoll.h>
20 #include <linux/jiffies.h>
21 #include <linux/kernel.h>
22 #include <linux/log2.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28 #include <linux/sched.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi-mem.h>
31 #include <linux/timer.h>
33 #define CQSPI_NAME "cadence-qspi"
34 #define CQSPI_MAX_CHIPSELECT 4
36 static_assert(CQSPI_MAX_CHIPSELECT
<= SPI_CS_CNT_MAX
);
39 #define CQSPI_NEEDS_WR_DELAY BIT(0)
40 #define CQSPI_DISABLE_DAC_MODE BIT(1)
41 #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2)
42 #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
43 #define CQSPI_SLOW_SRAM BIT(4)
44 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5)
47 #define CQSPI_SUPPORTS_OCTAL BIT(0)
49 #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0)
59 struct cqspi_flash_pdata
{
60 struct cqspi_st
*cqspi
;
71 struct platform_device
*pdev
;
72 struct spi_controller
*host
;
74 struct clk
*clks
[CLK_QSPI_NUM
];
78 void __iomem
*ahb_base
;
79 resource_size_t ahb_size
;
80 struct completion transfer_complete
;
82 struct dma_chan
*rx_chan
;
83 struct completion rx_dma_complete
;
84 dma_addr_t mmap_phys_base
;
87 unsigned long master_ref_clk_hz
;
96 bool use_direct_mode_wr
;
97 struct cqspi_flash_pdata f_pdata
[CQSPI_MAX_CHIPSELECT
];
104 bool is_jh7110
; /* Flag for StarFive JH7110 SoC */
107 struct cqspi_driver_platdata
{
110 int (*indirect_read_dma
)(struct cqspi_flash_pdata
*f_pdata
,
111 u_char
*rxbuf
, loff_t from_addr
, size_t n_rx
);
112 u32 (*get_dma_status
)(struct cqspi_st
*cqspi
);
113 int (*jh7110_clk_init
)(struct platform_device
*pdev
,
114 struct cqspi_st
*cqspi
);
117 /* Operation timeout value */
118 #define CQSPI_TIMEOUT_MS 500
119 #define CQSPI_READ_TIMEOUT_MS 10
121 /* Runtime_pm autosuspend delay */
122 #define CQSPI_AUTOSUSPEND_TIMEOUT 2000
124 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
125 #define CQSPI_DUMMY_BYTES_MAX 4
126 #define CQSPI_DUMMY_CLKS_MAX 31
128 #define CQSPI_STIG_DATA_LEN_MAX 8
131 #define CQSPI_REG_CONFIG 0x00
132 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
133 #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
134 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
135 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
136 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
137 #define CQSPI_REG_CONFIG_BAUD_LSB 19
138 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
139 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
140 #define CQSPI_REG_CONFIG_IDLE_LSB 31
141 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
142 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
144 #define CQSPI_REG_RD_INSTR 0x04
145 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
146 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
147 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
148 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
149 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
150 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
151 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
152 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
153 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
154 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
156 #define CQSPI_REG_WR_INSTR 0x08
157 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
158 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
159 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
161 #define CQSPI_REG_DELAY 0x0C
162 #define CQSPI_REG_DELAY_TSLCH_LSB 0
163 #define CQSPI_REG_DELAY_TCHSH_LSB 8
164 #define CQSPI_REG_DELAY_TSD2D_LSB 16
165 #define CQSPI_REG_DELAY_TSHSL_LSB 24
166 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
167 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
168 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
169 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
171 #define CQSPI_REG_READCAPTURE 0x10
172 #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0
173 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1
174 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF
176 #define CQSPI_REG_SIZE 0x14
177 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
178 #define CQSPI_REG_SIZE_PAGE_LSB 4
179 #define CQSPI_REG_SIZE_BLOCK_LSB 16
180 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
181 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
182 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
184 #define CQSPI_REG_SRAMPARTITION 0x18
185 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
187 #define CQSPI_REG_DMA 0x20
188 #define CQSPI_REG_DMA_SINGLE_LSB 0
189 #define CQSPI_REG_DMA_BURST_LSB 8
190 #define CQSPI_REG_DMA_SINGLE_MASK 0xFF
191 #define CQSPI_REG_DMA_BURST_MASK 0xFF
193 #define CQSPI_REG_REMAP 0x24
194 #define CQSPI_REG_MODE_BIT 0x28
196 #define CQSPI_REG_SDRAMLEVEL 0x2C
197 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
198 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
199 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
200 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
202 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
203 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
205 #define CQSPI_REG_IRQSTATUS 0x40
206 #define CQSPI_REG_IRQMASK 0x44
208 #define CQSPI_REG_INDIRECTRD 0x60
209 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
210 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
211 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
213 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
214 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
215 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
217 #define CQSPI_REG_CMDCTRL 0x90
218 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
219 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
220 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
221 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
222 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
223 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
224 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
225 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
226 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
227 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
228 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
229 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
230 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
231 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
233 #define CQSPI_REG_INDIRECTWR 0x70
234 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
235 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
236 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
238 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
239 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
240 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
242 #define CQSPI_REG_INDTRIG_ADDRRANGE 0x80
244 #define CQSPI_REG_CMDADDRESS 0x94
245 #define CQSPI_REG_CMDREADDATALOWER 0xA0
246 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
247 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
248 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
250 #define CQSPI_REG_POLLING_STATUS 0xB0
251 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16
253 #define CQSPI_REG_OP_EXT_LOWER 0xE0
254 #define CQSPI_REG_OP_EXT_READ_LSB 24
255 #define CQSPI_REG_OP_EXT_WRITE_LSB 16
256 #define CQSPI_REG_OP_EXT_STIG_LSB 0
258 #define CQSPI_REG_VERSAL_DMA_SRC_ADDR 0x1000
260 #define CQSPI_REG_VERSAL_DMA_DST_ADDR 0x1800
261 #define CQSPI_REG_VERSAL_DMA_DST_SIZE 0x1804
263 #define CQSPI_REG_VERSAL_DMA_DST_CTRL 0x180C
265 #define CQSPI_REG_VERSAL_DMA_DST_I_STS 0x1814
266 #define CQSPI_REG_VERSAL_DMA_DST_I_EN 0x1818
267 #define CQSPI_REG_VERSAL_DMA_DST_I_DIS 0x181C
268 #define CQSPI_REG_VERSAL_DMA_DST_DONE_MASK BIT(1)
270 #define CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB 0x1828
272 #define CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL 0xF43FFA00
273 #define CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL 0x6
275 /* Interrupt status bits */
276 #define CQSPI_REG_IRQ_MODE_ERR BIT(0)
277 #define CQSPI_REG_IRQ_UNDERFLOW BIT(1)
278 #define CQSPI_REG_IRQ_IND_COMP BIT(2)
279 #define CQSPI_REG_IRQ_IND_RD_REJECT BIT(3)
280 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR BIT(4)
281 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR BIT(5)
282 #define CQSPI_REG_IRQ_WATERMARK BIT(6)
283 #define CQSPI_REG_IRQ_IND_SRAM_FULL BIT(12)
285 #define CQSPI_IRQ_MASK_RD (CQSPI_REG_IRQ_WATERMARK | \
286 CQSPI_REG_IRQ_IND_SRAM_FULL | \
287 CQSPI_REG_IRQ_IND_COMP)
289 #define CQSPI_IRQ_MASK_WR (CQSPI_REG_IRQ_IND_COMP | \
290 CQSPI_REG_IRQ_WATERMARK | \
291 CQSPI_REG_IRQ_UNDERFLOW)
293 #define CQSPI_IRQ_STATUS_MASK 0x1FFFF
294 #define CQSPI_DMA_UNALIGN 0x3
296 #define CQSPI_REG_VERSAL_DMA_VAL 0x602
298 static int cqspi_wait_for_bit(void __iomem
*reg
, const u32 mask
, bool clr
)
302 return readl_relaxed_poll_timeout(reg
, val
,
303 (((clr
? ~val
: val
) & mask
) == mask
),
304 10, CQSPI_TIMEOUT_MS
* 1000);
307 static bool cqspi_is_idle(struct cqspi_st
*cqspi
)
309 u32 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
311 return reg
& (1UL << CQSPI_REG_CONFIG_IDLE_LSB
);
314 static u32
cqspi_get_rd_sram_level(struct cqspi_st
*cqspi
)
316 u32 reg
= readl(cqspi
->iobase
+ CQSPI_REG_SDRAMLEVEL
);
318 reg
>>= CQSPI_REG_SDRAMLEVEL_RD_LSB
;
319 return reg
& CQSPI_REG_SDRAMLEVEL_RD_MASK
;
322 static u32
cqspi_get_versal_dma_status(struct cqspi_st
*cqspi
)
326 dma_status
= readl(cqspi
->iobase
+
327 CQSPI_REG_VERSAL_DMA_DST_I_STS
);
328 writel(dma_status
, cqspi
->iobase
+
329 CQSPI_REG_VERSAL_DMA_DST_I_STS
);
331 return dma_status
& CQSPI_REG_VERSAL_DMA_DST_DONE_MASK
;
334 static irqreturn_t
cqspi_irq_handler(int this_irq
, void *dev
)
336 struct cqspi_st
*cqspi
= dev
;
337 unsigned int irq_status
;
338 struct device
*device
= &cqspi
->pdev
->dev
;
339 const struct cqspi_driver_platdata
*ddata
;
341 ddata
= of_device_get_match_data(device
);
343 /* Read interrupt status */
344 irq_status
= readl(cqspi
->iobase
+ CQSPI_REG_IRQSTATUS
);
346 /* Clear interrupt */
347 writel(irq_status
, cqspi
->iobase
+ CQSPI_REG_IRQSTATUS
);
349 if (cqspi
->use_dma_read
&& ddata
&& ddata
->get_dma_status
) {
350 if (ddata
->get_dma_status(cqspi
)) {
351 complete(&cqspi
->transfer_complete
);
356 else if (!cqspi
->slow_sram
)
357 irq_status
&= CQSPI_IRQ_MASK_RD
| CQSPI_IRQ_MASK_WR
;
359 irq_status
&= CQSPI_REG_IRQ_WATERMARK
| CQSPI_IRQ_MASK_WR
;
362 complete(&cqspi
->transfer_complete
);
367 static unsigned int cqspi_calc_rdreg(const struct spi_mem_op
*op
)
371 rdreg
|= CQSPI_OP_WIDTH(op
->cmd
) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB
;
372 rdreg
|= CQSPI_OP_WIDTH(op
->addr
) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB
;
373 rdreg
|= CQSPI_OP_WIDTH(op
->data
) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB
;
378 static unsigned int cqspi_calc_dummy(const struct spi_mem_op
*op
)
380 unsigned int dummy_clk
;
382 if (!op
->dummy
.nbytes
)
385 dummy_clk
= op
->dummy
.nbytes
* (8 / op
->dummy
.buswidth
);
392 static int cqspi_wait_idle(struct cqspi_st
*cqspi
)
394 const unsigned int poll_idle_retry
= 3;
395 unsigned int count
= 0;
396 unsigned long timeout
;
398 timeout
= jiffies
+ msecs_to_jiffies(CQSPI_TIMEOUT_MS
);
401 * Read few times in succession to ensure the controller
402 * is indeed idle, that is, the bit does not transition
405 if (cqspi_is_idle(cqspi
))
410 if (count
>= poll_idle_retry
)
413 if (time_after(jiffies
, timeout
)) {
414 /* Timeout, in busy mode. */
415 dev_err(&cqspi
->pdev
->dev
,
416 "QSPI is still busy after %dms timeout.\n",
425 static int cqspi_exec_flash_cmd(struct cqspi_st
*cqspi
, unsigned int reg
)
427 void __iomem
*reg_base
= cqspi
->iobase
;
430 /* Write the CMDCTRL without start execution. */
431 writel(reg
, reg_base
+ CQSPI_REG_CMDCTRL
);
433 reg
|= CQSPI_REG_CMDCTRL_EXECUTE_MASK
;
434 writel(reg
, reg_base
+ CQSPI_REG_CMDCTRL
);
436 /* Polling for completion. */
437 ret
= cqspi_wait_for_bit(reg_base
+ CQSPI_REG_CMDCTRL
,
438 CQSPI_REG_CMDCTRL_INPROGRESS_MASK
, 1);
440 dev_err(&cqspi
->pdev
->dev
,
441 "Flash command execution timed out.\n");
445 /* Polling QSPI idle status. */
446 return cqspi_wait_idle(cqspi
);
449 static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata
*f_pdata
,
450 const struct spi_mem_op
*op
,
453 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
454 void __iomem
*reg_base
= cqspi
->iobase
;
458 if (op
->cmd
.nbytes
!= 2)
461 /* Opcode extension is the LSB. */
462 ext
= op
->cmd
.opcode
& 0xff;
464 reg
= readl(reg_base
+ CQSPI_REG_OP_EXT_LOWER
);
465 reg
&= ~(0xff << shift
);
467 writel(reg
, reg_base
+ CQSPI_REG_OP_EXT_LOWER
);
472 static int cqspi_enable_dtr(struct cqspi_flash_pdata
*f_pdata
,
473 const struct spi_mem_op
*op
, unsigned int shift
)
475 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
476 void __iomem
*reg_base
= cqspi
->iobase
;
480 reg
= readl(reg_base
+ CQSPI_REG_CONFIG
);
483 * We enable dual byte opcode here. The callers have to set up the
484 * extension opcode based on which type of operation it is.
487 reg
|= CQSPI_REG_CONFIG_DTR_PROTO
;
488 reg
|= CQSPI_REG_CONFIG_DUAL_OPCODE
;
490 /* Set up command opcode extension. */
491 ret
= cqspi_setup_opcode_ext(f_pdata
, op
, shift
);
495 reg
&= ~CQSPI_REG_CONFIG_DTR_PROTO
;
496 reg
&= ~CQSPI_REG_CONFIG_DUAL_OPCODE
;
499 writel(reg
, reg_base
+ CQSPI_REG_CONFIG
);
501 return cqspi_wait_idle(cqspi
);
504 static int cqspi_command_read(struct cqspi_flash_pdata
*f_pdata
,
505 const struct spi_mem_op
*op
)
507 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
508 void __iomem
*reg_base
= cqspi
->iobase
;
509 u8
*rxbuf
= op
->data
.buf
.in
;
511 size_t n_rx
= op
->data
.nbytes
;
514 unsigned int dummy_clk
;
518 status
= cqspi_enable_dtr(f_pdata
, op
, CQSPI_REG_OP_EXT_STIG_LSB
);
522 if (!n_rx
|| n_rx
> CQSPI_STIG_DATA_LEN_MAX
|| !rxbuf
) {
523 dev_err(&cqspi
->pdev
->dev
,
524 "Invalid input argument, len %zu rxbuf 0x%p\n",
530 opcode
= op
->cmd
.opcode
>> 8;
532 opcode
= op
->cmd
.opcode
;
534 reg
= opcode
<< CQSPI_REG_CMDCTRL_OPCODE_LSB
;
536 rdreg
= cqspi_calc_rdreg(op
);
537 writel(rdreg
, reg_base
+ CQSPI_REG_RD_INSTR
);
539 dummy_clk
= cqspi_calc_dummy(op
);
540 if (dummy_clk
> CQSPI_DUMMY_CLKS_MAX
)
544 reg
|= (dummy_clk
& CQSPI_REG_CMDCTRL_DUMMY_MASK
)
545 << CQSPI_REG_CMDCTRL_DUMMY_LSB
;
547 reg
|= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB
);
549 /* 0 means 1 byte. */
550 reg
|= (((n_rx
- 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK
)
551 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB
);
553 /* setup ADDR BIT field */
554 if (op
->addr
.nbytes
) {
555 reg
|= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB
);
556 reg
|= ((op
->addr
.nbytes
- 1) &
557 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK
)
558 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB
;
560 writel(op
->addr
.val
, reg_base
+ CQSPI_REG_CMDADDRESS
);
563 status
= cqspi_exec_flash_cmd(cqspi
, reg
);
567 reg
= readl(reg_base
+ CQSPI_REG_CMDREADDATALOWER
);
569 /* Put the read value into rx_buf */
570 read_len
= (n_rx
> 4) ? 4 : n_rx
;
571 memcpy(rxbuf
, ®
, read_len
);
575 reg
= readl(reg_base
+ CQSPI_REG_CMDREADDATAUPPER
);
577 read_len
= n_rx
- read_len
;
578 memcpy(rxbuf
, ®
, read_len
);
581 /* Reset CMD_CTRL Reg once command read completes */
582 writel(0, reg_base
+ CQSPI_REG_CMDCTRL
);
587 static int cqspi_command_write(struct cqspi_flash_pdata
*f_pdata
,
588 const struct spi_mem_op
*op
)
590 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
591 void __iomem
*reg_base
= cqspi
->iobase
;
593 const u8
*txbuf
= op
->data
.buf
.out
;
594 size_t n_tx
= op
->data
.nbytes
;
600 ret
= cqspi_enable_dtr(f_pdata
, op
, CQSPI_REG_OP_EXT_STIG_LSB
);
604 if (n_tx
> CQSPI_STIG_DATA_LEN_MAX
|| (n_tx
&& !txbuf
)) {
605 dev_err(&cqspi
->pdev
->dev
,
606 "Invalid input argument, cmdlen %zu txbuf 0x%p\n",
611 reg
= cqspi_calc_rdreg(op
);
612 writel(reg
, reg_base
+ CQSPI_REG_RD_INSTR
);
615 opcode
= op
->cmd
.opcode
>> 8;
617 opcode
= op
->cmd
.opcode
;
619 reg
= opcode
<< CQSPI_REG_CMDCTRL_OPCODE_LSB
;
621 if (op
->addr
.nbytes
) {
622 reg
|= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB
);
623 reg
|= ((op
->addr
.nbytes
- 1) &
624 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK
)
625 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB
;
627 writel(op
->addr
.val
, reg_base
+ CQSPI_REG_CMDADDRESS
);
631 reg
|= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB
);
632 reg
|= ((n_tx
- 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK
)
633 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB
;
635 write_len
= (n_tx
> 4) ? 4 : n_tx
;
636 memcpy(&data
, txbuf
, write_len
);
638 writel(data
, reg_base
+ CQSPI_REG_CMDWRITEDATALOWER
);
642 write_len
= n_tx
- 4;
643 memcpy(&data
, txbuf
, write_len
);
644 writel(data
, reg_base
+ CQSPI_REG_CMDWRITEDATAUPPER
);
648 ret
= cqspi_exec_flash_cmd(cqspi
, reg
);
650 /* Reset CMD_CTRL Reg once command write completes */
651 writel(0, reg_base
+ CQSPI_REG_CMDCTRL
);
656 static int cqspi_read_setup(struct cqspi_flash_pdata
*f_pdata
,
657 const struct spi_mem_op
*op
)
659 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
660 void __iomem
*reg_base
= cqspi
->iobase
;
661 unsigned int dummy_clk
= 0;
666 ret
= cqspi_enable_dtr(f_pdata
, op
, CQSPI_REG_OP_EXT_READ_LSB
);
671 opcode
= op
->cmd
.opcode
>> 8;
673 opcode
= op
->cmd
.opcode
;
675 reg
= opcode
<< CQSPI_REG_RD_INSTR_OPCODE_LSB
;
676 reg
|= cqspi_calc_rdreg(op
);
678 /* Setup dummy clock cycles */
679 dummy_clk
= cqspi_calc_dummy(op
);
681 if (dummy_clk
> CQSPI_DUMMY_CLKS_MAX
)
685 reg
|= (dummy_clk
& CQSPI_REG_RD_INSTR_DUMMY_MASK
)
686 << CQSPI_REG_RD_INSTR_DUMMY_LSB
;
688 writel(reg
, reg_base
+ CQSPI_REG_RD_INSTR
);
690 /* Set address width */
691 reg
= readl(reg_base
+ CQSPI_REG_SIZE
);
692 reg
&= ~CQSPI_REG_SIZE_ADDRESS_MASK
;
693 reg
|= (op
->addr
.nbytes
- 1);
694 writel(reg
, reg_base
+ CQSPI_REG_SIZE
);
698 static int cqspi_indirect_read_execute(struct cqspi_flash_pdata
*f_pdata
,
699 u8
*rxbuf
, loff_t from_addr
,
702 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
703 struct device
*dev
= &cqspi
->pdev
->dev
;
704 void __iomem
*reg_base
= cqspi
->iobase
;
705 void __iomem
*ahb_base
= cqspi
->ahb_base
;
706 unsigned int remaining
= n_rx
;
707 unsigned int mod_bytes
= n_rx
% 4;
708 unsigned int bytes_to_read
= 0;
709 u8
*rxbuf_end
= rxbuf
+ n_rx
;
712 writel(from_addr
, reg_base
+ CQSPI_REG_INDIRECTRDSTARTADDR
);
713 writel(remaining
, reg_base
+ CQSPI_REG_INDIRECTRDBYTES
);
715 /* Clear all interrupts. */
716 writel(CQSPI_IRQ_STATUS_MASK
, reg_base
+ CQSPI_REG_IRQSTATUS
);
719 * On SoCFPGA platform reading the SRAM is slow due to
720 * hardware limitation and causing read interrupt storm to CPU,
721 * so enabling only watermark interrupt to disable all read
722 * interrupts later as we want to run "bytes to read" loop with
723 * all the read interrupts disabled for max performance.
726 if (!cqspi
->slow_sram
)
727 writel(CQSPI_IRQ_MASK_RD
, reg_base
+ CQSPI_REG_IRQMASK
);
729 writel(CQSPI_REG_IRQ_WATERMARK
, reg_base
+ CQSPI_REG_IRQMASK
);
731 reinit_completion(&cqspi
->transfer_complete
);
732 writel(CQSPI_REG_INDIRECTRD_START_MASK
,
733 reg_base
+ CQSPI_REG_INDIRECTRD
);
735 while (remaining
> 0) {
736 if (!wait_for_completion_timeout(&cqspi
->transfer_complete
,
737 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS
)))
741 * Disable all read interrupts until
742 * we are out of "bytes to read"
744 if (cqspi
->slow_sram
)
745 writel(0x0, reg_base
+ CQSPI_REG_IRQMASK
);
747 bytes_to_read
= cqspi_get_rd_sram_level(cqspi
);
749 if (ret
&& bytes_to_read
== 0) {
750 dev_err(dev
, "Indirect read timeout, no bytes\n");
754 while (bytes_to_read
!= 0) {
755 unsigned int word_remain
= round_down(remaining
, 4);
757 bytes_to_read
*= cqspi
->fifo_width
;
758 bytes_to_read
= bytes_to_read
> remaining
?
759 remaining
: bytes_to_read
;
760 bytes_to_read
= round_down(bytes_to_read
, 4);
761 /* Read 4 byte word chunks then single bytes */
763 ioread32_rep(ahb_base
, rxbuf
,
764 (bytes_to_read
/ 4));
765 } else if (!word_remain
&& mod_bytes
) {
766 unsigned int temp
= ioread32(ahb_base
);
768 bytes_to_read
= mod_bytes
;
769 memcpy(rxbuf
, &temp
, min((unsigned int)
773 rxbuf
+= bytes_to_read
;
774 remaining
-= bytes_to_read
;
775 bytes_to_read
= cqspi_get_rd_sram_level(cqspi
);
779 reinit_completion(&cqspi
->transfer_complete
);
780 if (cqspi
->slow_sram
)
781 writel(CQSPI_REG_IRQ_WATERMARK
, reg_base
+ CQSPI_REG_IRQMASK
);
785 /* Check indirect done status */
786 ret
= cqspi_wait_for_bit(reg_base
+ CQSPI_REG_INDIRECTRD
,
787 CQSPI_REG_INDIRECTRD_DONE_MASK
, 0);
789 dev_err(dev
, "Indirect read completion error (%i)\n", ret
);
793 /* Disable interrupt */
794 writel(0, reg_base
+ CQSPI_REG_IRQMASK
);
796 /* Clear indirect completion status */
797 writel(CQSPI_REG_INDIRECTRD_DONE_MASK
, reg_base
+ CQSPI_REG_INDIRECTRD
);
802 /* Disable interrupt */
803 writel(0, reg_base
+ CQSPI_REG_IRQMASK
);
805 /* Cancel the indirect read */
806 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK
,
807 reg_base
+ CQSPI_REG_INDIRECTRD
);
811 static void cqspi_controller_enable(struct cqspi_st
*cqspi
, bool enable
)
813 void __iomem
*reg_base
= cqspi
->iobase
;
816 reg
= readl(reg_base
+ CQSPI_REG_CONFIG
);
819 reg
|= CQSPI_REG_CONFIG_ENABLE_MASK
;
821 reg
&= ~CQSPI_REG_CONFIG_ENABLE_MASK
;
823 writel(reg
, reg_base
+ CQSPI_REG_CONFIG
);
826 static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata
*f_pdata
,
827 u_char
*rxbuf
, loff_t from_addr
,
830 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
831 struct device
*dev
= &cqspi
->pdev
->dev
;
832 void __iomem
*reg_base
= cqspi
->iobase
;
833 u32 reg
, bytes_to_dma
;
834 loff_t addr
= from_addr
;
840 bytes_rem
= n_rx
% 4;
841 bytes_to_dma
= (n_rx
- bytes_rem
);
846 ret
= zynqmp_pm_ospi_mux_select(cqspi
->pd_dev_id
, PM_OSPI_MUX_SEL_DMA
);
850 cqspi_controller_enable(cqspi
, 0);
852 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
853 reg
|= CQSPI_REG_CONFIG_DMA_MASK
;
854 writel(reg
, cqspi
->iobase
+ CQSPI_REG_CONFIG
);
856 cqspi_controller_enable(cqspi
, 1);
858 dma_addr
= dma_map_single(dev
, rxbuf
, bytes_to_dma
, DMA_FROM_DEVICE
);
859 if (dma_mapping_error(dev
, dma_addr
)) {
860 dev_err(dev
, "dma mapping failed\n");
864 writel(from_addr
, reg_base
+ CQSPI_REG_INDIRECTRDSTARTADDR
);
865 writel(bytes_to_dma
, reg_base
+ CQSPI_REG_INDIRECTRDBYTES
);
866 writel(CQSPI_REG_VERSAL_ADDRRANGE_WIDTH_VAL
,
867 reg_base
+ CQSPI_REG_INDTRIG_ADDRRANGE
);
869 /* Clear all interrupts. */
870 writel(CQSPI_IRQ_STATUS_MASK
, reg_base
+ CQSPI_REG_IRQSTATUS
);
872 /* Enable DMA done interrupt */
873 writel(CQSPI_REG_VERSAL_DMA_DST_DONE_MASK
,
874 reg_base
+ CQSPI_REG_VERSAL_DMA_DST_I_EN
);
876 /* Default DMA periph configuration */
877 writel(CQSPI_REG_VERSAL_DMA_VAL
, reg_base
+ CQSPI_REG_DMA
);
879 /* Configure DMA Dst address */
880 writel(lower_32_bits(dma_addr
),
881 reg_base
+ CQSPI_REG_VERSAL_DMA_DST_ADDR
);
882 writel(upper_32_bits(dma_addr
),
883 reg_base
+ CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB
);
885 /* Configure DMA Src address */
886 writel(cqspi
->trigger_address
, reg_base
+
887 CQSPI_REG_VERSAL_DMA_SRC_ADDR
);
889 /* Set DMA destination size */
890 writel(bytes_to_dma
, reg_base
+ CQSPI_REG_VERSAL_DMA_DST_SIZE
);
892 /* Set DMA destination control */
893 writel(CQSPI_REG_VERSAL_DMA_DST_CTRL_VAL
,
894 reg_base
+ CQSPI_REG_VERSAL_DMA_DST_CTRL
);
896 writel(CQSPI_REG_INDIRECTRD_START_MASK
,
897 reg_base
+ CQSPI_REG_INDIRECTRD
);
899 reinit_completion(&cqspi
->transfer_complete
);
901 if (!wait_for_completion_timeout(&cqspi
->transfer_complete
,
902 msecs_to_jiffies(max_t(size_t, bytes_to_dma
, 500)))) {
907 /* Disable DMA interrupt */
908 writel(0x0, cqspi
->iobase
+ CQSPI_REG_VERSAL_DMA_DST_I_DIS
);
910 /* Clear indirect completion status */
911 writel(CQSPI_REG_INDIRECTRD_DONE_MASK
,
912 cqspi
->iobase
+ CQSPI_REG_INDIRECTRD
);
913 dma_unmap_single(dev
, dma_addr
, bytes_to_dma
, DMA_FROM_DEVICE
);
915 cqspi_controller_enable(cqspi
, 0);
917 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
918 reg
&= ~CQSPI_REG_CONFIG_DMA_MASK
;
919 writel(reg
, cqspi
->iobase
+ CQSPI_REG_CONFIG
);
921 cqspi_controller_enable(cqspi
, 1);
923 ret
= zynqmp_pm_ospi_mux_select(cqspi
->pd_dev_id
,
924 PM_OSPI_MUX_SEL_LINEAR
);
930 addr
+= bytes_to_dma
;
932 ret
= cqspi_indirect_read_execute(f_pdata
, buf
, addr
,
941 /* Disable DMA interrupt */
942 writel(0x0, reg_base
+ CQSPI_REG_VERSAL_DMA_DST_I_DIS
);
944 /* Cancel the indirect read */
945 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK
,
946 reg_base
+ CQSPI_REG_INDIRECTRD
);
948 dma_unmap_single(dev
, dma_addr
, bytes_to_dma
, DMA_FROM_DEVICE
);
950 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
951 reg
&= ~CQSPI_REG_CONFIG_DMA_MASK
;
952 writel(reg
, cqspi
->iobase
+ CQSPI_REG_CONFIG
);
954 zynqmp_pm_ospi_mux_select(cqspi
->pd_dev_id
, PM_OSPI_MUX_SEL_LINEAR
);
959 static int cqspi_write_setup(struct cqspi_flash_pdata
*f_pdata
,
960 const struct spi_mem_op
*op
)
964 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
965 void __iomem
*reg_base
= cqspi
->iobase
;
968 ret
= cqspi_enable_dtr(f_pdata
, op
, CQSPI_REG_OP_EXT_WRITE_LSB
);
973 opcode
= op
->cmd
.opcode
>> 8;
975 opcode
= op
->cmd
.opcode
;
978 reg
= opcode
<< CQSPI_REG_WR_INSTR_OPCODE_LSB
;
979 reg
|= CQSPI_OP_WIDTH(op
->data
) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB
;
980 reg
|= CQSPI_OP_WIDTH(op
->addr
) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB
;
981 writel(reg
, reg_base
+ CQSPI_REG_WR_INSTR
);
982 reg
= cqspi_calc_rdreg(op
);
983 writel(reg
, reg_base
+ CQSPI_REG_RD_INSTR
);
986 * SPI NAND flashes require the address of the status register to be
987 * passed in the Read SR command. Also, some SPI NOR flashes like the
988 * cypress Semper flash expect a 4-byte dummy address in the Read SR
989 * command in DTR mode.
991 * But this controller does not support address phase in the Read SR
992 * command when doing auto-HW polling. So, disable write completion
993 * polling on the controller's side. spinand and spi-nor will take
994 * care of polling the status register.
996 if (cqspi
->wr_completion
) {
997 reg
= readl(reg_base
+ CQSPI_REG_WR_COMPLETION_CTRL
);
998 reg
|= CQSPI_REG_WR_DISABLE_AUTO_POLL
;
999 writel(reg
, reg_base
+ CQSPI_REG_WR_COMPLETION_CTRL
);
1001 * DAC mode require auto polling as flash needs to be polled
1002 * for write completion in case of bubble in SPI transaction
1003 * due to slow CPU/DMA master.
1005 cqspi
->use_direct_mode_wr
= false;
1008 reg
= readl(reg_base
+ CQSPI_REG_SIZE
);
1009 reg
&= ~CQSPI_REG_SIZE_ADDRESS_MASK
;
1010 reg
|= (op
->addr
.nbytes
- 1);
1011 writel(reg
, reg_base
+ CQSPI_REG_SIZE
);
1015 static int cqspi_indirect_write_execute(struct cqspi_flash_pdata
*f_pdata
,
1016 loff_t to_addr
, const u8
*txbuf
,
1019 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1020 struct device
*dev
= &cqspi
->pdev
->dev
;
1021 void __iomem
*reg_base
= cqspi
->iobase
;
1022 unsigned int remaining
= n_tx
;
1023 unsigned int write_bytes
;
1026 writel(to_addr
, reg_base
+ CQSPI_REG_INDIRECTWRSTARTADDR
);
1027 writel(remaining
, reg_base
+ CQSPI_REG_INDIRECTWRBYTES
);
1029 /* Clear all interrupts. */
1030 writel(CQSPI_IRQ_STATUS_MASK
, reg_base
+ CQSPI_REG_IRQSTATUS
);
1032 writel(CQSPI_IRQ_MASK_WR
, reg_base
+ CQSPI_REG_IRQMASK
);
1034 reinit_completion(&cqspi
->transfer_complete
);
1035 writel(CQSPI_REG_INDIRECTWR_START_MASK
,
1036 reg_base
+ CQSPI_REG_INDIRECTWR
);
1038 * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
1039 * Controller programming sequence, couple of cycles of
1040 * QSPI_REF_CLK delay is required for the above bit to
1041 * be internally synchronized by the QSPI module. Provide 5
1044 if (cqspi
->wr_delay
)
1045 ndelay(cqspi
->wr_delay
);
1048 * If a hazard exists between the APB and AHB interfaces, perform a
1049 * dummy readback from the controller to ensure synchronization.
1051 if (cqspi
->apb_ahb_hazard
)
1052 readl(reg_base
+ CQSPI_REG_INDIRECTWR
);
1054 while (remaining
> 0) {
1055 size_t write_words
, mod_bytes
;
1057 write_bytes
= remaining
;
1058 write_words
= write_bytes
/ 4;
1059 mod_bytes
= write_bytes
% 4;
1060 /* Write 4 bytes at a time then single bytes. */
1062 iowrite32_rep(cqspi
->ahb_base
, txbuf
, write_words
);
1063 txbuf
+= (write_words
* 4);
1066 unsigned int temp
= 0xFFFFFFFF;
1068 memcpy(&temp
, txbuf
, mod_bytes
);
1069 iowrite32(temp
, cqspi
->ahb_base
);
1073 if (!wait_for_completion_timeout(&cqspi
->transfer_complete
,
1074 msecs_to_jiffies(CQSPI_TIMEOUT_MS
))) {
1075 dev_err(dev
, "Indirect write timeout\n");
1080 remaining
-= write_bytes
;
1083 reinit_completion(&cqspi
->transfer_complete
);
1086 /* Check indirect done status */
1087 ret
= cqspi_wait_for_bit(reg_base
+ CQSPI_REG_INDIRECTWR
,
1088 CQSPI_REG_INDIRECTWR_DONE_MASK
, 0);
1090 dev_err(dev
, "Indirect write completion error (%i)\n", ret
);
1094 /* Disable interrupt. */
1095 writel(0, reg_base
+ CQSPI_REG_IRQMASK
);
1097 /* Clear indirect completion status */
1098 writel(CQSPI_REG_INDIRECTWR_DONE_MASK
, reg_base
+ CQSPI_REG_INDIRECTWR
);
1100 cqspi_wait_idle(cqspi
);
1105 /* Disable interrupt. */
1106 writel(0, reg_base
+ CQSPI_REG_IRQMASK
);
1108 /* Cancel the indirect write */
1109 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK
,
1110 reg_base
+ CQSPI_REG_INDIRECTWR
);
1114 static void cqspi_chipselect(struct cqspi_flash_pdata
*f_pdata
)
1116 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1117 void __iomem
*reg_base
= cqspi
->iobase
;
1118 unsigned int chip_select
= f_pdata
->cs
;
1121 reg
= readl(reg_base
+ CQSPI_REG_CONFIG
);
1122 if (cqspi
->is_decoded_cs
) {
1123 reg
|= CQSPI_REG_CONFIG_DECODE_MASK
;
1125 reg
&= ~CQSPI_REG_CONFIG_DECODE_MASK
;
1127 /* Convert CS if without decoder.
1133 chip_select
= 0xF & ~(1 << chip_select
);
1136 reg
&= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
1137 << CQSPI_REG_CONFIG_CHIPSELECT_LSB
);
1138 reg
|= (chip_select
& CQSPI_REG_CONFIG_CHIPSELECT_MASK
)
1139 << CQSPI_REG_CONFIG_CHIPSELECT_LSB
;
1140 writel(reg
, reg_base
+ CQSPI_REG_CONFIG
);
1143 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz
,
1144 const unsigned int ns_val
)
1148 ticks
= ref_clk_hz
/ 1000; /* kHz */
1149 ticks
= DIV_ROUND_UP(ticks
* ns_val
, 1000000);
1154 static void cqspi_delay(struct cqspi_flash_pdata
*f_pdata
)
1156 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1157 void __iomem
*iobase
= cqspi
->iobase
;
1158 const unsigned int ref_clk_hz
= cqspi
->master_ref_clk_hz
;
1159 unsigned int tshsl
, tchsh
, tslch
, tsd2d
;
1163 /* calculate the number of ref ticks for one sclk tick */
1164 tsclk
= DIV_ROUND_UP(ref_clk_hz
, cqspi
->sclk
);
1166 tshsl
= calculate_ticks_for_ns(ref_clk_hz
, f_pdata
->tshsl_ns
);
1167 /* this particular value must be at least one sclk */
1171 tchsh
= calculate_ticks_for_ns(ref_clk_hz
, f_pdata
->tchsh_ns
);
1172 tslch
= calculate_ticks_for_ns(ref_clk_hz
, f_pdata
->tslch_ns
);
1173 tsd2d
= calculate_ticks_for_ns(ref_clk_hz
, f_pdata
->tsd2d_ns
);
1175 reg
= (tshsl
& CQSPI_REG_DELAY_TSHSL_MASK
)
1176 << CQSPI_REG_DELAY_TSHSL_LSB
;
1177 reg
|= (tchsh
& CQSPI_REG_DELAY_TCHSH_MASK
)
1178 << CQSPI_REG_DELAY_TCHSH_LSB
;
1179 reg
|= (tslch
& CQSPI_REG_DELAY_TSLCH_MASK
)
1180 << CQSPI_REG_DELAY_TSLCH_LSB
;
1181 reg
|= (tsd2d
& CQSPI_REG_DELAY_TSD2D_MASK
)
1182 << CQSPI_REG_DELAY_TSD2D_LSB
;
1183 writel(reg
, iobase
+ CQSPI_REG_DELAY
);
1186 static void cqspi_config_baudrate_div(struct cqspi_st
*cqspi
)
1188 const unsigned int ref_clk_hz
= cqspi
->master_ref_clk_hz
;
1189 void __iomem
*reg_base
= cqspi
->iobase
;
1192 /* Recalculate the baudrate divisor based on QSPI specification. */
1193 div
= DIV_ROUND_UP(ref_clk_hz
, 2 * cqspi
->sclk
) - 1;
1195 /* Maximum baud divisor */
1196 if (div
> CQSPI_REG_CONFIG_BAUD_MASK
) {
1197 div
= CQSPI_REG_CONFIG_BAUD_MASK
;
1198 dev_warn(&cqspi
->pdev
->dev
,
1199 "Unable to adjust clock <= %d hz. Reduced to %d hz\n",
1200 cqspi
->sclk
, ref_clk_hz
/((div
+1)*2));
1203 reg
= readl(reg_base
+ CQSPI_REG_CONFIG
);
1204 reg
&= ~(CQSPI_REG_CONFIG_BAUD_MASK
<< CQSPI_REG_CONFIG_BAUD_LSB
);
1205 reg
|= (div
& CQSPI_REG_CONFIG_BAUD_MASK
) << CQSPI_REG_CONFIG_BAUD_LSB
;
1206 writel(reg
, reg_base
+ CQSPI_REG_CONFIG
);
1209 static void cqspi_readdata_capture(struct cqspi_st
*cqspi
,
1211 const unsigned int delay
)
1213 void __iomem
*reg_base
= cqspi
->iobase
;
1216 reg
= readl(reg_base
+ CQSPI_REG_READCAPTURE
);
1219 reg
|= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB
);
1221 reg
&= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB
);
1223 reg
&= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
1224 << CQSPI_REG_READCAPTURE_DELAY_LSB
);
1226 reg
|= (delay
& CQSPI_REG_READCAPTURE_DELAY_MASK
)
1227 << CQSPI_REG_READCAPTURE_DELAY_LSB
;
1229 writel(reg
, reg_base
+ CQSPI_REG_READCAPTURE
);
1232 static void cqspi_configure(struct cqspi_flash_pdata
*f_pdata
,
1235 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1236 int switch_cs
= (cqspi
->current_cs
!= f_pdata
->cs
);
1237 int switch_ck
= (cqspi
->sclk
!= sclk
);
1239 if (switch_cs
|| switch_ck
)
1240 cqspi_controller_enable(cqspi
, 0);
1242 /* Switch chip select. */
1244 cqspi
->current_cs
= f_pdata
->cs
;
1245 cqspi_chipselect(f_pdata
);
1248 /* Setup baudrate divisor and delays */
1251 cqspi_config_baudrate_div(cqspi
);
1252 cqspi_delay(f_pdata
);
1253 cqspi_readdata_capture(cqspi
, !cqspi
->rclk_en
,
1254 f_pdata
->read_delay
);
1257 if (switch_cs
|| switch_ck
)
1258 cqspi_controller_enable(cqspi
, 1);
1261 static ssize_t
cqspi_write(struct cqspi_flash_pdata
*f_pdata
,
1262 const struct spi_mem_op
*op
)
1264 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1265 loff_t to
= op
->addr
.val
;
1266 size_t len
= op
->data
.nbytes
;
1267 const u_char
*buf
= op
->data
.buf
.out
;
1270 ret
= cqspi_write_setup(f_pdata
, op
);
1275 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1276 * address (all 0s) with the read status register command in DTR mode.
1277 * But this controller does not support sending dummy address bytes to
1278 * the flash when it is polling the write completion register in DTR
1279 * mode. So, we can not use direct mode when in DTR mode for writing
1282 if (!op
->cmd
.dtr
&& cqspi
->use_direct_mode
&&
1283 cqspi
->use_direct_mode_wr
&& ((to
+ len
) <= cqspi
->ahb_size
)) {
1284 memcpy_toio(cqspi
->ahb_base
+ to
, buf
, len
);
1285 return cqspi_wait_idle(cqspi
);
1288 return cqspi_indirect_write_execute(f_pdata
, to
, buf
, len
);
1291 static void cqspi_rx_dma_callback(void *param
)
1293 struct cqspi_st
*cqspi
= param
;
1295 complete(&cqspi
->rx_dma_complete
);
1298 static int cqspi_direct_read_execute(struct cqspi_flash_pdata
*f_pdata
,
1299 u_char
*buf
, loff_t from
, size_t len
)
1301 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1302 struct device
*dev
= &cqspi
->pdev
->dev
;
1303 enum dma_ctrl_flags flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
;
1304 dma_addr_t dma_src
= (dma_addr_t
)cqspi
->mmap_phys_base
+ from
;
1306 struct dma_async_tx_descriptor
*tx
;
1307 dma_cookie_t cookie
;
1309 struct device
*ddev
;
1311 if (!cqspi
->rx_chan
|| !virt_addr_valid(buf
)) {
1312 memcpy_fromio(buf
, cqspi
->ahb_base
+ from
, len
);
1316 ddev
= cqspi
->rx_chan
->device
->dev
;
1317 dma_dst
= dma_map_single(ddev
, buf
, len
, DMA_FROM_DEVICE
);
1318 if (dma_mapping_error(ddev
, dma_dst
)) {
1319 dev_err(dev
, "dma mapping failed\n");
1322 tx
= dmaengine_prep_dma_memcpy(cqspi
->rx_chan
, dma_dst
, dma_src
,
1325 dev_err(dev
, "device_prep_dma_memcpy error\n");
1330 tx
->callback
= cqspi_rx_dma_callback
;
1331 tx
->callback_param
= cqspi
;
1332 cookie
= tx
->tx_submit(tx
);
1333 reinit_completion(&cqspi
->rx_dma_complete
);
1335 ret
= dma_submit_error(cookie
);
1337 dev_err(dev
, "dma_submit_error %d\n", cookie
);
1342 dma_async_issue_pending(cqspi
->rx_chan
);
1343 if (!wait_for_completion_timeout(&cqspi
->rx_dma_complete
,
1344 msecs_to_jiffies(max_t(size_t, len
, 500)))) {
1345 dmaengine_terminate_sync(cqspi
->rx_chan
);
1346 dev_err(dev
, "DMA wait_for_completion_timeout\n");
1352 dma_unmap_single(ddev
, dma_dst
, len
, DMA_FROM_DEVICE
);
1357 static ssize_t
cqspi_read(struct cqspi_flash_pdata
*f_pdata
,
1358 const struct spi_mem_op
*op
)
1360 struct cqspi_st
*cqspi
= f_pdata
->cqspi
;
1361 struct device
*dev
= &cqspi
->pdev
->dev
;
1362 const struct cqspi_driver_platdata
*ddata
;
1363 loff_t from
= op
->addr
.val
;
1364 size_t len
= op
->data
.nbytes
;
1365 u_char
*buf
= op
->data
.buf
.in
;
1366 u64 dma_align
= (u64
)(uintptr_t)buf
;
1369 ddata
= of_device_get_match_data(dev
);
1371 ret
= cqspi_read_setup(f_pdata
, op
);
1375 if (cqspi
->use_direct_mode
&& ((from
+ len
) <= cqspi
->ahb_size
))
1376 return cqspi_direct_read_execute(f_pdata
, buf
, from
, len
);
1378 if (cqspi
->use_dma_read
&& ddata
&& ddata
->indirect_read_dma
&&
1379 virt_addr_valid(buf
) && ((dma_align
& CQSPI_DMA_UNALIGN
) == 0))
1380 return ddata
->indirect_read_dma(f_pdata
, buf
, from
, len
);
1382 return cqspi_indirect_read_execute(f_pdata
, buf
, from
, len
);
1385 static int cqspi_mem_process(struct spi_mem
*mem
, const struct spi_mem_op
*op
)
1387 struct cqspi_st
*cqspi
= spi_controller_get_devdata(mem
->spi
->controller
);
1388 struct cqspi_flash_pdata
*f_pdata
;
1390 f_pdata
= &cqspi
->f_pdata
[spi_get_chipselect(mem
->spi
, 0)];
1391 cqspi_configure(f_pdata
, mem
->spi
->max_speed_hz
);
1393 if (op
->data
.dir
== SPI_MEM_DATA_IN
&& op
->data
.buf
.in
) {
1395 * Performing reads in DAC mode forces to read minimum 4 bytes
1396 * which is unsupported on some flash devices during register
1397 * reads, prefer STIG mode for such small reads.
1399 if (!op
->addr
.nbytes
||
1400 op
->data
.nbytes
<= CQSPI_STIG_DATA_LEN_MAX
)
1401 return cqspi_command_read(f_pdata
, op
);
1403 return cqspi_read(f_pdata
, op
);
1406 if (!op
->addr
.nbytes
|| !op
->data
.buf
.out
)
1407 return cqspi_command_write(f_pdata
, op
);
1409 return cqspi_write(f_pdata
, op
);
1412 static int cqspi_exec_mem_op(struct spi_mem
*mem
, const struct spi_mem_op
*op
)
1415 struct cqspi_st
*cqspi
= spi_controller_get_devdata(mem
->spi
->controller
);
1416 struct device
*dev
= &cqspi
->pdev
->dev
;
1418 ret
= pm_runtime_resume_and_get(dev
);
1420 dev_err(&mem
->spi
->dev
, "resume failed with %d\n", ret
);
1424 ret
= cqspi_mem_process(mem
, op
);
1426 pm_runtime_mark_last_busy(dev
);
1427 pm_runtime_put_autosuspend(dev
);
1430 dev_err(&mem
->spi
->dev
, "operation failed with %d\n", ret
);
1435 static bool cqspi_supports_mem_op(struct spi_mem
*mem
,
1436 const struct spi_mem_op
*op
)
1438 bool all_true
, all_false
;
1441 * op->dummy.dtr is required for converting nbytes into ncycles.
1442 * Also, don't check the dtr field of the op phase having zero nbytes.
1444 all_true
= op
->cmd
.dtr
&&
1445 (!op
->addr
.nbytes
|| op
->addr
.dtr
) &&
1446 (!op
->dummy
.nbytes
|| op
->dummy
.dtr
) &&
1447 (!op
->data
.nbytes
|| op
->data
.dtr
);
1449 all_false
= !op
->cmd
.dtr
&& !op
->addr
.dtr
&& !op
->dummy
.dtr
&&
1453 /* Right now we only support 8-8-8 DTR mode. */
1454 if (op
->cmd
.nbytes
&& op
->cmd
.buswidth
!= 8)
1456 if (op
->addr
.nbytes
&& op
->addr
.buswidth
!= 8)
1458 if (op
->data
.nbytes
&& op
->data
.buswidth
!= 8)
1460 } else if (!all_false
) {
1461 /* Mixed DTR modes are not supported. */
1465 return spi_mem_default_supports_op(mem
, op
);
1468 static int cqspi_of_get_flash_pdata(struct platform_device
*pdev
,
1469 struct cqspi_flash_pdata
*f_pdata
,
1470 struct device_node
*np
)
1472 if (of_property_read_u32(np
, "cdns,read-delay", &f_pdata
->read_delay
)) {
1473 dev_err(&pdev
->dev
, "couldn't determine read-delay\n");
1477 if (of_property_read_u32(np
, "cdns,tshsl-ns", &f_pdata
->tshsl_ns
)) {
1478 dev_err(&pdev
->dev
, "couldn't determine tshsl-ns\n");
1482 if (of_property_read_u32(np
, "cdns,tsd2d-ns", &f_pdata
->tsd2d_ns
)) {
1483 dev_err(&pdev
->dev
, "couldn't determine tsd2d-ns\n");
1487 if (of_property_read_u32(np
, "cdns,tchsh-ns", &f_pdata
->tchsh_ns
)) {
1488 dev_err(&pdev
->dev
, "couldn't determine tchsh-ns\n");
1492 if (of_property_read_u32(np
, "cdns,tslch-ns", &f_pdata
->tslch_ns
)) {
1493 dev_err(&pdev
->dev
, "couldn't determine tslch-ns\n");
1497 if (of_property_read_u32(np
, "spi-max-frequency", &f_pdata
->clk_rate
)) {
1498 dev_err(&pdev
->dev
, "couldn't determine spi-max-frequency\n");
1505 static int cqspi_of_get_pdata(struct cqspi_st
*cqspi
)
1507 struct device
*dev
= &cqspi
->pdev
->dev
;
1508 struct device_node
*np
= dev
->of_node
;
1511 cqspi
->is_decoded_cs
= of_property_read_bool(np
, "cdns,is-decoded-cs");
1513 if (of_property_read_u32(np
, "cdns,fifo-depth", &cqspi
->fifo_depth
)) {
1514 dev_err(dev
, "couldn't determine fifo-depth\n");
1518 if (of_property_read_u32(np
, "cdns,fifo-width", &cqspi
->fifo_width
)) {
1519 dev_err(dev
, "couldn't determine fifo-width\n");
1523 if (of_property_read_u32(np
, "cdns,trigger-address",
1524 &cqspi
->trigger_address
)) {
1525 dev_err(dev
, "couldn't determine trigger-address\n");
1529 if (of_property_read_u32(np
, "num-cs", &cqspi
->num_chipselect
))
1530 cqspi
->num_chipselect
= CQSPI_MAX_CHIPSELECT
;
1532 cqspi
->rclk_en
= of_property_read_bool(np
, "cdns,rclk-en");
1534 if (!of_property_read_u32_array(np
, "power-domains", id
,
1536 cqspi
->pd_dev_id
= id
[1];
1541 static void cqspi_controller_init(struct cqspi_st
*cqspi
)
1545 cqspi_controller_enable(cqspi
, 0);
1547 /* Configure the remap address register, no remap */
1548 writel(0, cqspi
->iobase
+ CQSPI_REG_REMAP
);
1550 /* Disable all interrupts. */
1551 writel(0, cqspi
->iobase
+ CQSPI_REG_IRQMASK
);
1553 /* Configure the SRAM split to 1:1 . */
1554 writel(cqspi
->fifo_depth
/ 2, cqspi
->iobase
+ CQSPI_REG_SRAMPARTITION
);
1556 /* Load indirect trigger address. */
1557 writel(cqspi
->trigger_address
,
1558 cqspi
->iobase
+ CQSPI_REG_INDIRECTTRIGGER
);
1560 /* Program read watermark -- 1/2 of the FIFO. */
1561 writel(cqspi
->fifo_depth
* cqspi
->fifo_width
/ 2,
1562 cqspi
->iobase
+ CQSPI_REG_INDIRECTRDWATERMARK
);
1563 /* Program write watermark -- 1/8 of the FIFO. */
1564 writel(cqspi
->fifo_depth
* cqspi
->fifo_width
/ 8,
1565 cqspi
->iobase
+ CQSPI_REG_INDIRECTWRWATERMARK
);
1567 /* Disable direct access controller */
1568 if (!cqspi
->use_direct_mode
) {
1569 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
1570 reg
&= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL
;
1571 writel(reg
, cqspi
->iobase
+ CQSPI_REG_CONFIG
);
1574 /* Enable DMA interface */
1575 if (cqspi
->use_dma_read
) {
1576 reg
= readl(cqspi
->iobase
+ CQSPI_REG_CONFIG
);
1577 reg
|= CQSPI_REG_CONFIG_DMA_MASK
;
1578 writel(reg
, cqspi
->iobase
+ CQSPI_REG_CONFIG
);
1581 cqspi_controller_enable(cqspi
, 1);
1584 static int cqspi_request_mmap_dma(struct cqspi_st
*cqspi
)
1586 dma_cap_mask_t mask
;
1589 dma_cap_set(DMA_MEMCPY
, mask
);
1591 cqspi
->rx_chan
= dma_request_chan_by_mask(&mask
);
1592 if (IS_ERR(cqspi
->rx_chan
)) {
1593 int ret
= PTR_ERR(cqspi
->rx_chan
);
1595 cqspi
->rx_chan
= NULL
;
1596 return dev_err_probe(&cqspi
->pdev
->dev
, ret
, "No Rx DMA available\n");
1598 init_completion(&cqspi
->rx_dma_complete
);
1603 static const char *cqspi_get_name(struct spi_mem
*mem
)
1605 struct cqspi_st
*cqspi
= spi_controller_get_devdata(mem
->spi
->controller
);
1606 struct device
*dev
= &cqspi
->pdev
->dev
;
1608 return devm_kasprintf(dev
, GFP_KERNEL
, "%s.%d", dev_name(dev
),
1609 spi_get_chipselect(mem
->spi
, 0));
1612 static const struct spi_controller_mem_ops cqspi_mem_ops
= {
1613 .exec_op
= cqspi_exec_mem_op
,
1614 .get_name
= cqspi_get_name
,
1615 .supports_op
= cqspi_supports_mem_op
,
1618 static const struct spi_controller_mem_caps cqspi_mem_caps
= {
1622 static int cqspi_setup_flash(struct cqspi_st
*cqspi
)
1624 unsigned int max_cs
= cqspi
->num_chipselect
- 1;
1625 struct platform_device
*pdev
= cqspi
->pdev
;
1626 struct device
*dev
= &pdev
->dev
;
1627 struct device_node
*np
= dev
->of_node
;
1628 struct cqspi_flash_pdata
*f_pdata
;
1632 /* Get flash device data */
1633 for_each_available_child_of_node(dev
->of_node
, np
) {
1634 ret
= of_property_read_u32(np
, "reg", &cs
);
1636 dev_err(dev
, "Couldn't determine chip select.\n");
1641 if (cs
>= cqspi
->num_chipselect
) {
1642 dev_err(dev
, "Chip select %d out of range.\n", cs
);
1645 } else if (cs
< max_cs
) {
1649 f_pdata
= &cqspi
->f_pdata
[cs
];
1650 f_pdata
->cqspi
= cqspi
;
1653 ret
= cqspi_of_get_flash_pdata(pdev
, f_pdata
, np
);
1660 cqspi
->num_chipselect
= max_cs
+ 1;
1664 static int cqspi_jh7110_clk_init(struct platform_device
*pdev
, struct cqspi_st
*cqspi
)
1666 static struct clk_bulk_data qspiclk
[] = {
1673 ret
= devm_clk_bulk_get(&pdev
->dev
, ARRAY_SIZE(qspiclk
), qspiclk
);
1675 dev_err(&pdev
->dev
, "%s: failed to get qspi clocks\n", __func__
);
1679 cqspi
->clks
[CLK_QSPI_APB
] = qspiclk
[0].clk
;
1680 cqspi
->clks
[CLK_QSPI_AHB
] = qspiclk
[1].clk
;
1682 ret
= clk_prepare_enable(cqspi
->clks
[CLK_QSPI_APB
]);
1684 dev_err(&pdev
->dev
, "%s: failed to enable CLK_QSPI_APB\n", __func__
);
1688 ret
= clk_prepare_enable(cqspi
->clks
[CLK_QSPI_AHB
]);
1690 dev_err(&pdev
->dev
, "%s: failed to enable CLK_QSPI_AHB\n", __func__
);
1691 goto disable_apb_clk
;
1694 cqspi
->is_jh7110
= true;
1699 clk_disable_unprepare(cqspi
->clks
[CLK_QSPI_APB
]);
1704 static void cqspi_jh7110_disable_clk(struct platform_device
*pdev
, struct cqspi_st
*cqspi
)
1706 clk_disable_unprepare(cqspi
->clks
[CLK_QSPI_AHB
]);
1707 clk_disable_unprepare(cqspi
->clks
[CLK_QSPI_APB
]);
1709 static int cqspi_probe(struct platform_device
*pdev
)
1711 const struct cqspi_driver_platdata
*ddata
;
1712 struct reset_control
*rstc
, *rstc_ocp
, *rstc_ref
;
1713 struct device
*dev
= &pdev
->dev
;
1714 struct spi_controller
*host
;
1715 struct resource
*res_ahb
;
1716 struct cqspi_st
*cqspi
;
1720 host
= devm_spi_alloc_host(&pdev
->dev
, sizeof(*cqspi
));
1724 host
->mode_bits
= SPI_RX_QUAD
| SPI_RX_DUAL
;
1725 host
->mem_ops
= &cqspi_mem_ops
;
1726 host
->mem_caps
= &cqspi_mem_caps
;
1727 host
->dev
.of_node
= pdev
->dev
.of_node
;
1729 cqspi
= spi_controller_get_devdata(host
);
1733 cqspi
->is_jh7110
= false;
1734 platform_set_drvdata(pdev
, cqspi
);
1736 /* Obtain configuration from OF. */
1737 ret
= cqspi_of_get_pdata(cqspi
);
1739 dev_err(dev
, "Cannot get mandatory OF data.\n");
1743 /* Obtain QSPI clock. */
1744 cqspi
->clk
= devm_clk_get(dev
, NULL
);
1745 if (IS_ERR(cqspi
->clk
)) {
1746 dev_err(dev
, "Cannot claim QSPI clock.\n");
1747 ret
= PTR_ERR(cqspi
->clk
);
1751 /* Obtain and remap controller address. */
1752 cqspi
->iobase
= devm_platform_ioremap_resource(pdev
, 0);
1753 if (IS_ERR(cqspi
->iobase
)) {
1754 dev_err(dev
, "Cannot remap controller address.\n");
1755 ret
= PTR_ERR(cqspi
->iobase
);
1759 /* Obtain and remap AHB address. */
1760 cqspi
->ahb_base
= devm_platform_get_and_ioremap_resource(pdev
, 1, &res_ahb
);
1761 if (IS_ERR(cqspi
->ahb_base
)) {
1762 dev_err(dev
, "Cannot remap AHB address.\n");
1763 ret
= PTR_ERR(cqspi
->ahb_base
);
1766 cqspi
->mmap_phys_base
= (dma_addr_t
)res_ahb
->start
;
1767 cqspi
->ahb_size
= resource_size(res_ahb
);
1769 init_completion(&cqspi
->transfer_complete
);
1771 /* Obtain IRQ line. */
1772 irq
= platform_get_irq(pdev
, 0);
1776 ret
= pm_runtime_set_active(dev
);
1781 ret
= clk_prepare_enable(cqspi
->clk
);
1783 dev_err(dev
, "Cannot enable QSPI clock.\n");
1784 goto probe_clk_failed
;
1787 /* Obtain QSPI reset control */
1788 rstc
= devm_reset_control_get_optional_exclusive(dev
, "qspi");
1790 ret
= PTR_ERR(rstc
);
1791 dev_err(dev
, "Cannot get QSPI reset.\n");
1792 goto probe_reset_failed
;
1795 rstc_ocp
= devm_reset_control_get_optional_exclusive(dev
, "qspi-ocp");
1796 if (IS_ERR(rstc_ocp
)) {
1797 ret
= PTR_ERR(rstc_ocp
);
1798 dev_err(dev
, "Cannot get QSPI OCP reset.\n");
1799 goto probe_reset_failed
;
1802 if (of_device_is_compatible(pdev
->dev
.of_node
, "starfive,jh7110-qspi")) {
1803 rstc_ref
= devm_reset_control_get_optional_exclusive(dev
, "rstc_ref");
1804 if (IS_ERR(rstc_ref
)) {
1805 ret
= PTR_ERR(rstc_ref
);
1806 dev_err(dev
, "Cannot get QSPI REF reset.\n");
1807 goto probe_reset_failed
;
1809 reset_control_assert(rstc_ref
);
1810 reset_control_deassert(rstc_ref
);
1813 reset_control_assert(rstc
);
1814 reset_control_deassert(rstc
);
1816 reset_control_assert(rstc_ocp
);
1817 reset_control_deassert(rstc_ocp
);
1819 cqspi
->master_ref_clk_hz
= clk_get_rate(cqspi
->clk
);
1820 host
->max_speed_hz
= cqspi
->master_ref_clk_hz
;
1822 /* write completion is supported by default */
1823 cqspi
->wr_completion
= true;
1825 ddata
= of_device_get_match_data(dev
);
1827 if (ddata
->quirks
& CQSPI_NEEDS_WR_DELAY
)
1828 cqspi
->wr_delay
= 50 * DIV_ROUND_UP(NSEC_PER_SEC
,
1829 cqspi
->master_ref_clk_hz
);
1830 if (ddata
->hwcaps_mask
& CQSPI_SUPPORTS_OCTAL
)
1831 host
->mode_bits
|= SPI_RX_OCTAL
| SPI_TX_OCTAL
;
1832 if (!(ddata
->quirks
& CQSPI_DISABLE_DAC_MODE
)) {
1833 cqspi
->use_direct_mode
= true;
1834 cqspi
->use_direct_mode_wr
= true;
1836 if (ddata
->quirks
& CQSPI_SUPPORT_EXTERNAL_DMA
)
1837 cqspi
->use_dma_read
= true;
1838 if (ddata
->quirks
& CQSPI_NO_SUPPORT_WR_COMPLETION
)
1839 cqspi
->wr_completion
= false;
1840 if (ddata
->quirks
& CQSPI_SLOW_SRAM
)
1841 cqspi
->slow_sram
= true;
1842 if (ddata
->quirks
& CQSPI_NEEDS_APB_AHB_HAZARD_WAR
)
1843 cqspi
->apb_ahb_hazard
= true;
1845 if (ddata
->jh7110_clk_init
) {
1846 ret
= cqspi_jh7110_clk_init(pdev
, cqspi
);
1848 goto probe_reset_failed
;
1851 if (of_device_is_compatible(pdev
->dev
.of_node
,
1852 "xlnx,versal-ospi-1.0")) {
1853 ret
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1855 goto probe_reset_failed
;
1859 ret
= devm_request_irq(dev
, irq
, cqspi_irq_handler
, 0,
1862 dev_err(dev
, "Cannot request IRQ.\n");
1863 goto probe_reset_failed
;
1866 cqspi_wait_idle(cqspi
);
1867 cqspi_controller_init(cqspi
);
1868 cqspi
->current_cs
= -1;
1871 ret
= cqspi_setup_flash(cqspi
);
1873 dev_err(dev
, "failed to setup flash parameters %d\n", ret
);
1874 goto probe_setup_failed
;
1877 host
->num_chipselect
= cqspi
->num_chipselect
;
1879 if (cqspi
->use_direct_mode
) {
1880 ret
= cqspi_request_mmap_dma(cqspi
);
1881 if (ret
== -EPROBE_DEFER
)
1882 goto probe_setup_failed
;
1885 ret
= devm_pm_runtime_enable(dev
);
1888 dma_release_channel(cqspi
->rx_chan
);
1889 goto probe_setup_failed
;
1892 pm_runtime_set_autosuspend_delay(dev
, CQSPI_AUTOSUSPEND_TIMEOUT
);
1893 pm_runtime_use_autosuspend(dev
);
1894 pm_runtime_get_noresume(dev
);
1896 ret
= spi_register_controller(host
);
1898 dev_err(&pdev
->dev
, "failed to register SPI ctlr %d\n", ret
);
1899 goto probe_setup_failed
;
1902 pm_runtime_mark_last_busy(dev
);
1903 pm_runtime_put_autosuspend(dev
);
1907 cqspi_controller_enable(cqspi
, 0);
1909 if (cqspi
->is_jh7110
)
1910 cqspi_jh7110_disable_clk(pdev
, cqspi
);
1911 clk_disable_unprepare(cqspi
->clk
);
1916 static void cqspi_remove(struct platform_device
*pdev
)
1918 struct cqspi_st
*cqspi
= platform_get_drvdata(pdev
);
1920 spi_unregister_controller(cqspi
->host
);
1921 cqspi_controller_enable(cqspi
, 0);
1924 dma_release_channel(cqspi
->rx_chan
);
1926 clk_disable_unprepare(cqspi
->clk
);
1928 if (cqspi
->is_jh7110
)
1929 cqspi_jh7110_disable_clk(pdev
, cqspi
);
1931 pm_runtime_put_sync(&pdev
->dev
);
1932 pm_runtime_disable(&pdev
->dev
);
1935 static int cqspi_runtime_suspend(struct device
*dev
)
1937 struct cqspi_st
*cqspi
= dev_get_drvdata(dev
);
1939 cqspi_controller_enable(cqspi
, 0);
1940 clk_disable_unprepare(cqspi
->clk
);
1944 static int cqspi_runtime_resume(struct device
*dev
)
1946 struct cqspi_st
*cqspi
= dev_get_drvdata(dev
);
1948 clk_prepare_enable(cqspi
->clk
);
1949 cqspi_wait_idle(cqspi
);
1950 cqspi_controller_init(cqspi
);
1952 cqspi
->current_cs
= -1;
1957 static int cqspi_suspend(struct device
*dev
)
1959 struct cqspi_st
*cqspi
= dev_get_drvdata(dev
);
1961 return spi_controller_suspend(cqspi
->host
);
1964 static int cqspi_resume(struct device
*dev
)
1966 struct cqspi_st
*cqspi
= dev_get_drvdata(dev
);
1968 return spi_controller_resume(cqspi
->host
);
1971 static const struct dev_pm_ops cqspi_dev_pm_ops
= {
1972 RUNTIME_PM_OPS(cqspi_runtime_suspend
, cqspi_runtime_resume
, NULL
)
1973 SYSTEM_SLEEP_PM_OPS(cqspi_suspend
, cqspi_resume
)
1976 static const struct cqspi_driver_platdata cdns_qspi
= {
1977 .quirks
= CQSPI_DISABLE_DAC_MODE
,
1980 static const struct cqspi_driver_platdata k2g_qspi
= {
1981 .quirks
= CQSPI_NEEDS_WR_DELAY
,
1984 static const struct cqspi_driver_platdata am654_ospi
= {
1985 .hwcaps_mask
= CQSPI_SUPPORTS_OCTAL
,
1986 .quirks
= CQSPI_NEEDS_WR_DELAY
,
1989 static const struct cqspi_driver_platdata intel_lgm_qspi
= {
1990 .quirks
= CQSPI_DISABLE_DAC_MODE
,
1993 static const struct cqspi_driver_platdata socfpga_qspi
= {
1994 .quirks
= CQSPI_DISABLE_DAC_MODE
1995 | CQSPI_NO_SUPPORT_WR_COMPLETION
1999 static const struct cqspi_driver_platdata versal_ospi
= {
2000 .hwcaps_mask
= CQSPI_SUPPORTS_OCTAL
,
2001 .quirks
= CQSPI_DISABLE_DAC_MODE
| CQSPI_SUPPORT_EXTERNAL_DMA
,
2002 .indirect_read_dma
= cqspi_versal_indirect_read_dma
,
2003 .get_dma_status
= cqspi_get_versal_dma_status
,
2006 static const struct cqspi_driver_platdata jh7110_qspi
= {
2007 .quirks
= CQSPI_DISABLE_DAC_MODE
,
2008 .jh7110_clk_init
= cqspi_jh7110_clk_init
,
2011 static const struct cqspi_driver_platdata pensando_cdns_qspi
= {
2012 .quirks
= CQSPI_NEEDS_APB_AHB_HAZARD_WAR
| CQSPI_DISABLE_DAC_MODE
,
2015 static const struct of_device_id cqspi_dt_ids
[] = {
2017 .compatible
= "cdns,qspi-nor",
2021 .compatible
= "ti,k2g-qspi",
2025 .compatible
= "ti,am654-ospi",
2026 .data
= &am654_ospi
,
2029 .compatible
= "intel,lgm-qspi",
2030 .data
= &intel_lgm_qspi
,
2033 .compatible
= "xlnx,versal-ospi-1.0",
2034 .data
= &versal_ospi
,
2037 .compatible
= "intel,socfpga-qspi",
2038 .data
= &socfpga_qspi
,
2041 .compatible
= "starfive,jh7110-qspi",
2042 .data
= &jh7110_qspi
,
2045 .compatible
= "amd,pensando-elba-qspi",
2046 .data
= &pensando_cdns_qspi
,
2048 { /* end of table */ }
2051 MODULE_DEVICE_TABLE(of
, cqspi_dt_ids
);
2053 static struct platform_driver cqspi_platform_driver
= {
2054 .probe
= cqspi_probe
,
2055 .remove_new
= cqspi_remove
,
2058 .pm
= pm_ptr(&cqspi_dev_pm_ops
),
2059 .of_match_table
= cqspi_dt_ids
,
2063 module_platform_driver(cqspi_platform_driver
);
2065 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
2066 MODULE_LICENSE("GPL v2");
2067 MODULE_ALIAS("platform:" CQSPI_NAME
);
2068 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
2069 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");
2070 MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
2071 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
2072 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");