drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include "spi-dw.h"
  25
  26 #ifdef CONFIG_DEBUG_FS
  27 #include <linux/debugfs.h>
  28 #endif
  29
  30 /* Slave spi_dev related */
  31 struct chip_data {
  32         u8 tmode;               /* TR/TO/RO/EEPROM */
  33         u8 type;                /* SPI/SSP/MicroWire */
  34
  35         u8 poll_mode;           /* 1 means use poll mode */
  36
  37         u16 clk_div;            /* baud rate divider */
  38         u32 speed_hz;           /* baud rate */
  39         void (*cs_control)(u32 command);
  40 };
  41
  42 #ifdef CONFIG_DEBUG_FS
  43 #define SPI_REGS_BUFSIZE        1024
  44 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  45                 size_t count, loff_t *ppos)
  46 {
  47         struct dw_spi *dws = file->private_data;
  48         char *buf;
  49         u32 len = 0;
  50         ssize_t ret;
  51
  52         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  53         if (!buf)
  54                 return 0;
  55
  56         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  57                         "%s registers:\n", dev_name(&dws->master->dev));
  58         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  59                         "=================================\n");
  60         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  61                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  62         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  63                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  64         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  65                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  66         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  67                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  68         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  69                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  70         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  71                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  72         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  73                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  74         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  75                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  76         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  77                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  78         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  79                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  80         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  81                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  82         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  83                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  84         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  85                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
  86         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
  88         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
  90         len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "=================================\n");
  92
  93         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
  94         kfree(buf);
  95         return ret;
  96 }
  97
  98 static const struct file_operations dw_spi_regs_ops = {
  99         .owner          = THIS_MODULE,
 100         .open           = simple_open,
 101         .read           = dw_spi_show_regs,
 102         .llseek         = default_llseek,
 103 };
 104
 105 static int dw_spi_debugfs_init(struct dw_spi *dws)
 106 {
 107         char name[32];
 108
 109         snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
 110         dws->debugfs = debugfs_create_dir(name, NULL);
 111         if (!dws->debugfs)
 112                 return -ENOMEM;
 113
 114         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 115                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 116         return 0;
 117 }
 118
 119 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 120 {
 121         debugfs_remove_recursive(dws->debugfs);
 122 }
 123
 124 #else
 125 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 126 {
 127         return 0;
 128 }
 129
 130 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 131 {
 132 }
 133 #endif /* CONFIG_DEBUG_FS */
 134
 135 void dw_spi_set_cs(struct spi_device *spi, bool enable)
 136 {
 137         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
 138         struct chip_data *chip = spi_get_ctldata(spi);
 139
 140         if (chip && chip->cs_control)
 141                 chip->cs_control(enable);
 142
 143         if (enable)
 144                 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
 145         else if (dws->cs_override)
 146                 dw_writel(dws, DW_SPI_SER, 0);
 147 }
 148 EXPORT_SYMBOL_GPL(dw_spi_set_cs);
 149
 150 /* Return the max entries we can fill into tx fifo */
 151 static inline u32 tx_max(struct dw_spi *dws)
 152 {
 153         u32 tx_left, tx_room, rxtx_gap;
 154
 155         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 156         tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
 157
 158         /*
 159          * Another concern is about the tx/rx mismatch, we
 160          * though to use (dws->fifo_len - rxflr - txflr) as
 161          * one maximum value for tx, but it doesn't cover the
 162          * data which is out of tx/rx fifo and inside the
 163          * shift registers. So a control from sw point of
 164          * view is taken.
 165          */
 166         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 167                         / dws->n_bytes;
 168
 169         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 170 }
 171
 172 /* Return the max entries we should read out of rx fifo */
 173 static inline u32 rx_max(struct dw_spi *dws)
 174 {
 175         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 176
 177         return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
 178 }
 179
 180 static void dw_writer(struct dw_spi *dws)
 181 {
 182         u32 max = tx_max(dws);
 183         u16 txw = 0;
 184
 185         while (max--) {
 186                 /* Set the tx word if the transfer's original "tx" is not null */
 187                 if (dws->tx_end - dws->len) {
 188                         if (dws->n_bytes == 1)
 189                                 txw = *(u8 *)(dws->tx);
 190                         else
 191                                 txw = *(u16 *)(dws->tx);
 192                 }
 193                 dw_write_io_reg(dws, DW_SPI_DR, txw);
 194                 dws->tx += dws->n_bytes;
 195         }
 196 }
 197
 198 static void dw_reader(struct dw_spi *dws)
 199 {
 200         u32 max = rx_max(dws);
 201         u16 rxw;
 202
 203         while (max--) {
 204                 rxw = dw_read_io_reg(dws, DW_SPI_DR);
 205                 /* Care rx only if the transfer's original "rx" is not null */
 206                 if (dws->rx_end - dws->len) {
 207                         if (dws->n_bytes == 1)
 208                                 *(u8 *)(dws->rx) = rxw;
 209                         else
 210                                 *(u16 *)(dws->rx) = rxw;
 211                 }
 212                 dws->rx += dws->n_bytes;
 213         }
 214 }
 215
 216 static void int_error_stop(struct dw_spi *dws, const char *msg)
 217 {
 218         spi_reset_chip(dws);
 219
 220         dev_err(&dws->master->dev, "%s\n", msg);
 221         dws->master->cur_msg->status = -EIO;
 222         spi_finalize_current_transfer(dws->master);
 223 }
 224
 225 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 226 {
 227         u16 irq_status = dw_readl(dws, DW_SPI_ISR);
 228
 229         /* Error handling */
 230         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 231                 dw_readl(dws, DW_SPI_ICR);
 232                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 233                 return IRQ_HANDLED;
 234         }
 235
 236         dw_reader(dws);
 237         if (dws->rx_end == dws->rx) {
 238                 spi_mask_intr(dws, SPI_INT_TXEI);
 239                 spi_finalize_current_transfer(dws->master);
 240                 return IRQ_HANDLED;
 241         }
 242         if (irq_status & SPI_INT_TXEI) {
 243                 spi_mask_intr(dws, SPI_INT_TXEI);
 244                 dw_writer(dws);
 245                 /* Enable TX irq always, it will be disabled when RX finished */
 246                 spi_umask_intr(dws, SPI_INT_TXEI);
 247         }
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 253 {
 254         struct spi_controller *master = dev_id;
 255         struct dw_spi *dws = spi_controller_get_devdata(master);
 256         u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
 257
 258         if (!irq_status)
 259                 return IRQ_NONE;
 260
 261         if (!master->cur_msg) {
 262                 spi_mask_intr(dws, SPI_INT_TXEI);
 263                 return IRQ_HANDLED;
 264         }
 265
 266         return dws->transfer_handler(dws);
 267 }
 268
 269 /* Must be called inside pump_transfers() */
 270 static int poll_transfer(struct dw_spi *dws)
 271 {
 272         do {
 273                 dw_writer(dws);
 274                 dw_reader(dws);
 275                 cpu_relax();
 276         } while (dws->rx_end > dws->rx);
 277
 278         return 0;
 279 }
 280
 281 static int dw_spi_transfer_one(struct spi_controller *master,
 282                 struct spi_device *spi, struct spi_transfer *transfer)
 283 {
 284         struct dw_spi *dws = spi_controller_get_devdata(master);
 285         struct chip_data *chip = spi_get_ctldata(spi);
 286         u8 imask = 0;
 287         u16 txlevel = 0;
 288         u32 cr0;
 289         int ret;
 290
 291         dws->dma_mapped = 0;
 292
 293         dws->tx = (void *)transfer->tx_buf;
 294         dws->tx_end = dws->tx + transfer->len;
 295         dws->rx = transfer->rx_buf;
 296         dws->rx_end = dws->rx + transfer->len;
 297         dws->len = transfer->len;
 298
 299         spi_enable_chip(dws, 0);
 300
 301         /* Handle per transfer options for bpw and speed */
 302         if (transfer->speed_hz != dws->current_freq) {
 303                 if (transfer->speed_hz != chip->speed_hz) {
 304                         /* clk_div doesn't support odd number */
 305                         chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
 306                         chip->speed_hz = transfer->speed_hz;
 307                 }
 308                 dws->current_freq = transfer->speed_hz;
 309                 spi_set_clk(dws, chip->clk_div);
 310         }
 311
 312         dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 313         dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
 314
 315         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 316         cr0 = (transfer->bits_per_word - 1)
 317                 | (chip->type << SPI_FRF_OFFSET)
 318                 | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
 319                         (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET))
 320                 | (chip->tmode << SPI_TMOD_OFFSET);
 321
 322         /*
 323          * Adjust transfer mode if necessary. Requires platform dependent
 324          * chipselect mechanism.
 325          */
 326         if (chip->cs_control) {
 327                 if (dws->rx && dws->tx)
 328                         chip->tmode = SPI_TMOD_TR;
 329                 else if (dws->rx)
 330                         chip->tmode = SPI_TMOD_RO;
 331                 else
 332                         chip->tmode = SPI_TMOD_TO;
 333
 334                 cr0 &= ~SPI_TMOD_MASK;
 335                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 336         }
 337
 338         dw_writel(dws, DW_SPI_CTRL0, cr0);
 339
 340         /* Check if current transfer is a DMA transaction */
 341         if (master->can_dma && master->can_dma(master, spi, transfer))
 342                 dws->dma_mapped = master->cur_msg_mapped;
 343
 344         /* For poll mode just disable all interrupts */
 345         spi_mask_intr(dws, 0xff);
 346
 347         /*
 348          * Interrupt mode
 349          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 350          */
 351         if (dws->dma_mapped) {
 352                 ret = dws->dma_ops->dma_setup(dws, transfer);
 353                 if (ret < 0) {
 354                         spi_enable_chip(dws, 1);
 355                         return ret;
 356                 }
 357         } else if (!chip->poll_mode) {
 358                 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
 359                 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
 360
 361                 /* Set the interrupt mask */
 362                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 363                          SPI_INT_RXUI | SPI_INT_RXOI;
 364                 spi_umask_intr(dws, imask);
 365
 366                 dws->transfer_handler = interrupt_transfer;
 367         }
 368
 369         spi_enable_chip(dws, 1);
 370
 371         if (dws->dma_mapped) {
 372                 ret = dws->dma_ops->dma_transfer(dws, transfer);
 373                 if (ret < 0)
 374                         return ret;
 375         }
 376
 377         if (chip->poll_mode)
 378                 return poll_transfer(dws);
 379
 380         return 1;
 381 }
 382
 383 static void dw_spi_handle_err(struct spi_controller *master,
 384                 struct spi_message *msg)
 385 {
 386         struct dw_spi *dws = spi_controller_get_devdata(master);
 387
 388         if (dws->dma_mapped)
 389                 dws->dma_ops->dma_stop(dws);
 390
 391         spi_reset_chip(dws);
 392 }
 393
 394 /* This may be called twice for each spi dev */
 395 static int dw_spi_setup(struct spi_device *spi)
 396 {
 397         struct dw_spi_chip *chip_info = NULL;
 398         struct chip_data *chip;
 399
 400         /* Only alloc on first setup */
 401         chip = spi_get_ctldata(spi);
 402         if (!chip) {
 403                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 404                 if (!chip)
 405                         return -ENOMEM;
 406                 spi_set_ctldata(spi, chip);
 407         }
 408
 409         /*
 410          * Protocol drivers may change the chip settings, so...
 411          * if chip_info exists, use it
 412          */
 413         chip_info = spi->controller_data;
 414
 415         /* chip_info doesn't always exist */
 416         if (chip_info) {
 417                 if (chip_info->cs_control)
 418                         chip->cs_control = chip_info->cs_control;
 419
 420                 chip->poll_mode = chip_info->poll_mode;
 421                 chip->type = chip_info->type;
 422         }
 423
 424         chip->tmode = SPI_TMOD_TR;
 425
 426         return 0;
 427 }
 428
 429 static void dw_spi_cleanup(struct spi_device *spi)
 430 {
 431         struct chip_data *chip = spi_get_ctldata(spi);
 432
 433         kfree(chip);
 434         spi_set_ctldata(spi, NULL);
 435 }
 436
 437 /* Restart the controller, disable all interrupts, clean rx fifo */
 438 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
 439 {
 440         spi_reset_chip(dws);
 441
 442         /*
 443          * Try to detect the FIFO depth if not set by interface driver,
 444          * the depth could be from 2 to 256 from HW spec
 445          */
 446         if (!dws->fifo_len) {
 447                 u32 fifo;
 448
 449                 for (fifo = 1; fifo < 256; fifo++) {
 450                         dw_writel(dws, DW_SPI_TXFLTR, fifo);
 451                         if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
 452                                 break;
 453                 }
 454                 dw_writel(dws, DW_SPI_TXFLTR, 0);
 455
 456                 dws->fifo_len = (fifo == 1) ? 0 : fifo;
 457                 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
 458         }
 459
 460         /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
 461         if (dws->cs_override)
 462                 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
 463 }
 464
 465 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 466 {
 467         struct spi_controller *master;
 468         int ret;
 469
 470         BUG_ON(dws == NULL);
 471
 472         master = spi_alloc_master(dev, 0);
 473         if (!master)
 474                 return -ENOMEM;
 475
 476         dws->master = master;
 477         dws->type = SSI_MOTO_SPI;
 478         dws->dma_inited = 0;
 479         dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
 480
 481         spi_controller_set_devdata(master, dws);
 482
 483         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
 484                           master);
 485         if (ret < 0) {
 486                 dev_err(dev, "can not get IRQ\n");
 487                 goto err_free_master;
 488         }
 489
 490         master->use_gpio_descriptors = true;
 491         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 492         master->bits_per_word_mask =  SPI_BPW_RANGE_MASK(4, 16);
 493         master->bus_num = dws->bus_num;
 494         master->num_chipselect = dws->num_cs;
 495         master->setup = dw_spi_setup;
 496         master->cleanup = dw_spi_cleanup;
 497         master->set_cs = dw_spi_set_cs;
 498         master->transfer_one = dw_spi_transfer_one;
 499         master->handle_err = dw_spi_handle_err;
 500         master->max_speed_hz = dws->max_freq;
 501         master->dev.of_node = dev->of_node;
 502         master->dev.fwnode = dev->fwnode;
 503         master->flags = SPI_MASTER_GPIO_SS;
 504
 505         if (dws->set_cs)
 506                 master->set_cs = dws->set_cs;
 507
 508         /* Basic HW init */
 509         spi_hw_init(dev, dws);
 510
 511         if (dws->dma_ops && dws->dma_ops->dma_init) {
 512                 ret = dws->dma_ops->dma_init(dws);
 513                 if (ret) {
 514                         dev_warn(dev, "DMA init failed\n");
 515                         dws->dma_inited = 0;
 516                 } else {
 517                         master->can_dma = dws->dma_ops->can_dma;
 518                 }
 519         }
 520
 521         ret = devm_spi_register_controller(dev, master);
 522         if (ret) {
 523                 dev_err(&master->dev, "problem registering spi master\n");
 524                 goto err_dma_exit;
 525         }
 526
 527         dw_spi_debugfs_init(dws);
 528         return 0;
 529
 530 err_dma_exit:
 531         if (dws->dma_ops && dws->dma_ops->dma_exit)
 532                 dws->dma_ops->dma_exit(dws);
 533         spi_enable_chip(dws, 0);
 534         free_irq(dws->irq, master);
 535 err_free_master:
 536         spi_controller_put(master);
 537         return ret;
 538 }
 539 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 540
 541 void dw_spi_remove_host(struct dw_spi *dws)
 542 {
 543         dw_spi_debugfs_remove(dws);
 544
 545         if (dws->dma_ops && dws->dma_ops->dma_exit)
 546                 dws->dma_ops->dma_exit(dws);
 547
 548         spi_shutdown_chip(dws);
 549
 550         free_irq(dws->irq, dws->master);
 551 }
 552 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 553
 554 int dw_spi_suspend_host(struct dw_spi *dws)
 555 {
 556         int ret;
 557
 558         ret = spi_controller_suspend(dws->master);
 559         if (ret)
 560                 return ret;
 561
 562         spi_shutdown_chip(dws);
 563         return 0;
 564 }
 565 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 566
 567 int dw_spi_resume_host(struct dw_spi *dws)
 568 {
 569         spi_hw_init(&dws->master->dev, dws);
 570         return spi_controller_resume(dws->master);
 571 }
 572 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 573
 574 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 575 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 576 MODULE_LICENSE("GPL v2");