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Merge tag 'kvm-x86-generic-6.8' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / drivers / spi / spi-imx.c
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
4
5 #include <linux/clk.h>
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 #include <linux/of.h>
23 #include <linux/property.h>
24
25 #include <linux/dma/imx-dma.h>
26
27 #define DRIVER_NAME "spi_imx"
28
29 static bool use_dma = true;
30 module_param(use_dma, bool, 0644);
31 MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
32
33 /* define polling limits */
34 static unsigned int polling_limit_us = 30;
35 module_param(polling_limit_us, uint, 0664);
36 MODULE_PARM_DESC(polling_limit_us,
37 "time in us to run a transfer in polling mode\n");
38
39 #define MXC_RPM_TIMEOUT 2000 /* 2000ms */
40
41 #define MXC_CSPIRXDATA 0x00
42 #define MXC_CSPITXDATA 0x04
43 #define MXC_CSPICTRL 0x08
44 #define MXC_CSPIINT 0x0c
45 #define MXC_RESET 0x1c
46
47 /* generic defines to abstract from the different register layouts */
48 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
49 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
50 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
51
52 /* The maximum bytes that a sdma BD can transfer. */
53 #define MAX_SDMA_BD_BYTES (1 << 15)
54 #define MX51_ECSPI_CTRL_MAX_BURST 512
55 /* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/
56 #define MX53_MAX_TRANSFER_BYTES 512
57
58 enum spi_imx_devtype {
59 IMX1_CSPI,
60 IMX21_CSPI,
61 IMX27_CSPI,
62 IMX31_CSPI,
63 IMX35_CSPI, /* CSPI on all i.mx except above */
64 IMX51_ECSPI, /* ECSPI on i.mx51 */
65 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
66 };
67
68 struct spi_imx_data;
69
70 struct spi_imx_devtype_data {
71 void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
72 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
73 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
74 void (*trigger)(struct spi_imx_data *spi_imx);
75 int (*rx_available)(struct spi_imx_data *spi_imx);
76 void (*reset)(struct spi_imx_data *spi_imx);
77 void (*setup_wml)(struct spi_imx_data *spi_imx);
78 void (*disable)(struct spi_imx_data *spi_imx);
79 bool has_dmamode;
80 bool has_targetmode;
81 unsigned int fifo_size;
82 bool dynamic_burst;
83 /*
84 * ERR009165 fixed or not:
85 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
86 */
87 bool tx_glitch_fixed;
88 enum spi_imx_devtype devtype;
89 };
90
91 struct spi_imx_data {
92 struct spi_controller *controller;
93 struct device *dev;
94
95 struct completion xfer_done;
96 void __iomem *base;
97 unsigned long base_phys;
98
99 struct clk *clk_per;
100 struct clk *clk_ipg;
101 unsigned long spi_clk;
102 unsigned int spi_bus_clk;
103
104 unsigned int bits_per_word;
105 unsigned int spi_drctl;
106
107 unsigned int count, remainder;
108 void (*tx)(struct spi_imx_data *spi_imx);
109 void (*rx)(struct spi_imx_data *spi_imx);
110 void *rx_buf;
111 const void *tx_buf;
112 unsigned int txfifo; /* number of words pushed in tx FIFO */
113 unsigned int dynamic_burst;
114 bool rx_only;
115
116 /* Target mode */
117 bool target_mode;
118 bool target_aborted;
119 unsigned int target_burst;
120
121 /* DMA */
122 bool usedma;
123 u32 wml;
124 struct completion dma_rx_completion;
125 struct completion dma_tx_completion;
126
127 const struct spi_imx_devtype_data *devtype_data;
128 };
129
130 static inline int is_imx27_cspi(struct spi_imx_data *d)
131 {
132 return d->devtype_data->devtype == IMX27_CSPI;
133 }
134
135 static inline int is_imx35_cspi(struct spi_imx_data *d)
136 {
137 return d->devtype_data->devtype == IMX35_CSPI;
138 }
139
140 static inline int is_imx51_ecspi(struct spi_imx_data *d)
141 {
142 return d->devtype_data->devtype == IMX51_ECSPI;
143 }
144
145 static inline int is_imx53_ecspi(struct spi_imx_data *d)
146 {
147 return d->devtype_data->devtype == IMX53_ECSPI;
148 }
149
150 #define MXC_SPI_BUF_RX(type) \
151 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
152 { \
153 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
154 \
155 if (spi_imx->rx_buf) { \
156 *(type *)spi_imx->rx_buf = val; \
157 spi_imx->rx_buf += sizeof(type); \
158 } \
159 \
160 spi_imx->remainder -= sizeof(type); \
161 }
162
163 #define MXC_SPI_BUF_TX(type) \
164 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
165 { \
166 type val = 0; \
167 \
168 if (spi_imx->tx_buf) { \
169 val = *(type *)spi_imx->tx_buf; \
170 spi_imx->tx_buf += sizeof(type); \
171 } \
172 \
173 spi_imx->count -= sizeof(type); \
174 \
175 writel(val, spi_imx->base + MXC_CSPITXDATA); \
176 }
177
178 MXC_SPI_BUF_RX(u8)
179 MXC_SPI_BUF_TX(u8)
180 MXC_SPI_BUF_RX(u16)
181 MXC_SPI_BUF_TX(u16)
182 MXC_SPI_BUF_RX(u32)
183 MXC_SPI_BUF_TX(u32)
184
185 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
186 * (which is currently not the case in this driver)
187 */
188 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
189 256, 384, 512, 768, 1024};
190
191 /* MX21, MX27 */
192 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
193 unsigned int fspi, unsigned int max, unsigned int *fres)
194 {
195 int i;
196
197 for (i = 2; i < max; i++)
198 if (fspi * mxc_clkdivs[i] >= fin)
199 break;
200
201 *fres = fin / mxc_clkdivs[i];
202 return i;
203 }
204
205 /* MX1, MX31, MX35, MX51 CSPI */
206 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
207 unsigned int fspi, unsigned int *fres)
208 {
209 int i, div = 4;
210
211 for (i = 0; i < 7; i++) {
212 if (fspi * div >= fin)
213 goto out;
214 div <<= 1;
215 }
216
217 out:
218 *fres = fin / div;
219 return i;
220 }
221
222 static int spi_imx_bytes_per_word(const int bits_per_word)
223 {
224 if (bits_per_word <= 8)
225 return 1;
226 else if (bits_per_word <= 16)
227 return 2;
228 else
229 return 4;
230 }
231
232 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
233 struct spi_transfer *transfer)
234 {
235 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
236
237 if (!use_dma || controller->fallback)
238 return false;
239
240 if (!controller->dma_rx)
241 return false;
242
243 if (spi_imx->target_mode)
244 return false;
245
246 if (transfer->len < spi_imx->devtype_data->fifo_size)
247 return false;
248
249 spi_imx->dynamic_burst = 0;
250
251 return true;
252 }
253
254 /*
255 * Note the number of natively supported chip selects for MX51 is 4. Some
256 * devices may have less actual SS pins but the register map supports 4. When
257 * using gpio chip selects the cs values passed into the macros below can go
258 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
259 * corrupting bits outside the allocated locations.
260 *
261 * The simplest way to do this is to just mask the cs bits to 2 bits. This
262 * still allows all 4 native chip selects to work as well as gpio chip selects
263 * (which can use any of the 4 chip select configurations).
264 */
265
266 #define MX51_ECSPI_CTRL 0x08
267 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
268 #define MX51_ECSPI_CTRL_XCH (1 << 2)
269 #define MX51_ECSPI_CTRL_SMC (1 << 3)
270 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
271 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
272 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
273 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
274 #define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
275 #define MX51_ECSPI_CTRL_BL_OFFSET 20
276 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
277
278 #define MX51_ECSPI_CONFIG 0x0c
279 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
280 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
281 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
282 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
283 #define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16))
284 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
285
286 #define MX51_ECSPI_INT 0x10
287 #define MX51_ECSPI_INT_TEEN (1 << 0)
288 #define MX51_ECSPI_INT_RREN (1 << 3)
289 #define MX51_ECSPI_INT_RDREN (1 << 4)
290
291 #define MX51_ECSPI_DMA 0x14
292 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
293 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
294 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
295
296 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
297 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
298 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
299
300 #define MX51_ECSPI_STAT 0x18
301 #define MX51_ECSPI_STAT_RR (1 << 3)
302
303 #define MX51_ECSPI_TESTREG 0x20
304 #define MX51_ECSPI_TESTREG_LBC BIT(31)
305
306 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
307 {
308 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
309
310 if (spi_imx->rx_buf) {
311 #ifdef __LITTLE_ENDIAN
312 unsigned int bytes_per_word;
313
314 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
315 if (bytes_per_word == 1)
316 swab32s(&val);
317 else if (bytes_per_word == 2)
318 swahw32s(&val);
319 #endif
320 *(u32 *)spi_imx->rx_buf = val;
321 spi_imx->rx_buf += sizeof(u32);
322 }
323
324 spi_imx->remainder -= sizeof(u32);
325 }
326
327 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
328 {
329 int unaligned;
330 u32 val;
331
332 unaligned = spi_imx->remainder % 4;
333
334 if (!unaligned) {
335 spi_imx_buf_rx_swap_u32(spi_imx);
336 return;
337 }
338
339 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
340 spi_imx_buf_rx_u16(spi_imx);
341 return;
342 }
343
344 val = readl(spi_imx->base + MXC_CSPIRXDATA);
345
346 while (unaligned--) {
347 if (spi_imx->rx_buf) {
348 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
349 spi_imx->rx_buf++;
350 }
351 spi_imx->remainder--;
352 }
353 }
354
355 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
356 {
357 u32 val = 0;
358 #ifdef __LITTLE_ENDIAN
359 unsigned int bytes_per_word;
360 #endif
361
362 if (spi_imx->tx_buf) {
363 val = *(u32 *)spi_imx->tx_buf;
364 spi_imx->tx_buf += sizeof(u32);
365 }
366
367 spi_imx->count -= sizeof(u32);
368 #ifdef __LITTLE_ENDIAN
369 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
370
371 if (bytes_per_word == 1)
372 swab32s(&val);
373 else if (bytes_per_word == 2)
374 swahw32s(&val);
375 #endif
376 writel(val, spi_imx->base + MXC_CSPITXDATA);
377 }
378
379 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
380 {
381 int unaligned;
382 u32 val = 0;
383
384 unaligned = spi_imx->count % 4;
385
386 if (!unaligned) {
387 spi_imx_buf_tx_swap_u32(spi_imx);
388 return;
389 }
390
391 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
392 spi_imx_buf_tx_u16(spi_imx);
393 return;
394 }
395
396 while (unaligned--) {
397 if (spi_imx->tx_buf) {
398 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
399 spi_imx->tx_buf++;
400 }
401 spi_imx->count--;
402 }
403
404 writel(val, spi_imx->base + MXC_CSPITXDATA);
405 }
406
407 static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx)
408 {
409 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
410
411 if (spi_imx->rx_buf) {
412 int n_bytes = spi_imx->target_burst % sizeof(val);
413
414 if (!n_bytes)
415 n_bytes = sizeof(val);
416
417 memcpy(spi_imx->rx_buf,
418 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
419
420 spi_imx->rx_buf += n_bytes;
421 spi_imx->target_burst -= n_bytes;
422 }
423
424 spi_imx->remainder -= sizeof(u32);
425 }
426
427 static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx)
428 {
429 u32 val = 0;
430 int n_bytes = spi_imx->count % sizeof(val);
431
432 if (!n_bytes)
433 n_bytes = sizeof(val);
434
435 if (spi_imx->tx_buf) {
436 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
437 spi_imx->tx_buf, n_bytes);
438 val = cpu_to_be32(val);
439 spi_imx->tx_buf += n_bytes;
440 }
441
442 spi_imx->count -= n_bytes;
443
444 writel(val, spi_imx->base + MXC_CSPITXDATA);
445 }
446
447 /* MX51 eCSPI */
448 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
449 unsigned int fspi, unsigned int *fres)
450 {
451 /*
452 * there are two 4-bit dividers, the pre-divider divides by
453 * $pre, the post-divider by 2^$post
454 */
455 unsigned int pre, post;
456 unsigned int fin = spi_imx->spi_clk;
457
458 fspi = min(fspi, fin);
459
460 post = fls(fin) - fls(fspi);
461 if (fin > fspi << post)
462 post++;
463
464 /* now we have: (fin <= fspi << post) with post being minimal */
465
466 post = max(4U, post) - 4;
467 if (unlikely(post > 0xf)) {
468 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
469 fspi, fin);
470 return 0xff;
471 }
472
473 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
474
475 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
476 __func__, fin, fspi, post, pre);
477
478 /* Resulting frequency for the SCLK line. */
479 *fres = (fin / (pre + 1)) >> post;
480
481 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
482 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
483 }
484
485 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
486 {
487 unsigned int val = 0;
488
489 if (enable & MXC_INT_TE)
490 val |= MX51_ECSPI_INT_TEEN;
491
492 if (enable & MXC_INT_RR)
493 val |= MX51_ECSPI_INT_RREN;
494
495 if (enable & MXC_INT_RDR)
496 val |= MX51_ECSPI_INT_RDREN;
497
498 writel(val, spi_imx->base + MX51_ECSPI_INT);
499 }
500
501 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
502 {
503 u32 reg;
504
505 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
506 reg |= MX51_ECSPI_CTRL_XCH;
507 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
508 }
509
510 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
511 {
512 u32 ctrl;
513
514 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
515 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
516 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
517 }
518
519 static int mx51_ecspi_channel(const struct spi_device *spi)
520 {
521 if (!spi_get_csgpiod(spi, 0))
522 return spi_get_chipselect(spi, 0);
523 return spi->controller->unused_native_cs;
524 }
525
526 static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
527 struct spi_message *msg)
528 {
529 struct spi_device *spi = msg->spi;
530 struct spi_transfer *xfer;
531 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
532 u32 min_speed_hz = ~0U;
533 u32 testreg, delay;
534 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
535 u32 current_cfg = cfg;
536 int channel = mx51_ecspi_channel(spi);
537
538 /* set Host or Target mode */
539 if (spi_imx->target_mode)
540 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
541 else
542 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
543
544 /*
545 * Enable SPI_RDY handling (falling edge/level triggered).
546 */
547 if (spi->mode & SPI_READY)
548 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
549
550 /* set chip select to use */
551 ctrl |= MX51_ECSPI_CTRL_CS(channel);
552
553 /*
554 * The ctrl register must be written first, with the EN bit set other
555 * registers must not be written to.
556 */
557 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
558
559 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
560 if (spi->mode & SPI_LOOP)
561 testreg |= MX51_ECSPI_TESTREG_LBC;
562 else
563 testreg &= ~MX51_ECSPI_TESTREG_LBC;
564 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
565
566 /*
567 * eCSPI burst completion by Chip Select signal in Target mode
568 * is not functional for imx53 Soc, config SPI burst completed when
569 * BURST_LENGTH + 1 bits are received
570 */
571 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
572 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
573 else
574 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
575
576 if (spi->mode & SPI_CPOL) {
577 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
578 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
579 } else {
580 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
581 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
582 }
583
584 if (spi->mode & SPI_MOSI_IDLE_LOW)
585 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
586 else
587 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
588
589 if (spi->mode & SPI_CS_HIGH)
590 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
591 else
592 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
593
594 if (cfg == current_cfg)
595 return 0;
596
597 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
598
599 /*
600 * Wait until the changes in the configuration register CONFIGREG
601 * propagate into the hardware. It takes exactly one tick of the
602 * SCLK clock, but we will wait two SCLK clock just to be sure. The
603 * effect of the delay it takes for the hardware to apply changes
604 * is noticable if the SCLK clock run very slow. In such a case, if
605 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
606 * be asserted before the SCLK polarity changes, which would disrupt
607 * the SPI communication as the device on the other end would consider
608 * the change of SCLK polarity as a clock tick already.
609 *
610 * Because spi_imx->spi_bus_clk is only set in prepare_message
611 * callback, iterate over all the transfers in spi_message, find the
612 * one with lowest bus frequency, and use that bus frequency for the
613 * delay calculation. In case all transfers have speed_hz == 0, then
614 * min_speed_hz is ~0 and the resulting delay is zero.
615 */
616 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
617 if (!xfer->speed_hz)
618 continue;
619 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
620 }
621
622 delay = (2 * 1000000) / min_speed_hz;
623 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
624 udelay(delay);
625 else /* SCLK is _very_ slow */
626 usleep_range(delay, delay + 10);
627
628 return 0;
629 }
630
631 static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
632 struct spi_device *spi)
633 {
634 bool cpha = (spi->mode & SPI_CPHA);
635 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
636 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
637 int channel = mx51_ecspi_channel(spi);
638
639 /* Flip cpha logical value iff flip_cpha */
640 cpha ^= flip_cpha;
641
642 if (cpha)
643 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
644 else
645 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
646
647 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
648 }
649
650 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
651 struct spi_device *spi)
652 {
653 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
654 u32 clk;
655
656 /* Clear BL field and set the right value */
657 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
658 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
659 ctrl |= (spi_imx->target_burst * 8 - 1)
660 << MX51_ECSPI_CTRL_BL_OFFSET;
661 else {
662 if (spi_imx->usedma) {
663 ctrl |= (spi_imx->bits_per_word *
664 spi_imx_bytes_per_word(spi_imx->bits_per_word) - 1)
665 << MX51_ECSPI_CTRL_BL_OFFSET;
666 } else {
667 if (spi_imx->count >= MX51_ECSPI_CTRL_MAX_BURST)
668 ctrl |= (MX51_ECSPI_CTRL_MAX_BURST - 1)
669 << MX51_ECSPI_CTRL_BL_OFFSET;
670 else
671 ctrl |= (spi_imx->count * spi_imx->bits_per_word - 1)
672 << MX51_ECSPI_CTRL_BL_OFFSET;
673 }
674 }
675
676 /* set clock speed */
677 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
678 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
679 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
680 spi_imx->spi_bus_clk = clk;
681
682 mx51_configure_cpha(spi_imx, spi);
683
684 /*
685 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
686 * before i.mx6ul.
687 */
688 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
689 ctrl |= MX51_ECSPI_CTRL_SMC;
690 else
691 ctrl &= ~MX51_ECSPI_CTRL_SMC;
692
693 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
694
695 return 0;
696 }
697
698 static void mx51_setup_wml(struct spi_imx_data *spi_imx)
699 {
700 u32 tx_wml = 0;
701
702 if (spi_imx->devtype_data->tx_glitch_fixed)
703 tx_wml = spi_imx->wml;
704 /*
705 * Configure the DMA register: setup the watermark
706 * and enable DMA request.
707 */
708 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
709 MX51_ECSPI_DMA_TX_WML(tx_wml) |
710 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
711 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
712 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
713 }
714
715 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
716 {
717 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
718 }
719
720 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
721 {
722 /* drain receive buffer */
723 while (mx51_ecspi_rx_available(spi_imx))
724 readl(spi_imx->base + MXC_CSPIRXDATA);
725 }
726
727 #define MX31_INTREG_TEEN (1 << 0)
728 #define MX31_INTREG_RREN (1 << 3)
729
730 #define MX31_CSPICTRL_ENABLE (1 << 0)
731 #define MX31_CSPICTRL_HOST (1 << 1)
732 #define MX31_CSPICTRL_XCH (1 << 2)
733 #define MX31_CSPICTRL_SMC (1 << 3)
734 #define MX31_CSPICTRL_POL (1 << 4)
735 #define MX31_CSPICTRL_PHA (1 << 5)
736 #define MX31_CSPICTRL_SSCTL (1 << 6)
737 #define MX31_CSPICTRL_SSPOL (1 << 7)
738 #define MX31_CSPICTRL_BC_SHIFT 8
739 #define MX35_CSPICTRL_BL_SHIFT 20
740 #define MX31_CSPICTRL_CS_SHIFT 24
741 #define MX35_CSPICTRL_CS_SHIFT 12
742 #define MX31_CSPICTRL_DR_SHIFT 16
743
744 #define MX31_CSPI_DMAREG 0x10
745 #define MX31_DMAREG_RH_DEN (1<<4)
746 #define MX31_DMAREG_TH_DEN (1<<1)
747
748 #define MX31_CSPISTATUS 0x14
749 #define MX31_STATUS_RR (1 << 3)
750
751 #define MX31_CSPI_TESTREG 0x1C
752 #define MX31_TEST_LBC (1 << 14)
753
754 /* These functions also work for the i.MX35, but be aware that
755 * the i.MX35 has a slightly different register layout for bits
756 * we do not use here.
757 */
758 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
759 {
760 unsigned int val = 0;
761
762 if (enable & MXC_INT_TE)
763 val |= MX31_INTREG_TEEN;
764 if (enable & MXC_INT_RR)
765 val |= MX31_INTREG_RREN;
766
767 writel(val, spi_imx->base + MXC_CSPIINT);
768 }
769
770 static void mx31_trigger(struct spi_imx_data *spi_imx)
771 {
772 unsigned int reg;
773
774 reg = readl(spi_imx->base + MXC_CSPICTRL);
775 reg |= MX31_CSPICTRL_XCH;
776 writel(reg, spi_imx->base + MXC_CSPICTRL);
777 }
778
779 static int mx31_prepare_message(struct spi_imx_data *spi_imx,
780 struct spi_message *msg)
781 {
782 return 0;
783 }
784
785 static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
786 struct spi_device *spi)
787 {
788 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
789 unsigned int clk;
790
791 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
792 MX31_CSPICTRL_DR_SHIFT;
793 spi_imx->spi_bus_clk = clk;
794
795 if (is_imx35_cspi(spi_imx)) {
796 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
797 reg |= MX31_CSPICTRL_SSCTL;
798 } else {
799 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
800 }
801
802 if (spi->mode & SPI_CPHA)
803 reg |= MX31_CSPICTRL_PHA;
804 if (spi->mode & SPI_CPOL)
805 reg |= MX31_CSPICTRL_POL;
806 if (spi->mode & SPI_CS_HIGH)
807 reg |= MX31_CSPICTRL_SSPOL;
808 if (!spi_get_csgpiod(spi, 0))
809 reg |= (spi_get_chipselect(spi, 0)) <<
810 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
811 MX31_CSPICTRL_CS_SHIFT);
812
813 if (spi_imx->usedma)
814 reg |= MX31_CSPICTRL_SMC;
815
816 writel(reg, spi_imx->base + MXC_CSPICTRL);
817
818 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
819 if (spi->mode & SPI_LOOP)
820 reg |= MX31_TEST_LBC;
821 else
822 reg &= ~MX31_TEST_LBC;
823 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
824
825 if (spi_imx->usedma) {
826 /*
827 * configure DMA requests when RXFIFO is half full and
828 * when TXFIFO is half empty
829 */
830 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
831 spi_imx->base + MX31_CSPI_DMAREG);
832 }
833
834 return 0;
835 }
836
837 static int mx31_rx_available(struct spi_imx_data *spi_imx)
838 {
839 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
840 }
841
842 static void mx31_reset(struct spi_imx_data *spi_imx)
843 {
844 /* drain receive buffer */
845 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
846 readl(spi_imx->base + MXC_CSPIRXDATA);
847 }
848
849 #define MX21_INTREG_RR (1 << 4)
850 #define MX21_INTREG_TEEN (1 << 9)
851 #define MX21_INTREG_RREN (1 << 13)
852
853 #define MX21_CSPICTRL_POL (1 << 5)
854 #define MX21_CSPICTRL_PHA (1 << 6)
855 #define MX21_CSPICTRL_SSPOL (1 << 8)
856 #define MX21_CSPICTRL_XCH (1 << 9)
857 #define MX21_CSPICTRL_ENABLE (1 << 10)
858 #define MX21_CSPICTRL_HOST (1 << 11)
859 #define MX21_CSPICTRL_DR_SHIFT 14
860 #define MX21_CSPICTRL_CS_SHIFT 19
861
862 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
863 {
864 unsigned int val = 0;
865
866 if (enable & MXC_INT_TE)
867 val |= MX21_INTREG_TEEN;
868 if (enable & MXC_INT_RR)
869 val |= MX21_INTREG_RREN;
870
871 writel(val, spi_imx->base + MXC_CSPIINT);
872 }
873
874 static void mx21_trigger(struct spi_imx_data *spi_imx)
875 {
876 unsigned int reg;
877
878 reg = readl(spi_imx->base + MXC_CSPICTRL);
879 reg |= MX21_CSPICTRL_XCH;
880 writel(reg, spi_imx->base + MXC_CSPICTRL);
881 }
882
883 static int mx21_prepare_message(struct spi_imx_data *spi_imx,
884 struct spi_message *msg)
885 {
886 return 0;
887 }
888
889 static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
890 struct spi_device *spi)
891 {
892 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
893 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
894 unsigned int clk;
895
896 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
897 << MX21_CSPICTRL_DR_SHIFT;
898 spi_imx->spi_bus_clk = clk;
899
900 reg |= spi_imx->bits_per_word - 1;
901
902 if (spi->mode & SPI_CPHA)
903 reg |= MX21_CSPICTRL_PHA;
904 if (spi->mode & SPI_CPOL)
905 reg |= MX21_CSPICTRL_POL;
906 if (spi->mode & SPI_CS_HIGH)
907 reg |= MX21_CSPICTRL_SSPOL;
908 if (!spi_get_csgpiod(spi, 0))
909 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
910
911 writel(reg, spi_imx->base + MXC_CSPICTRL);
912
913 return 0;
914 }
915
916 static int mx21_rx_available(struct spi_imx_data *spi_imx)
917 {
918 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
919 }
920
921 static void mx21_reset(struct spi_imx_data *spi_imx)
922 {
923 writel(1, spi_imx->base + MXC_RESET);
924 }
925
926 #define MX1_INTREG_RR (1 << 3)
927 #define MX1_INTREG_TEEN (1 << 8)
928 #define MX1_INTREG_RREN (1 << 11)
929
930 #define MX1_CSPICTRL_POL (1 << 4)
931 #define MX1_CSPICTRL_PHA (1 << 5)
932 #define MX1_CSPICTRL_XCH (1 << 8)
933 #define MX1_CSPICTRL_ENABLE (1 << 9)
934 #define MX1_CSPICTRL_HOST (1 << 10)
935 #define MX1_CSPICTRL_DR_SHIFT 13
936
937 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
938 {
939 unsigned int val = 0;
940
941 if (enable & MXC_INT_TE)
942 val |= MX1_INTREG_TEEN;
943 if (enable & MXC_INT_RR)
944 val |= MX1_INTREG_RREN;
945
946 writel(val, spi_imx->base + MXC_CSPIINT);
947 }
948
949 static void mx1_trigger(struct spi_imx_data *spi_imx)
950 {
951 unsigned int reg;
952
953 reg = readl(spi_imx->base + MXC_CSPICTRL);
954 reg |= MX1_CSPICTRL_XCH;
955 writel(reg, spi_imx->base + MXC_CSPICTRL);
956 }
957
958 static int mx1_prepare_message(struct spi_imx_data *spi_imx,
959 struct spi_message *msg)
960 {
961 return 0;
962 }
963
964 static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
965 struct spi_device *spi)
966 {
967 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
968 unsigned int clk;
969
970 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
971 MX1_CSPICTRL_DR_SHIFT;
972 spi_imx->spi_bus_clk = clk;
973
974 reg |= spi_imx->bits_per_word - 1;
975
976 if (spi->mode & SPI_CPHA)
977 reg |= MX1_CSPICTRL_PHA;
978 if (spi->mode & SPI_CPOL)
979 reg |= MX1_CSPICTRL_POL;
980
981 writel(reg, spi_imx->base + MXC_CSPICTRL);
982
983 return 0;
984 }
985
986 static int mx1_rx_available(struct spi_imx_data *spi_imx)
987 {
988 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
989 }
990
991 static void mx1_reset(struct spi_imx_data *spi_imx)
992 {
993 writel(1, spi_imx->base + MXC_RESET);
994 }
995
996 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
997 .intctrl = mx1_intctrl,
998 .prepare_message = mx1_prepare_message,
999 .prepare_transfer = mx1_prepare_transfer,
1000 .trigger = mx1_trigger,
1001 .rx_available = mx1_rx_available,
1002 .reset = mx1_reset,
1003 .fifo_size = 8,
1004 .has_dmamode = false,
1005 .dynamic_burst = false,
1006 .has_targetmode = false,
1007 .devtype = IMX1_CSPI,
1008 };
1009
1010 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1011 .intctrl = mx21_intctrl,
1012 .prepare_message = mx21_prepare_message,
1013 .prepare_transfer = mx21_prepare_transfer,
1014 .trigger = mx21_trigger,
1015 .rx_available = mx21_rx_available,
1016 .reset = mx21_reset,
1017 .fifo_size = 8,
1018 .has_dmamode = false,
1019 .dynamic_burst = false,
1020 .has_targetmode = false,
1021 .devtype = IMX21_CSPI,
1022 };
1023
1024 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1025 /* i.mx27 cspi shares the functions with i.mx21 one */
1026 .intctrl = mx21_intctrl,
1027 .prepare_message = mx21_prepare_message,
1028 .prepare_transfer = mx21_prepare_transfer,
1029 .trigger = mx21_trigger,
1030 .rx_available = mx21_rx_available,
1031 .reset = mx21_reset,
1032 .fifo_size = 8,
1033 .has_dmamode = false,
1034 .dynamic_burst = false,
1035 .has_targetmode = false,
1036 .devtype = IMX27_CSPI,
1037 };
1038
1039 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1040 .intctrl = mx31_intctrl,
1041 .prepare_message = mx31_prepare_message,
1042 .prepare_transfer = mx31_prepare_transfer,
1043 .trigger = mx31_trigger,
1044 .rx_available = mx31_rx_available,
1045 .reset = mx31_reset,
1046 .fifo_size = 8,
1047 .has_dmamode = false,
1048 .dynamic_burst = false,
1049 .has_targetmode = false,
1050 .devtype = IMX31_CSPI,
1051 };
1052
1053 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1054 /* i.mx35 and later cspi shares the functions with i.mx31 one */
1055 .intctrl = mx31_intctrl,
1056 .prepare_message = mx31_prepare_message,
1057 .prepare_transfer = mx31_prepare_transfer,
1058 .trigger = mx31_trigger,
1059 .rx_available = mx31_rx_available,
1060 .reset = mx31_reset,
1061 .fifo_size = 8,
1062 .has_dmamode = true,
1063 .dynamic_burst = false,
1064 .has_targetmode = false,
1065 .devtype = IMX35_CSPI,
1066 };
1067
1068 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1069 .intctrl = mx51_ecspi_intctrl,
1070 .prepare_message = mx51_ecspi_prepare_message,
1071 .prepare_transfer = mx51_ecspi_prepare_transfer,
1072 .trigger = mx51_ecspi_trigger,
1073 .rx_available = mx51_ecspi_rx_available,
1074 .reset = mx51_ecspi_reset,
1075 .setup_wml = mx51_setup_wml,
1076 .fifo_size = 64,
1077 .has_dmamode = true,
1078 .dynamic_burst = true,
1079 .has_targetmode = true,
1080 .disable = mx51_ecspi_disable,
1081 .devtype = IMX51_ECSPI,
1082 };
1083
1084 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1085 .intctrl = mx51_ecspi_intctrl,
1086 .prepare_message = mx51_ecspi_prepare_message,
1087 .prepare_transfer = mx51_ecspi_prepare_transfer,
1088 .trigger = mx51_ecspi_trigger,
1089 .rx_available = mx51_ecspi_rx_available,
1090 .reset = mx51_ecspi_reset,
1091 .fifo_size = 64,
1092 .has_dmamode = true,
1093 .has_targetmode = true,
1094 .disable = mx51_ecspi_disable,
1095 .devtype = IMX53_ECSPI,
1096 };
1097
1098 static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1099 .intctrl = mx51_ecspi_intctrl,
1100 .prepare_message = mx51_ecspi_prepare_message,
1101 .prepare_transfer = mx51_ecspi_prepare_transfer,
1102 .trigger = mx51_ecspi_trigger,
1103 .rx_available = mx51_ecspi_rx_available,
1104 .reset = mx51_ecspi_reset,
1105 .setup_wml = mx51_setup_wml,
1106 .fifo_size = 64,
1107 .has_dmamode = true,
1108 .dynamic_burst = true,
1109 .has_targetmode = true,
1110 .tx_glitch_fixed = true,
1111 .disable = mx51_ecspi_disable,
1112 .devtype = IMX51_ECSPI,
1113 };
1114
1115 static const struct of_device_id spi_imx_dt_ids[] = {
1116 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1117 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1118 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1119 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1120 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1121 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1122 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1123 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1124 { /* sentinel */ }
1125 };
1126 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1127
1128 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1129 {
1130 u32 ctrl;
1131
1132 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1133 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1134 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1135 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1136 }
1137
1138 static void spi_imx_push(struct spi_imx_data *spi_imx)
1139 {
1140 unsigned int burst_len;
1141
1142 /*
1143 * Reload the FIFO when the remaining bytes to be transferred in the
1144 * current burst is 0. This only applies when bits_per_word is a
1145 * multiple of 8.
1146 */
1147 if (!spi_imx->remainder) {
1148 if (spi_imx->dynamic_burst) {
1149
1150 /* We need to deal unaligned data first */
1151 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1152
1153 if (!burst_len)
1154 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1155
1156 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1157
1158 spi_imx->remainder = burst_len;
1159 } else {
1160 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1161 }
1162 }
1163
1164 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1165 if (!spi_imx->count)
1166 break;
1167 if (spi_imx->dynamic_burst &&
1168 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1169 break;
1170 spi_imx->tx(spi_imx);
1171 spi_imx->txfifo++;
1172 }
1173
1174 if (!spi_imx->target_mode)
1175 spi_imx->devtype_data->trigger(spi_imx);
1176 }
1177
1178 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1179 {
1180 struct spi_imx_data *spi_imx = dev_id;
1181
1182 while (spi_imx->txfifo &&
1183 spi_imx->devtype_data->rx_available(spi_imx)) {
1184 spi_imx->rx(spi_imx);
1185 spi_imx->txfifo--;
1186 }
1187
1188 if (spi_imx->count) {
1189 spi_imx_push(spi_imx);
1190 return IRQ_HANDLED;
1191 }
1192
1193 if (spi_imx->txfifo) {
1194 /* No data left to push, but still waiting for rx data,
1195 * enable receive data available interrupt.
1196 */
1197 spi_imx->devtype_data->intctrl(
1198 spi_imx, MXC_INT_RR);
1199 return IRQ_HANDLED;
1200 }
1201
1202 spi_imx->devtype_data->intctrl(spi_imx, 0);
1203 complete(&spi_imx->xfer_done);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static int spi_imx_dma_configure(struct spi_controller *controller)
1209 {
1210 int ret;
1211 enum dma_slave_buswidth buswidth;
1212 struct dma_slave_config rx = {}, tx = {};
1213 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1214
1215 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1216 case 4:
1217 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1218 break;
1219 case 2:
1220 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1221 break;
1222 case 1:
1223 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 tx.direction = DMA_MEM_TO_DEV;
1230 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1231 tx.dst_addr_width = buswidth;
1232 tx.dst_maxburst = spi_imx->wml;
1233 ret = dmaengine_slave_config(controller->dma_tx, &tx);
1234 if (ret) {
1235 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1236 return ret;
1237 }
1238
1239 rx.direction = DMA_DEV_TO_MEM;
1240 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1241 rx.src_addr_width = buswidth;
1242 rx.src_maxburst = spi_imx->wml;
1243 ret = dmaengine_slave_config(controller->dma_rx, &rx);
1244 if (ret) {
1245 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1246 return ret;
1247 }
1248
1249 return 0;
1250 }
1251
1252 static int spi_imx_setupxfer(struct spi_device *spi,
1253 struct spi_transfer *t)
1254 {
1255 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1256
1257 if (!t)
1258 return 0;
1259
1260 if (!t->speed_hz) {
1261 if (!spi->max_speed_hz) {
1262 dev_err(&spi->dev, "no speed_hz provided!\n");
1263 return -EINVAL;
1264 }
1265 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1266 spi_imx->spi_bus_clk = spi->max_speed_hz;
1267 } else
1268 spi_imx->spi_bus_clk = t->speed_hz;
1269
1270 spi_imx->bits_per_word = t->bits_per_word;
1271 spi_imx->count = t->len;
1272
1273 /*
1274 * Initialize the functions for transfer. To transfer non byte-aligned
1275 * words, we have to use multiple word-size bursts, we can't use
1276 * dynamic_burst in that case.
1277 */
1278 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
1279 !(spi->mode & SPI_CS_WORD) &&
1280 (spi_imx->bits_per_word == 8 ||
1281 spi_imx->bits_per_word == 16 ||
1282 spi_imx->bits_per_word == 32)) {
1283
1284 spi_imx->rx = spi_imx_buf_rx_swap;
1285 spi_imx->tx = spi_imx_buf_tx_swap;
1286 spi_imx->dynamic_burst = 1;
1287
1288 } else {
1289 if (spi_imx->bits_per_word <= 8) {
1290 spi_imx->rx = spi_imx_buf_rx_u8;
1291 spi_imx->tx = spi_imx_buf_tx_u8;
1292 } else if (spi_imx->bits_per_word <= 16) {
1293 spi_imx->rx = spi_imx_buf_rx_u16;
1294 spi_imx->tx = spi_imx_buf_tx_u16;
1295 } else {
1296 spi_imx->rx = spi_imx_buf_rx_u32;
1297 spi_imx->tx = spi_imx_buf_tx_u32;
1298 }
1299 spi_imx->dynamic_burst = 0;
1300 }
1301
1302 if (spi_imx_can_dma(spi_imx->controller, spi, t))
1303 spi_imx->usedma = true;
1304 else
1305 spi_imx->usedma = false;
1306
1307 spi_imx->rx_only = ((t->tx_buf == NULL)
1308 || (t->tx_buf == spi->controller->dummy_tx));
1309
1310 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) {
1311 spi_imx->rx = mx53_ecspi_rx_target;
1312 spi_imx->tx = mx53_ecspi_tx_target;
1313 spi_imx->target_burst = t->len;
1314 }
1315
1316 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1317
1318 return 0;
1319 }
1320
1321 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1322 {
1323 struct spi_controller *controller = spi_imx->controller;
1324
1325 if (controller->dma_rx) {
1326 dma_release_channel(controller->dma_rx);
1327 controller->dma_rx = NULL;
1328 }
1329
1330 if (controller->dma_tx) {
1331 dma_release_channel(controller->dma_tx);
1332 controller->dma_tx = NULL;
1333 }
1334 }
1335
1336 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1337 struct spi_controller *controller)
1338 {
1339 int ret;
1340
1341 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1342
1343 /* Prepare for TX DMA: */
1344 controller->dma_tx = dma_request_chan(dev, "tx");
1345 if (IS_ERR(controller->dma_tx)) {
1346 ret = PTR_ERR(controller->dma_tx);
1347 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1348 controller->dma_tx = NULL;
1349 goto err;
1350 }
1351
1352 /* Prepare for RX : */
1353 controller->dma_rx = dma_request_chan(dev, "rx");
1354 if (IS_ERR(controller->dma_rx)) {
1355 ret = PTR_ERR(controller->dma_rx);
1356 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1357 controller->dma_rx = NULL;
1358 goto err;
1359 }
1360
1361 init_completion(&spi_imx->dma_rx_completion);
1362 init_completion(&spi_imx->dma_tx_completion);
1363 controller->can_dma = spi_imx_can_dma;
1364 controller->max_dma_len = MAX_SDMA_BD_BYTES;
1365 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1366 SPI_CONTROLLER_MUST_TX;
1367
1368 return 0;
1369 err:
1370 spi_imx_sdma_exit(spi_imx);
1371 return ret;
1372 }
1373
1374 static void spi_imx_dma_rx_callback(void *cookie)
1375 {
1376 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1377
1378 complete(&spi_imx->dma_rx_completion);
1379 }
1380
1381 static void spi_imx_dma_tx_callback(void *cookie)
1382 {
1383 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1384
1385 complete(&spi_imx->dma_tx_completion);
1386 }
1387
1388 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1389 {
1390 unsigned long timeout = 0;
1391
1392 /* Time with actual data transfer and CS change delay related to HW */
1393 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1394
1395 /* Add extra second for scheduler related activities */
1396 timeout += 1;
1397
1398 /* Double calculated timeout */
1399 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1400 }
1401
1402 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1403 struct spi_transfer *transfer)
1404 {
1405 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1406 unsigned long transfer_timeout;
1407 unsigned long timeout;
1408 struct spi_controller *controller = spi_imx->controller;
1409 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1410 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1411 unsigned int bytes_per_word, i;
1412 int ret;
1413
1414 /* Get the right burst length from the last sg to ensure no tail data */
1415 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1416 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1417 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1418 break;
1419 }
1420 /* Use 1 as wml in case no available burst length got */
1421 if (i == 0)
1422 i = 1;
1423
1424 spi_imx->wml = i;
1425
1426 ret = spi_imx_dma_configure(controller);
1427 if (ret)
1428 goto dma_failure_no_start;
1429
1430 if (!spi_imx->devtype_data->setup_wml) {
1431 dev_err(spi_imx->dev, "No setup_wml()?\n");
1432 ret = -EINVAL;
1433 goto dma_failure_no_start;
1434 }
1435 spi_imx->devtype_data->setup_wml(spi_imx);
1436
1437 /*
1438 * The TX DMA setup starts the transfer, so make sure RX is configured
1439 * before TX.
1440 */
1441 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1442 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1443 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1444 if (!desc_rx) {
1445 ret = -EINVAL;
1446 goto dma_failure_no_start;
1447 }
1448
1449 desc_rx->callback = spi_imx_dma_rx_callback;
1450 desc_rx->callback_param = (void *)spi_imx;
1451 dmaengine_submit(desc_rx);
1452 reinit_completion(&spi_imx->dma_rx_completion);
1453 dma_async_issue_pending(controller->dma_rx);
1454
1455 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1456 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1458 if (!desc_tx) {
1459 dmaengine_terminate_all(controller->dma_tx);
1460 dmaengine_terminate_all(controller->dma_rx);
1461 return -EINVAL;
1462 }
1463
1464 desc_tx->callback = spi_imx_dma_tx_callback;
1465 desc_tx->callback_param = (void *)spi_imx;
1466 dmaengine_submit(desc_tx);
1467 reinit_completion(&spi_imx->dma_tx_completion);
1468 dma_async_issue_pending(controller->dma_tx);
1469
1470 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1471
1472 /* Wait SDMA to finish the data transfer.*/
1473 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1474 transfer_timeout);
1475 if (!timeout) {
1476 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1477 dmaengine_terminate_all(controller->dma_tx);
1478 dmaengine_terminate_all(controller->dma_rx);
1479 return -ETIMEDOUT;
1480 }
1481
1482 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1483 transfer_timeout);
1484 if (!timeout) {
1485 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1486 spi_imx->devtype_data->reset(spi_imx);
1487 dmaengine_terminate_all(controller->dma_rx);
1488 return -ETIMEDOUT;
1489 }
1490
1491 return 0;
1492 /* fallback to pio */
1493 dma_failure_no_start:
1494 transfer->error |= SPI_TRANS_FAIL_NO_START;
1495 return ret;
1496 }
1497
1498 static int spi_imx_pio_transfer(struct spi_device *spi,
1499 struct spi_transfer *transfer)
1500 {
1501 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1502 unsigned long transfer_timeout;
1503 unsigned long timeout;
1504
1505 spi_imx->tx_buf = transfer->tx_buf;
1506 spi_imx->rx_buf = transfer->rx_buf;
1507 spi_imx->count = transfer->len;
1508 spi_imx->txfifo = 0;
1509 spi_imx->remainder = 0;
1510
1511 reinit_completion(&spi_imx->xfer_done);
1512
1513 spi_imx_push(spi_imx);
1514
1515 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1516
1517 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1518
1519 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1520 transfer_timeout);
1521 if (!timeout) {
1522 dev_err(&spi->dev, "I/O Error in PIO\n");
1523 spi_imx->devtype_data->reset(spi_imx);
1524 return -ETIMEDOUT;
1525 }
1526
1527 return 0;
1528 }
1529
1530 static int spi_imx_poll_transfer(struct spi_device *spi,
1531 struct spi_transfer *transfer)
1532 {
1533 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1534 unsigned long timeout;
1535
1536 spi_imx->tx_buf = transfer->tx_buf;
1537 spi_imx->rx_buf = transfer->rx_buf;
1538 spi_imx->count = transfer->len;
1539 spi_imx->txfifo = 0;
1540 spi_imx->remainder = 0;
1541
1542 /* fill in the fifo before timeout calculations if we are
1543 * interrupted here, then the data is getting transferred by
1544 * the HW while we are interrupted
1545 */
1546 spi_imx_push(spi_imx);
1547
1548 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1549 while (spi_imx->txfifo) {
1550 /* RX */
1551 while (spi_imx->txfifo &&
1552 spi_imx->devtype_data->rx_available(spi_imx)) {
1553 spi_imx->rx(spi_imx);
1554 spi_imx->txfifo--;
1555 }
1556
1557 /* TX */
1558 if (spi_imx->count) {
1559 spi_imx_push(spi_imx);
1560 continue;
1561 }
1562
1563 if (spi_imx->txfifo &&
1564 time_after(jiffies, timeout)) {
1565
1566 dev_err_ratelimited(&spi->dev,
1567 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1568 jiffies - timeout);
1569
1570 /* fall back to interrupt mode */
1571 return spi_imx_pio_transfer(spi, transfer);
1572 }
1573 }
1574
1575 return 0;
1576 }
1577
1578 static int spi_imx_pio_transfer_target(struct spi_device *spi,
1579 struct spi_transfer *transfer)
1580 {
1581 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1582 int ret = 0;
1583
1584 if (is_imx53_ecspi(spi_imx) &&
1585 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1586 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1587 MX53_MAX_TRANSFER_BYTES);
1588 return -EMSGSIZE;
1589 }
1590
1591 spi_imx->tx_buf = transfer->tx_buf;
1592 spi_imx->rx_buf = transfer->rx_buf;
1593 spi_imx->count = transfer->len;
1594 spi_imx->txfifo = 0;
1595 spi_imx->remainder = 0;
1596
1597 reinit_completion(&spi_imx->xfer_done);
1598 spi_imx->target_aborted = false;
1599
1600 spi_imx_push(spi_imx);
1601
1602 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1603
1604 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1605 spi_imx->target_aborted) {
1606 dev_dbg(&spi->dev, "interrupted\n");
1607 ret = -EINTR;
1608 }
1609
1610 /* ecspi has a HW issue when works in Target mode,
1611 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1612 * ECSPI_TXDATA keeps shift out the last word data,
1613 * so we have to disable ECSPI when in target mode after the
1614 * transfer completes
1615 */
1616 if (spi_imx->devtype_data->disable)
1617 spi_imx->devtype_data->disable(spi_imx);
1618
1619 return ret;
1620 }
1621
1622 static int spi_imx_transfer_one(struct spi_controller *controller,
1623 struct spi_device *spi,
1624 struct spi_transfer *transfer)
1625 {
1626 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1627 unsigned long hz_per_byte, byte_limit;
1628
1629 spi_imx_setupxfer(spi, transfer);
1630 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1631
1632 /* flush rxfifo before transfer */
1633 while (spi_imx->devtype_data->rx_available(spi_imx))
1634 readl(spi_imx->base + MXC_CSPIRXDATA);
1635
1636 if (spi_imx->target_mode)
1637 return spi_imx_pio_transfer_target(spi, transfer);
1638
1639 /*
1640 * If we decided in spi_imx_can_dma() that we want to do a DMA
1641 * transfer, the SPI transfer has already been mapped, so we
1642 * have to do the DMA transfer here.
1643 */
1644 if (spi_imx->usedma)
1645 return spi_imx_dma_transfer(spi_imx, transfer);
1646 /*
1647 * Calculate the estimated time in us the transfer runs. Find
1648 * the number of Hz per byte per polling limit.
1649 */
1650 hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
1651 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
1652
1653 /* run in polling mode for short transfers */
1654 if (transfer->len < byte_limit)
1655 return spi_imx_poll_transfer(spi, transfer);
1656
1657 return spi_imx_pio_transfer(spi, transfer);
1658 }
1659
1660 static int spi_imx_setup(struct spi_device *spi)
1661 {
1662 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1663 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1664
1665 return 0;
1666 }
1667
1668 static void spi_imx_cleanup(struct spi_device *spi)
1669 {
1670 }
1671
1672 static int
1673 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1674 {
1675 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1676 int ret;
1677
1678 ret = pm_runtime_resume_and_get(spi_imx->dev);
1679 if (ret < 0) {
1680 dev_err(spi_imx->dev, "failed to enable clock\n");
1681 return ret;
1682 }
1683
1684 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1685 if (ret) {
1686 pm_runtime_mark_last_busy(spi_imx->dev);
1687 pm_runtime_put_autosuspend(spi_imx->dev);
1688 }
1689
1690 return ret;
1691 }
1692
1693 static int
1694 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1695 {
1696 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1697
1698 pm_runtime_mark_last_busy(spi_imx->dev);
1699 pm_runtime_put_autosuspend(spi_imx->dev);
1700 return 0;
1701 }
1702
1703 static int spi_imx_target_abort(struct spi_controller *controller)
1704 {
1705 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1706
1707 spi_imx->target_aborted = true;
1708 complete(&spi_imx->xfer_done);
1709
1710 return 0;
1711 }
1712
1713 static int spi_imx_probe(struct platform_device *pdev)
1714 {
1715 struct device_node *np = pdev->dev.of_node;
1716 struct spi_controller *controller;
1717 struct spi_imx_data *spi_imx;
1718 struct resource *res;
1719 int ret, irq, spi_drctl;
1720 const struct spi_imx_devtype_data *devtype_data =
1721 of_device_get_match_data(&pdev->dev);
1722 bool target_mode;
1723 u32 val;
1724
1725 target_mode = devtype_data->has_targetmode &&
1726 of_property_read_bool(np, "spi-slave");
1727 if (target_mode)
1728 controller = spi_alloc_target(&pdev->dev,
1729 sizeof(struct spi_imx_data));
1730 else
1731 controller = spi_alloc_host(&pdev->dev,
1732 sizeof(struct spi_imx_data));
1733 if (!controller)
1734 return -ENOMEM;
1735
1736 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1737 if ((ret < 0) || (spi_drctl >= 0x3)) {
1738 /* '11' is reserved */
1739 spi_drctl = 0;
1740 }
1741
1742 platform_set_drvdata(pdev, controller);
1743
1744 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1745 controller->bus_num = np ? -1 : pdev->id;
1746 controller->use_gpio_descriptors = true;
1747
1748 spi_imx = spi_controller_get_devdata(controller);
1749 spi_imx->controller = controller;
1750 spi_imx->dev = &pdev->dev;
1751 spi_imx->target_mode = target_mode;
1752
1753 spi_imx->devtype_data = devtype_data;
1754
1755 /*
1756 * Get number of chip selects from device properties. This can be
1757 * coming from device tree or boardfiles, if it is not defined,
1758 * a default value of 3 chip selects will be used, as all the legacy
1759 * board files have <= 3 chip selects.
1760 */
1761 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1762 controller->num_chipselect = val;
1763 else
1764 controller->num_chipselect = 3;
1765
1766 controller->transfer_one = spi_imx_transfer_one;
1767 controller->setup = spi_imx_setup;
1768 controller->cleanup = spi_imx_cleanup;
1769 controller->prepare_message = spi_imx_prepare_message;
1770 controller->unprepare_message = spi_imx_unprepare_message;
1771 controller->target_abort = spi_imx_target_abort;
1772 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1773 SPI_MOSI_IDLE_LOW;
1774
1775 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1776 is_imx53_ecspi(spi_imx))
1777 controller->mode_bits |= SPI_LOOP | SPI_READY;
1778
1779 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1780 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1781
1782 if (is_imx51_ecspi(spi_imx) &&
1783 device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1784 /*
1785 * When using HW-CS implementing SPI_CS_WORD can be done by just
1786 * setting the burst length to the word size. This is
1787 * considerably faster than manually controlling the CS.
1788 */
1789 controller->mode_bits |= SPI_CS_WORD;
1790
1791 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1792 controller->max_native_cs = 4;
1793 controller->flags |= SPI_CONTROLLER_GPIO_SS;
1794 }
1795
1796 spi_imx->spi_drctl = spi_drctl;
1797
1798 init_completion(&spi_imx->xfer_done);
1799
1800 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1801 if (IS_ERR(spi_imx->base)) {
1802 ret = PTR_ERR(spi_imx->base);
1803 goto out_controller_put;
1804 }
1805 spi_imx->base_phys = res->start;
1806
1807 irq = platform_get_irq(pdev, 0);
1808 if (irq < 0) {
1809 ret = irq;
1810 goto out_controller_put;
1811 }
1812
1813 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1814 dev_name(&pdev->dev), spi_imx);
1815 if (ret) {
1816 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1817 goto out_controller_put;
1818 }
1819
1820 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1821 if (IS_ERR(spi_imx->clk_ipg)) {
1822 ret = PTR_ERR(spi_imx->clk_ipg);
1823 goto out_controller_put;
1824 }
1825
1826 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1827 if (IS_ERR(spi_imx->clk_per)) {
1828 ret = PTR_ERR(spi_imx->clk_per);
1829 goto out_controller_put;
1830 }
1831
1832 ret = clk_prepare_enable(spi_imx->clk_per);
1833 if (ret)
1834 goto out_controller_put;
1835
1836 ret = clk_prepare_enable(spi_imx->clk_ipg);
1837 if (ret)
1838 goto out_put_per;
1839
1840 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1841 pm_runtime_use_autosuspend(spi_imx->dev);
1842 pm_runtime_get_noresume(spi_imx->dev);
1843 pm_runtime_set_active(spi_imx->dev);
1844 pm_runtime_enable(spi_imx->dev);
1845
1846 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1847 /*
1848 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1849 * if validated on other chips.
1850 */
1851 if (spi_imx->devtype_data->has_dmamode) {
1852 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1853 if (ret == -EPROBE_DEFER)
1854 goto out_runtime_pm_put;
1855
1856 if (ret < 0)
1857 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1858 ret);
1859 }
1860
1861 spi_imx->devtype_data->reset(spi_imx);
1862
1863 spi_imx->devtype_data->intctrl(spi_imx, 0);
1864
1865 controller->dev.of_node = pdev->dev.of_node;
1866 ret = spi_register_controller(controller);
1867 if (ret) {
1868 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1869 goto out_register_controller;
1870 }
1871
1872 pm_runtime_mark_last_busy(spi_imx->dev);
1873 pm_runtime_put_autosuspend(spi_imx->dev);
1874
1875 return ret;
1876
1877 out_register_controller:
1878 if (spi_imx->devtype_data->has_dmamode)
1879 spi_imx_sdma_exit(spi_imx);
1880 out_runtime_pm_put:
1881 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1882 pm_runtime_set_suspended(&pdev->dev);
1883 pm_runtime_disable(spi_imx->dev);
1884
1885 clk_disable_unprepare(spi_imx->clk_ipg);
1886 out_put_per:
1887 clk_disable_unprepare(spi_imx->clk_per);
1888 out_controller_put:
1889 spi_controller_put(controller);
1890
1891 return ret;
1892 }
1893
1894 static void spi_imx_remove(struct platform_device *pdev)
1895 {
1896 struct spi_controller *controller = platform_get_drvdata(pdev);
1897 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1898 int ret;
1899
1900 spi_unregister_controller(controller);
1901
1902 ret = pm_runtime_get_sync(spi_imx->dev);
1903 if (ret >= 0)
1904 writel(0, spi_imx->base + MXC_CSPICTRL);
1905 else
1906 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1907
1908 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1909 pm_runtime_put_sync(spi_imx->dev);
1910 pm_runtime_disable(spi_imx->dev);
1911
1912 spi_imx_sdma_exit(spi_imx);
1913 }
1914
1915 static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1916 {
1917 struct spi_controller *controller = dev_get_drvdata(dev);
1918 struct spi_imx_data *spi_imx;
1919 int ret;
1920
1921 spi_imx = spi_controller_get_devdata(controller);
1922
1923 ret = clk_prepare_enable(spi_imx->clk_per);
1924 if (ret)
1925 return ret;
1926
1927 ret = clk_prepare_enable(spi_imx->clk_ipg);
1928 if (ret) {
1929 clk_disable_unprepare(spi_imx->clk_per);
1930 return ret;
1931 }
1932
1933 return 0;
1934 }
1935
1936 static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1937 {
1938 struct spi_controller *controller = dev_get_drvdata(dev);
1939 struct spi_imx_data *spi_imx;
1940
1941 spi_imx = spi_controller_get_devdata(controller);
1942
1943 clk_disable_unprepare(spi_imx->clk_per);
1944 clk_disable_unprepare(spi_imx->clk_ipg);
1945
1946 return 0;
1947 }
1948
1949 static int __maybe_unused spi_imx_suspend(struct device *dev)
1950 {
1951 pinctrl_pm_select_sleep_state(dev);
1952 return 0;
1953 }
1954
1955 static int __maybe_unused spi_imx_resume(struct device *dev)
1956 {
1957 pinctrl_pm_select_default_state(dev);
1958 return 0;
1959 }
1960
1961 static const struct dev_pm_ops imx_spi_pm = {
1962 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1963 spi_imx_runtime_resume, NULL)
1964 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1965 };
1966
1967 static struct platform_driver spi_imx_driver = {
1968 .driver = {
1969 .name = DRIVER_NAME,
1970 .of_match_table = spi_imx_dt_ids,
1971 .pm = &imx_spi_pm,
1972 },
1973 .probe = spi_imx_probe,
1974 .remove_new = spi_imx_remove,
1975 };
1976 module_platform_driver(spi_imx_driver);
1977
1978 MODULE_DESCRIPTION("i.MX SPI Controller driver");
1979 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1980 MODULE_LICENSE("GPL");
1981 MODULE_ALIAS("platform:" DRIVER_NAME);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git