1 // SPDX-License-Identifier: GPL-2.0+
4 * NXP FlexSPI(FSPI) controller driver.
6 * Copyright 2019-2020 NXP
7 * Copyright 2020 Puresoftware Ltd.
9 * FlexSPI is a flexsible SPI host controller which supports two SPI
10 * channels and up to 4 external devices. Each channel supports
11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
16 * A valid sequence consists of four LUT registers.
17 * Maximum 32 LUT sequences can be programmed simultaneously.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
22 * Software triggered Flash read/write access by IP Bus.
24 * Memory mapped read access by AHB Bus.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
30 * Boris Brezillon <bbrezillon@kernel.org>
31 * Frieder Schrempf <frieder.schrempf@kontron.de>
34 #include <linux/acpi.h>
35 #include <linux/bitops.h>
36 #include <linux/bitfield.h>
37 #include <linux/clk.h>
38 #include <linux/completion.h>
39 #include <linux/delay.h>
40 #include <linux/err.h>
41 #include <linux/errno.h>
42 #include <linux/interrupt.h>
44 #include <linux/iopoll.h>
45 #include <linux/jiffies.h>
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/mutex.h>
50 #include <linux/platform_device.h>
51 #include <linux/pm_qos.h>
52 #include <linux/regmap.h>
53 #include <linux/sizes.h>
54 #include <linux/sys_soc.h>
56 #include <linux/mfd/syscon.h>
57 #include <linux/spi/spi.h>
58 #include <linux/spi/spi-mem.h>
61 * The driver only uses one single LUT entry, that is updated on
62 * each call of exec_op(). Index 0 is preset at boot with a basic
63 * read operation, so let's use the last entry (31).
67 /* Registers used by the driver */
68 #define FSPI_MCR0 0x00
69 #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
70 #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
71 #define FSPI_MCR0_LEARN_EN BIT(15)
72 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
73 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
74 #define FSPI_MCR0_DOZE_EN BIT(12)
75 #define FSPI_MCR0_HSEN BIT(11)
76 #define FSPI_MCR0_SERCLKDIV BIT(8)
77 #define FSPI_MCR0_ATDF_EN BIT(7)
78 #define FSPI_MCR0_ARDF_EN BIT(6)
79 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
80 #define FSPI_MCR0_END_CFG(x) ((x) << 2)
81 #define FSPI_MCR0_MDIS BIT(1)
82 #define FSPI_MCR0_SWRST BIT(0)
84 #define FSPI_MCR1 0x04
85 #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
86 #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
88 #define FSPI_MCR2 0x08
89 #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
90 #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
91 #define FSPI_MCR2_CLRLRPHS BIT(14)
92 #define FSPI_MCR2_ABRDATSZ BIT(8)
93 #define FSPI_MCR2_ABRLEARN BIT(7)
94 #define FSPI_MCR2_ABR_READ BIT(6)
95 #define FSPI_MCR2_ABRWRITE BIT(5)
96 #define FSPI_MCR2_ABRDUMMY BIT(4)
97 #define FSPI_MCR2_ABR_MODE BIT(3)
98 #define FSPI_MCR2_ABRCADDR BIT(2)
99 #define FSPI_MCR2_ABRRADDR BIT(1)
100 #define FSPI_MCR2_ABR_CMD BIT(0)
102 #define FSPI_AHBCR 0x0c
103 #define FSPI_AHBCR_RDADDROPT BIT(6)
104 #define FSPI_AHBCR_PREF_EN BIT(5)
105 #define FSPI_AHBCR_BUFF_EN BIT(4)
106 #define FSPI_AHBCR_CACH_EN BIT(3)
107 #define FSPI_AHBCR_CLRTXBUF BIT(2)
108 #define FSPI_AHBCR_CLRRXBUF BIT(1)
109 #define FSPI_AHBCR_PAR_EN BIT(0)
111 #define FSPI_INTEN 0x10
112 #define FSPI_INTEN_SCLKSBWR BIT(9)
113 #define FSPI_INTEN_SCLKSBRD BIT(8)
114 #define FSPI_INTEN_DATALRNFL BIT(7)
115 #define FSPI_INTEN_IPTXWE BIT(6)
116 #define FSPI_INTEN_IPRXWA BIT(5)
117 #define FSPI_INTEN_AHBCMDERR BIT(4)
118 #define FSPI_INTEN_IPCMDERR BIT(3)
119 #define FSPI_INTEN_AHBCMDGE BIT(2)
120 #define FSPI_INTEN_IPCMDGE BIT(1)
121 #define FSPI_INTEN_IPCMDDONE BIT(0)
123 #define FSPI_INTR 0x14
124 #define FSPI_INTR_SCLKSBWR BIT(9)
125 #define FSPI_INTR_SCLKSBRD BIT(8)
126 #define FSPI_INTR_DATALRNFL BIT(7)
127 #define FSPI_INTR_IPTXWE BIT(6)
128 #define FSPI_INTR_IPRXWA BIT(5)
129 #define FSPI_INTR_AHBCMDERR BIT(4)
130 #define FSPI_INTR_IPCMDERR BIT(3)
131 #define FSPI_INTR_AHBCMDGE BIT(2)
132 #define FSPI_INTR_IPCMDGE BIT(1)
133 #define FSPI_INTR_IPCMDDONE BIT(0)
135 #define FSPI_LUTKEY 0x18
136 #define FSPI_LUTKEY_VALUE 0x5AF05AF0
138 #define FSPI_LCKCR 0x1C
140 #define FSPI_LCKER_LOCK 0x1
141 #define FSPI_LCKER_UNLOCK 0x2
143 #define FSPI_BUFXCR_INVALID_MSTRID 0xE
144 #define FSPI_AHBRX_BUF0CR0 0x20
145 #define FSPI_AHBRX_BUF1CR0 0x24
146 #define FSPI_AHBRX_BUF2CR0 0x28
147 #define FSPI_AHBRX_BUF3CR0 0x2C
148 #define FSPI_AHBRX_BUF4CR0 0x30
149 #define FSPI_AHBRX_BUF5CR0 0x34
150 #define FSPI_AHBRX_BUF6CR0 0x38
151 #define FSPI_AHBRX_BUF7CR0 0x3C
152 #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
154 #define FSPI_AHBRX_BUF0CR1 0x40
155 #define FSPI_AHBRX_BUF1CR1 0x44
156 #define FSPI_AHBRX_BUF2CR1 0x48
157 #define FSPI_AHBRX_BUF3CR1 0x4C
158 #define FSPI_AHBRX_BUF4CR1 0x50
159 #define FSPI_AHBRX_BUF5CR1 0x54
160 #define FSPI_AHBRX_BUF6CR1 0x58
161 #define FSPI_AHBRX_BUF7CR1 0x5C
163 #define FSPI_FLSHA1CR0 0x60
164 #define FSPI_FLSHA2CR0 0x64
165 #define FSPI_FLSHB1CR0 0x68
166 #define FSPI_FLSHB2CR0 0x6C
167 #define FSPI_FLSHXCR0_SZ_KB 10
168 #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
170 #define FSPI_FLSHA1CR1 0x70
171 #define FSPI_FLSHA2CR1 0x74
172 #define FSPI_FLSHB1CR1 0x78
173 #define FSPI_FLSHB2CR1 0x7C
174 #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
175 #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
176 #define FSPI_FLSHXCR1_WA BIT(10)
177 #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
178 #define FSPI_FLSHXCR1_TCSS(x) (x)
180 #define FSPI_FLSHA1CR2 0x80
181 #define FSPI_FLSHA2CR2 0x84
182 #define FSPI_FLSHB1CR2 0x88
183 #define FSPI_FLSHB2CR2 0x8C
184 #define FSPI_FLSHXCR2_CLRINSP BIT(24)
185 #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
186 #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
187 #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
188 #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
189 #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
191 #define FSPI_IPCR0 0xA0
193 #define FSPI_IPCR1 0xA4
194 #define FSPI_IPCR1_IPAREN BIT(31)
195 #define FSPI_IPCR1_SEQNUM_SHIFT 24
196 #define FSPI_IPCR1_SEQID_SHIFT 16
197 #define FSPI_IPCR1_IDATSZ(x) (x)
199 #define FSPI_IPCMD 0xB0
200 #define FSPI_IPCMD_TRG BIT(0)
202 #define FSPI_DLPR 0xB4
204 #define FSPI_IPRXFCR 0xB8
205 #define FSPI_IPRXFCR_CLR BIT(0)
206 #define FSPI_IPRXFCR_DMA_EN BIT(1)
207 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
209 #define FSPI_IPTXFCR 0xBC
210 #define FSPI_IPTXFCR_CLR BIT(0)
211 #define FSPI_IPTXFCR_DMA_EN BIT(1)
212 #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
214 #define FSPI_DLLACR 0xC0
215 #define FSPI_DLLACR_OVRDEN BIT(8)
216 #define FSPI_DLLACR_SLVDLY(x) ((x) << 3)
217 #define FSPI_DLLACR_DLLRESET BIT(1)
218 #define FSPI_DLLACR_DLLEN BIT(0)
220 #define FSPI_DLLBCR 0xC4
221 #define FSPI_DLLBCR_OVRDEN BIT(8)
222 #define FSPI_DLLBCR_SLVDLY(x) ((x) << 3)
223 #define FSPI_DLLBCR_DLLRESET BIT(1)
224 #define FSPI_DLLBCR_DLLEN BIT(0)
226 #define FSPI_STS0 0xE0
227 #define FSPI_STS0_DLPHB(x) ((x) << 8)
228 #define FSPI_STS0_DLPHA(x) ((x) << 4)
229 #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
230 #define FSPI_STS0_ARB_IDLE BIT(1)
231 #define FSPI_STS0_SEQ_IDLE BIT(0)
233 #define FSPI_STS1 0xE4
234 #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
235 #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
236 #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
237 #define FSPI_STS1_AHB_ERRID(x) (x)
239 #define FSPI_STS2 0xE8
240 #define FSPI_STS2_BREFLOCK BIT(17)
241 #define FSPI_STS2_BSLVLOCK BIT(16)
242 #define FSPI_STS2_AREFLOCK BIT(1)
243 #define FSPI_STS2_ASLVLOCK BIT(0)
244 #define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \
245 FSPI_STS2_BSLVLOCK | \
246 FSPI_STS2_AREFLOCK | \
249 #define FSPI_AHBSPNST 0xEC
250 #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
251 #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
252 #define FSPI_AHBSPNST_ACTIVE BIT(0)
254 #define FSPI_IPRXFSTS 0xF0
255 #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
256 #define FSPI_IPRXFSTS_FILL(x) (x)
258 #define FSPI_IPTXFSTS 0xF4
259 #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
260 #define FSPI_IPTXFSTS_FILL(x) (x)
262 #define FSPI_RFDR 0x100
263 #define FSPI_TFDR 0x180
265 #define FSPI_LUT_BASE 0x200
266 #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
267 #define FSPI_LUT_REG(idx) \
268 (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
270 /* register map end */
272 /* Instruction set for the LUT register. */
273 #define LUT_STOP 0x00
275 #define LUT_ADDR 0x02
276 #define LUT_CADDR_SDR 0x03
277 #define LUT_MODE 0x04
278 #define LUT_MODE2 0x05
279 #define LUT_MODE4 0x06
280 #define LUT_MODE8 0x07
281 #define LUT_NXP_WRITE 0x08
282 #define LUT_NXP_READ 0x09
283 #define LUT_LEARN_SDR 0x0A
284 #define LUT_DATSZ_SDR 0x0B
285 #define LUT_DUMMY 0x0C
286 #define LUT_DUMMY_RWDS_SDR 0x0D
287 #define LUT_JMP_ON_CS 0x1F
288 #define LUT_CMD_DDR 0x21
289 #define LUT_ADDR_DDR 0x22
290 #define LUT_CADDR_DDR 0x23
291 #define LUT_MODE_DDR 0x24
292 #define LUT_MODE2_DDR 0x25
293 #define LUT_MODE4_DDR 0x26
294 #define LUT_MODE8_DDR 0x27
295 #define LUT_WRITE_DDR 0x28
296 #define LUT_READ_DDR 0x29
297 #define LUT_LEARN_DDR 0x2A
298 #define LUT_DATSZ_DDR 0x2B
299 #define LUT_DUMMY_DDR 0x2C
300 #define LUT_DUMMY_RWDS_DDR 0x2D
303 * Calculate number of required PAD bits for LUT register.
305 * The pad stands for the number of IO lines [0:7].
306 * For example, the octal read needs eight IO lines,
307 * so you should use LUT_PAD(8). This macro
308 * returns 3 i.e. use eight (2^3) IP lines for read.
310 #define LUT_PAD(x) (fls(x) - 1)
313 * Macro for constructing the LUT entries with the following
316 * ---------------------------------------------------
317 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
318 * ---------------------------------------------------
321 #define INSTR_SHIFT 10
322 #define OPRND_SHIFT 16
324 /* Macros for constructing the LUT register. */
325 #define LUT_DEF(idx, ins, pad, opr) \
326 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
327 (opr)) << (((idx) % 2) * OPRND_SHIFT))
329 #define POLL_TOUT 5000
330 #define NXP_FSPI_MAX_CHIPSELECT 4
331 #define NXP_FSPI_MIN_IOMAP SZ_4M
333 #define DCFG_RCWSR1 0x100
334 #define SYS_PLL_RAT GENMASK(6, 2)
336 /* Access flash memory using IP bus only */
337 #define FSPI_QUIRK_USE_IP_ONLY BIT(0)
339 struct nxp_fspi_devtype_data
{
342 unsigned int ahb_buf_size
;
347 static struct nxp_fspi_devtype_data lx2160a_data
= {
348 .rxfifo
= SZ_512
, /* (64 * 64 bits) */
349 .txfifo
= SZ_1K
, /* (128 * 64 bits) */
350 .ahb_buf_size
= SZ_2K
, /* (256 * 64 bits) */
352 .little_endian
= true, /* little-endian */
355 static struct nxp_fspi_devtype_data imx8mm_data
= {
356 .rxfifo
= SZ_512
, /* (64 * 64 bits) */
357 .txfifo
= SZ_1K
, /* (128 * 64 bits) */
358 .ahb_buf_size
= SZ_2K
, /* (256 * 64 bits) */
360 .little_endian
= true, /* little-endian */
363 static struct nxp_fspi_devtype_data imx8qxp_data
= {
364 .rxfifo
= SZ_512
, /* (64 * 64 bits) */
365 .txfifo
= SZ_1K
, /* (128 * 64 bits) */
366 .ahb_buf_size
= SZ_2K
, /* (256 * 64 bits) */
368 .little_endian
= true, /* little-endian */
371 static struct nxp_fspi_devtype_data imx8dxl_data
= {
372 .rxfifo
= SZ_512
, /* (64 * 64 bits) */
373 .txfifo
= SZ_1K
, /* (128 * 64 bits) */
374 .ahb_buf_size
= SZ_2K
, /* (256 * 64 bits) */
375 .quirks
= FSPI_QUIRK_USE_IP_ONLY
,
376 .little_endian
= true, /* little-endian */
380 void __iomem
*iobase
;
381 void __iomem
*ahb_addr
;
386 struct clk
*clk
, *clk_en
;
389 struct nxp_fspi_devtype_data
*devtype_data
;
391 struct pm_qos_request pm_qos_req
;
395 static inline int needs_ip_only(struct nxp_fspi
*f
)
397 return f
->devtype_data
->quirks
& FSPI_QUIRK_USE_IP_ONLY
;
401 * R/W functions for big- or little-endian registers:
402 * The FSPI controller's endianness is independent of
403 * the CPU core's endianness. So far, although the CPU
404 * core is little-endian the FSPI controller can use
405 * big-endian or little-endian.
407 static void fspi_writel(struct nxp_fspi
*f
, u32 val
, void __iomem
*addr
)
409 if (f
->devtype_data
->little_endian
)
410 iowrite32(val
, addr
);
412 iowrite32be(val
, addr
);
415 static u32
fspi_readl(struct nxp_fspi
*f
, void __iomem
*addr
)
417 if (f
->devtype_data
->little_endian
)
418 return ioread32(addr
);
420 return ioread32be(addr
);
423 static irqreturn_t
nxp_fspi_irq_handler(int irq
, void *dev_id
)
425 struct nxp_fspi
*f
= dev_id
;
428 /* clear interrupt */
429 reg
= fspi_readl(f
, f
->iobase
+ FSPI_INTR
);
430 fspi_writel(f
, FSPI_INTR_IPCMDDONE
, f
->iobase
+ FSPI_INTR
);
432 if (reg
& FSPI_INTR_IPCMDDONE
)
438 static int nxp_fspi_check_buswidth(struct nxp_fspi
*f
, u8 width
)
451 static bool nxp_fspi_supports_op(struct spi_mem
*mem
,
452 const struct spi_mem_op
*op
)
454 struct nxp_fspi
*f
= spi_controller_get_devdata(mem
->spi
->master
);
457 ret
= nxp_fspi_check_buswidth(f
, op
->cmd
.buswidth
);
460 ret
|= nxp_fspi_check_buswidth(f
, op
->addr
.buswidth
);
462 if (op
->dummy
.nbytes
)
463 ret
|= nxp_fspi_check_buswidth(f
, op
->dummy
.buswidth
);
466 ret
|= nxp_fspi_check_buswidth(f
, op
->data
.buswidth
);
472 * The number of address bytes should be equal to or less than 4 bytes.
474 if (op
->addr
.nbytes
> 4)
478 * If requested address value is greater than controller assigned
479 * memory mapped space, return error as it didn't fit in the range
480 * of assigned address space.
482 if (op
->addr
.val
>= f
->memmap_phy_size
)
485 /* Max 64 dummy clock cycles supported */
486 if (op
->dummy
.buswidth
&&
487 (op
->dummy
.nbytes
* 8 / op
->dummy
.buswidth
> 64))
490 /* Max data length, check controller limits and alignment */
491 if (op
->data
.dir
== SPI_MEM_DATA_IN
&&
492 (op
->data
.nbytes
> f
->devtype_data
->ahb_buf_size
||
493 (op
->data
.nbytes
> f
->devtype_data
->rxfifo
- 4 &&
494 !IS_ALIGNED(op
->data
.nbytes
, 8))))
497 if (op
->data
.dir
== SPI_MEM_DATA_OUT
&&
498 op
->data
.nbytes
> f
->devtype_data
->txfifo
)
501 return spi_mem_default_supports_op(mem
, op
);
504 /* Instead of busy looping invoke readl_poll_timeout functionality. */
505 static int fspi_readl_poll_tout(struct nxp_fspi
*f
, void __iomem
*base
,
506 u32 mask
, u32 delay_us
,
507 u32 timeout_us
, bool c
)
511 if (!f
->devtype_data
->little_endian
)
512 mask
= (u32
)cpu_to_be32(mask
);
515 return readl_poll_timeout(base
, reg
, (reg
& mask
),
516 delay_us
, timeout_us
);
518 return readl_poll_timeout(base
, reg
, !(reg
& mask
),
519 delay_us
, timeout_us
);
523 * If the slave device content being changed by Write/Erase, need to
524 * invalidate the AHB buffer. This can be achieved by doing the reset
525 * of controller after setting MCR0[SWRESET] bit.
527 static inline void nxp_fspi_invalid(struct nxp_fspi
*f
)
532 reg
= fspi_readl(f
, f
->iobase
+ FSPI_MCR0
);
533 fspi_writel(f
, reg
| FSPI_MCR0_SWRST
, f
->iobase
+ FSPI_MCR0
);
535 /* w1c register, wait unit clear */
536 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_MCR0
,
537 FSPI_MCR0_SWRST
, 0, POLL_TOUT
, false);
541 static void nxp_fspi_prepare_lut(struct nxp_fspi
*f
,
542 const struct spi_mem_op
*op
)
544 void __iomem
*base
= f
->iobase
;
549 lutval
[0] |= LUT_DEF(0, LUT_CMD
, LUT_PAD(op
->cmd
.buswidth
),
553 if (op
->addr
.nbytes
) {
554 lutval
[lutidx
/ 2] |= LUT_DEF(lutidx
, LUT_ADDR
,
555 LUT_PAD(op
->addr
.buswidth
),
556 op
->addr
.nbytes
* 8);
560 /* dummy bytes, if needed */
561 if (op
->dummy
.nbytes
) {
562 lutval
[lutidx
/ 2] |= LUT_DEF(lutidx
, LUT_DUMMY
,
564 * Due to FlexSPI controller limitation number of PAD for dummy
565 * buswidth needs to be programmed as equal to data buswidth.
567 LUT_PAD(op
->data
.buswidth
),
568 op
->dummy
.nbytes
* 8 /
573 /* read/write data bytes */
574 if (op
->data
.nbytes
) {
575 lutval
[lutidx
/ 2] |= LUT_DEF(lutidx
,
576 op
->data
.dir
== SPI_MEM_DATA_IN
?
577 LUT_NXP_READ
: LUT_NXP_WRITE
,
578 LUT_PAD(op
->data
.buswidth
),
583 /* stop condition. */
584 lutval
[lutidx
/ 2] |= LUT_DEF(lutidx
, LUT_STOP
, 0, 0);
587 fspi_writel(f
, FSPI_LUTKEY_VALUE
, f
->iobase
+ FSPI_LUTKEY
);
588 fspi_writel(f
, FSPI_LCKER_UNLOCK
, f
->iobase
+ FSPI_LCKCR
);
591 for (i
= 0; i
< ARRAY_SIZE(lutval
); i
++)
592 fspi_writel(f
, lutval
[i
], base
+ FSPI_LUT_REG(i
));
594 dev_dbg(f
->dev
, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n",
595 op
->cmd
.opcode
, lutval
[0], lutval
[1], lutval
[2], lutval
[3], op
->data
.nbytes
);
598 fspi_writel(f
, FSPI_LUTKEY_VALUE
, f
->iobase
+ FSPI_LUTKEY
);
599 fspi_writel(f
, FSPI_LCKER_LOCK
, f
->iobase
+ FSPI_LCKCR
);
602 static int nxp_fspi_clk_prep_enable(struct nxp_fspi
*f
)
606 if (is_acpi_node(dev_fwnode(f
->dev
)))
609 ret
= clk_prepare_enable(f
->clk_en
);
613 ret
= clk_prepare_enable(f
->clk
);
615 clk_disable_unprepare(f
->clk_en
);
622 static int nxp_fspi_clk_disable_unprep(struct nxp_fspi
*f
)
624 if (is_acpi_node(dev_fwnode(f
->dev
)))
627 clk_disable_unprepare(f
->clk
);
628 clk_disable_unprepare(f
->clk_en
);
633 static void nxp_fspi_dll_calibration(struct nxp_fspi
*f
)
637 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */
638 fspi_writel(f
, FSPI_DLLACR_DLLRESET
, f
->iobase
+ FSPI_DLLACR
);
639 fspi_writel(f
, FSPI_DLLBCR_DLLRESET
, f
->iobase
+ FSPI_DLLBCR
);
640 fspi_writel(f
, 0, f
->iobase
+ FSPI_DLLACR
);
641 fspi_writel(f
, 0, f
->iobase
+ FSPI_DLLBCR
);
644 * Enable the DLL calibration mode.
645 * The delay target for slave delay line is:
646 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock.
647 * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which
648 * means half of clock cycle of reference clock.
650 fspi_writel(f
, FSPI_DLLACR_DLLEN
| FSPI_DLLACR_SLVDLY(0xF),
651 f
->iobase
+ FSPI_DLLACR
);
652 fspi_writel(f
, FSPI_DLLBCR_DLLEN
| FSPI_DLLBCR_SLVDLY(0xF),
653 f
->iobase
+ FSPI_DLLBCR
);
655 /* Wait to get REF/SLV lock */
656 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_STS2
, FSPI_STS2_AB_LOCK
,
659 dev_warn(f
->dev
, "DLL lock failed, please fix it!\n");
663 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
664 * register and start base address of the slave device.
667 * -------- <-- FLSHB2CR0
670 * B2 start address --> -------- <-- FLSHB1CR0
673 * B1 start address --> -------- <-- FLSHA2CR0
676 * A2 start address --> -------- <-- FLSHA1CR0
679 * A1 start address --> -------- (Lower address)
682 * Start base address defines the starting address range for given CS and
683 * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
685 * But, different targets are having different combinations of number of CS,
686 * some targets only have single CS or two CS covering controller's full
687 * memory mapped space area.
688 * Thus, implementation is being done as independent of the size and number
689 * of the connected slave device.
690 * Assign controller memory mapped space size as the size to the connected
692 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
693 * chip-select Flash configuration register.
695 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
696 * memory mapped size of the controller.
697 * Value for rest of the CS FLSHxxCR0 register would be zero.
700 static void nxp_fspi_select_mem(struct nxp_fspi
*f
, struct spi_device
*spi
)
702 unsigned long rate
= spi
->max_speed_hz
;
707 * Return, if previously selected slave device is same as current
708 * requested slave device.
710 if (f
->selected
== spi_get_chipselect(spi
, 0))
713 /* Reset FLSHxxCR0 registers */
714 fspi_writel(f
, 0, f
->iobase
+ FSPI_FLSHA1CR0
);
715 fspi_writel(f
, 0, f
->iobase
+ FSPI_FLSHA2CR0
);
716 fspi_writel(f
, 0, f
->iobase
+ FSPI_FLSHB1CR0
);
717 fspi_writel(f
, 0, f
->iobase
+ FSPI_FLSHB2CR0
);
719 /* Assign controller memory mapped space as size, KBytes, of flash. */
720 size_kb
= FSPI_FLSHXCR0_SZ(f
->memmap_phy_size
);
722 fspi_writel(f
, size_kb
, f
->iobase
+ FSPI_FLSHA1CR0
+
723 4 * spi_get_chipselect(spi
, 0));
725 dev_dbg(f
->dev
, "Slave device [CS:%x] selected\n", spi_get_chipselect(spi
, 0));
727 nxp_fspi_clk_disable_unprep(f
);
729 ret
= clk_set_rate(f
->clk
, rate
);
733 ret
= nxp_fspi_clk_prep_enable(f
);
738 * If clock rate > 100MHz, then switch from DLL override mode to
739 * DLL calibration mode.
741 if (rate
> 100000000)
742 nxp_fspi_dll_calibration(f
);
744 f
->selected
= spi_get_chipselect(spi
, 0);
747 static int nxp_fspi_read_ahb(struct nxp_fspi
*f
, const struct spi_mem_op
*op
)
749 u32 start
= op
->addr
.val
;
750 u32 len
= op
->data
.nbytes
;
752 /* if necessary, ioremap before AHB read */
753 if ((!f
->ahb_addr
) || start
< f
->memmap_start
||
754 start
+ len
> f
->memmap_start
+ f
->memmap_len
) {
756 iounmap(f
->ahb_addr
);
758 f
->memmap_start
= start
;
759 f
->memmap_len
= len
> NXP_FSPI_MIN_IOMAP
?
760 len
: NXP_FSPI_MIN_IOMAP
;
762 f
->ahb_addr
= ioremap_wc(f
->memmap_phy
+ f
->memmap_start
,
766 dev_err(f
->dev
, "failed to alloc memory\n");
771 /* Read out the data directly from the AHB buffer. */
772 memcpy_fromio(op
->data
.buf
.in
,
773 f
->ahb_addr
+ start
- f
->memmap_start
, len
);
778 static void nxp_fspi_fill_txfifo(struct nxp_fspi
*f
,
779 const struct spi_mem_op
*op
)
781 void __iomem
*base
= f
->iobase
;
783 u8
*buf
= (u8
*) op
->data
.buf
.out
;
785 /* clear the TX FIFO. */
786 fspi_writel(f
, FSPI_IPTXFCR_CLR
, base
+ FSPI_IPTXFCR
);
789 * Default value of water mark level is 8 bytes, hence in single
790 * write request controller can write max 8 bytes of data.
793 for (i
= 0; i
< ALIGN_DOWN(op
->data
.nbytes
, 8); i
+= 8) {
794 /* Wait for TXFIFO empty */
795 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_INTR
,
800 fspi_writel(f
, *(u32
*) (buf
+ i
), base
+ FSPI_TFDR
);
801 fspi_writel(f
, *(u32
*) (buf
+ i
+ 4), base
+ FSPI_TFDR
+ 4);
802 fspi_writel(f
, FSPI_INTR_IPTXWE
, base
+ FSPI_INTR
);
805 if (i
< op
->data
.nbytes
) {
808 /* Wait for TXFIFO empty */
809 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_INTR
,
814 for (j
= 0; j
< ALIGN(op
->data
.nbytes
- i
, 4); j
+= 4) {
815 memcpy(&data
, buf
+ i
+ j
, 4);
816 fspi_writel(f
, data
, base
+ FSPI_TFDR
+ j
);
818 fspi_writel(f
, FSPI_INTR_IPTXWE
, base
+ FSPI_INTR
);
822 static void nxp_fspi_read_rxfifo(struct nxp_fspi
*f
,
823 const struct spi_mem_op
*op
)
825 void __iomem
*base
= f
->iobase
;
827 int len
= op
->data
.nbytes
;
828 u8
*buf
= (u8
*) op
->data
.buf
.in
;
831 * Default value of water mark level is 8 bytes, hence in single
832 * read request controller can read max 8 bytes of data.
834 for (i
= 0; i
< ALIGN_DOWN(len
, 8); i
+= 8) {
835 /* Wait for RXFIFO available */
836 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_INTR
,
841 *(u32
*)(buf
+ i
) = fspi_readl(f
, base
+ FSPI_RFDR
);
842 *(u32
*)(buf
+ i
+ 4) = fspi_readl(f
, base
+ FSPI_RFDR
+ 4);
843 /* move the FIFO pointer */
844 fspi_writel(f
, FSPI_INTR_IPRXWA
, base
+ FSPI_INTR
);
851 buf
= op
->data
.buf
.in
+ i
;
852 /* Wait for RXFIFO available */
853 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_INTR
,
858 len
= op
->data
.nbytes
- i
;
859 for (j
= 0; j
< op
->data
.nbytes
- i
; j
+= 4) {
860 tmp
= fspi_readl(f
, base
+ FSPI_RFDR
+ j
);
862 memcpy(buf
+ j
, &tmp
, size
);
867 /* invalid the RXFIFO */
868 fspi_writel(f
, FSPI_IPRXFCR_CLR
, base
+ FSPI_IPRXFCR
);
869 /* move the FIFO pointer */
870 fspi_writel(f
, FSPI_INTR_IPRXWA
, base
+ FSPI_INTR
);
873 static int nxp_fspi_do_op(struct nxp_fspi
*f
, const struct spi_mem_op
*op
)
875 void __iomem
*base
= f
->iobase
;
880 reg
= fspi_readl(f
, base
+ FSPI_IPRXFCR
);
881 /* invalid RXFIFO first */
882 reg
&= ~FSPI_IPRXFCR_DMA_EN
;
883 reg
= reg
| FSPI_IPRXFCR_CLR
;
884 fspi_writel(f
, reg
, base
+ FSPI_IPRXFCR
);
886 init_completion(&f
->c
);
888 fspi_writel(f
, op
->addr
.val
, base
+ FSPI_IPCR0
);
890 * Always start the sequence at the same index since we update
891 * the LUT at each exec_op() call. And also specify the DATA
892 * length, since it's has not been specified in the LUT.
894 fspi_writel(f
, op
->data
.nbytes
|
895 (SEQID_LUT
<< FSPI_IPCR1_SEQID_SHIFT
) |
896 (seqnum
<< FSPI_IPCR1_SEQNUM_SHIFT
),
899 /* Trigger the LUT now. */
900 fspi_writel(f
, FSPI_IPCMD_TRG
, base
+ FSPI_IPCMD
);
902 /* Wait for the interrupt. */
903 if (!wait_for_completion_timeout(&f
->c
, msecs_to_jiffies(1000)))
906 /* Invoke IP data read, if request is of data read. */
907 if (!err
&& op
->data
.nbytes
&& op
->data
.dir
== SPI_MEM_DATA_IN
)
908 nxp_fspi_read_rxfifo(f
, op
);
913 static int nxp_fspi_exec_op(struct spi_mem
*mem
, const struct spi_mem_op
*op
)
915 struct nxp_fspi
*f
= spi_controller_get_devdata(mem
->spi
->master
);
918 mutex_lock(&f
->lock
);
920 /* Wait for controller being ready. */
921 err
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_STS0
,
922 FSPI_STS0_ARB_IDLE
, 1, POLL_TOUT
, true);
925 nxp_fspi_select_mem(f
, mem
->spi
);
927 nxp_fspi_prepare_lut(f
, op
);
929 * If we have large chunks of data, we read them through the AHB bus by
930 * accessing the mapped memory. In all other cases we use IP commands
931 * to access the flash. Read via AHB bus may be corrupted due to
932 * existence of an errata and therefore discard AHB read in such cases.
934 if (op
->data
.nbytes
> (f
->devtype_data
->rxfifo
- 4) &&
935 op
->data
.dir
== SPI_MEM_DATA_IN
&&
937 err
= nxp_fspi_read_ahb(f
, op
);
939 if (op
->data
.nbytes
&& op
->data
.dir
== SPI_MEM_DATA_OUT
)
940 nxp_fspi_fill_txfifo(f
, op
);
942 err
= nxp_fspi_do_op(f
, op
);
945 /* Invalidate the data in the AHB buffer. */
948 mutex_unlock(&f
->lock
);
953 static int nxp_fspi_adjust_op_size(struct spi_mem
*mem
, struct spi_mem_op
*op
)
955 struct nxp_fspi
*f
= spi_controller_get_devdata(mem
->spi
->master
);
957 if (op
->data
.dir
== SPI_MEM_DATA_OUT
) {
958 if (op
->data
.nbytes
> f
->devtype_data
->txfifo
)
959 op
->data
.nbytes
= f
->devtype_data
->txfifo
;
961 if (op
->data
.nbytes
> f
->devtype_data
->ahb_buf_size
)
962 op
->data
.nbytes
= f
->devtype_data
->ahb_buf_size
;
963 else if (op
->data
.nbytes
> (f
->devtype_data
->rxfifo
- 4))
964 op
->data
.nbytes
= ALIGN_DOWN(op
->data
.nbytes
, 8);
967 /* Limit data bytes to RX FIFO in case of IP read only */
968 if (op
->data
.dir
== SPI_MEM_DATA_IN
&&
970 op
->data
.nbytes
> f
->devtype_data
->rxfifo
)
971 op
->data
.nbytes
= f
->devtype_data
->rxfifo
;
976 static void erratum_err050568(struct nxp_fspi
*f
)
978 static const struct soc_device_attribute ls1028a_soc_attr
[] = {
979 { .family
= "QorIQ LS1028A" },
983 u32 val
, sys_pll_ratio
;
986 /* Check for LS1028A family */
987 if (!soc_device_match(ls1028a_soc_attr
)) {
988 dev_dbg(f
->dev
, "Errata applicable only for LS1028A\n");
992 map
= syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg");
994 dev_err(f
->dev
, "No syscon regmap\n");
998 ret
= regmap_read(map
, DCFG_RCWSR1
, &val
);
1002 sys_pll_ratio
= FIELD_GET(SYS_PLL_RAT
, val
);
1003 dev_dbg(f
->dev
, "val: 0x%08x, sys_pll_ratio: %d\n", val
, sys_pll_ratio
);
1005 /* Use IP bus only if platform clock is 300MHz */
1006 if (sys_pll_ratio
== 3)
1007 f
->devtype_data
->quirks
|= FSPI_QUIRK_USE_IP_ONLY
;
1012 dev_err(f
->dev
, "Errata cannot be executed. Read via IP bus may not work\n");
1015 static int nxp_fspi_default_setup(struct nxp_fspi
*f
)
1017 void __iomem
*base
= f
->iobase
;
1021 /* disable and unprepare clock to avoid glitch pass to controller */
1022 nxp_fspi_clk_disable_unprep(f
);
1024 /* the default frequency, we will change it later if necessary. */
1025 ret
= clk_set_rate(f
->clk
, 20000000);
1029 ret
= nxp_fspi_clk_prep_enable(f
);
1034 * ERR050568: Flash access by FlexSPI AHB command may not work with
1035 * platform frequency equal to 300 MHz on LS1028A.
1036 * LS1028A reuses LX2160A compatible entry. Make errata applicable for
1037 * Layerscape LS1028A platform.
1039 if (of_device_is_compatible(f
->dev
->of_node
, "nxp,lx2160a-fspi"))
1040 erratum_err050568(f
);
1042 /* Reset the module */
1043 /* w1c register, wait unit clear */
1044 ret
= fspi_readl_poll_tout(f
, f
->iobase
+ FSPI_MCR0
,
1045 FSPI_MCR0_SWRST
, 0, POLL_TOUT
, false);
1048 /* Disable the module */
1049 fspi_writel(f
, FSPI_MCR0_MDIS
, base
+ FSPI_MCR0
);
1052 * Config the DLL register to default value, enable the slave clock delay
1053 * line delay cell override mode, and use 1 fixed delay cell in DLL delay
1054 * chain, this is the suggested setting when clock rate < 100MHz.
1056 fspi_writel(f
, FSPI_DLLACR_OVRDEN
, base
+ FSPI_DLLACR
);
1057 fspi_writel(f
, FSPI_DLLBCR_OVRDEN
, base
+ FSPI_DLLBCR
);
1060 fspi_writel(f
, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
1061 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32
) FSPI_MCR0_OCTCOMB_EN
,
1065 * Disable same device enable bit and configure all slave devices
1068 reg
= fspi_readl(f
, f
->iobase
+ FSPI_MCR2
);
1069 reg
= reg
& ~(FSPI_MCR2_SAMEDEVICEEN
);
1070 fspi_writel(f
, reg
, base
+ FSPI_MCR2
);
1072 /* AHB configuration for access buffer 0~7. */
1073 for (i
= 0; i
< 7; i
++)
1074 fspi_writel(f
, 0, base
+ FSPI_AHBRX_BUF0CR0
+ 4 * i
);
1077 * Set ADATSZ with the maximum AHB buffer size to improve the read
1080 fspi_writel(f
, (f
->devtype_data
->ahb_buf_size
/ 8 |
1081 FSPI_AHBRXBUF0CR7_PREF
), base
+ FSPI_AHBRX_BUF7CR0
);
1083 /* prefetch and no start address alignment limitation */
1084 fspi_writel(f
, FSPI_AHBCR_PREF_EN
| FSPI_AHBCR_RDADDROPT
,
1087 /* Reset the FLSHxCR1 registers. */
1088 reg
= FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3);
1089 fspi_writel(f
, reg
, base
+ FSPI_FLSHA1CR1
);
1090 fspi_writel(f
, reg
, base
+ FSPI_FLSHA2CR1
);
1091 fspi_writel(f
, reg
, base
+ FSPI_FLSHB1CR1
);
1092 fspi_writel(f
, reg
, base
+ FSPI_FLSHB2CR1
);
1094 /* AHB Read - Set lut sequence ID for all CS. */
1095 fspi_writel(f
, SEQID_LUT
, base
+ FSPI_FLSHA1CR2
);
1096 fspi_writel(f
, SEQID_LUT
, base
+ FSPI_FLSHA2CR2
);
1097 fspi_writel(f
, SEQID_LUT
, base
+ FSPI_FLSHB1CR2
);
1098 fspi_writel(f
, SEQID_LUT
, base
+ FSPI_FLSHB2CR2
);
1102 /* enable the interrupt */
1103 fspi_writel(f
, FSPI_INTEN_IPCMDDONE
, base
+ FSPI_INTEN
);
1108 static const char *nxp_fspi_get_name(struct spi_mem
*mem
)
1110 struct nxp_fspi
*f
= spi_controller_get_devdata(mem
->spi
->master
);
1111 struct device
*dev
= &mem
->spi
->dev
;
1114 // Set custom name derived from the platform_device of the controller.
1115 if (of_get_available_child_count(f
->dev
->of_node
) == 1)
1116 return dev_name(f
->dev
);
1118 name
= devm_kasprintf(dev
, GFP_KERNEL
,
1119 "%s-%d", dev_name(f
->dev
),
1120 spi_get_chipselect(mem
->spi
, 0));
1123 dev_err(dev
, "failed to get memory for custom flash name\n");
1124 return ERR_PTR(-ENOMEM
);
1130 static const struct spi_controller_mem_ops nxp_fspi_mem_ops
= {
1131 .adjust_op_size
= nxp_fspi_adjust_op_size
,
1132 .supports_op
= nxp_fspi_supports_op
,
1133 .exec_op
= nxp_fspi_exec_op
,
1134 .get_name
= nxp_fspi_get_name
,
1137 static int nxp_fspi_probe(struct platform_device
*pdev
)
1139 struct spi_controller
*ctlr
;
1140 struct device
*dev
= &pdev
->dev
;
1141 struct device_node
*np
= dev
->of_node
;
1142 struct resource
*res
;
1147 ctlr
= spi_alloc_master(&pdev
->dev
, sizeof(*f
));
1151 ctlr
->mode_bits
= SPI_RX_DUAL
| SPI_RX_QUAD
| SPI_RX_OCTAL
|
1152 SPI_TX_DUAL
| SPI_TX_QUAD
| SPI_TX_OCTAL
;
1154 f
= spi_controller_get_devdata(ctlr
);
1156 f
->devtype_data
= (struct nxp_fspi_devtype_data
*)device_get_match_data(dev
);
1157 if (!f
->devtype_data
) {
1162 platform_set_drvdata(pdev
, f
);
1164 /* find the resources - configuration register address space */
1165 if (is_acpi_node(dev_fwnode(f
->dev
)))
1166 f
->iobase
= devm_platform_ioremap_resource(pdev
, 0);
1168 f
->iobase
= devm_platform_ioremap_resource_byname(pdev
, "fspi_base");
1170 if (IS_ERR(f
->iobase
)) {
1171 ret
= PTR_ERR(f
->iobase
);
1175 /* find the resources - controller memory mapped space */
1176 if (is_acpi_node(dev_fwnode(f
->dev
)))
1177 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1179 res
= platform_get_resource_byname(pdev
,
1180 IORESOURCE_MEM
, "fspi_mmap");
1187 /* assign memory mapped starting address and mapped size. */
1188 f
->memmap_phy
= res
->start
;
1189 f
->memmap_phy_size
= resource_size(res
);
1191 /* find the clocks */
1192 if (dev_of_node(&pdev
->dev
)) {
1193 f
->clk_en
= devm_clk_get(dev
, "fspi_en");
1194 if (IS_ERR(f
->clk_en
)) {
1195 ret
= PTR_ERR(f
->clk_en
);
1199 f
->clk
= devm_clk_get(dev
, "fspi");
1200 if (IS_ERR(f
->clk
)) {
1201 ret
= PTR_ERR(f
->clk
);
1205 ret
= nxp_fspi_clk_prep_enable(f
);
1207 dev_err(dev
, "can not enable the clock\n");
1212 /* Clear potential interrupts */
1213 reg
= fspi_readl(f
, f
->iobase
+ FSPI_INTR
);
1215 fspi_writel(f
, reg
, f
->iobase
+ FSPI_INTR
);
1218 ret
= platform_get_irq(pdev
, 0);
1220 goto err_disable_clk
;
1222 ret
= devm_request_irq(dev
, ret
,
1223 nxp_fspi_irq_handler
, 0, pdev
->name
, f
);
1225 dev_err(dev
, "failed to request irq: %d\n", ret
);
1226 goto err_disable_clk
;
1229 mutex_init(&f
->lock
);
1232 ctlr
->num_chipselect
= NXP_FSPI_MAX_CHIPSELECT
;
1233 ctlr
->mem_ops
= &nxp_fspi_mem_ops
;
1235 nxp_fspi_default_setup(f
);
1237 ctlr
->dev
.of_node
= np
;
1239 ret
= devm_spi_register_controller(&pdev
->dev
, ctlr
);
1241 goto err_destroy_mutex
;
1246 mutex_destroy(&f
->lock
);
1249 nxp_fspi_clk_disable_unprep(f
);
1252 spi_controller_put(ctlr
);
1254 dev_err(dev
, "NXP FSPI probe failed\n");
1258 static void nxp_fspi_remove(struct platform_device
*pdev
)
1260 struct nxp_fspi
*f
= platform_get_drvdata(pdev
);
1262 /* disable the hardware */
1263 fspi_writel(f
, FSPI_MCR0_MDIS
, f
->iobase
+ FSPI_MCR0
);
1265 nxp_fspi_clk_disable_unprep(f
);
1267 mutex_destroy(&f
->lock
);
1270 iounmap(f
->ahb_addr
);
1273 static int nxp_fspi_suspend(struct device
*dev
)
1278 static int nxp_fspi_resume(struct device
*dev
)
1280 struct nxp_fspi
*f
= dev_get_drvdata(dev
);
1282 nxp_fspi_default_setup(f
);
1287 static const struct of_device_id nxp_fspi_dt_ids
[] = {
1288 { .compatible
= "nxp,lx2160a-fspi", .data
= (void *)&lx2160a_data
, },
1289 { .compatible
= "nxp,imx8mm-fspi", .data
= (void *)&imx8mm_data
, },
1290 { .compatible
= "nxp,imx8mp-fspi", .data
= (void *)&imx8mm_data
, },
1291 { .compatible
= "nxp,imx8qxp-fspi", .data
= (void *)&imx8qxp_data
, },
1292 { .compatible
= "nxp,imx8dxl-fspi", .data
= (void *)&imx8dxl_data
, },
1295 MODULE_DEVICE_TABLE(of
, nxp_fspi_dt_ids
);
1298 static const struct acpi_device_id nxp_fspi_acpi_ids
[] = {
1299 { "NXP0009", .driver_data
= (kernel_ulong_t
)&lx2160a_data
, },
1302 MODULE_DEVICE_TABLE(acpi
, nxp_fspi_acpi_ids
);
1305 static const struct dev_pm_ops nxp_fspi_pm_ops
= {
1306 .suspend
= nxp_fspi_suspend
,
1307 .resume
= nxp_fspi_resume
,
1310 static struct platform_driver nxp_fspi_driver
= {
1313 .of_match_table
= nxp_fspi_dt_ids
,
1314 .acpi_match_table
= ACPI_PTR(nxp_fspi_acpi_ids
),
1315 .pm
= &nxp_fspi_pm_ops
,
1317 .probe
= nxp_fspi_probe
,
1318 .remove_new
= nxp_fspi_remove
,
1320 module_platform_driver(nxp_fspi_driver
);
1322 MODULE_DESCRIPTION("NXP FSPI Controller Driver");
1323 MODULE_AUTHOR("NXP Semiconductor");
1324 MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>");
1325 MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>");
1326 MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>");
1327 MODULE_LICENSE("GPL v2");