1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
5 * Author: Shadi Ammouri <shadi@marvell.com>
6 * Copyright (C) 2007-2008 Marvell Ltd.
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/platform_device.h>
12 #include <linux/err.h>
14 #include <linux/spi/spi.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/clk.h>
22 #include <linux/sizes.h>
23 #include <linux/gpio.h>
24 #include <asm/unaligned.h>
26 #define DRIVER_NAME "orion_spi"
28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
29 #define SPI_AUTOSUSPEND_TIMEOUT 200
31 /* Some SoCs using this driver support up to 8 chip selects.
32 * It is up to the implementer to only use the chip selects
35 #define ORION_NUM_CHIPSELECTS 8
37 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
39 #define ORION_SPI_IF_CTRL_REG 0x00
40 #define ORION_SPI_IF_CONFIG_REG 0x04
41 #define ORION_SPI_IF_RXLSBF BIT(14)
42 #define ORION_SPI_IF_TXLSBF BIT(13)
43 #define ORION_SPI_DATA_OUT_REG 0x08
44 #define ORION_SPI_DATA_IN_REG 0x0c
45 #define ORION_SPI_INT_CAUSE_REG 0x10
46 #define ORION_SPI_TIMING_PARAMS_REG 0x18
48 /* Register for the "Direct Mode" */
49 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
51 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
52 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
53 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
55 #define ORION_SPI_MODE_CPOL (1 << 11)
56 #define ORION_SPI_MODE_CPHA (1 << 12)
57 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
58 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
59 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
60 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
62 #define ORION_SPI_CS_MASK 0x1C
63 #define ORION_SPI_CS_SHIFT 2
64 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
72 struct orion_spi_dev
{
73 enum orion_spi_type typ
;
75 * min_divisor and max_hz should be exclusive, the only we can
76 * have both is for managing the armada-370-spi case with old
80 unsigned int min_divisor
;
81 unsigned int max_divisor
;
83 bool is_errata_50mhz_ac
;
86 struct orion_direct_acc
{
91 struct orion_child_options
{
92 struct orion_direct_acc direct_access
;
96 struct spi_master
*master
;
100 const struct orion_spi_dev
*devdata
;
103 struct orion_child_options child
[ORION_NUM_CHIPSELECTS
];
106 static inline void __iomem
*spi_reg(struct orion_spi
*orion_spi
, u32 reg
)
108 return orion_spi
->base
+ reg
;
112 orion_spi_setbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
114 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
117 val
= readl(reg_addr
);
119 writel(val
, reg_addr
);
123 orion_spi_clrbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
125 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
128 val
= readl(reg_addr
);
130 writel(val
, reg_addr
);
133 static int orion_spi_baudrate_set(struct spi_device
*spi
, unsigned int speed
)
139 struct orion_spi
*orion_spi
;
140 const struct orion_spi_dev
*devdata
;
142 orion_spi
= spi_master_get_devdata(spi
->master
);
143 devdata
= orion_spi
->devdata
;
145 tclk_hz
= clk_get_rate(orion_spi
->clk
);
147 if (devdata
->typ
== ARMADA_SPI
) {
149 * Given the core_clk (tclk_hz) and the target rate (speed) we
150 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
153 * core_clk / (SPR * 2 ** SPPR)
155 * is as big as possible but not bigger than speed.
158 /* best integer divider: */
159 unsigned divider
= DIV_ROUND_UP(tclk_hz
, speed
);
163 /* This is the easy case, divider is less than 16 */
168 unsigned two_pow_sppr
;
170 * Find the highest bit set in divider. This and the
171 * three next bits define SPR (apart from rounding).
172 * SPPR is then the number of zero bits that must be
175 sppr
= fls(divider
) - 4;
178 * As SPR only has 4 bits, we have to round divider up
179 * to the next multiple of 2 ** sppr.
181 two_pow_sppr
= 1 << sppr
;
182 divider
= (divider
+ two_pow_sppr
- 1) & -two_pow_sppr
;
185 * recalculate sppr as rounding up divider might have
186 * increased it enough to change the position of the
187 * highest set bit. In this case the bit that now
188 * doesn't make it into SPR is 0, so there is no need to
191 sppr
= fls(divider
) - 4;
192 spr
= divider
>> sppr
;
195 * Now do range checking. SPR is constructed to have a
196 * width of 4 bits, so this is fine for sure. So we
197 * still need to check for sppr to fit into 3 bits:
203 prescale
= ((sppr
& 0x6) << 5) | ((sppr
& 0x1) << 4) | spr
;
206 * the supported rates are: 4,6,8...30
207 * round up as we look for equal or less speed
209 rate
= DIV_ROUND_UP(tclk_hz
, speed
);
210 rate
= roundup(rate
, 2);
212 /* check if requested speed is too small */
219 /* Convert the rate to SPI clock divisor value. */
220 prescale
= 0x10 + rate
/2;
223 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
224 reg
= ((reg
& ~devdata
->prescale_mask
) | prescale
);
225 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
231 orion_spi_mode_set(struct spi_device
*spi
)
234 struct orion_spi
*orion_spi
;
236 orion_spi
= spi_master_get_devdata(spi
->master
);
238 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
239 reg
&= ~ORION_SPI_MODE_MASK
;
240 if (spi
->mode
& SPI_CPOL
)
241 reg
|= ORION_SPI_MODE_CPOL
;
242 if (spi
->mode
& SPI_CPHA
)
243 reg
|= ORION_SPI_MODE_CPHA
;
244 if (spi
->mode
& SPI_LSB_FIRST
)
245 reg
|= ORION_SPI_IF_RXLSBF
| ORION_SPI_IF_TXLSBF
;
247 reg
&= ~(ORION_SPI_IF_RXLSBF
| ORION_SPI_IF_TXLSBF
);
249 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
253 orion_spi_50mhz_ac_timing_erratum(struct spi_device
*spi
, unsigned int speed
)
256 struct orion_spi
*orion_spi
;
258 orion_spi
= spi_master_get_devdata(spi
->master
);
261 * Erratum description: (Erratum NO. FE-9144572) The device
262 * SPI interface supports frequencies of up to 50 MHz.
263 * However, due to this erratum, when the device core clock is
264 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
265 * clock and CPOL=CPHA=1 there might occur data corruption on
266 * reads from the SPI device.
267 * Erratum Workaround:
268 * Work in one of the following configurations:
269 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
271 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
272 * Register" before setting the interface.
274 reg
= readl(spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
275 reg
&= ~ORION_SPI_TMISO_SAMPLE_MASK
;
277 if (clk_get_rate(orion_spi
->clk
) == 250000000 &&
278 speed
== 50000000 && spi
->mode
& SPI_CPOL
&&
279 spi
->mode
& SPI_CPHA
)
280 reg
|= ORION_SPI_TMISO_SAMPLE_2
;
282 reg
|= ORION_SPI_TMISO_SAMPLE_1
; /* This is the default value */
284 writel(reg
, spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
288 * called only when no transfer is active on the bus
291 orion_spi_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
293 struct orion_spi
*orion_spi
;
294 unsigned int speed
= spi
->max_speed_hz
;
295 unsigned int bits_per_word
= spi
->bits_per_word
;
298 orion_spi
= spi_master_get_devdata(spi
->master
);
300 if ((t
!= NULL
) && t
->speed_hz
)
303 if ((t
!= NULL
) && t
->bits_per_word
)
304 bits_per_word
= t
->bits_per_word
;
306 orion_spi_mode_set(spi
);
308 if (orion_spi
->devdata
->is_errata_50mhz_ac
)
309 orion_spi_50mhz_ac_timing_erratum(spi
, speed
);
311 rc
= orion_spi_baudrate_set(spi
, speed
);
315 if (bits_per_word
== 16)
316 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
317 ORION_SPI_IF_8_16_BIT_MODE
);
319 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
320 ORION_SPI_IF_8_16_BIT_MODE
);
325 static void orion_spi_set_cs(struct spi_device
*spi
, bool enable
)
327 struct orion_spi
*orion_spi
;
330 orion_spi
= spi_master_get_devdata(spi
->master
);
332 if (gpio_is_valid(spi
->cs_gpio
))
333 cs
= orion_spi
->unused_hw_gpio
;
335 cs
= spi
->chip_select
;
337 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, ORION_SPI_CS_MASK
);
338 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
,
341 /* Chip select logic is inverted from spi_set_cs */
343 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
345 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
348 static inline int orion_spi_wait_till_ready(struct orion_spi
*orion_spi
)
352 for (i
= 0; i
< ORION_SPI_WAIT_RDY_MAX_LOOP
; i
++) {
353 if (readl(spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
)))
363 orion_spi_write_read_8bit(struct spi_device
*spi
,
364 const u8
**tx_buf
, u8
**rx_buf
)
366 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
367 struct orion_spi
*orion_spi
;
369 orion_spi
= spi_master_get_devdata(spi
->master
);
370 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
371 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
372 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
374 /* clear the interrupt cause register */
375 writel(0x0, int_reg
);
377 if (tx_buf
&& *tx_buf
)
378 writel(*(*tx_buf
)++, tx_reg
);
382 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
383 dev_err(&spi
->dev
, "TXS timed out\n");
387 if (rx_buf
&& *rx_buf
)
388 *(*rx_buf
)++ = readl(rx_reg
);
394 orion_spi_write_read_16bit(struct spi_device
*spi
,
395 const u16
**tx_buf
, u16
**rx_buf
)
397 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
398 struct orion_spi
*orion_spi
;
400 orion_spi
= spi_master_get_devdata(spi
->master
);
401 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
402 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
403 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
405 /* clear the interrupt cause register */
406 writel(0x0, int_reg
);
408 if (tx_buf
&& *tx_buf
)
409 writel(__cpu_to_le16(get_unaligned((*tx_buf
)++)), tx_reg
);
413 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
414 dev_err(&spi
->dev
, "TXS timed out\n");
418 if (rx_buf
&& *rx_buf
)
419 put_unaligned(__le16_to_cpu(readl(rx_reg
)), (*rx_buf
)++);
425 orion_spi_write_read(struct spi_device
*spi
, struct spi_transfer
*xfer
)
429 struct orion_spi
*orion_spi
;
430 int cs
= spi
->chip_select
;
433 word_len
= spi
->bits_per_word
;
436 orion_spi
= spi_master_get_devdata(spi
->master
);
439 * Use SPI direct write mode if base address is available. Otherwise
440 * fall back to PIO mode for this transfer.
442 vaddr
= orion_spi
->child
[cs
].direct_access
.vaddr
;
444 if (vaddr
&& xfer
->tx_buf
&& word_len
== 8) {
445 unsigned int cnt
= count
/ 4;
446 unsigned int rem
= count
% 4;
449 * Send the TX-data to the SPI device via the direct
450 * mapped address window
452 iowrite32_rep(vaddr
, xfer
->tx_buf
, cnt
);
454 u32
*buf
= (u32
*)xfer
->tx_buf
;
456 iowrite8_rep(vaddr
, &buf
[cnt
], rem
);
463 const u8
*tx
= xfer
->tx_buf
;
464 u8
*rx
= xfer
->rx_buf
;
467 if (orion_spi_write_read_8bit(spi
, &tx
, &rx
) < 0)
470 spi_delay_exec(&xfer
->word_delay
, xfer
);
472 } else if (word_len
== 16) {
473 const u16
*tx
= xfer
->tx_buf
;
474 u16
*rx
= xfer
->rx_buf
;
477 if (orion_spi_write_read_16bit(spi
, &tx
, &rx
) < 0)
480 spi_delay_exec(&xfer
->word_delay
, xfer
);
485 return xfer
->len
- count
;
488 static int orion_spi_transfer_one(struct spi_master
*master
,
489 struct spi_device
*spi
,
490 struct spi_transfer
*t
)
494 status
= orion_spi_setup_transfer(spi
, t
);
499 orion_spi_write_read(spi
, t
);
504 static int orion_spi_setup(struct spi_device
*spi
)
506 if (gpio_is_valid(spi
->cs_gpio
)) {
507 gpio_direction_output(spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
509 return orion_spi_setup_transfer(spi
, NULL
);
512 static int orion_spi_reset(struct orion_spi
*orion_spi
)
514 /* Verify that the CS is deasserted */
515 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
517 /* Don't deassert CS between the direct mapped SPI transfers */
518 writel(0, spi_reg(orion_spi
, SPI_DIRECT_WRITE_CONFIG_REG
));
523 static const struct orion_spi_dev orion_spi_dev_data
= {
527 .prescale_mask
= ORION_SPI_CLK_PRESCALE_MASK
,
530 static const struct orion_spi_dev armada_370_spi_dev_data
= {
535 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
538 static const struct orion_spi_dev armada_xp_spi_dev_data
= {
542 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
545 static const struct orion_spi_dev armada_375_spi_dev_data
= {
549 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
552 static const struct orion_spi_dev armada_380_spi_dev_data
= {
556 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
557 .is_errata_50mhz_ac
= true,
560 static const struct of_device_id orion_spi_of_match_table
[] = {
562 .compatible
= "marvell,orion-spi",
563 .data
= &orion_spi_dev_data
,
566 .compatible
= "marvell,armada-370-spi",
567 .data
= &armada_370_spi_dev_data
,
570 .compatible
= "marvell,armada-375-spi",
571 .data
= &armada_375_spi_dev_data
,
574 .compatible
= "marvell,armada-380-spi",
575 .data
= &armada_380_spi_dev_data
,
578 .compatible
= "marvell,armada-390-spi",
579 .data
= &armada_xp_spi_dev_data
,
582 .compatible
= "marvell,armada-xp-spi",
583 .data
= &armada_xp_spi_dev_data
,
588 MODULE_DEVICE_TABLE(of
, orion_spi_of_match_table
);
590 static int orion_spi_probe(struct platform_device
*pdev
)
592 const struct of_device_id
*of_id
;
593 const struct orion_spi_dev
*devdata
;
594 struct spi_master
*master
;
595 struct orion_spi
*spi
;
597 unsigned long tclk_hz
;
599 struct device_node
*np
;
601 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
602 if (master
== NULL
) {
603 dev_dbg(&pdev
->dev
, "master allocation failed\n");
608 master
->bus_num
= pdev
->id
;
609 if (pdev
->dev
.of_node
) {
612 if (!of_property_read_u32(pdev
->dev
.of_node
, "cell-index",
614 master
->bus_num
= cell_index
;
617 /* we support all 4 SPI modes and LSB first option */
618 master
->mode_bits
= SPI_CPHA
| SPI_CPOL
| SPI_LSB_FIRST
;
619 master
->set_cs
= orion_spi_set_cs
;
620 master
->transfer_one
= orion_spi_transfer_one
;
621 master
->num_chipselect
= ORION_NUM_CHIPSELECTS
;
622 master
->setup
= orion_spi_setup
;
623 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
624 master
->auto_runtime_pm
= true;
625 master
->flags
= SPI_MASTER_GPIO_SS
;
627 platform_set_drvdata(pdev
, master
);
629 spi
= spi_master_get_devdata(master
);
630 spi
->master
= master
;
631 spi
->unused_hw_gpio
= -1;
633 of_id
= of_match_device(orion_spi_of_match_table
, &pdev
->dev
);
634 devdata
= (of_id
) ? of_id
->data
: &orion_spi_dev_data
;
635 spi
->devdata
= devdata
;
637 spi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
638 if (IS_ERR(spi
->clk
)) {
639 status
= PTR_ERR(spi
->clk
);
643 status
= clk_prepare_enable(spi
->clk
);
647 /* The following clock is only used by some SoCs */
648 spi
->axi_clk
= devm_clk_get(&pdev
->dev
, "axi");
649 if (PTR_ERR(spi
->axi_clk
) == -EPROBE_DEFER
) {
650 status
= -EPROBE_DEFER
;
653 if (!IS_ERR(spi
->axi_clk
))
654 clk_prepare_enable(spi
->axi_clk
);
656 tclk_hz
= clk_get_rate(spi
->clk
);
659 * With old device tree, armada-370-spi could be used with
660 * Armada XP, however for this SoC the maximum frequency is
661 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
662 * higher than 200MHz. So, in order to be able to handle both
663 * SoCs, we can take the minimum of 50MHz and tclk/4.
665 if (of_device_is_compatible(pdev
->dev
.of_node
,
666 "marvell,armada-370-spi"))
667 master
->max_speed_hz
= min(devdata
->max_hz
,
668 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
));
669 else if (devdata
->min_divisor
)
670 master
->max_speed_hz
=
671 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
);
673 master
->max_speed_hz
= devdata
->max_hz
;
674 master
->min_speed_hz
= DIV_ROUND_UP(tclk_hz
, devdata
->max_divisor
);
676 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
677 spi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
678 if (IS_ERR(spi
->base
)) {
679 status
= PTR_ERR(spi
->base
);
680 goto out_rel_axi_clk
;
683 for_each_available_child_of_node(pdev
->dev
.of_node
, np
) {
684 struct orion_direct_acc
*dir_acc
;
688 /* Get chip-select number from the "reg" property */
689 status
= of_property_read_u32(np
, "reg", &cs
);
692 "%pOF has no valid 'reg' property (%d)\n",
698 * Initialize the CS GPIO:
699 * - properly request the actual GPIO signal
700 * - de-assert the logical signal so that all GPIO CS lines
701 * are inactive when probing for slaves
702 * - find an unused physical CS which will be driven for any
703 * slave which uses a CS GPIO
705 cs_gpio
= of_get_named_gpio(pdev
->dev
.of_node
, "cs-gpios", cs
);
710 if (spi
->unused_hw_gpio
== -1) {
712 "Selected unused HW CS#%d for any GPIO CSes\n",
714 spi
->unused_hw_gpio
= cs
;
717 gpio_name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
,
718 "%s-CS%d", dev_name(&pdev
->dev
), cs
);
721 goto out_rel_axi_clk
;
724 cs_flags
= of_property_read_bool(np
, "spi-cs-high") ?
725 GPIOF_OUT_INIT_LOW
: GPIOF_OUT_INIT_HIGH
;
726 status
= devm_gpio_request_one(&pdev
->dev
, cs_gpio
,
727 cs_flags
, gpio_name
);
730 "Can't request GPIO for CS %d\n", cs
);
731 goto out_rel_axi_clk
;
736 * Check if an address is configured for this SPI device. If
737 * not, the MBus mapping via the 'ranges' property in the 'soc'
738 * node is not configured and this device should not use the
739 * direct mode. In this case, just continue with the next
742 status
= of_address_to_resource(pdev
->dev
.of_node
, cs
+ 1, r
);
747 * Only map one page for direct access. This is enough for the
748 * simple TX transfer which only writes to the first word.
749 * This needs to get extended for the direct SPI-NOR / SPI-NAND
750 * support, once this gets implemented.
752 dir_acc
= &spi
->child
[cs
].direct_access
;
753 dir_acc
->vaddr
= devm_ioremap(&pdev
->dev
, r
->start
, PAGE_SIZE
);
754 if (!dir_acc
->vaddr
) {
756 goto out_rel_axi_clk
;
758 dir_acc
->size
= PAGE_SIZE
;
760 dev_info(&pdev
->dev
, "CS%d configured for direct access\n", cs
);
763 pm_runtime_set_active(&pdev
->dev
);
764 pm_runtime_use_autosuspend(&pdev
->dev
);
765 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
766 pm_runtime_enable(&pdev
->dev
);
768 status
= orion_spi_reset(spi
);
772 master
->dev
.of_node
= pdev
->dev
.of_node
;
773 status
= spi_register_master(master
);
780 pm_runtime_disable(&pdev
->dev
);
782 clk_disable_unprepare(spi
->axi_clk
);
784 clk_disable_unprepare(spi
->clk
);
786 spi_master_put(master
);
791 static int orion_spi_remove(struct platform_device
*pdev
)
793 struct spi_master
*master
= platform_get_drvdata(pdev
);
794 struct orion_spi
*spi
= spi_master_get_devdata(master
);
796 pm_runtime_get_sync(&pdev
->dev
);
797 clk_disable_unprepare(spi
->axi_clk
);
798 clk_disable_unprepare(spi
->clk
);
800 spi_unregister_master(master
);
801 pm_runtime_disable(&pdev
->dev
);
806 MODULE_ALIAS("platform:" DRIVER_NAME
);
809 static int orion_spi_runtime_suspend(struct device
*dev
)
811 struct spi_master
*master
= dev_get_drvdata(dev
);
812 struct orion_spi
*spi
= spi_master_get_devdata(master
);
814 clk_disable_unprepare(spi
->axi_clk
);
815 clk_disable_unprepare(spi
->clk
);
819 static int orion_spi_runtime_resume(struct device
*dev
)
821 struct spi_master
*master
= dev_get_drvdata(dev
);
822 struct orion_spi
*spi
= spi_master_get_devdata(master
);
824 if (!IS_ERR(spi
->axi_clk
))
825 clk_prepare_enable(spi
->axi_clk
);
826 return clk_prepare_enable(spi
->clk
);
830 static const struct dev_pm_ops orion_spi_pm_ops
= {
831 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend
,
832 orion_spi_runtime_resume
,
836 static struct platform_driver orion_spi_driver
= {
839 .pm
= &orion_spi_pm_ops
,
840 .of_match_table
= of_match_ptr(orion_spi_of_match_table
),
842 .probe
= orion_spi_probe
,
843 .remove
= orion_spi_remove
,
846 module_platform_driver(orion_spi_driver
);
848 MODULE_DESCRIPTION("Orion SPI driver");
849 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
850 MODULE_LICENSE("GPL");