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[thirdparty/kernel/stable.git] / drivers / spi / spi-rspi.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH RSPI driver
4 *
5 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
6 * Copyright (C) 2014 Glider bvba
7 *
8 * Based on spi-sh.c:
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/sched.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/of_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sh_dma.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/rspi.h>
27
28 #define RSPI_SPCR 0x00 /* Control Register */
29 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
30 #define RSPI_SPPCR 0x02 /* Pin Control Register */
31 #define RSPI_SPSR 0x03 /* Status Register */
32 #define RSPI_SPDR 0x04 /* Data Register */
33 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
34 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
35 #define RSPI_SPBR 0x0a /* Bit Rate Register */
36 #define RSPI_SPDCR 0x0b /* Data Control Register */
37 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
38 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
39 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
40 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
41 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
42 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
43 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
44 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
45 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
46 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
47 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
48 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
49 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
50 #define RSPI_NUM_SPCMD 8
51 #define RSPI_RZ_NUM_SPCMD 4
52 #define QSPI_NUM_SPCMD 4
53
54 /* RSPI on RZ only */
55 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
56 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
57
58 /* QSPI only */
59 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
60 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
61 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
62 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
63 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
64 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
65 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
66
67 /* SPCR - Control Register */
68 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
69 #define SPCR_SPE 0x40 /* Function Enable */
70 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
71 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
72 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
73 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
74 /* RSPI on SH only */
75 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
76 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
77 /* QSPI on R-Car Gen2 only */
78 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
79 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
80
81 /* SSLP - Slave Select Polarity Register */
82 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
83 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
84
85 /* SPPCR - Pin Control Register */
86 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
87 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
88 #define SPPCR_SPOM 0x04
89 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
90 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
91
92 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
93 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
94
95 /* SPSR - Status Register */
96 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
97 #define SPSR_TEND 0x40 /* Transmit End */
98 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
99 #define SPSR_PERF 0x08 /* Parity Error Flag */
100 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
101 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
102 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
103
104 /* SPSCR - Sequence Control Register */
105 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
106
107 /* SPSSR - Sequence Status Register */
108 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
109 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
110
111 /* SPDCR - Data Control Register */
112 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
113 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
114 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
115 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
116 #define SPDCR_SPLWORD SPDCR_SPLW1
117 #define SPDCR_SPLBYTE SPDCR_SPLW0
118 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
119 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
120 #define SPDCR_SLSEL1 0x08
121 #define SPDCR_SLSEL0 0x04
122 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
123 #define SPDCR_SPFC1 0x02
124 #define SPDCR_SPFC0 0x01
125 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
126
127 /* SPCKD - Clock Delay Register */
128 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
129
130 /* SSLND - Slave Select Negation Delay Register */
131 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
132
133 /* SPND - Next-Access Delay Register */
134 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
135
136 /* SPCR2 - Control Register 2 */
137 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
138 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
139 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
140 #define SPCR2_SPPE 0x01 /* Parity Enable */
141
142 /* SPCMDn - Command Registers */
143 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
144 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
145 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
146 #define SPCMD_LSBF 0x1000 /* LSB First */
147 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
148 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
149 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
150 #define SPCMD_SPB_16BIT 0x0100
151 #define SPCMD_SPB_20BIT 0x0000
152 #define SPCMD_SPB_24BIT 0x0100
153 #define SPCMD_SPB_32BIT 0x0200
154 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
155 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
156 #define SPCMD_SPIMOD1 0x0040
157 #define SPCMD_SPIMOD0 0x0020
158 #define SPCMD_SPIMOD_SINGLE 0
159 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
160 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
161 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
162 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
163 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
164 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
165 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
166
167 /* SPBFCR - Buffer Control Register */
168 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
169 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
170 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
171 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
172 /* QSPI on R-Car Gen2 */
173 #define SPBFCR_TXTRG_1B 0x00 /* 31 bytes (1 byte available) */
174 #define SPBFCR_TXTRG_32B 0x30 /* 0 byte (32 bytes available) */
175 #define SPBFCR_RXTRG_1B 0x00 /* 1 byte (31 bytes available) */
176 #define SPBFCR_RXTRG_32B 0x07 /* 32 bytes (0 byte available) */
177
178 #define QSPI_BUFFER_SIZE 32u
179
180 struct rspi_data {
181 void __iomem *addr;
182 u32 max_speed_hz;
183 struct spi_controller *ctlr;
184 wait_queue_head_t wait;
185 struct clk *clk;
186 u16 spcmd;
187 u8 spsr;
188 u8 sppcr;
189 int rx_irq, tx_irq;
190 const struct spi_ops *ops;
191
192 unsigned dma_callbacked:1;
193 unsigned byte_access:1;
194 };
195
196 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
197 {
198 iowrite8(data, rspi->addr + offset);
199 }
200
201 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
202 {
203 iowrite16(data, rspi->addr + offset);
204 }
205
206 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
207 {
208 iowrite32(data, rspi->addr + offset);
209 }
210
211 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
212 {
213 return ioread8(rspi->addr + offset);
214 }
215
216 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
217 {
218 return ioread16(rspi->addr + offset);
219 }
220
221 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
222 {
223 if (rspi->byte_access)
224 rspi_write8(rspi, data, RSPI_SPDR);
225 else /* 16 bit */
226 rspi_write16(rspi, data, RSPI_SPDR);
227 }
228
229 static u16 rspi_read_data(const struct rspi_data *rspi)
230 {
231 if (rspi->byte_access)
232 return rspi_read8(rspi, RSPI_SPDR);
233 else /* 16 bit */
234 return rspi_read16(rspi, RSPI_SPDR);
235 }
236
237 /* optional functions */
238 struct spi_ops {
239 int (*set_config_register)(struct rspi_data *rspi, int access_size);
240 int (*transfer_one)(struct spi_controller *ctlr,
241 struct spi_device *spi, struct spi_transfer *xfer);
242 u16 mode_bits;
243 u16 flags;
244 u16 fifo_size;
245 };
246
247 /*
248 * functions for RSPI on legacy SH
249 */
250 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
251 {
252 int spbr;
253
254 /* Sets output mode, MOSI signal, and (optionally) loopback */
255 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
256
257 /* Sets transfer bit rate */
258 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
259 2 * rspi->max_speed_hz) - 1;
260 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
261
262 /* Disable dummy transmission, set 16-bit word access, 1 frame */
263 rspi_write8(rspi, 0, RSPI_SPDCR);
264 rspi->byte_access = 0;
265
266 /* Sets RSPCK, SSL, next-access delay value */
267 rspi_write8(rspi, 0x00, RSPI_SPCKD);
268 rspi_write8(rspi, 0x00, RSPI_SSLND);
269 rspi_write8(rspi, 0x00, RSPI_SPND);
270
271 /* Sets parity, interrupt mask */
272 rspi_write8(rspi, 0x00, RSPI_SPCR2);
273
274 /* Sets SPCMD */
275 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
276 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
277
278 /* Sets RSPI mode */
279 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
280
281 return 0;
282 }
283
284 /*
285 * functions for RSPI on RZ
286 */
287 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
288 {
289 int spbr;
290 int div = 0;
291 unsigned long clksrc;
292
293 /* Sets output mode, MOSI signal, and (optionally) loopback */
294 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
295
296 clksrc = clk_get_rate(rspi->clk);
297 while (div < 3) {
298 if (rspi->max_speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
299 break;
300 div++;
301 clksrc /= 2;
302 }
303
304 /* Sets transfer bit rate */
305 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307 rspi->spcmd |= div << 2;
308
309 /* Disable dummy transmission, set byte access */
310 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
311 rspi->byte_access = 1;
312
313 /* Sets RSPCK, SSL, next-access delay value */
314 rspi_write8(rspi, 0x00, RSPI_SPCKD);
315 rspi_write8(rspi, 0x00, RSPI_SSLND);
316 rspi_write8(rspi, 0x00, RSPI_SPND);
317
318 /* Sets SPCMD */
319 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
320 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
321
322 /* Sets RSPI mode */
323 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
324
325 return 0;
326 }
327
328 /*
329 * functions for QSPI
330 */
331 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
332 {
333 int spbr;
334
335 /* Sets output mode, MOSI signal, and (optionally) loopback */
336 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
337
338 /* Sets transfer bit rate */
339 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
340 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
341
342 /* Disable dummy transmission, set byte access */
343 rspi_write8(rspi, 0, RSPI_SPDCR);
344 rspi->byte_access = 1;
345
346 /* Sets RSPCK, SSL, next-access delay value */
347 rspi_write8(rspi, 0x00, RSPI_SPCKD);
348 rspi_write8(rspi, 0x00, RSPI_SSLND);
349 rspi_write8(rspi, 0x00, RSPI_SPND);
350
351 /* Data Length Setting */
352 if (access_size == 8)
353 rspi->spcmd |= SPCMD_SPB_8BIT;
354 else if (access_size == 16)
355 rspi->spcmd |= SPCMD_SPB_16BIT;
356 else
357 rspi->spcmd |= SPCMD_SPB_32BIT;
358
359 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
360
361 /* Resets transfer data length */
362 rspi_write32(rspi, 0, QSPI_SPBMUL0);
363
364 /* Resets transmit and receive buffer */
365 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
366 /* Sets buffer to allow normal operation */
367 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
368
369 /* Sets SPCMD */
370 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
371
372 /* Sets RSPI mode */
373 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
374
375 return 0;
376 }
377
378 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
379 {
380 u8 data;
381
382 data = rspi_read8(rspi, reg);
383 data &= ~mask;
384 data |= (val & mask);
385 rspi_write8(rspi, data, reg);
386 }
387
388 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
389 unsigned int len)
390 {
391 unsigned int n;
392
393 n = min(len, QSPI_BUFFER_SIZE);
394
395 if (len >= QSPI_BUFFER_SIZE) {
396 /* sets triggering number to 32 bytes */
397 qspi_update(rspi, SPBFCR_TXTRG_MASK,
398 SPBFCR_TXTRG_32B, QSPI_SPBFCR);
399 } else {
400 /* sets triggering number to 1 byte */
401 qspi_update(rspi, SPBFCR_TXTRG_MASK,
402 SPBFCR_TXTRG_1B, QSPI_SPBFCR);
403 }
404
405 return n;
406 }
407
408 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
409 {
410 unsigned int n;
411
412 n = min(len, QSPI_BUFFER_SIZE);
413
414 if (len >= QSPI_BUFFER_SIZE) {
415 /* sets triggering number to 32 bytes */
416 qspi_update(rspi, SPBFCR_RXTRG_MASK,
417 SPBFCR_RXTRG_32B, QSPI_SPBFCR);
418 } else {
419 /* sets triggering number to 1 byte */
420 qspi_update(rspi, SPBFCR_RXTRG_MASK,
421 SPBFCR_RXTRG_1B, QSPI_SPBFCR);
422 }
423 return n;
424 }
425
426 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
427
428 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
429 {
430 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
431 }
432
433 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
434 {
435 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
436 }
437
438 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
439 u8 enable_bit)
440 {
441 int ret;
442
443 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
444 if (rspi->spsr & wait_mask)
445 return 0;
446
447 rspi_enable_irq(rspi, enable_bit);
448 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
449 if (ret == 0 && !(rspi->spsr & wait_mask))
450 return -ETIMEDOUT;
451
452 return 0;
453 }
454
455 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
456 {
457 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
458 }
459
460 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
461 {
462 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
463 }
464
465 static int rspi_data_out(struct rspi_data *rspi, u8 data)
466 {
467 int error = rspi_wait_for_tx_empty(rspi);
468 if (error < 0) {
469 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
470 return error;
471 }
472 rspi_write_data(rspi, data);
473 return 0;
474 }
475
476 static int rspi_data_in(struct rspi_data *rspi)
477 {
478 int error;
479 u8 data;
480
481 error = rspi_wait_for_rx_full(rspi);
482 if (error < 0) {
483 dev_err(&rspi->ctlr->dev, "receive timeout\n");
484 return error;
485 }
486 data = rspi_read_data(rspi);
487 return data;
488 }
489
490 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
491 unsigned int n)
492 {
493 while (n-- > 0) {
494 if (tx) {
495 int ret = rspi_data_out(rspi, *tx++);
496 if (ret < 0)
497 return ret;
498 }
499 if (rx) {
500 int ret = rspi_data_in(rspi);
501 if (ret < 0)
502 return ret;
503 *rx++ = ret;
504 }
505 }
506
507 return 0;
508 }
509
510 static void rspi_dma_complete(void *arg)
511 {
512 struct rspi_data *rspi = arg;
513
514 rspi->dma_callbacked = 1;
515 wake_up_interruptible(&rspi->wait);
516 }
517
518 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
519 struct sg_table *rx)
520 {
521 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
522 u8 irq_mask = 0;
523 unsigned int other_irq = 0;
524 dma_cookie_t cookie;
525 int ret;
526
527 /* First prepare and submit the DMA request(s), as this may fail */
528 if (rx) {
529 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
530 rx->nents, DMA_DEV_TO_MEM,
531 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
532 if (!desc_rx) {
533 ret = -EAGAIN;
534 goto no_dma_rx;
535 }
536
537 desc_rx->callback = rspi_dma_complete;
538 desc_rx->callback_param = rspi;
539 cookie = dmaengine_submit(desc_rx);
540 if (dma_submit_error(cookie)) {
541 ret = cookie;
542 goto no_dma_rx;
543 }
544
545 irq_mask |= SPCR_SPRIE;
546 }
547
548 if (tx) {
549 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
550 tx->nents, DMA_MEM_TO_DEV,
551 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
552 if (!desc_tx) {
553 ret = -EAGAIN;
554 goto no_dma_tx;
555 }
556
557 if (rx) {
558 /* No callback */
559 desc_tx->callback = NULL;
560 } else {
561 desc_tx->callback = rspi_dma_complete;
562 desc_tx->callback_param = rspi;
563 }
564 cookie = dmaengine_submit(desc_tx);
565 if (dma_submit_error(cookie)) {
566 ret = cookie;
567 goto no_dma_tx;
568 }
569
570 irq_mask |= SPCR_SPTIE;
571 }
572
573 /*
574 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be
575 * called. So, this driver disables the IRQ while DMA transfer.
576 */
577 if (tx)
578 disable_irq(other_irq = rspi->tx_irq);
579 if (rx && rspi->rx_irq != other_irq)
580 disable_irq(rspi->rx_irq);
581
582 rspi_enable_irq(rspi, irq_mask);
583 rspi->dma_callbacked = 0;
584
585 /* Now start DMA */
586 if (rx)
587 dma_async_issue_pending(rspi->ctlr->dma_rx);
588 if (tx)
589 dma_async_issue_pending(rspi->ctlr->dma_tx);
590
591 ret = wait_event_interruptible_timeout(rspi->wait,
592 rspi->dma_callbacked, HZ);
593 if (ret > 0 && rspi->dma_callbacked) {
594 ret = 0;
595 } else {
596 if (!ret) {
597 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
598 ret = -ETIMEDOUT;
599 }
600 if (tx)
601 dmaengine_terminate_all(rspi->ctlr->dma_tx);
602 if (rx)
603 dmaengine_terminate_all(rspi->ctlr->dma_rx);
604 }
605
606 rspi_disable_irq(rspi, irq_mask);
607
608 if (tx)
609 enable_irq(rspi->tx_irq);
610 if (rx && rspi->rx_irq != other_irq)
611 enable_irq(rspi->rx_irq);
612
613 return ret;
614
615 no_dma_tx:
616 if (rx)
617 dmaengine_terminate_all(rspi->ctlr->dma_rx);
618 no_dma_rx:
619 if (ret == -EAGAIN) {
620 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
621 dev_driver_string(&rspi->ctlr->dev),
622 dev_name(&rspi->ctlr->dev));
623 }
624 return ret;
625 }
626
627 static void rspi_receive_init(const struct rspi_data *rspi)
628 {
629 u8 spsr;
630
631 spsr = rspi_read8(rspi, RSPI_SPSR);
632 if (spsr & SPSR_SPRF)
633 rspi_read_data(rspi); /* dummy read */
634 if (spsr & SPSR_OVRF)
635 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
636 RSPI_SPSR);
637 }
638
639 static void rspi_rz_receive_init(const struct rspi_data *rspi)
640 {
641 rspi_receive_init(rspi);
642 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
643 rspi_write8(rspi, 0, RSPI_SPBFCR);
644 }
645
646 static void qspi_receive_init(const struct rspi_data *rspi)
647 {
648 u8 spsr;
649
650 spsr = rspi_read8(rspi, RSPI_SPSR);
651 if (spsr & SPSR_SPRF)
652 rspi_read_data(rspi); /* dummy read */
653 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
654 rspi_write8(rspi, 0, QSPI_SPBFCR);
655 }
656
657 static bool __rspi_can_dma(const struct rspi_data *rspi,
658 const struct spi_transfer *xfer)
659 {
660 return xfer->len > rspi->ops->fifo_size;
661 }
662
663 static bool rspi_can_dma(struct spi_controller *ctlr, struct spi_device *spi,
664 struct spi_transfer *xfer)
665 {
666 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
667
668 return __rspi_can_dma(rspi, xfer);
669 }
670
671 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
672 struct spi_transfer *xfer)
673 {
674 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
675 return -EAGAIN;
676
677 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */
678 return rspi_dma_transfer(rspi, &xfer->tx_sg,
679 xfer->rx_buf ? &xfer->rx_sg : NULL);
680 }
681
682 static int rspi_common_transfer(struct rspi_data *rspi,
683 struct spi_transfer *xfer)
684 {
685 int ret;
686
687 ret = rspi_dma_check_then_transfer(rspi, xfer);
688 if (ret != -EAGAIN)
689 return ret;
690
691 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
692 if (ret < 0)
693 return ret;
694
695 /* Wait for the last transmission */
696 rspi_wait_for_tx_empty(rspi);
697
698 return 0;
699 }
700
701 static int rspi_transfer_one(struct spi_controller *ctlr,
702 struct spi_device *spi, struct spi_transfer *xfer)
703 {
704 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
705 u8 spcr;
706
707 spcr = rspi_read8(rspi, RSPI_SPCR);
708 if (xfer->rx_buf) {
709 rspi_receive_init(rspi);
710 spcr &= ~SPCR_TXMD;
711 } else {
712 spcr |= SPCR_TXMD;
713 }
714 rspi_write8(rspi, spcr, RSPI_SPCR);
715
716 return rspi_common_transfer(rspi, xfer);
717 }
718
719 static int rspi_rz_transfer_one(struct spi_controller *ctlr,
720 struct spi_device *spi,
721 struct spi_transfer *xfer)
722 {
723 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
724
725 rspi_rz_receive_init(rspi);
726
727 return rspi_common_transfer(rspi, xfer);
728 }
729
730 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
731 u8 *rx, unsigned int len)
732 {
733 unsigned int i, n;
734 int ret;
735
736 while (len > 0) {
737 n = qspi_set_send_trigger(rspi, len);
738 qspi_set_receive_trigger(rspi, len);
739 if (n == QSPI_BUFFER_SIZE) {
740 ret = rspi_wait_for_tx_empty(rspi);
741 if (ret < 0) {
742 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
743 return ret;
744 }
745 for (i = 0; i < n; i++)
746 rspi_write_data(rspi, *tx++);
747
748 ret = rspi_wait_for_rx_full(rspi);
749 if (ret < 0) {
750 dev_err(&rspi->ctlr->dev, "receive timeout\n");
751 return ret;
752 }
753 for (i = 0; i < n; i++)
754 *rx++ = rspi_read_data(rspi);
755 } else {
756 ret = rspi_pio_transfer(rspi, tx, rx, n);
757 if (ret < 0)
758 return ret;
759 }
760 len -= n;
761 }
762
763 return 0;
764 }
765
766 static int qspi_transfer_out_in(struct rspi_data *rspi,
767 struct spi_transfer *xfer)
768 {
769 int ret;
770
771 qspi_receive_init(rspi);
772
773 ret = rspi_dma_check_then_transfer(rspi, xfer);
774 if (ret != -EAGAIN)
775 return ret;
776
777 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
778 xfer->rx_buf, xfer->len);
779 }
780
781 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
782 {
783 const u8 *tx = xfer->tx_buf;
784 unsigned int n = xfer->len;
785 unsigned int i, len;
786 int ret;
787
788 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
789 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
790 if (ret != -EAGAIN)
791 return ret;
792 }
793
794 while (n > 0) {
795 len = qspi_set_send_trigger(rspi, n);
796 if (len == QSPI_BUFFER_SIZE) {
797 ret = rspi_wait_for_tx_empty(rspi);
798 if (ret < 0) {
799 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
800 return ret;
801 }
802 for (i = 0; i < len; i++)
803 rspi_write_data(rspi, *tx++);
804 } else {
805 ret = rspi_pio_transfer(rspi, tx, NULL, len);
806 if (ret < 0)
807 return ret;
808 }
809 n -= len;
810 }
811
812 /* Wait for the last transmission */
813 rspi_wait_for_tx_empty(rspi);
814
815 return 0;
816 }
817
818 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
819 {
820 u8 *rx = xfer->rx_buf;
821 unsigned int n = xfer->len;
822 unsigned int i, len;
823 int ret;
824
825 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
826 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
827 if (ret != -EAGAIN)
828 return ret;
829 }
830
831 while (n > 0) {
832 len = qspi_set_receive_trigger(rspi, n);
833 if (len == QSPI_BUFFER_SIZE) {
834 ret = rspi_wait_for_rx_full(rspi);
835 if (ret < 0) {
836 dev_err(&rspi->ctlr->dev, "receive timeout\n");
837 return ret;
838 }
839 for (i = 0; i < len; i++)
840 *rx++ = rspi_read_data(rspi);
841 } else {
842 ret = rspi_pio_transfer(rspi, NULL, rx, len);
843 if (ret < 0)
844 return ret;
845 }
846 n -= len;
847 }
848
849 return 0;
850 }
851
852 static int qspi_transfer_one(struct spi_controller *ctlr,
853 struct spi_device *spi, struct spi_transfer *xfer)
854 {
855 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
856
857 if (spi->mode & SPI_LOOP) {
858 return qspi_transfer_out_in(rspi, xfer);
859 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
860 /* Quad or Dual SPI Write */
861 return qspi_transfer_out(rspi, xfer);
862 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
863 /* Quad or Dual SPI Read */
864 return qspi_transfer_in(rspi, xfer);
865 } else {
866 /* Single SPI Transfer */
867 return qspi_transfer_out_in(rspi, xfer);
868 }
869 }
870
871 static int rspi_setup(struct spi_device *spi)
872 {
873 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
874
875 rspi->max_speed_hz = spi->max_speed_hz;
876
877 rspi->spcmd = SPCMD_SSLKP;
878 if (spi->mode & SPI_CPOL)
879 rspi->spcmd |= SPCMD_CPOL;
880 if (spi->mode & SPI_CPHA)
881 rspi->spcmd |= SPCMD_CPHA;
882
883 /* CMOS output mode and MOSI signal from previous transfer */
884 rspi->sppcr = 0;
885 if (spi->mode & SPI_LOOP)
886 rspi->sppcr |= SPPCR_SPLP;
887
888 set_config_register(rspi, 8);
889
890 return 0;
891 }
892
893 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
894 {
895 if (xfer->tx_buf)
896 switch (xfer->tx_nbits) {
897 case SPI_NBITS_QUAD:
898 return SPCMD_SPIMOD_QUAD;
899 case SPI_NBITS_DUAL:
900 return SPCMD_SPIMOD_DUAL;
901 default:
902 return 0;
903 }
904 if (xfer->rx_buf)
905 switch (xfer->rx_nbits) {
906 case SPI_NBITS_QUAD:
907 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
908 case SPI_NBITS_DUAL:
909 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
910 default:
911 return 0;
912 }
913
914 return 0;
915 }
916
917 static int qspi_setup_sequencer(struct rspi_data *rspi,
918 const struct spi_message *msg)
919 {
920 const struct spi_transfer *xfer;
921 unsigned int i = 0, len = 0;
922 u16 current_mode = 0xffff, mode;
923
924 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
925 mode = qspi_transfer_mode(xfer);
926 if (mode == current_mode) {
927 len += xfer->len;
928 continue;
929 }
930
931 /* Transfer mode change */
932 if (i) {
933 /* Set transfer data length of previous transfer */
934 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
935 }
936
937 if (i >= QSPI_NUM_SPCMD) {
938 dev_err(&msg->spi->dev,
939 "Too many different transfer modes");
940 return -EINVAL;
941 }
942
943 /* Program transfer mode for this transfer */
944 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
945 current_mode = mode;
946 len = xfer->len;
947 i++;
948 }
949 if (i) {
950 /* Set final transfer data length and sequence length */
951 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
952 rspi_write8(rspi, i - 1, RSPI_SPSCR);
953 }
954
955 return 0;
956 }
957
958 static int rspi_prepare_message(struct spi_controller *ctlr,
959 struct spi_message *msg)
960 {
961 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
962 int ret;
963
964 if (msg->spi->mode &
965 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
966 /* Setup sequencer for messages with multiple transfer modes */
967 ret = qspi_setup_sequencer(rspi, msg);
968 if (ret < 0)
969 return ret;
970 }
971
972 /* Enable SPI function in master mode */
973 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
974 return 0;
975 }
976
977 static int rspi_unprepare_message(struct spi_controller *ctlr,
978 struct spi_message *msg)
979 {
980 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
981
982 /* Disable SPI function */
983 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
984
985 /* Reset sequencer for Single SPI Transfers */
986 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
987 rspi_write8(rspi, 0, RSPI_SPSCR);
988 return 0;
989 }
990
991 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
992 {
993 struct rspi_data *rspi = _sr;
994 u8 spsr;
995 irqreturn_t ret = IRQ_NONE;
996 u8 disable_irq = 0;
997
998 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
999 if (spsr & SPSR_SPRF)
1000 disable_irq |= SPCR_SPRIE;
1001 if (spsr & SPSR_SPTEF)
1002 disable_irq |= SPCR_SPTIE;
1003
1004 if (disable_irq) {
1005 ret = IRQ_HANDLED;
1006 rspi_disable_irq(rspi, disable_irq);
1007 wake_up(&rspi->wait);
1008 }
1009
1010 return ret;
1011 }
1012
1013 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
1014 {
1015 struct rspi_data *rspi = _sr;
1016 u8 spsr;
1017
1018 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1019 if (spsr & SPSR_SPRF) {
1020 rspi_disable_irq(rspi, SPCR_SPRIE);
1021 wake_up(&rspi->wait);
1022 return IRQ_HANDLED;
1023 }
1024
1025 return 0;
1026 }
1027
1028 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
1029 {
1030 struct rspi_data *rspi = _sr;
1031 u8 spsr;
1032
1033 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1034 if (spsr & SPSR_SPTEF) {
1035 rspi_disable_irq(rspi, SPCR_SPTIE);
1036 wake_up(&rspi->wait);
1037 return IRQ_HANDLED;
1038 }
1039
1040 return 0;
1041 }
1042
1043 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
1044 enum dma_transfer_direction dir,
1045 unsigned int id,
1046 dma_addr_t port_addr)
1047 {
1048 dma_cap_mask_t mask;
1049 struct dma_chan *chan;
1050 struct dma_slave_config cfg;
1051 int ret;
1052
1053 dma_cap_zero(mask);
1054 dma_cap_set(DMA_SLAVE, mask);
1055
1056 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1057 (void *)(unsigned long)id, dev,
1058 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1059 if (!chan) {
1060 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1061 return NULL;
1062 }
1063
1064 memset(&cfg, 0, sizeof(cfg));
1065 cfg.direction = dir;
1066 if (dir == DMA_MEM_TO_DEV) {
1067 cfg.dst_addr = port_addr;
1068 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1069 } else {
1070 cfg.src_addr = port_addr;
1071 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1072 }
1073
1074 ret = dmaengine_slave_config(chan, &cfg);
1075 if (ret) {
1076 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1077 dma_release_channel(chan);
1078 return NULL;
1079 }
1080
1081 return chan;
1082 }
1083
1084 static int rspi_request_dma(struct device *dev, struct spi_controller *ctlr,
1085 const struct resource *res)
1086 {
1087 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev);
1088 unsigned int dma_tx_id, dma_rx_id;
1089
1090 if (dev->of_node) {
1091 /* In the OF case we will get the slave IDs from the DT */
1092 dma_tx_id = 0;
1093 dma_rx_id = 0;
1094 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) {
1095 dma_tx_id = rspi_pd->dma_tx_id;
1096 dma_rx_id = rspi_pd->dma_rx_id;
1097 } else {
1098 /* The driver assumes no error. */
1099 return 0;
1100 }
1101
1102 ctlr->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id,
1103 res->start + RSPI_SPDR);
1104 if (!ctlr->dma_tx)
1105 return -ENODEV;
1106
1107 ctlr->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id,
1108 res->start + RSPI_SPDR);
1109 if (!ctlr->dma_rx) {
1110 dma_release_channel(ctlr->dma_tx);
1111 ctlr->dma_tx = NULL;
1112 return -ENODEV;
1113 }
1114
1115 ctlr->can_dma = rspi_can_dma;
1116 dev_info(dev, "DMA available");
1117 return 0;
1118 }
1119
1120 static void rspi_release_dma(struct spi_controller *ctlr)
1121 {
1122 if (ctlr->dma_tx)
1123 dma_release_channel(ctlr->dma_tx);
1124 if (ctlr->dma_rx)
1125 dma_release_channel(ctlr->dma_rx);
1126 }
1127
1128 static int rspi_remove(struct platform_device *pdev)
1129 {
1130 struct rspi_data *rspi = platform_get_drvdata(pdev);
1131
1132 rspi_release_dma(rspi->ctlr);
1133 pm_runtime_disable(&pdev->dev);
1134
1135 return 0;
1136 }
1137
1138 static const struct spi_ops rspi_ops = {
1139 .set_config_register = rspi_set_config_register,
1140 .transfer_one = rspi_transfer_one,
1141 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1142 .flags = SPI_CONTROLLER_MUST_TX,
1143 .fifo_size = 8,
1144 };
1145
1146 static const struct spi_ops rspi_rz_ops = {
1147 .set_config_register = rspi_rz_set_config_register,
1148 .transfer_one = rspi_rz_transfer_one,
1149 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1150 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1151 .fifo_size = 8, /* 8 for TX, 32 for RX */
1152 };
1153
1154 static const struct spi_ops qspi_ops = {
1155 .set_config_register = qspi_set_config_register,
1156 .transfer_one = qspi_transfer_one,
1157 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1158 SPI_TX_DUAL | SPI_TX_QUAD |
1159 SPI_RX_DUAL | SPI_RX_QUAD,
1160 .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX,
1161 .fifo_size = 32,
1162 };
1163
1164 #ifdef CONFIG_OF
1165 static const struct of_device_id rspi_of_match[] = {
1166 /* RSPI on legacy SH */
1167 { .compatible = "renesas,rspi", .data = &rspi_ops },
1168 /* RSPI on RZ/A1H */
1169 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1170 /* QSPI on R-Car Gen2 */
1171 { .compatible = "renesas,qspi", .data = &qspi_ops },
1172 { /* sentinel */ }
1173 };
1174
1175 MODULE_DEVICE_TABLE(of, rspi_of_match);
1176
1177 static int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1178 {
1179 u32 num_cs;
1180 int error;
1181
1182 /* Parse DT properties */
1183 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1184 if (error) {
1185 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1186 return error;
1187 }
1188
1189 ctlr->num_chipselect = num_cs;
1190 return 0;
1191 }
1192 #else
1193 #define rspi_of_match NULL
1194 static inline int rspi_parse_dt(struct device *dev, struct spi_controller *ctlr)
1195 {
1196 return -EINVAL;
1197 }
1198 #endif /* CONFIG_OF */
1199
1200 static int rspi_request_irq(struct device *dev, unsigned int irq,
1201 irq_handler_t handler, const char *suffix,
1202 void *dev_id)
1203 {
1204 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s",
1205 dev_name(dev), suffix);
1206 if (!name)
1207 return -ENOMEM;
1208
1209 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1210 }
1211
1212 static int rspi_probe(struct platform_device *pdev)
1213 {
1214 struct resource *res;
1215 struct spi_controller *ctlr;
1216 struct rspi_data *rspi;
1217 int ret;
1218 const struct rspi_plat_data *rspi_pd;
1219 const struct spi_ops *ops;
1220
1221 ctlr = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1222 if (ctlr == NULL)
1223 return -ENOMEM;
1224
1225 ops = of_device_get_match_data(&pdev->dev);
1226 if (ops) {
1227 ret = rspi_parse_dt(&pdev->dev, ctlr);
1228 if (ret)
1229 goto error1;
1230 } else {
1231 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1232 rspi_pd = dev_get_platdata(&pdev->dev);
1233 if (rspi_pd && rspi_pd->num_chipselect)
1234 ctlr->num_chipselect = rspi_pd->num_chipselect;
1235 else
1236 ctlr->num_chipselect = 2; /* default */
1237 }
1238
1239 /* ops parameter check */
1240 if (!ops->set_config_register) {
1241 dev_err(&pdev->dev, "there is no set_config_register\n");
1242 ret = -ENODEV;
1243 goto error1;
1244 }
1245
1246 rspi = spi_controller_get_devdata(ctlr);
1247 platform_set_drvdata(pdev, rspi);
1248 rspi->ops = ops;
1249 rspi->ctlr = ctlr;
1250
1251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1252 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1253 if (IS_ERR(rspi->addr)) {
1254 ret = PTR_ERR(rspi->addr);
1255 goto error1;
1256 }
1257
1258 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1259 if (IS_ERR(rspi->clk)) {
1260 dev_err(&pdev->dev, "cannot get clock\n");
1261 ret = PTR_ERR(rspi->clk);
1262 goto error1;
1263 }
1264
1265 pm_runtime_enable(&pdev->dev);
1266
1267 init_waitqueue_head(&rspi->wait);
1268
1269 ctlr->bus_num = pdev->id;
1270 ctlr->setup = rspi_setup;
1271 ctlr->auto_runtime_pm = true;
1272 ctlr->transfer_one = ops->transfer_one;
1273 ctlr->prepare_message = rspi_prepare_message;
1274 ctlr->unprepare_message = rspi_unprepare_message;
1275 ctlr->mode_bits = ops->mode_bits;
1276 ctlr->flags = ops->flags;
1277 ctlr->dev.of_node = pdev->dev.of_node;
1278
1279 ret = platform_get_irq_byname(pdev, "rx");
1280 if (ret < 0) {
1281 ret = platform_get_irq_byname(pdev, "mux");
1282 if (ret < 0)
1283 ret = platform_get_irq(pdev, 0);
1284 if (ret >= 0)
1285 rspi->rx_irq = rspi->tx_irq = ret;
1286 } else {
1287 rspi->rx_irq = ret;
1288 ret = platform_get_irq_byname(pdev, "tx");
1289 if (ret >= 0)
1290 rspi->tx_irq = ret;
1291 }
1292 if (ret < 0) {
1293 dev_err(&pdev->dev, "platform_get_irq error\n");
1294 goto error2;
1295 }
1296
1297 if (rspi->rx_irq == rspi->tx_irq) {
1298 /* Single multiplexed interrupt */
1299 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1300 "mux", rspi);
1301 } else {
1302 /* Multi-interrupt mode, only SPRI and SPTI are used */
1303 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1304 "rx", rspi);
1305 if (!ret)
1306 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1307 rspi_irq_tx, "tx", rspi);
1308 }
1309 if (ret < 0) {
1310 dev_err(&pdev->dev, "request_irq error\n");
1311 goto error2;
1312 }
1313
1314 ret = rspi_request_dma(&pdev->dev, ctlr, res);
1315 if (ret < 0)
1316 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1317
1318 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1321 goto error3;
1322 }
1323
1324 dev_info(&pdev->dev, "probed\n");
1325
1326 return 0;
1327
1328 error3:
1329 rspi_release_dma(ctlr);
1330 error2:
1331 pm_runtime_disable(&pdev->dev);
1332 error1:
1333 spi_controller_put(ctlr);
1334
1335 return ret;
1336 }
1337
1338 static const struct platform_device_id spi_driver_ids[] = {
1339 { "rspi", (kernel_ulong_t)&rspi_ops },
1340 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1341 { "qspi", (kernel_ulong_t)&qspi_ops },
1342 {},
1343 };
1344
1345 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1346
1347 #ifdef CONFIG_PM_SLEEP
1348 static int rspi_suspend(struct device *dev)
1349 {
1350 struct rspi_data *rspi = dev_get_drvdata(dev);
1351
1352 return spi_controller_suspend(rspi->ctlr);
1353 }
1354
1355 static int rspi_resume(struct device *dev)
1356 {
1357 struct rspi_data *rspi = dev_get_drvdata(dev);
1358
1359 return spi_controller_resume(rspi->ctlr);
1360 }
1361
1362 static SIMPLE_DEV_PM_OPS(rspi_pm_ops, rspi_suspend, rspi_resume);
1363 #define DEV_PM_OPS &rspi_pm_ops
1364 #else
1365 #define DEV_PM_OPS NULL
1366 #endif /* CONFIG_PM_SLEEP */
1367
1368 static struct platform_driver rspi_driver = {
1369 .probe = rspi_probe,
1370 .remove = rspi_remove,
1371 .id_table = spi_driver_ids,
1372 .driver = {
1373 .name = "renesas_spi",
1374 .pm = DEV_PM_OPS,
1375 .of_match_table = of_match_ptr(rspi_of_match),
1376 },
1377 };
1378 module_platform_driver(rspi_driver);
1379
1380 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1381 MODULE_LICENSE("GPL v2");
1382 MODULE_AUTHOR("Yoshihiro Shimoda");
1383 MODULE_ALIAS("platform:rspi");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git