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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/spi/stm32_spi.c
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
16 #include <linux/bitfield.h>
17 #include <linux/iopoll.h>
19 /* STM32 SPI registers */
20 #define STM32_SPI_CR1 0x00
21 #define STM32_SPI_CR2 0x04
22 #define STM32_SPI_CFG1 0x08
23 #define STM32_SPI_CFG2 0x0C
24 #define STM32_SPI_SR 0x14
25 #define STM32_SPI_IFCR 0x18
26 #define STM32_SPI_TXDR 0x20
27 #define STM32_SPI_RXDR 0x30
28 #define STM32_SPI_I2SCFGR 0x50
30 /* STM32_SPI_CR1 bit fields */
31 #define SPI_CR1_SPE BIT(0)
32 #define SPI_CR1_MASRX BIT(8)
33 #define SPI_CR1_CSTART BIT(9)
34 #define SPI_CR1_CSUSP BIT(10)
35 #define SPI_CR1_HDDIR BIT(11)
36 #define SPI_CR1_SSI BIT(12)
38 /* STM32_SPI_CR2 bit fields */
39 #define SPI_CR2_TSIZE GENMASK(15, 0)
41 /* STM32_SPI_CFG1 bit fields */
42 #define SPI_CFG1_DSIZE GENMASK(4, 0)
43 #define SPI_CFG1_DSIZE_MIN 3
44 #define SPI_CFG1_FTHLV_SHIFT 5
45 #define SPI_CFG1_FTHLV GENMASK(8, 5)
46 #define SPI_CFG1_MBR_SHIFT 28
47 #define SPI_CFG1_MBR GENMASK(30, 28)
48 #define SPI_CFG1_MBR_MIN 0
49 #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
51 /* STM32_SPI_CFG2 bit fields */
52 #define SPI_CFG2_COMM_SHIFT 17
53 #define SPI_CFG2_COMM GENMASK(18, 17)
54 #define SPI_CFG2_MASTER BIT(22)
55 #define SPI_CFG2_LSBFRST BIT(23)
56 #define SPI_CFG2_CPHA BIT(24)
57 #define SPI_CFG2_CPOL BIT(25)
58 #define SPI_CFG2_SSM BIT(26)
59 #define SPI_CFG2_AFCNTR BIT(31)
61 /* STM32_SPI_SR bit fields */
62 #define SPI_SR_RXP BIT(0)
63 #define SPI_SR_TXP BIT(1)
64 #define SPI_SR_EOT BIT(3)
65 #define SPI_SR_TXTF BIT(4)
66 #define SPI_SR_OVR BIT(6)
67 #define SPI_SR_SUSP BIT(11)
68 #define SPI_SR_RXPLVL_SHIFT 13
69 #define SPI_SR_RXPLVL GENMASK(14, 13)
70 #define SPI_SR_RXWNE BIT(15)
72 /* STM32_SPI_IFCR bit fields */
73 #define SPI_IFCR_ALL GENMASK(11, 3)
75 /* STM32_SPI_I2SCFGR bit fields */
76 #define SPI_I2SCFGR_I2SMOD BIT(0)
78 #define MAX_CS_COUNT 4
80 /* SPI Master Baud Rate min/max divisor */
81 #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
82 #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
84 #define STM32_SPI_TIMEOUT_US 100000
86 /* SPI Communication mode */
87 #define SPI_FULL_DUPLEX 0
88 #define SPI_SIMPLEX_TX 1
89 #define SPI_SIMPLEX_RX 2
90 #define SPI_HALF_DUPLEX 3
92 struct stm32_spi_priv
{
95 struct reset_ctl rst_ctl
;
96 struct gpio_desc cs_gpios
[MAX_CS_COUNT
];
98 unsigned int fifo_size
;
101 unsigned int cur_xferlen
; /* current transfer length in bytes */
102 int tx_len
; /* number of data to be written in bytes */
103 int rx_len
; /* number of data to be read in bytes */
104 const void *tx_buf
; /* data to be written, or NULL */
105 void *rx_buf
; /* data to be read, or NULL */
110 static void stm32_spi_write_txfifo(struct stm32_spi_priv
*priv
)
112 while ((priv
->tx_len
> 0) &&
113 (readl(priv
->base
+ STM32_SPI_SR
) & SPI_SR_TXP
)) {
114 u32 offs
= priv
->cur_xferlen
- priv
->tx_len
;
116 if (priv
->tx_len
>= sizeof(u32
) &&
117 IS_ALIGNED((uintptr_t)(priv
->tx_buf
+ offs
), sizeof(u32
))) {
118 const u32
*tx_buf32
= (const u32
*)(priv
->tx_buf
+ offs
);
120 writel(*tx_buf32
, priv
->base
+ STM32_SPI_TXDR
);
121 priv
->tx_len
-= sizeof(u32
);
122 } else if (priv
->tx_len
>= sizeof(u16
) &&
123 IS_ALIGNED((uintptr_t)(priv
->tx_buf
+ offs
), sizeof(u16
))) {
124 const u16
*tx_buf16
= (const u16
*)(priv
->tx_buf
+ offs
);
126 writew(*tx_buf16
, priv
->base
+ STM32_SPI_TXDR
);
127 priv
->tx_len
-= sizeof(u16
);
129 const u8
*tx_buf8
= (const u8
*)(priv
->tx_buf
+ offs
);
131 writeb(*tx_buf8
, priv
->base
+ STM32_SPI_TXDR
);
132 priv
->tx_len
-= sizeof(u8
);
136 debug("%s: %d bytes left\n", __func__
, priv
->tx_len
);
139 static void stm32_spi_read_rxfifo(struct stm32_spi_priv
*priv
)
141 u32 sr
= readl(priv
->base
+ STM32_SPI_SR
);
142 u32 rxplvl
= (sr
& SPI_SR_RXPLVL
) >> SPI_SR_RXPLVL_SHIFT
;
144 while ((priv
->rx_len
> 0) &&
145 ((sr
& SPI_SR_RXP
) ||
146 ((sr
& SPI_SR_EOT
) && ((sr
& SPI_SR_RXWNE
) || (rxplvl
> 0))))) {
147 u32 offs
= priv
->cur_xferlen
- priv
->rx_len
;
149 if (IS_ALIGNED((uintptr_t)(priv
->rx_buf
+ offs
), sizeof(u32
)) &&
150 (priv
->rx_len
>= sizeof(u32
) || (sr
& SPI_SR_RXWNE
))) {
151 u32
*rx_buf32
= (u32
*)(priv
->rx_buf
+ offs
);
153 *rx_buf32
= readl(priv
->base
+ STM32_SPI_RXDR
);
154 priv
->rx_len
-= sizeof(u32
);
155 } else if (IS_ALIGNED((uintptr_t)(priv
->rx_buf
+ offs
), sizeof(u16
)) &&
156 (priv
->rx_len
>= sizeof(u16
) ||
157 (!(sr
& SPI_SR_RXWNE
) &&
158 (rxplvl
>= 2 || priv
->cur_bpw
> 8)))) {
159 u16
*rx_buf16
= (u16
*)(priv
->rx_buf
+ offs
);
161 *rx_buf16
= readw(priv
->base
+ STM32_SPI_RXDR
);
162 priv
->rx_len
-= sizeof(u16
);
164 u8
*rx_buf8
= (u8
*)(priv
->rx_buf
+ offs
);
166 *rx_buf8
= readb(priv
->base
+ STM32_SPI_RXDR
);
167 priv
->rx_len
-= sizeof(u8
);
170 sr
= readl(priv
->base
+ STM32_SPI_SR
);
171 rxplvl
= (sr
& SPI_SR_RXPLVL
) >> SPI_SR_RXPLVL_SHIFT
;
174 debug("%s: %d bytes left\n", __func__
, priv
->rx_len
);
177 static int stm32_spi_enable(struct stm32_spi_priv
*priv
)
179 debug("%s\n", __func__
);
181 /* Enable the SPI hardware */
182 setbits_le32(priv
->base
+ STM32_SPI_CR1
, SPI_CR1_SPE
);
187 static int stm32_spi_disable(struct stm32_spi_priv
*priv
)
189 debug("%s\n", __func__
);
191 /* Disable the SPI hardware */
192 clrbits_le32(priv
->base
+ STM32_SPI_CR1
, SPI_CR1_SPE
);
197 static int stm32_spi_claim_bus(struct udevice
*slave
)
199 struct udevice
*bus
= dev_get_parent(slave
);
200 struct stm32_spi_priv
*priv
= dev_get_priv(bus
);
202 debug("%s\n", __func__
);
204 /* Enable the SPI hardware */
205 return stm32_spi_enable(priv
);
208 static int stm32_spi_release_bus(struct udevice
*slave
)
210 struct udevice
*bus
= dev_get_parent(slave
);
211 struct stm32_spi_priv
*priv
= dev_get_priv(bus
);
213 debug("%s\n", __func__
);
215 /* Disable the SPI hardware */
216 return stm32_spi_disable(priv
);
219 static void stm32_spi_stopxfer(struct udevice
*dev
)
221 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
225 debug("%s\n", __func__
);
227 cr1
= readl(priv
->base
+ STM32_SPI_CR1
);
229 if (!(cr1
& SPI_CR1_SPE
))
232 /* Wait on EOT or suspend the flow */
233 ret
= readl_poll_timeout(priv
->base
+ STM32_SPI_SR
, sr
,
234 !(sr
& SPI_SR_EOT
), 100000);
236 if (cr1
& SPI_CR1_CSTART
) {
237 writel(cr1
| SPI_CR1_CSUSP
, priv
->base
+ STM32_SPI_CR1
);
238 if (readl_poll_timeout(priv
->base
+ STM32_SPI_SR
,
239 sr
, !(sr
& SPI_SR_SUSP
),
241 dev_err(dev
, "Suspend request timeout\n");
245 /* clear status flags */
246 setbits_le32(priv
->base
+ STM32_SPI_IFCR
, SPI_IFCR_ALL
);
249 static int stm32_spi_set_cs(struct udevice
*dev
, unsigned int cs
, bool enable
)
251 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
253 debug("%s: cs=%d enable=%d\n", __func__
, cs
, enable
);
255 if (cs
>= MAX_CS_COUNT
)
258 if (!dm_gpio_is_valid(&priv
->cs_gpios
[cs
]))
264 return dm_gpio_set_value(&priv
->cs_gpios
[cs
], enable
? 1 : 0);
267 static int stm32_spi_set_mode(struct udevice
*bus
, uint mode
)
269 struct stm32_spi_priv
*priv
= dev_get_priv(bus
);
270 u32 cfg2_clrb
= 0, cfg2_setb
= 0;
272 debug("%s: mode=%d\n", __func__
, mode
);
275 cfg2_setb
|= SPI_CFG2_CPOL
;
277 cfg2_clrb
|= SPI_CFG2_CPOL
;
280 cfg2_setb
|= SPI_CFG2_CPHA
;
282 cfg2_clrb
|= SPI_CFG2_CPHA
;
284 if (mode
& SPI_LSB_FIRST
)
285 cfg2_setb
|= SPI_CFG2_LSBFRST
;
287 cfg2_clrb
|= SPI_CFG2_LSBFRST
;
289 if (cfg2_clrb
|| cfg2_setb
)
290 clrsetbits_le32(priv
->base
+ STM32_SPI_CFG2
,
291 cfg2_clrb
, cfg2_setb
);
293 if (mode
& SPI_CS_HIGH
)
294 priv
->cs_high
= true;
296 priv
->cs_high
= false;
300 static int stm32_spi_set_fthlv(struct udevice
*dev
, u32 xfer_len
)
302 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
303 u32 fthlv
, half_fifo
;
305 /* data packet should not exceed 1/2 of fifo space */
306 half_fifo
= (priv
->fifo_size
/ 2);
308 /* data_packet should not exceed transfer length */
309 fthlv
= (half_fifo
> xfer_len
) ? xfer_len
: half_fifo
;
311 /* align packet size with data registers access */
312 fthlv
-= (fthlv
% 4);
316 clrsetbits_le32(priv
->base
+ STM32_SPI_CFG1
, SPI_CFG1_FTHLV
,
317 (fthlv
- 1) << SPI_CFG1_FTHLV_SHIFT
);
322 static int stm32_spi_set_speed(struct udevice
*bus
, uint hz
)
324 struct stm32_spi_priv
*priv
= dev_get_priv(bus
);
327 debug("%s: hz=%d\n", __func__
, hz
);
329 if (priv
->cur_hz
== hz
)
332 div
= DIV_ROUND_UP(priv
->bus_clk_rate
, hz
);
334 if (div
< STM32_MBR_DIV_MIN
||
335 div
> STM32_MBR_DIV_MAX
)
338 /* Determine the first power of 2 greater than or equal to div */
342 mbrdiv
= fls(div
) - 1;
344 if ((mbrdiv
- 1) < 0)
347 clrsetbits_le32(priv
->base
+ STM32_SPI_CFG1
, SPI_CFG1_MBR
,
348 (mbrdiv
- 1) << SPI_CFG1_MBR_SHIFT
);
355 static int stm32_spi_xfer(struct udevice
*slave
, unsigned int bitlen
,
356 const void *dout
, void *din
, unsigned long flags
)
358 struct udevice
*bus
= dev_get_parent(slave
);
359 struct dm_spi_slave_platdata
*slave_plat
;
360 struct stm32_spi_priv
*priv
= dev_get_priv(bus
);
367 xferlen
= bitlen
/ 8;
369 if (xferlen
<= SPI_CR2_TSIZE
)
370 writel(xferlen
, priv
->base
+ STM32_SPI_CR2
);
376 priv
->tx_len
= priv
->tx_buf
? bitlen
/ 8 : 0;
377 priv
->rx_len
= priv
->rx_buf
? bitlen
/ 8 : 0;
379 mode
= SPI_FULL_DUPLEX
;
381 mode
= SPI_SIMPLEX_RX
;
382 else if (!priv
->rx_buf
)
383 mode
= SPI_SIMPLEX_TX
;
385 if (priv
->cur_xferlen
!= xferlen
|| priv
->cur_mode
!= mode
) {
386 priv
->cur_mode
= mode
;
387 priv
->cur_xferlen
= xferlen
;
389 /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
390 stm32_spi_disable(priv
);
392 clrsetbits_le32(priv
->base
+ STM32_SPI_CFG2
, SPI_CFG2_COMM
,
393 mode
<< SPI_CFG2_COMM_SHIFT
);
395 stm32_spi_set_fthlv(bus
, xferlen
);
397 /* Enable the SPI hardware */
398 stm32_spi_enable(priv
);
401 debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__
,
402 priv
->tx_len
, priv
->rx_len
);
404 slave_plat
= dev_get_parent_platdata(slave
);
405 if (flags
& SPI_XFER_BEGIN
)
406 stm32_spi_set_cs(bus
, slave_plat
->cs
, false);
408 /* Be sure to have data in fifo before starting data transfer */
410 stm32_spi_write_txfifo(priv
);
412 setbits_le32(priv
->base
+ STM32_SPI_CR1
, SPI_CR1_CSTART
);
415 sr
= readl(priv
->base
+ STM32_SPI_SR
);
417 if (sr
& SPI_SR_OVR
) {
418 dev_err(bus
, "Overrun: RX data lost\n");
423 if (sr
& SPI_SR_SUSP
) {
424 dev_warn(bus
, "System too slow is limiting data throughput\n");
426 if (priv
->rx_buf
&& priv
->rx_len
> 0)
427 stm32_spi_read_rxfifo(priv
);
432 if (sr
& SPI_SR_TXTF
)
436 if (priv
->tx_buf
&& priv
->tx_len
> 0)
437 stm32_spi_write_txfifo(priv
);
440 if (priv
->rx_buf
&& priv
->rx_len
> 0)
441 stm32_spi_read_rxfifo(priv
);
443 if (sr
& SPI_SR_EOT
) {
444 if (priv
->rx_buf
&& priv
->rx_len
> 0)
445 stm32_spi_read_rxfifo(priv
);
449 writel(ifcr
, priv
->base
+ STM32_SPI_IFCR
);
452 /* clear status flags */
453 setbits_le32(priv
->base
+ STM32_SPI_IFCR
, SPI_IFCR_ALL
);
454 stm32_spi_stopxfer(bus
);
456 if (flags
& SPI_XFER_END
)
457 stm32_spi_set_cs(bus
, slave_plat
->cs
, true);
462 static int stm32_spi_get_fifo_size(struct udevice
*dev
)
464 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
467 stm32_spi_enable(priv
);
469 while (readl(priv
->base
+ STM32_SPI_SR
) & SPI_SR_TXP
)
470 writeb(++count
, priv
->base
+ STM32_SPI_TXDR
);
472 stm32_spi_disable(priv
);
474 debug("%s %d x 8-bit fifo size\n", __func__
, count
);
479 static int stm32_spi_probe(struct udevice
*dev
)
481 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
482 unsigned long clk_rate
;
486 priv
->base
= dev_remap_addr(dev
);
491 ret
= clk_get_by_index(dev
, 0, &priv
->clk
);
495 ret
= clk_enable(&priv
->clk
);
499 clk_rate
= clk_get_rate(&priv
->clk
);
505 priv
->bus_clk_rate
= clk_rate
;
508 ret
= reset_get_by_index(dev
, 0, &priv
->rst_ctl
);
512 reset_assert(&priv
->rst_ctl
);
514 reset_deassert(&priv
->rst_ctl
);
516 ret
= gpio_request_list_by_name(dev
, "cs-gpios", priv
->cs_gpios
,
517 ARRAY_SIZE(priv
->cs_gpios
), 0);
519 pr_err("Can't get %s cs gpios: %d", dev
->name
, ret
);
523 priv
->fifo_size
= stm32_spi_get_fifo_size(dev
);
525 priv
->cur_mode
= SPI_FULL_DUPLEX
;
526 priv
->cur_xferlen
= 0;
527 priv
->cur_bpw
= SPI_DEFAULT_WORDLEN
;
528 clrsetbits_le32(priv
->base
+ STM32_SPI_CFG1
, SPI_CFG1_DSIZE
,
531 for (i
= 0; i
< ARRAY_SIZE(priv
->cs_gpios
); i
++) {
532 if (!dm_gpio_is_valid(&priv
->cs_gpios
[i
]))
535 dm_gpio_set_dir_flags(&priv
->cs_gpios
[i
],
536 GPIOD_IS_OUT
| GPIOD_IS_OUT_ACTIVE
);
539 /* Ensure I2SMOD bit is kept cleared */
540 clrbits_le32(priv
->base
+ STM32_SPI_I2SCFGR
, SPI_I2SCFGR_I2SMOD
);
543 * - SS input value high
544 * - transmitter half duplex direction
545 * - automatic communication suspend when RX-Fifo is full
547 setbits_le32(priv
->base
+ STM32_SPI_CR1
,
548 SPI_CR1_SSI
| SPI_CR1_HDDIR
| SPI_CR1_MASRX
);
551 * - Set the master mode (default Motorola mode)
552 * - Consider 1 master/n slaves configuration and
553 * SS input value is determined by the SSI bit
554 * - keep control of all associated GPIOs
556 setbits_le32(priv
->base
+ STM32_SPI_CFG2
,
557 SPI_CFG2_MASTER
| SPI_CFG2_SSM
| SPI_CFG2_AFCNTR
);
562 reset_free(&priv
->rst_ctl
);
565 clk_disable(&priv
->clk
);
566 clk_free(&priv
->clk
);
571 static int stm32_spi_remove(struct udevice
*dev
)
573 struct stm32_spi_priv
*priv
= dev_get_priv(dev
);
576 stm32_spi_stopxfer(dev
);
577 stm32_spi_disable(priv
);
579 ret
= reset_assert(&priv
->rst_ctl
);
583 reset_free(&priv
->rst_ctl
);
585 ret
= clk_disable(&priv
->clk
);
589 clk_free(&priv
->clk
);
594 static const struct dm_spi_ops stm32_spi_ops
= {
595 .claim_bus
= stm32_spi_claim_bus
,
596 .release_bus
= stm32_spi_release_bus
,
597 .set_mode
= stm32_spi_set_mode
,
598 .set_speed
= stm32_spi_set_speed
,
599 .xfer
= stm32_spi_xfer
,
602 static const struct udevice_id stm32_spi_ids
[] = {
603 { .compatible
= "st,stm32h7-spi", },
607 U_BOOT_DRIVER(stm32_spi
) = {
610 .of_match
= stm32_spi_ids
,
611 .ops
= &stm32_spi_ops
,
612 .priv_auto_alloc_size
= sizeof(struct stm32_spi_priv
),
613 .probe
= stm32_spi_probe
,
614 .remove
= stm32_spi_remove
,