2 * Copyright (c) 2010-2013 NVIDIA Corporation
3 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch-tegra/clk_rst.h>
19 #include "tegra_spi.h"
21 DECLARE_GLOBAL_DATA_PTR
;
23 #define SPI_CMD_GO (1 << 30)
24 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
25 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
26 #define SPI_CMD_CK_SDA (1 << 21)
27 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
28 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
29 #define SPI_CMD_CS_POL (1 << 16)
30 #define SPI_CMD_TXEN (1 << 15)
31 #define SPI_CMD_RXEN (1 << 14)
32 #define SPI_CMD_CS_VAL (1 << 13)
33 #define SPI_CMD_CS_SOFT (1 << 12)
34 #define SPI_CMD_CS_DELAY (1 << 9)
35 #define SPI_CMD_CS3_EN (1 << 8)
36 #define SPI_CMD_CS2_EN (1 << 7)
37 #define SPI_CMD_CS1_EN (1 << 6)
38 #define SPI_CMD_CS0_EN (1 << 5)
39 #define SPI_CMD_BIT_LENGTH (1 << 4)
40 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
42 #define SPI_STAT_BSY (1 << 31)
43 #define SPI_STAT_RDY (1 << 30)
44 #define SPI_STAT_RXF_FLUSH (1 << 29)
45 #define SPI_STAT_TXF_FLUSH (1 << 28)
46 #define SPI_STAT_RXF_UNR (1 << 27)
47 #define SPI_STAT_TXF_OVF (1 << 26)
48 #define SPI_STAT_RXF_EMPTY (1 << 25)
49 #define SPI_STAT_RXF_FULL (1 << 24)
50 #define SPI_STAT_TXF_EMPTY (1 << 23)
51 #define SPI_STAT_TXF_FULL (1 << 22)
52 #define SPI_STAT_SEL_TXRX_N (1 << 16)
53 #define SPI_STAT_CUR_BLKCNT (1 << 15)
55 #define SPI_TIMEOUT 1000
56 #define TEGRA_SPI_MAX_FREQ 52000000
59 u32 command
; /* SPI_COMMAND_0 register */
60 u32 status
; /* SPI_STATUS_0 register */
61 u32 rx_cmp
; /* SPI_RX_CMP_0 register */
62 u32 dma_ctl
; /* SPI_DMA_CTL_0 register */
63 u32 tx_fifo
; /* SPI_TX_FIFO_0 register */
64 u32 rsvd
[3]; /* offsets 0x14 to 0x1F reserved */
65 u32 rx_fifo
; /* SPI_RX_FIFO_0 register */
68 struct tegra20_sflash_priv
{
69 struct spi_regs
*regs
;
74 int last_transaction_us
;
77 int tegra20_sflash_cs_info(struct udevice
*bus
, unsigned int cs
,
78 struct spi_cs_info
*info
)
80 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
87 static int tegra20_sflash_ofdata_to_platdata(struct udevice
*bus
)
89 struct tegra_spi_platdata
*plat
= bus
->platdata
;
90 const void *blob
= gd
->fdt_blob
;
91 int node
= bus
->of_offset
;
93 plat
->base
= fdtdec_get_addr(blob
, node
, "reg");
94 plat
->periph_id
= clock_decode_periph_id(blob
, node
);
96 if (plat
->periph_id
== PERIPH_ID_NONE
) {
97 debug("%s: could not decode periph id %d\n", __func__
,
99 return -FDT_ERR_NOTFOUND
;
102 /* Use 500KHz as a suitable default */
103 plat
->frequency
= fdtdec_get_int(blob
, node
, "spi-max-frequency",
105 plat
->deactivate_delay_us
= fdtdec_get_int(blob
, node
,
106 "spi-deactivate-delay", 0);
107 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
108 __func__
, plat
->base
, plat
->periph_id
, plat
->frequency
,
109 plat
->deactivate_delay_us
);
114 static int tegra20_sflash_probe(struct udevice
*bus
)
116 struct tegra_spi_platdata
*plat
= dev_get_platdata(bus
);
117 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
119 priv
->regs
= (struct spi_regs
*)plat
->base
;
121 priv
->last_transaction_us
= timer_get_us();
122 priv
->freq
= plat
->frequency
;
123 priv
->periph_id
= plat
->periph_id
;
128 static int tegra20_sflash_claim_bus(struct udevice
*bus
)
130 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
131 struct spi_regs
*regs
= priv
->regs
;
134 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
135 clock_start_periph_pll(priv
->periph_id
, CLOCK_ID_PERIPH
,
138 /* Clear stale status here */
139 reg
= SPI_STAT_RDY
| SPI_STAT_RXF_FLUSH
| SPI_STAT_TXF_FLUSH
| \
140 SPI_STAT_RXF_UNR
| SPI_STAT_TXF_OVF
;
141 writel(reg
, ®s
->status
);
142 debug("%s: STATUS = %08x\n", __func__
, readl(®s
->status
));
145 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
147 reg
= (priv
->mode
& 1) << SPI_CMD_ACTIVE_SDA_SHIFT
;
149 reg
|= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT
;
150 clrsetbits_le32(®s
->command
, SPI_CMD_ACTIVE_SCLK_MASK
|
151 SPI_CMD_ACTIVE_SDA_MASK
, SPI_CMD_CS_SOFT
| reg
);
152 debug("%s: COMMAND = %08x\n", __func__
, readl(®s
->command
));
155 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
158 pinmux_set_func(PMUX_PINGRP_GMD
, PMUX_FUNC_SFLASH
);
159 pinmux_tristate_disable(PMUX_PINGRP_LSPI
);
160 pinmux_set_func(PMUX_PINGRP_GMC
, PMUX_FUNC_SFLASH
);
165 static void spi_cs_activate(struct udevice
*dev
)
167 struct udevice
*bus
= dev
->parent
;
168 struct tegra_spi_platdata
*pdata
= dev_get_platdata(bus
);
169 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
171 /* If it's too soon to do another transaction, wait */
172 if (pdata
->deactivate_delay_us
&&
173 priv
->last_transaction_us
) {
174 ulong delay_us
; /* The delay completed so far */
175 delay_us
= timer_get_us() - priv
->last_transaction_us
;
176 if (delay_us
< pdata
->deactivate_delay_us
)
177 udelay(pdata
->deactivate_delay_us
- delay_us
);
180 /* CS is negated on Tegra, so drive a 1 to get a 0 */
181 setbits_le32(&priv
->regs
->command
, SPI_CMD_CS_VAL
);
184 static void spi_cs_deactivate(struct udevice
*dev
)
186 struct udevice
*bus
= dev
->parent
;
187 struct tegra_spi_platdata
*pdata
= dev_get_platdata(bus
);
188 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
190 /* CS is negated on Tegra, so drive a 0 to get a 1 */
191 clrbits_le32(&priv
->regs
->command
, SPI_CMD_CS_VAL
);
193 /* Remember time of this transaction so we can honour the bus delay */
194 if (pdata
->deactivate_delay_us
)
195 priv
->last_transaction_us
= timer_get_us();
198 static int tegra20_sflash_xfer(struct udevice
*dev
, unsigned int bitlen
,
199 const void *data_out
, void *data_in
,
202 struct udevice
*bus
= dev
->parent
;
203 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
204 struct spi_regs
*regs
= priv
->regs
;
205 u32 reg
, tmpdout
, tmpdin
= 0;
206 const u8
*dout
= data_out
;
211 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
212 __func__
, bus
->seq
, spi_chip_select(dev
), dout
, din
, bitlen
);
215 num_bytes
= bitlen
/ 8;
219 reg
= readl(®s
->status
);
220 writel(reg
, ®s
->status
); /* Clear all SPI events via R/W */
221 debug("spi_xfer entry: STATUS = %08x\n", reg
);
223 reg
= readl(®s
->command
);
224 reg
|= SPI_CMD_TXEN
| SPI_CMD_RXEN
;
225 writel(reg
, ®s
->command
);
226 debug("spi_xfer: COMMAND = %08x\n", readl(®s
->command
));
228 if (flags
& SPI_XFER_BEGIN
)
229 spi_cs_activate(dev
);
231 /* handle data in 32-bit chunks */
232 while (num_bytes
> 0) {
238 bytes
= (num_bytes
> 4) ? 4 : num_bytes
;
241 for (i
= 0; i
< bytes
; ++i
)
242 tmpdout
= (tmpdout
<< 8) | dout
[i
];
249 clrsetbits_le32(®s
->command
, SPI_CMD_BIT_LENGTH_MASK
,
251 writel(tmpdout
, ®s
->tx_fifo
);
252 setbits_le32(®s
->command
, SPI_CMD_GO
);
255 * Wait for SPI transmit FIFO to empty, or to time out.
256 * The RX FIFO status will be read and cleared last
258 for (tm
= 0, is_read
= 0; tm
< SPI_TIMEOUT
; ++tm
) {
261 status
= readl(®s
->status
);
263 /* We can exit when we've had both RX and TX activity */
264 if (is_read
&& (status
& SPI_STAT_TXF_EMPTY
))
267 if ((status
& (SPI_STAT_BSY
| SPI_STAT_RDY
)) !=
271 else if (!(status
& SPI_STAT_RXF_EMPTY
)) {
272 tmpdin
= readl(®s
->rx_fifo
);
275 /* swap bytes read in */
277 for (i
= bytes
- 1; i
>= 0; --i
) {
278 din
[i
] = tmpdin
& 0xff;
286 if (tm
>= SPI_TIMEOUT
)
289 /* clear ACK RDY, etc. bits */
290 writel(readl(®s
->status
), ®s
->status
);
293 if (flags
& SPI_XFER_END
)
294 spi_cs_deactivate(dev
);
296 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
297 tmpdin
, readl(®s
->status
));
300 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret
);
307 static int tegra20_sflash_set_speed(struct udevice
*bus
, uint speed
)
309 struct tegra_spi_platdata
*plat
= bus
->platdata
;
310 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
312 if (speed
> plat
->frequency
)
313 speed
= plat
->frequency
;
315 debug("%s: regs=%p, speed=%d\n", __func__
, priv
->regs
, priv
->freq
);
320 static int tegra20_sflash_set_mode(struct udevice
*bus
, uint mode
)
322 struct tegra20_sflash_priv
*priv
= dev_get_priv(bus
);
325 debug("%s: regs=%p, mode=%d\n", __func__
, priv
->regs
, priv
->mode
);
330 static const struct dm_spi_ops tegra20_sflash_ops
= {
331 .claim_bus
= tegra20_sflash_claim_bus
,
332 .xfer
= tegra20_sflash_xfer
,
333 .set_speed
= tegra20_sflash_set_speed
,
334 .set_mode
= tegra20_sflash_set_mode
,
335 .cs_info
= tegra20_sflash_cs_info
,
338 static const struct udevice_id tegra20_sflash_ids
[] = {
339 { .compatible
= "nvidia,tegra20-sflash" },
343 U_BOOT_DRIVER(tegra20_sflash
) = {
344 .name
= "tegra20_sflash",
346 .of_match
= tegra20_sflash_ids
,
347 .ops
= &tegra20_sflash_ops
,
348 .ofdata_to_platdata
= tegra20_sflash_ofdata_to_platdata
,
349 .platdata_auto_alloc_size
= sizeof(struct tegra_spi_platdata
),
350 .priv_auto_alloc_size
= sizeof(struct tegra20_sflash_priv
),
351 .per_child_auto_alloc_size
= sizeof(struct spi_slave
),
352 .probe
= tegra20_sflash_probe
,