2 * NVIDIA Tegra SPI-SLINK controller
4 * Copyright (c) 2010-2013 NVIDIA Corporation
6 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/clock.h>
13 #include <asm/arch-tegra/clk_rst.h>
16 #include "tegra_spi.h"
18 DECLARE_GLOBAL_DATA_PTR
;
21 #define SLINK_CMD_ENB BIT(31)
22 #define SLINK_CMD_GO BIT(30)
23 #define SLINK_CMD_M_S BIT(28)
24 #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
25 #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
26 #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
27 #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
28 #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
29 #define SLINK_CMD_CK_SDA BIT(21)
30 #define SLINK_CMD_CS_POL BIT(13)
31 #define SLINK_CMD_CS_VAL BIT(12)
32 #define SLINK_CMD_CS_SOFT BIT(11)
33 #define SLINK_CMD_BIT_LENGTH BIT(4)
34 #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
36 #define SLINK_CMD2_TXEN BIT(30)
37 #define SLINK_CMD2_RXEN BIT(31)
38 #define SLINK_CMD2_SS_EN BIT(18)
39 #define SLINK_CMD2_SS_EN_SHIFT 18
40 #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
41 #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
43 #define SLINK_STAT_BSY BIT(31)
44 #define SLINK_STAT_RDY BIT(30)
45 #define SLINK_STAT_ERR BIT(29)
46 #define SLINK_STAT_RXF_FLUSH BIT(27)
47 #define SLINK_STAT_TXF_FLUSH BIT(26)
48 #define SLINK_STAT_RXF_OVF BIT(25)
49 #define SLINK_STAT_TXF_UNR BIT(24)
50 #define SLINK_STAT_RXF_EMPTY BIT(23)
51 #define SLINK_STAT_RXF_FULL BIT(22)
52 #define SLINK_STAT_TXF_EMPTY BIT(21)
53 #define SLINK_STAT_TXF_FULL BIT(20)
54 #define SLINK_STAT_TXF_OVF BIT(19)
55 #define SLINK_STAT_RXF_UNR BIT(18)
56 #define SLINK_STAT_CUR_BLKCNT BIT(15)
58 #define SLINK_STAT2_RXF_FULL_CNT BIT(16)
59 #define SLINK_STAT2_TXF_FULL_CNT BIT(0)
61 #define SPI_TIMEOUT 1000
62 #define TEGRA_SPI_MAX_FREQ 52000000
65 u32 command
; /* SLINK_COMMAND_0 register */
66 u32 command2
; /* SLINK_COMMAND2_0 reg */
67 u32 status
; /* SLINK_STATUS_0 register */
68 u32 reserved
; /* Reserved offset 0C */
69 u32 mas_data
; /* SLINK_MAS_DATA_0 reg */
70 u32 slav_data
; /* SLINK_SLAVE_DATA_0 reg */
71 u32 dma_ctl
; /* SLINK_DMA_CTL_0 register */
72 u32 status2
; /* SLINK_STATUS2_0 reg */
73 u32 rsvd
[56]; /* 0x20 to 0xFF reserved */
74 u32 tx_fifo
; /* SLINK_TX_FIFO_0 reg off 100h */
75 u32 rsvd2
[31]; /* 0x104 to 0x17F reserved */
76 u32 rx_fifo
; /* SLINK_RX_FIFO_0 reg off 180h */
79 struct tegra30_spi_priv
{
80 struct spi_regs
*regs
;
85 int last_transaction_us
;
88 struct tegra_spi_slave
{
89 struct spi_slave slave
;
90 struct tegra30_spi_priv
*ctrl
;
93 static int tegra30_spi_ofdata_to_platdata(struct udevice
*bus
)
95 struct tegra_spi_platdata
*plat
= bus
->platdata
;
96 const void *blob
= gd
->fdt_blob
;
97 int node
= dev_of_offset(bus
);
99 plat
->base
= devfdt_get_addr(bus
);
100 plat
->periph_id
= clock_decode_periph_id(bus
);
102 if (plat
->periph_id
== PERIPH_ID_NONE
) {
103 debug("%s: could not decode periph id %d\n", __func__
,
105 return -FDT_ERR_NOTFOUND
;
108 /* Use 500KHz as a suitable default */
109 plat
->frequency
= fdtdec_get_int(blob
, node
, "spi-max-frequency",
111 plat
->deactivate_delay_us
= fdtdec_get_int(blob
, node
,
112 "spi-deactivate-delay", 0);
113 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
114 __func__
, plat
->base
, plat
->periph_id
, plat
->frequency
,
115 plat
->deactivate_delay_us
);
120 static int tegra30_spi_probe(struct udevice
*bus
)
122 struct tegra_spi_platdata
*plat
= dev_get_platdata(bus
);
123 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
125 priv
->regs
= (struct spi_regs
*)plat
->base
;
127 priv
->last_transaction_us
= timer_get_us();
128 priv
->freq
= plat
->frequency
;
129 priv
->periph_id
= plat
->periph_id
;
131 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
132 clock_start_periph_pll(priv
->periph_id
, CLOCK_ID_PERIPH
,
138 static int tegra30_spi_claim_bus(struct udevice
*dev
)
140 struct udevice
*bus
= dev
->parent
;
141 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
142 struct spi_regs
*regs
= priv
->regs
;
145 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
146 clock_start_periph_pll(priv
->periph_id
, CLOCK_ID_PERIPH
,
149 /* Clear stale status here */
150 reg
= SLINK_STAT_RDY
| SLINK_STAT_RXF_FLUSH
| SLINK_STAT_TXF_FLUSH
| \
151 SLINK_STAT_RXF_UNR
| SLINK_STAT_TXF_OVF
;
152 writel(reg
, ®s
->status
);
153 debug("%s: STATUS = %08x\n", __func__
, readl(®s
->status
));
155 /* Set master mode and sw controlled CS */
156 reg
= readl(®s
->command
);
157 reg
|= SLINK_CMD_M_S
| SLINK_CMD_CS_SOFT
;
158 writel(reg
, ®s
->command
);
159 debug("%s: COMMAND = %08x\n", __func__
, readl(®s
->command
));
164 static void spi_cs_activate(struct udevice
*dev
)
166 struct udevice
*bus
= dev
->parent
;
167 struct tegra_spi_platdata
*pdata
= dev_get_platdata(bus
);
168 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
170 /* If it's too soon to do another transaction, wait */
171 if (pdata
->deactivate_delay_us
&&
172 priv
->last_transaction_us
) {
173 ulong delay_us
; /* The delay completed so far */
174 delay_us
= timer_get_us() - priv
->last_transaction_us
;
175 if (delay_us
< pdata
->deactivate_delay_us
)
176 udelay(pdata
->deactivate_delay_us
- delay_us
);
179 /* CS is negated on Tegra, so drive a 1 to get a 0 */
180 setbits_le32(&priv
->regs
->command
, SLINK_CMD_CS_VAL
);
183 static void spi_cs_deactivate(struct udevice
*dev
)
185 struct udevice
*bus
= dev
->parent
;
186 struct tegra_spi_platdata
*pdata
= dev_get_platdata(bus
);
187 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
189 /* CS is negated on Tegra, so drive a 0 to get a 1 */
190 clrbits_le32(&priv
->regs
->command
, SLINK_CMD_CS_VAL
);
192 /* Remember time of this transaction so we can honour the bus delay */
193 if (pdata
->deactivate_delay_us
)
194 priv
->last_transaction_us
= timer_get_us();
197 static int tegra30_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
198 const void *data_out
, void *data_in
,
201 struct udevice
*bus
= dev
->parent
;
202 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
203 struct spi_regs
*regs
= priv
->regs
;
204 u32 reg
, tmpdout
, tmpdin
= 0;
205 const u8
*dout
= data_out
;
210 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
211 __func__
, bus
->seq
, spi_chip_select(dev
), dout
, din
, bitlen
);
214 num_bytes
= bitlen
/ 8;
218 reg
= readl(®s
->status
);
219 writel(reg
, ®s
->status
); /* Clear all SPI events via R/W */
220 debug("%s entry: STATUS = %08x\n", __func__
, reg
);
222 reg
= readl(®s
->status2
);
223 writel(reg
, ®s
->status2
); /* Clear all STATUS2 events via R/W */
224 debug("%s entry: STATUS2 = %08x\n", __func__
, reg
);
226 debug("%s entry: COMMAND = %08x\n", __func__
, readl(®s
->command
));
228 clrsetbits_le32(®s
->command2
, SLINK_CMD2_SS_EN_MASK
,
229 SLINK_CMD2_TXEN
| SLINK_CMD2_RXEN
|
230 (spi_chip_select(dev
) << SLINK_CMD2_SS_EN_SHIFT
));
231 debug("%s entry: COMMAND2 = %08x\n", __func__
, readl(®s
->command2
));
233 if (flags
& SPI_XFER_BEGIN
)
234 spi_cs_activate(dev
);
236 /* handle data in 32-bit chunks */
237 while (num_bytes
> 0) {
243 bytes
= (num_bytes
> 4) ? 4 : num_bytes
;
246 for (i
= 0; i
< bytes
; ++i
)
247 tmpdout
= (tmpdout
<< 8) | dout
[i
];
253 clrsetbits_le32(®s
->command
, SLINK_CMD_BIT_LENGTH_MASK
,
255 writel(tmpdout
, ®s
->tx_fifo
);
256 setbits_le32(®s
->command
, SLINK_CMD_GO
);
259 * Wait for SPI transmit FIFO to empty, or to time out.
260 * The RX FIFO status will be read and cleared last
262 for (tm
= 0, is_read
= 0; tm
< SPI_TIMEOUT
; ++tm
) {
265 status
= readl(®s
->status
);
267 /* We can exit when we've had both RX and TX activity */
268 if (is_read
&& (status
& SLINK_STAT_TXF_EMPTY
))
271 if ((status
& (SLINK_STAT_BSY
| SLINK_STAT_RDY
)) !=
275 else if (!(status
& SLINK_STAT_RXF_EMPTY
)) {
276 tmpdin
= readl(®s
->rx_fifo
);
279 /* swap bytes read in */
281 for (i
= bytes
- 1; i
>= 0; --i
) {
282 din
[i
] = tmpdin
& 0xff;
290 if (tm
>= SPI_TIMEOUT
)
293 /* clear ACK RDY, etc. bits */
294 writel(readl(®s
->status
), ®s
->status
);
297 if (flags
& SPI_XFER_END
)
298 spi_cs_deactivate(dev
);
300 debug("%s: transfer ended. Value=%08x, status = %08x\n",
301 __func__
, tmpdin
, readl(®s
->status
));
304 printf("%s: timeout during SPI transfer, tm %d\n",
312 static int tegra30_spi_set_speed(struct udevice
*bus
, uint speed
)
314 struct tegra_spi_platdata
*plat
= bus
->platdata
;
315 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
317 if (speed
> plat
->frequency
)
318 speed
= plat
->frequency
;
320 debug("%s: regs=%p, speed=%d\n", __func__
, priv
->regs
, priv
->freq
);
325 static int tegra30_spi_set_mode(struct udevice
*bus
, uint mode
)
327 struct tegra30_spi_priv
*priv
= dev_get_priv(bus
);
328 struct spi_regs
*regs
= priv
->regs
;
331 reg
= readl(®s
->command
);
333 /* Set CPOL and CPHA */
334 reg
&= ~(SLINK_CMD_IDLE_SCLK_MASK
| SLINK_CMD_CK_SDA
);
336 reg
|= SLINK_CMD_CK_SDA
;
339 reg
|= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH
;
341 reg
|= SLINK_CMD_IDLE_SCLK_DRIVE_LOW
;
343 writel(reg
, ®s
->command
);
346 debug("%s: regs=%p, mode=%d\n", __func__
, priv
->regs
, priv
->mode
);
351 static const struct dm_spi_ops tegra30_spi_ops
= {
352 .claim_bus
= tegra30_spi_claim_bus
,
353 .xfer
= tegra30_spi_xfer
,
354 .set_speed
= tegra30_spi_set_speed
,
355 .set_mode
= tegra30_spi_set_mode
,
357 * cs_info is not needed, since we require all chip selects to be
358 * in the device tree explicitly
362 static const struct udevice_id tegra30_spi_ids
[] = {
363 { .compatible
= "nvidia,tegra20-slink" },
367 U_BOOT_DRIVER(tegra30_spi
) = {
368 .name
= "tegra20_slink",
370 .of_match
= tegra30_spi_ids
,
371 .ops
= &tegra30_spi_ops
,
372 .ofdata_to_platdata
= tegra30_spi_ofdata_to_platdata
,
373 .platdata_auto_alloc_size
= sizeof(struct tegra_spi_platdata
),
374 .priv_auto_alloc_size
= sizeof(struct tegra30_spi_priv
),
375 .probe
= tegra30_spi_probe
,