4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/omap_common.h>
18 #include <asm/ti-common/ti-edma3.h>
19 #include <linux/kernel.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 /* ti qpsi register bit masks */
26 #define QSPI_TIMEOUT 2000000
27 #define QSPI_FCLK 192000000
28 #define QSPI_DRA7XX_FCLK 76800000
29 #define QSPI_WLEN_MAX_BITS 128
30 #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)
31 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
33 #define QSPI_CLK_EN BIT(31)
34 #define QSPI_CLK_DIV_MAX 0xffff
36 #define QSPI_EN_CS(n) (n << 28)
37 #define QSPI_WLEN(n) ((n-1) << 19)
38 #define QSPI_3_PIN BIT(18)
39 #define QSPI_RD_SNGL BIT(16)
40 #define QSPI_WR_SNGL (2 << 16)
41 #define QSPI_INVAL (4 << 16)
42 #define QSPI_RD_QUAD (7 << 16)
44 #define QSPI_DD(m, n) (m << (3 + n*8))
45 #define QSPI_CKPHA(n) (1 << (2 + n*8))
46 #define QSPI_CSPOL(n) (1 << (1 + n*8))
47 #define QSPI_CKPOL(n) (1 << (n*8))
49 #define QSPI_WC BIT(1)
50 #define QSPI_BUSY BIT(0)
51 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
52 #define QSPI_XFER_DONE QSPI_WC
53 #define MM_SWITCH 0x01
54 #define MEM_CS(cs) ((cs + 1) << 8)
55 #define MEM_CS_UNSELECT 0xfffff8ff
56 #define MMAP_START_ADDR_DRA 0x5c000000
57 #define MMAP_START_ADDR_AM43x 0x30000000
58 #define CORE_CTRL_IO 0x4a002558
60 #define QSPI_CMD_READ (0x3 << 0)
61 #define QSPI_CMD_READ_DUAL (0x6b << 0)
62 #define QSPI_CMD_READ_QUAD (0x6c << 0)
63 #define QSPI_CMD_READ_FAST (0x0b << 0)
64 #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
65 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
66 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
67 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
68 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
69 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
70 #define QSPI_CMD_WRITE (0x12 << 16)
71 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
73 /* ti qspi register set */
101 struct ti_qspi_priv
{
102 #ifndef CONFIG_DM_SPI
103 struct spi_slave slave
;
109 struct ti_qspi_regs
*base
;
117 static void ti_spi_set_speed(struct ti_qspi_priv
*priv
, uint hz
)
124 clk_div
= DIV_ROUND_UP(priv
->fclk
, hz
) - 1;
126 /* truncate clk_div value to QSPI_CLK_DIV_MAX */
127 if (clk_div
> QSPI_CLK_DIV_MAX
)
128 clk_div
= QSPI_CLK_DIV_MAX
;
130 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz
, clk_div
);
133 writel(readl(&priv
->base
->clk_ctrl
) & ~QSPI_CLK_EN
,
134 &priv
->base
->clk_ctrl
);
135 /* enable SCLK and program the clk divider */
136 writel(QSPI_CLK_EN
| clk_div
, &priv
->base
->clk_ctrl
);
139 static void ti_qspi_cs_deactivate(struct ti_qspi_priv
*priv
)
141 writel(priv
->cmd
| QSPI_INVAL
, &priv
->base
->cmd
);
142 /* dummy readl to ensure bus sync */
143 readl(&priv
->base
->cmd
);
146 static int __ti_qspi_set_mode(struct ti_qspi_priv
*priv
, unsigned int mode
)
150 priv
->dc
|= QSPI_CKPHA(0);
152 priv
->dc
|= QSPI_CKPOL(0);
153 if (mode
& SPI_CS_HIGH
)
154 priv
->dc
|= QSPI_CSPOL(0);
159 static int __ti_qspi_claim_bus(struct ti_qspi_priv
*priv
, int cs
)
161 writel(priv
->dc
, &priv
->base
->dc
);
162 writel(0, &priv
->base
->cmd
);
163 writel(0, &priv
->base
->data
);
166 writel(priv
->dc
, &priv
->base
->dc
);
171 static void __ti_qspi_release_bus(struct ti_qspi_priv
*priv
)
173 writel(0, &priv
->base
->dc
);
174 writel(0, &priv
->base
->cmd
);
175 writel(0, &priv
->base
->data
);
178 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap
, int cs
, bool enable
)
182 val
= readl(ctrl_mod_mmap
);
186 val
&= MEM_CS_UNSELECT
;
187 writel(val
, ctrl_mod_mmap
);
190 static int __ti_qspi_xfer(struct ti_qspi_priv
*priv
, unsigned int bitlen
,
191 const void *dout
, void *din
, unsigned long flags
,
194 uint words
= bitlen
>> 3; /* fixed 8-bit word length */
195 const uchar
*txp
= dout
;
200 /* Setup mmap flags */
201 if (flags
& SPI_XFER_MMAP
) {
202 writel(MM_SWITCH
, &priv
->base
->memswitch
);
203 if (priv
->ctrl_mod_mmap
)
204 ti_qspi_ctrl_mode_mmap(priv
->ctrl_mod_mmap
, cs
, true);
206 } else if (flags
& SPI_XFER_MMAP_END
) {
207 writel(~MM_SWITCH
, &priv
->base
->memswitch
);
208 if (priv
->ctrl_mod_mmap
)
209 ti_qspi_ctrl_mode_mmap(priv
->ctrl_mod_mmap
, cs
, false);
217 debug("spi_xfer: Non byte aligned SPI transfer\n");
221 /* Setup command reg */
223 priv
->cmd
|= QSPI_WLEN(8);
224 priv
->cmd
|= QSPI_EN_CS(cs
);
225 if (priv
->mode
& SPI_3WIRE
)
226 priv
->cmd
|= QSPI_3_PIN
;
235 if (words
>= QSPI_WLEN_MAX_BYTES
) {
236 u32
*txbuf
= (u32
*)txp
;
239 data
= cpu_to_be32(*txbuf
++);
240 writel(data
, &priv
->base
->data3
);
241 data
= cpu_to_be32(*txbuf
++);
242 writel(data
, &priv
->base
->data2
);
243 data
= cpu_to_be32(*txbuf
++);
244 writel(data
, &priv
->base
->data1
);
245 data
= cpu_to_be32(*txbuf
++);
246 writel(data
, &priv
->base
->data
);
247 cmd
&= ~QSPI_WLEN_MASK
;
248 cmd
|= QSPI_WLEN(QSPI_WLEN_MAX_BITS
);
249 xfer_len
= QSPI_WLEN_MAX_BYTES
;
251 writeb(*txp
, &priv
->base
->data
);
254 debug("tx cmd %08x dc %08x\n",
255 cmd
| QSPI_WR_SNGL
, priv
->dc
);
256 writel(cmd
| QSPI_WR_SNGL
, &priv
->base
->cmd
);
257 status
= readl(&priv
->base
->status
);
258 timeout
= QSPI_TIMEOUT
;
259 while ((status
& QSPI_WC_BUSY
) != QSPI_XFER_DONE
) {
261 printf("spi_xfer: TX timeout!\n");
264 status
= readl(&priv
->base
->status
);
267 debug("tx done, status %08x\n", status
);
270 debug("rx cmd %08x dc %08x\n",
271 ((u32
)(priv
->cmd
| QSPI_RD_SNGL
)), priv
->dc
);
272 writel(priv
->cmd
| QSPI_RD_SNGL
, &priv
->base
->cmd
);
273 status
= readl(&priv
->base
->status
);
274 timeout
= QSPI_TIMEOUT
;
275 while ((status
& QSPI_WC_BUSY
) != QSPI_XFER_DONE
) {
277 printf("spi_xfer: RX timeout!\n");
280 status
= readl(&priv
->base
->status
);
282 *rxp
++ = readl(&priv
->base
->data
);
284 debug("rx done, status %08x, read %02x\n",
290 /* Terminate frame */
291 if (flags
& SPI_XFER_END
)
292 ti_qspi_cs_deactivate(priv
);
297 /* TODO: control from sf layer to here through dm-spi */
298 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
299 void spi_flash_copy_mmap(void *data
, void *offset
, size_t len
)
301 unsigned int addr
= (unsigned int) (data
);
302 unsigned int edma_slot_num
= 1;
304 /* Invalidate the area, so no writeback into the RAM races with DMA */
305 invalidate_dcache_range(addr
, addr
+ roundup(len
, ARCH_DMA_MINALIGN
));
307 /* enable edma3 clocks */
308 enable_edma3_clocks();
310 /* Call edma3 api to do actual DMA transfer */
311 edma3_transfer(EDMA3_BASE
, edma_slot_num
, data
, offset
, len
);
313 /* disable edma3 clocks */
314 disable_edma3_clocks();
316 *((unsigned int *)offset
) += len
;
320 #ifndef CONFIG_DM_SPI
322 static inline struct ti_qspi_priv
*to_ti_qspi_priv(struct spi_slave
*slave
)
324 return container_of(slave
, struct ti_qspi_priv
, slave
);
327 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
332 void spi_cs_activate(struct spi_slave
*slave
)
334 /* CS handled in xfer */
338 void spi_cs_deactivate(struct spi_slave
*slave
)
340 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
341 ti_qspi_cs_deactivate(priv
);
349 static void ti_spi_setup_spi_register(struct ti_qspi_priv
*priv
)
353 #ifdef CONFIG_QSPI_QUAD_SUPPORT
354 struct spi_slave
*slave
= &priv
->slave
;
355 memval
|= (QSPI_CMD_READ_QUAD
| QSPI_SETUP0_NUM_A_BYTES
|
356 QSPI_SETUP0_NUM_D_BYTES_8_BITS
|
357 QSPI_SETUP0_READ_QUAD
| QSPI_CMD_WRITE
|
358 QSPI_NUM_DUMMY_BITS
);
359 slave
->mode
|= SPI_RX_QUAD
;
361 memval
|= QSPI_CMD_READ
| QSPI_SETUP0_NUM_A_BYTES
|
362 QSPI_SETUP0_NUM_D_BYTES_NO_BITS
|
363 QSPI_SETUP0_READ_NORMAL
| QSPI_CMD_WRITE
|
367 writel(memval
, &priv
->base
->setup0
);
370 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
371 unsigned int max_hz
, unsigned int mode
)
373 struct ti_qspi_priv
*priv
;
376 gpio_request(CONFIG_QSPI_SEL_GPIO
, "qspi_gpio");
377 gpio_direction_output(CONFIG_QSPI_SEL_GPIO
, 1);
380 priv
= spi_alloc_slave(struct ti_qspi_priv
, bus
, cs
);
382 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
386 priv
->base
= (struct ti_qspi_regs
*)QSPI_BASE
;
388 #if defined(CONFIG_DRA7XX)
389 priv
->ctrl_mod_mmap
= (void *)CORE_CTRL_IO
;
390 priv
->slave
.memory_map
= (void *)MMAP_START_ADDR_DRA
;
391 priv
->fclk
= QSPI_DRA7XX_FCLK
;
393 priv
->slave
.memory_map
= (void *)MMAP_START_ADDR_AM43x
;
394 priv
->fclk
= QSPI_FCLK
;
397 ti_spi_set_speed(priv
, max_hz
);
399 #ifdef CONFIG_TI_SPI_MMAP
400 ti_spi_setup_spi_register(priv
);
406 void spi_free_slave(struct spi_slave
*slave
)
408 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
412 int spi_claim_bus(struct spi_slave
*slave
)
414 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
416 debug("%s: bus:%i cs:%i\n", __func__
, priv
->slave
.bus
, priv
->slave
.cs
);
417 __ti_qspi_set_mode(priv
, priv
->mode
);
418 return __ti_qspi_claim_bus(priv
, priv
->slave
.cs
);
420 void spi_release_bus(struct spi_slave
*slave
)
422 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
424 debug("%s: bus:%i cs:%i\n", __func__
, priv
->slave
.bus
, priv
->slave
.cs
);
425 __ti_qspi_release_bus(priv
);
428 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
429 void *din
, unsigned long flags
)
431 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
433 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
434 priv
->slave
.bus
, priv
->slave
.cs
, bitlen
, flags
);
435 return __ti_qspi_xfer(priv
, bitlen
, dout
, din
, flags
, priv
->slave
.cs
);
438 #else /* CONFIG_DM_SPI */
440 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv
*priv
,
441 struct spi_slave
*slave
,
445 u32 mode
= slave
->mode
& (SPI_RX_QUAD
| SPI_RX_DUAL
);
448 writel(0, &priv
->base
->setup0
);
452 memval
= QSPI_SETUP0_NUM_A_BYTES
| QSPI_CMD_WRITE
| QSPI_NUM_DUMMY_BITS
;
456 memval
|= QSPI_CMD_READ_QUAD
;
457 memval
|= QSPI_SETUP0_NUM_D_BYTES_8_BITS
;
458 memval
|= QSPI_SETUP0_READ_QUAD
;
459 slave
->mode
|= SPI_RX_QUAD
;
462 memval
|= QSPI_CMD_READ_DUAL
;
463 memval
|= QSPI_SETUP0_NUM_D_BYTES_8_BITS
;
464 memval
|= QSPI_SETUP0_READ_DUAL
;
467 memval
|= QSPI_CMD_READ
;
468 memval
|= QSPI_SETUP0_NUM_D_BYTES_NO_BITS
;
469 memval
|= QSPI_SETUP0_READ_NORMAL
;
473 writel(memval
, &priv
->base
->setup0
);
477 static int ti_qspi_set_speed(struct udevice
*bus
, uint max_hz
)
479 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
481 ti_spi_set_speed(priv
, max_hz
);
486 static int ti_qspi_set_mode(struct udevice
*bus
, uint mode
)
488 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
489 return __ti_qspi_set_mode(priv
, mode
);
492 static int ti_qspi_claim_bus(struct udevice
*dev
)
494 struct dm_spi_slave_platdata
*slave_plat
= dev_get_parent_platdata(dev
);
495 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
496 struct ti_qspi_priv
*priv
;
500 priv
= dev_get_priv(bus
);
502 if (slave_plat
->cs
> priv
->num_cs
) {
503 debug("invalid qspi chip select\n");
507 __ti_qspi_setup_memorymap(priv
, slave
, true);
509 return __ti_qspi_claim_bus(priv
, slave_plat
->cs
);
512 static int ti_qspi_release_bus(struct udevice
*dev
)
514 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
515 struct ti_qspi_priv
*priv
;
519 priv
= dev_get_priv(bus
);
521 __ti_qspi_setup_memorymap(priv
, slave
, false);
522 __ti_qspi_release_bus(priv
);
527 static int ti_qspi_xfer(struct udevice
*dev
, unsigned int bitlen
,
528 const void *dout
, void *din
, unsigned long flags
)
530 struct dm_spi_slave_platdata
*slave
= dev_get_parent_platdata(dev
);
531 struct ti_qspi_priv
*priv
;
535 priv
= dev_get_priv(bus
);
537 if (slave
->cs
> priv
->num_cs
) {
538 debug("invalid qspi chip select\n");
542 return __ti_qspi_xfer(priv
, bitlen
, dout
, din
, flags
, slave
->cs
);
545 static int ti_qspi_probe(struct udevice
*bus
)
547 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
549 priv
->fclk
= dev_get_driver_data(bus
);
554 static void *map_syscon_chipselects(struct udevice
*bus
)
556 #if CONFIG_IS_ENABLED(SYSCON)
557 struct udevice
*syscon
;
558 struct regmap
*regmap
;
562 err
= uclass_get_device_by_phandle(UCLASS_SYSCON
, bus
,
563 "syscon-chipselects", &syscon
);
565 debug("%s: unable to find syscon device (%d)\n", __func__
,
570 regmap
= syscon_get_regmap(syscon
);
571 if (IS_ERR(regmap
)) {
572 debug("%s: unable to find regmap (%ld)\n", __func__
,
577 cell
= fdt_getprop(gd
->fdt_blob
, dev_of_offset(bus
),
578 "syscon-chipselects", &len
);
579 if (len
< 2*sizeof(fdt32_t
)) {
580 debug("%s: offset not available\n", __func__
);
584 return fdtdec_get_number(cell
+ 1, 1) + regmap_get_range(regmap
, 0);
587 addr
= devfdt_get_addr_index(bus
, 2);
588 return (addr
== FDT_ADDR_T_NONE
) ? NULL
:
589 map_physmem(addr
, 0, MAP_NOCACHE
);
593 static int ti_qspi_ofdata_to_platdata(struct udevice
*bus
)
595 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
596 const void *blob
= gd
->fdt_blob
;
597 int node
= dev_of_offset(bus
);
599 priv
->ctrl_mod_mmap
= map_syscon_chipselects(bus
);
600 priv
->base
= map_physmem(devfdt_get_addr(bus
),
601 sizeof(struct ti_qspi_regs
), MAP_NOCACHE
);
602 priv
->memory_map
= map_physmem(devfdt_get_addr_index(bus
, 1), 0,
605 priv
->max_hz
= fdtdec_get_int(blob
, node
, "spi-max-frequency", -1);
606 if (priv
->max_hz
< 0) {
607 debug("Error: Max frequency missing\n");
610 priv
->num_cs
= fdtdec_get_int(blob
, node
, "num-cs", 4);
612 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__
,
613 (int)priv
->base
, priv
->max_hz
);
618 static int ti_qspi_child_pre_probe(struct udevice
*dev
)
620 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
621 struct udevice
*bus
= dev_get_parent(dev
);
622 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
624 slave
->memory_map
= priv
->memory_map
;
628 static const struct dm_spi_ops ti_qspi_ops
= {
629 .claim_bus
= ti_qspi_claim_bus
,
630 .release_bus
= ti_qspi_release_bus
,
631 .xfer
= ti_qspi_xfer
,
632 .set_speed
= ti_qspi_set_speed
,
633 .set_mode
= ti_qspi_set_mode
,
636 static const struct udevice_id ti_qspi_ids
[] = {
637 { .compatible
= "ti,dra7xxx-qspi", .data
= QSPI_DRA7XX_FCLK
},
638 { .compatible
= "ti,am4372-qspi", .data
= QSPI_FCLK
},
642 U_BOOT_DRIVER(ti_qspi
) = {
645 .of_match
= ti_qspi_ids
,
647 .ofdata_to_platdata
= ti_qspi_ofdata_to_platdata
,
648 .priv_auto_alloc_size
= sizeof(struct ti_qspi_priv
),
649 .probe
= ti_qspi_probe
,
650 .child_pre_probe
= ti_qspi_child_pre_probe
,
652 #endif /* CONFIG_DM_SPI */