drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/cache.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/omap.h>
  13 #include <malloc.h>
  14 #include <spi.h>
  15 #include <spi-mem.h>
  16 #include <dm.h>
  17 #include <asm/gpio.h>
  18 #include <asm/omap_gpio.h>
  19 #include <asm/omap_common.h>
  20 #include <asm/ti-common/ti-edma3.h>
  21 #include <linux/err.h>
  22 #include <linux/kernel.h>
  23 #include <regmap.h>
  24 #include <syscon.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* ti qpsi register bit masks */
  29 #define QSPI_TIMEOUT                    2000000
  30 #define QSPI_FCLK                       192000000
  31 #define QSPI_DRA7XX_FCLK                76800000
  32 #define QSPI_WLEN_MAX_BITS              128
  33 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  34 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  35 /* clock control */
  36 #define QSPI_CLK_EN                     BIT(31)
  37 #define QSPI_CLK_DIV_MAX                0xffff
  38 /* command */
  39 #define QSPI_EN_CS(n)                   (n << 28)
  40 #define QSPI_WLEN(n)                    ((n-1) << 19)
  41 #define QSPI_3_PIN                      BIT(18)
  42 #define QSPI_RD_SNGL                    BIT(16)
  43 #define QSPI_WR_SNGL                    (2 << 16)
  44 #define QSPI_INVAL                      (4 << 16)
  45 #define QSPI_RD_QUAD                    (7 << 16)
  46 /* device control */
  47 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  48 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  49 #define QSPI_CKPOL(n)                   (1 << (n*8))
  50 /* status */
  51 #define QSPI_WC                         BIT(1)
  52 #define QSPI_BUSY                       BIT(0)
  53 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  54 #define QSPI_XFER_DONE                  QSPI_WC
  55 #define MM_SWITCH                       0x01
  56 #define MEM_CS(cs)                      ((cs + 1) << 8)
  57 #define MEM_CS_UNSELECT                 0xfffff8ff
  58
  59 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  60 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  61 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  62 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  63 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  64
  65 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  66
  67 /* ti qspi register set */
  68 struct ti_qspi_regs {
  69         u32 pid;
  70         u32 pad0[3];
  71         u32 sysconfig;
  72         u32 pad1[3];
  73         u32 int_stat_raw;
  74         u32 int_stat_en;
  75         u32 int_en_set;
  76         u32 int_en_ctlr;
  77         u32 intc_eoi;
  78         u32 pad2[3];
  79         u32 clk_ctrl;
  80         u32 dc;
  81         u32 cmd;
  82         u32 status;
  83         u32 data;
  84         u32 setup0;
  85         u32 setup1;
  86         u32 setup2;
  87         u32 setup3;
  88         u32 memswitch;
  89         u32 data1;
  90         u32 data2;
  91         u32 data3;
  92 };
  93
  94 /* ti qspi priv */
  95 struct ti_qspi_priv {
  96         void *memory_map;
  97         size_t mmap_size;
  98         uint max_hz;
  99         u32 num_cs;
 100         struct ti_qspi_regs *base;
 101         void *ctrl_mod_mmap;
 102         ulong fclk;
 103         unsigned int mode;
 104         u32 cmd;
 105         u32 dc;
 106 };
 107
 108 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 109 {
 110         struct ti_qspi_priv *priv = dev_get_priv(bus);
 111         uint clk_div;
 112
 113         if (!hz)
 114                 clk_div = 0;
 115         else
 116                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 117
 118         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 119         if (clk_div > QSPI_CLK_DIV_MAX)
 120                 clk_div = QSPI_CLK_DIV_MAX;
 121
 122         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 123
 124         /* disable SCLK */
 125         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 126                &priv->base->clk_ctrl);
 127         /* enable SCLK and program the clk divider */
 128         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 129
 130         return 0;
 131 }
 132
 133 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 134 {
 135         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 136         /* dummy readl to ensure bus sync */
 137         readl(&priv->base->cmd);
 138 }
 139
 140 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 141 {
 142         u32 val;
 143
 144         val = readl(ctrl_mod_mmap);
 145         if (enable)
 146                 val |= MEM_CS(cs);
 147         else
 148                 val &= MEM_CS_UNSELECT;
 149         writel(val, ctrl_mod_mmap);
 150 }
 151
 152 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 153                         const void *dout, void *din, unsigned long flags)
 154 {
 155         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 156         struct ti_qspi_priv *priv;
 157         struct udevice *bus;
 158         uint words = bitlen >> 3; /* fixed 8-bit word length */
 159         const uchar *txp = dout;
 160         uchar *rxp = din;
 161         uint status;
 162         int timeout;
 163         unsigned int cs = slave->cs;
 164
 165         bus = dev->parent;
 166         priv = dev_get_priv(bus);
 167
 168         if (cs > priv->num_cs) {
 169                 debug("invalid qspi chip select\n");
 170                 return -EINVAL;
 171         }
 172
 173         if (bitlen == 0)
 174                 return -1;
 175
 176         if (bitlen % 8) {
 177                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 178                 return -1;
 179         }
 180
 181         /* Setup command reg */
 182         priv->cmd = 0;
 183         priv->cmd |= QSPI_WLEN(8);
 184         priv->cmd |= QSPI_EN_CS(cs);
 185         if (priv->mode & SPI_3WIRE)
 186                 priv->cmd |= QSPI_3_PIN;
 187         priv->cmd |= 0xfff;
 188
 189         while (words) {
 190                 u8 xfer_len = 0;
 191
 192                 if (txp) {
 193                         u32 cmd = priv->cmd;
 194
 195                         if (words >= QSPI_WLEN_MAX_BYTES) {
 196                                 u32 *txbuf = (u32 *)txp;
 197                                 u32 data;
 198
 199                                 data = cpu_to_be32(*txbuf++);
 200                                 writel(data, &priv->base->data3);
 201                                 data = cpu_to_be32(*txbuf++);
 202                                 writel(data, &priv->base->data2);
 203                                 data = cpu_to_be32(*txbuf++);
 204                                 writel(data, &priv->base->data1);
 205                                 data = cpu_to_be32(*txbuf++);
 206                                 writel(data, &priv->base->data);
 207                                 cmd &= ~QSPI_WLEN_MASK;
 208                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 209                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 210                         } else {
 211                                 writeb(*txp, &priv->base->data);
 212                                 xfer_len = 1;
 213                         }
 214                         debug("tx cmd %08x dc %08x\n",
 215                               cmd | QSPI_WR_SNGL, priv->dc);
 216                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 217                         status = readl(&priv->base->status);
 218                         timeout = QSPI_TIMEOUT;
 219                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 220                                 if (--timeout < 0) {
 221                                         printf("spi_xfer: TX timeout!\n");
 222                                         return -1;
 223                                 }
 224                                 status = readl(&priv->base->status);
 225                         }
 226                         txp += xfer_len;
 227                         debug("tx done, status %08x\n", status);
 228                 }
 229                 if (rxp) {
 230                         debug("rx cmd %08x dc %08x\n",
 231                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 232                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 233                         status = readl(&priv->base->status);
 234                         timeout = QSPI_TIMEOUT;
 235                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 236                                 if (--timeout < 0) {
 237                                         printf("spi_xfer: RX timeout!\n");
 238                                         return -1;
 239                                 }
 240                                 status = readl(&priv->base->status);
 241                         }
 242                         *rxp++ = readl(&priv->base->data);
 243                         xfer_len = 1;
 244                         debug("rx done, status %08x, read %02x\n",
 245                               status, *(rxp-1));
 246                 }
 247                 words -= xfer_len;
 248         }
 249
 250         /* Terminate frame */
 251         if (flags & SPI_XFER_END)
 252                 ti_qspi_cs_deactivate(priv);
 253
 254         return 0;
 255 }
 256
 257 /* TODO: control from sf layer to here through dm-spi */
 258 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 259 {
 260 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 261         unsigned int                    addr = (unsigned int) (data);
 262         unsigned int                    edma_slot_num = 1;
 263
 264         /* Invalidate the area, so no writeback into the RAM races with DMA */
 265         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 266
 267         /* enable edma3 clocks */
 268         enable_edma3_clocks();
 269
 270         /* Call edma3 api to do actual DMA transfer     */
 271         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 272
 273         /* disable edma3 clocks */
 274         disable_edma3_clocks();
 275 #else
 276         memcpy_fromio(data, offset, len);
 277 #endif
 278
 279         *((unsigned int *)offset) += len;
 280 }
 281
 282 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 283                                     u8 opcode, u8 data_nbits, u8 addr_width,
 284                                     u8 dummy_bytes)
 285 {
 286         u32 memval = opcode;
 287
 288         switch (data_nbits) {
 289         case 4:
 290                 memval |= QSPI_SETUP0_READ_QUAD;
 291                 break;
 292         case 2:
 293                 memval |= QSPI_SETUP0_READ_DUAL;
 294                 break;
 295         default:
 296                 memval |= QSPI_SETUP0_READ_NORMAL;
 297                 break;
 298         }
 299
 300         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 301                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 302
 303         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 304 }
 305
 306 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 307 {
 308         struct ti_qspi_priv *priv = dev_get_priv(bus);
 309
 310         priv->dc = 0;
 311         if (mode & SPI_CPHA)
 312                 priv->dc |= QSPI_CKPHA(0);
 313         if (mode & SPI_CPOL)
 314                 priv->dc |= QSPI_CKPOL(0);
 315         if (mode & SPI_CS_HIGH)
 316                 priv->dc |= QSPI_CSPOL(0);
 317
 318         return 0;
 319 }
 320
 321 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 322                                const struct spi_mem_op *op)
 323 {
 324         struct dm_spi_slave_platdata *slave_plat;
 325         struct ti_qspi_priv *priv;
 326         struct udevice *bus;
 327         u32 from = 0;
 328         int ret = 0;
 329
 330         bus = slave->dev->parent;
 331         priv = dev_get_priv(bus);
 332         slave_plat = dev_get_parent_platdata(slave->dev);
 333
 334         /* Only optimize read path. */
 335         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 336             !op->addr.nbytes || op->addr.nbytes > 4)
 337                 return -ENOTSUPP;
 338
 339         /* Address exceeds MMIO window size, fall back to regular mode. */
 340         from = op->addr.val;
 341         if (from + op->data.nbytes > priv->mmap_size)
 342                 return -ENOTSUPP;
 343
 344         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 345                                 op->data.buswidth, op->addr.nbytes,
 346                                 op->dummy.nbytes);
 347
 348         ti_qspi_copy_mmap((void *)op->data.buf.in,
 349                           (void *)priv->memory_map + from, op->data.nbytes);
 350
 351         return ret;
 352 }
 353
 354 static int ti_qspi_claim_bus(struct udevice *dev)
 355 {
 356         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 357         struct ti_qspi_priv *priv;
 358         struct udevice *bus;
 359
 360         bus = dev->parent;
 361         priv = dev_get_priv(bus);
 362
 363         if (slave_plat->cs > priv->num_cs) {
 364                 debug("invalid qspi chip select\n");
 365                 return -EINVAL;
 366         }
 367
 368         writel(MM_SWITCH, &priv->base->memswitch);
 369         if (priv->ctrl_mod_mmap)
 370                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 371                                        slave_plat->cs, true);
 372
 373         writel(priv->dc, &priv->base->dc);
 374         writel(0, &priv->base->cmd);
 375         writel(0, &priv->base->data);
 376
 377         priv->dc <<= slave_plat->cs * 8;
 378         writel(priv->dc, &priv->base->dc);
 379
 380         return 0;
 381 }
 382
 383 static int ti_qspi_release_bus(struct udevice *dev)
 384 {
 385         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 386         struct ti_qspi_priv *priv;
 387         struct udevice *bus;
 388
 389         bus = dev->parent;
 390         priv = dev_get_priv(bus);
 391
 392         writel(~MM_SWITCH, &priv->base->memswitch);
 393         if (priv->ctrl_mod_mmap)
 394                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 395                                        slave_plat->cs, false);
 396
 397         writel(0, &priv->base->dc);
 398         writel(0, &priv->base->cmd);
 399         writel(0, &priv->base->data);
 400         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 401
 402         return 0;
 403 }
 404
 405 static int ti_qspi_probe(struct udevice *bus)
 406 {
 407         struct ti_qspi_priv *priv = dev_get_priv(bus);
 408
 409         priv->fclk = dev_get_driver_data(bus);
 410
 411         return 0;
 412 }
 413
 414 static void *map_syscon_chipselects(struct udevice *bus)
 415 {
 416 #if CONFIG_IS_ENABLED(SYSCON)
 417         struct udevice *syscon;
 418         struct regmap *regmap;
 419         const fdt32_t *cell;
 420         int len, err;
 421
 422         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 423                                            "syscon-chipselects", &syscon);
 424         if (err) {
 425                 debug("%s: unable to find syscon device (%d)\n", __func__,
 426                       err);
 427                 return NULL;
 428         }
 429
 430         regmap = syscon_get_regmap(syscon);
 431         if (IS_ERR(regmap)) {
 432                 debug("%s: unable to find regmap (%ld)\n", __func__,
 433                       PTR_ERR(regmap));
 434                 return NULL;
 435         }
 436
 437         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 438                            "syscon-chipselects", &len);
 439         if (len < 2*sizeof(fdt32_t)) {
 440                 debug("%s: offset not available\n", __func__);
 441                 return NULL;
 442         }
 443
 444         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 445 #else
 446         fdt_addr_t addr;
 447         addr = devfdt_get_addr_index(bus, 2);
 448         return (addr == FDT_ADDR_T_NONE) ? NULL :
 449                 map_physmem(addr, 0, MAP_NOCACHE);
 450 #endif
 451 }
 452
 453 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 454 {
 455         struct ti_qspi_priv *priv = dev_get_priv(bus);
 456         const void *blob = gd->fdt_blob;
 457         int node = dev_of_offset(bus);
 458         fdt_addr_t mmap_addr;
 459         fdt_addr_t mmap_size;
 460
 461         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 462         priv->base = map_physmem(devfdt_get_addr(bus),
 463                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 464         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 465         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 466         priv->mmap_size = mmap_size;
 467
 468         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 469         if (priv->max_hz < 0) {
 470                 debug("Error: Max frequency missing\n");
 471                 return -ENODEV;
 472         }
 473         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 474
 475         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 476               (int)priv->base, priv->max_hz);
 477
 478         return 0;
 479 }
 480
 481 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 482         .exec_op = ti_qspi_exec_mem_op,
 483 };
 484
 485 static const struct dm_spi_ops ti_qspi_ops = {
 486         .claim_bus      = ti_qspi_claim_bus,
 487         .release_bus    = ti_qspi_release_bus,
 488         .xfer           = ti_qspi_xfer,
 489         .set_speed      = ti_qspi_set_speed,
 490         .set_mode       = ti_qspi_set_mode,
 491         .mem_ops        = &ti_qspi_mem_ops,
 492 };
 493
 494 static const struct udevice_id ti_qspi_ids[] = {
 495         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 496         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 497         { }
 498 };
 499
 500 U_BOOT_DRIVER(ti_qspi) = {
 501         .name   = "ti_qspi",
 502         .id     = UCLASS_SPI,
 503         .of_match = ti_qspi_ids,
 504         .ops    = &ti_qspi_ops,
 505         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 506         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 507         .probe  = ti_qspi_probe,
 508 };