1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
14 #include "mp_precomp.h"
15 #include "phydm_precomp.h"
16 #include <linux/module.h>
18 static int _rtl_phydm_init_com_info(struct rtl_priv
*rtlpriv
,
19 enum odm_ic_type ic_type
,
20 struct rtl_phydm_params
*params
)
22 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
23 struct rtl_hal
*rtlhal
= rtl_hal(rtlpriv
);
24 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
25 struct rtl_mac
*mac
= rtl_mac(rtlpriv
);
26 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtlpriv
);
27 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtlpriv
);
28 u8 odm_board_type
= ODM_BOARD_DEFAULT
;
32 dm
->adapter
= (void *)rtlpriv
;
34 odm_cmn_info_init(dm
, ODM_CMNINFO_PLATFORM
, ODM_CE
);
36 odm_cmn_info_init(dm
, ODM_CMNINFO_IC_TYPE
, ic_type
);
38 odm_cmn_info_init(dm
, ODM_CMNINFO_INTERFACE
, ODM_ITRF_PCIE
);
40 odm_cmn_info_init(dm
, ODM_CMNINFO_MP_TEST_CHIP
, params
->mp_chip
);
42 odm_cmn_info_init(dm
, ODM_CMNINFO_PATCH_ID
, rtlhal
->oem_id
);
44 odm_cmn_info_init(dm
, ODM_CMNINFO_BWIFI_TEST
, 1);
46 if (rtlphy
->rf_type
== RF_1T1R
)
47 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_1T1R
);
48 else if (rtlphy
->rf_type
== RF_1T2R
)
49 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_1T2R
);
50 else if (rtlphy
->rf_type
== RF_2T2R
)
51 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_2T2R
);
52 else if (rtlphy
->rf_type
== RF_2T2R_GREEN
)
53 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_2T2R_GREEN
);
54 else if (rtlphy
->rf_type
== RF_2T3R
)
55 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_2T3R
);
56 else if (rtlphy
->rf_type
== RF_2T4R
)
57 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_2T4R
);
58 else if (rtlphy
->rf_type
== RF_3T3R
)
59 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_3T3R
);
60 else if (rtlphy
->rf_type
== RF_3T4R
)
61 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_3T4R
);
62 else if (rtlphy
->rf_type
== RF_4T4R
)
63 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_4T4R
);
65 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_TYPE
, ODM_XTXR
);
67 /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
68 if (rtlhal
->external_lna_2g
!= 0) {
69 odm_board_type
|= ODM_BOARD_EXT_LNA
;
70 odm_cmn_info_init(dm
, ODM_CMNINFO_EXT_LNA
, 1);
72 if (rtlhal
->external_lna_5g
!= 0) {
73 odm_board_type
|= ODM_BOARD_EXT_LNA_5G
;
74 odm_cmn_info_init(dm
, ODM_CMNINFO_5G_EXT_LNA
, 1);
76 if (rtlhal
->external_pa_2g
!= 0) {
77 odm_board_type
|= ODM_BOARD_EXT_PA
;
78 odm_cmn_info_init(dm
, ODM_CMNINFO_EXT_PA
, 1);
80 if (rtlhal
->external_pa_5g
!= 0) {
81 odm_board_type
|= ODM_BOARD_EXT_PA_5G
;
82 odm_cmn_info_init(dm
, ODM_CMNINFO_5G_EXT_PA
, 1);
84 if (rtlpriv
->cfg
->ops
->get_btc_status())
85 odm_board_type
|= ODM_BOARD_BT
;
87 odm_cmn_info_init(dm
, ODM_CMNINFO_BOARD_TYPE
, odm_board_type
);
88 /* 1 ============== End of BoardType ============== */
90 odm_cmn_info_init(dm
, ODM_CMNINFO_GPA
, rtlhal
->type_gpa
);
91 odm_cmn_info_init(dm
, ODM_CMNINFO_APA
, rtlhal
->type_apa
);
92 odm_cmn_info_init(dm
, ODM_CMNINFO_GLNA
, rtlhal
->type_glna
);
93 odm_cmn_info_init(dm
, ODM_CMNINFO_ALNA
, rtlhal
->type_alna
);
95 odm_cmn_info_init(dm
, ODM_CMNINFO_RFE_TYPE
, rtlhal
->rfe_type
);
97 odm_cmn_info_init(dm
, ODM_CMNINFO_EXT_TRSW
, 0);
99 /*Add by YuChen for kfree init*/
100 odm_cmn_info_init(dm
, ODM_CMNINFO_REGRFKFREEENABLE
, 2);
101 odm_cmn_info_init(dm
, ODM_CMNINFO_RFKFREEENABLE
, 0);
103 /*Antenna diversity relative parameters*/
104 odm_cmn_info_hook(dm
, ODM_CMNINFO_ANT_DIV
,
105 &rtlefuse
->antenna_div_cfg
);
106 odm_cmn_info_init(dm
, ODM_CMNINFO_RF_ANTENNA_TYPE
,
107 rtlefuse
->antenna_div_type
);
108 odm_cmn_info_init(dm
, ODM_CMNINFO_BE_FIX_TX_ANT
, 0);
109 odm_cmn_info_init(dm
, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH
, 0);
111 /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
112 odm_cmn_info_init(dm
, ODM_CMNINFO_EFUSE0X3D7
, params
->efuse0x3d7
);
113 odm_cmn_info_init(dm
, ODM_CMNINFO_EFUSE0X3D8
, params
->efuse0x3d8
);
115 /*Add by YuChen for adaptivity init*/
116 odm_cmn_info_hook(dm
, ODM_CMNINFO_ADAPTIVITY
,
117 &rtlpriv
->phydm
.adaptivity_en
);
118 phydm_adaptivity_info_init(dm
, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE
,
120 phydm_adaptivity_info_init(dm
, PHYDM_ADAPINFO_DCBACKOFF
, 0);
121 phydm_adaptivity_info_init(dm
, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY
,
123 phydm_adaptivity_info_init(dm
, PHYDM_ADAPINFO_TH_L2H_INI
, 0);
124 phydm_adaptivity_info_init(dm
, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF
, 0);
126 odm_cmn_info_init(dm
, ODM_CMNINFO_IQKFWOFFLOAD
, 0);
128 /* Pointer reference */
129 odm_cmn_info_hook(dm
, ODM_CMNINFO_TX_UNI
,
130 &rtlpriv
->stats
.txbytesunicast
);
131 odm_cmn_info_hook(dm
, ODM_CMNINFO_RX_UNI
,
132 &rtlpriv
->stats
.rxbytesunicast
);
133 odm_cmn_info_hook(dm
, ODM_CMNINFO_BAND
, &rtlhal
->current_bandtype
);
134 odm_cmn_info_hook(dm
, ODM_CMNINFO_FORCED_RATE
,
135 &rtlpriv
->phydm
.forced_data_rate
);
136 odm_cmn_info_hook(dm
, ODM_CMNINFO_FORCED_IGI_LB
,
137 &rtlpriv
->phydm
.forced_igi_lb
);
139 odm_cmn_info_hook(dm
, ODM_CMNINFO_SEC_CHNL_OFFSET
,
140 &mac
->cur_40_prime_sc
);
141 odm_cmn_info_hook(dm
, ODM_CMNINFO_BW
, &rtlphy
->current_chan_bw
);
142 odm_cmn_info_hook(dm
, ODM_CMNINFO_CHNL
, &rtlphy
->current_channel
);
144 odm_cmn_info_hook(dm
, ODM_CMNINFO_SCAN
, &mac
->act_scanning
);
145 odm_cmn_info_hook(dm
, ODM_CMNINFO_POWER_SAVING
,
146 &ppsc
->dot11_psmode
); /* may add new boolean flag */
147 /*Add by Yuchen for phydm beamforming*/
148 odm_cmn_info_hook(dm
, ODM_CMNINFO_TX_TP
,
149 &rtlpriv
->stats
.txbytesunicast_inperiod_tp
);
150 odm_cmn_info_hook(dm
, ODM_CMNINFO_RX_TP
,
151 &rtlpriv
->stats
.rxbytesunicast_inperiod_tp
);
152 odm_cmn_info_hook(dm
, ODM_CMNINFO_ANT_TEST
,
153 &rtlpriv
->phydm
.antenna_test
);
154 for (i
= 0; i
< ODM_ASSOCIATE_ENTRY_NUM
; i
++)
155 odm_cmn_info_ptr_array_hook(dm
, ODM_CMNINFO_STA_STATUS
, i
,
158 phydm_init_debug_setting(dm
);
160 odm_cmn_info_init(dm
, ODM_CMNINFO_FAB_VER
, params
->fab_ver
);
161 odm_cmn_info_init(dm
, ODM_CMNINFO_CUT_VER
, params
->cut_ver
);
163 /* after ifup, ability is updated again */
164 support_ability
= ODM_RF_CALIBRATION
| ODM_RF_TX_PWR_TRACK
;
165 odm_cmn_info_update(dm
, ODM_CMNINFO_ABILITY
, support_ability
);
170 static int rtl_phydm_init_priv(struct rtl_priv
*rtlpriv
,
171 struct rtl_phydm_params
*params
)
173 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
176 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
181 rtlpriv
->phydm
.internal
=
182 kzalloc(sizeof(struct phy_dm_struct
), GFP_KERNEL
);
184 _rtl_phydm_init_com_info(rtlpriv
, ic
, params
);
186 odm_init_all_timers(dm
);
191 static int rtl_phydm_deinit_priv(struct rtl_priv
*rtlpriv
)
193 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
195 odm_cancel_all_timers(dm
);
197 kfree(rtlpriv
->phydm
.internal
);
198 rtlpriv
->phydm
.internal
= NULL
;
203 static bool rtl_phydm_load_txpower_by_rate(struct rtl_priv
*rtlpriv
)
205 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
206 enum hal_status status
;
208 status
= odm_config_bb_with_header_file(dm
, CONFIG_BB_PHY_REG_PG
);
209 if (status
!= HAL_STATUS_SUCCESS
)
215 static bool rtl_phydm_load_txpower_limit(struct rtl_priv
*rtlpriv
)
217 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
218 enum hal_status status
;
220 if (IS_HARDWARE_TYPE_8822B(rtlpriv
)) {
221 odm_read_and_config_mp_8822b_txpwr_lmt(dm
);
223 status
= odm_config_rf_with_header_file(dm
, CONFIG_RF_TXPWR_LMT
,
225 if (status
!= HAL_STATUS_SUCCESS
)
232 static int rtl_phydm_init_dm(struct rtl_priv
*rtlpriv
)
234 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
235 u32 support_ability
= 0;
237 /* clang-format off */
241 | ODM_BB_DYNAMIC_TXPWR
243 | ODM_BB_RSSI_MONITOR
245 /* | ODM_BB_PWR_SAVE*/
246 | ODM_BB_CFO_TRACKING
248 | ODM_RF_TX_PWR_TRACK
251 /* | ODM_BB_PWR_TRAIN*/
253 /* clang-format on */
255 odm_cmn_info_update(dm
, ODM_CMNINFO_ABILITY
, support_ability
);
262 static int rtl_phydm_deinit_dm(struct rtl_priv
*rtlpriv
)
267 static int rtl_phydm_reset_dm(struct rtl_priv
*rtlpriv
)
269 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
276 static bool rtl_phydm_parameter_init(struct rtl_priv
*rtlpriv
, bool post
)
278 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
280 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
281 return config_phydm_parameter_init(dm
, post
? ODM_POST_SETTING
:
287 static bool rtl_phydm_phy_bb_config(struct rtl_priv
*rtlpriv
)
289 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
290 enum hal_status status
;
292 status
= odm_config_bb_with_header_file(dm
, CONFIG_BB_PHY_REG
);
293 if (status
!= HAL_STATUS_SUCCESS
)
296 status
= odm_config_bb_with_header_file(dm
, CONFIG_BB_AGC_TAB
);
297 if (status
!= HAL_STATUS_SUCCESS
)
303 static bool rtl_phydm_phy_rf_config(struct rtl_priv
*rtlpriv
)
305 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
306 struct rtl_phy
*rtlphy
= &rtlpriv
->phy
;
307 enum hal_status status
;
308 enum odm_rf_radio_path rfpath
;
310 for (rfpath
= 0; rfpath
< rtlphy
->num_total_rfpath
; rfpath
++) {
311 status
= odm_config_rf_with_header_file(dm
, CONFIG_RF_RADIO
,
313 if (status
!= HAL_STATUS_SUCCESS
)
317 status
= odm_config_rf_with_tx_pwr_track_header_file(dm
);
318 if (status
!= HAL_STATUS_SUCCESS
)
324 static bool rtl_phydm_phy_mac_config(struct rtl_priv
*rtlpriv
)
326 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
327 enum hal_status status
;
329 status
= odm_config_mac_with_header_file(dm
);
330 if (status
!= HAL_STATUS_SUCCESS
)
336 static bool rtl_phydm_trx_mode(struct rtl_priv
*rtlpriv
,
337 enum radio_mask tx_path
, enum radio_mask rx_path
,
340 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
342 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
343 return config_phydm_trx_mode_8822b(dm
,
344 (enum odm_rf_path
)tx_path
,
345 (enum odm_rf_path
)rx_path
,
351 static bool rtl_phydm_watchdog(struct rtl_priv
*rtlpriv
)
353 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
354 struct rtl_mac
*mac
= rtl_mac(rtlpriv
);
355 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtlpriv
);
356 bool fw_current_inpsmode
= false;
357 bool fw_ps_awake
= true;
358 u8 is_linked
= false;
359 u8 bsta_state
= false;
360 u8 is_bt_enabled
= false;
362 /* check whether do watchdog */
363 rtlpriv
->cfg
->ops
->get_hw_reg(rtlpriv
->hw
, HW_VAR_FW_PSMODE_STATUS
,
364 (u8
*)(&fw_current_inpsmode
));
365 rtlpriv
->cfg
->ops
->get_hw_reg(rtlpriv
->hw
, HW_VAR_FWLPS_RF_ON
,
366 (u8
*)(&fw_ps_awake
));
367 if (ppsc
->p2p_ps_info
.p2p_ps_mode
)
370 if ((ppsc
->rfpwr_state
== ERFON
) &&
371 ((!fw_current_inpsmode
) && fw_ps_awake
) &&
372 (!ppsc
->rfchange_inprogress
))
377 /* update common info before doing watchdog */
378 if (mac
->link_state
>= MAC80211_LINKED
) {
380 if (mac
->vif
&& mac
->vif
->type
== NL80211_IFTYPE_STATION
)
384 if (rtlpriv
->cfg
->ops
->get_btc_status())
385 is_bt_enabled
= !rtlpriv
->btcoexist
.btc_ops
->btc_is_bt_disabled(
388 odm_cmn_info_update(dm
, ODM_CMNINFO_LINK
, is_linked
);
389 odm_cmn_info_update(dm
, ODM_CMNINFO_STATION_STATE
, bsta_state
);
390 odm_cmn_info_update(dm
, ODM_CMNINFO_BT_ENABLED
, is_bt_enabled
);
398 static bool rtl_phydm_switch_band(struct rtl_priv
*rtlpriv
, u8 central_ch
)
400 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
402 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
403 return config_phydm_switch_band_8822b(dm
, central_ch
);
408 static bool rtl_phydm_switch_channel(struct rtl_priv
*rtlpriv
, u8 central_ch
)
410 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
412 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
413 return config_phydm_switch_channel_8822b(dm
, central_ch
);
418 static bool rtl_phydm_switch_bandwidth(struct rtl_priv
*rtlpriv
,
420 enum ht_channel_width bandwidth
)
422 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
423 enum odm_bw odm_bw
= (enum odm_bw
)bandwidth
;
425 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
426 return config_phydm_switch_bandwidth_8822b(dm
, primary_ch_idx
,
432 static bool rtl_phydm_iq_calibrate(struct rtl_priv
*rtlpriv
)
434 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
436 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
437 phy_iq_calibrate_8822b(dm
, false);
444 static bool rtl_phydm_clear_txpowertracking_state(struct rtl_priv
*rtlpriv
)
446 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
448 odm_clear_txpowertracking_state(dm
);
453 static bool rtl_phydm_pause_dig(struct rtl_priv
*rtlpriv
, bool pause
)
455 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
458 odm_pause_dig(dm
, PHYDM_PAUSE
, PHYDM_PAUSE_LEVEL_0
, 0x1e);
460 odm_pause_dig(dm
, PHYDM_RESUME
, PHYDM_PAUSE_LEVEL_0
, 0xff);
465 static u32
rtl_phydm_read_rf_reg(struct rtl_priv
*rtlpriv
,
466 enum radio_path rfpath
, u32 addr
, u32 mask
)
468 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
469 enum odm_rf_radio_path odm_rfpath
= (enum odm_rf_radio_path
)rfpath
;
471 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
472 return config_phydm_read_rf_reg_8822b(dm
, odm_rfpath
, addr
,
478 static bool rtl_phydm_write_rf_reg(struct rtl_priv
*rtlpriv
,
479 enum radio_path rfpath
, u32 addr
, u32 mask
,
482 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
483 enum odm_rf_radio_path odm_rfpath
= (enum odm_rf_radio_path
)rfpath
;
485 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
486 return config_phydm_write_rf_reg_8822b(dm
, odm_rfpath
, addr
,
492 static u8
rtl_phydm_read_txagc(struct rtl_priv
*rtlpriv
, enum radio_path rfpath
,
495 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
496 enum odm_rf_radio_path odm_rfpath
= (enum odm_rf_radio_path
)rfpath
;
498 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
499 return config_phydm_read_txagc_8822b(dm
, odm_rfpath
, hw_rate
);
504 static bool rtl_phydm_write_txagc(struct rtl_priv
*rtlpriv
, u32 power_index
,
505 enum radio_path rfpath
, u8 hw_rate
)
507 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
508 enum odm_rf_radio_path odm_rfpath
= (enum odm_rf_radio_path
)rfpath
;
510 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
511 return config_phydm_write_txagc_8822b(dm
, power_index
,
512 odm_rfpath
, hw_rate
);
517 static bool rtl_phydm_c2h_content_parsing(struct rtl_priv
*rtlpriv
, u8 cmd_id
,
518 u8 cmd_len
, u8
*content
)
520 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
522 if (phydm_c2H_content_parsing(dm
, cmd_id
, cmd_len
, content
))
528 static bool rtl_phydm_query_phy_status(struct rtl_priv
*rtlpriv
, u8
*phystrpt
,
529 struct ieee80211_hdr
*hdr
,
530 struct rtl_stats
*pstatus
)
532 /* NOTE: phystrpt may be NULL, and need to fill default value */
534 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
535 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtlpriv
);
536 struct rtl_mac
*mac
= rtl_mac(rtlpriv
);
537 struct dm_per_pkt_info pktinfo
; /* input of pydm */
538 struct dm_phy_status_info phy_info
; /* output of phydm */
539 __le16 fc
= hdr
->frame_control
;
541 /* fill driver pstatus */
542 ether_addr_copy(pstatus
->psaddr
, ieee80211_get_SA(hdr
));
545 memset(&pktinfo
, 0, sizeof(pktinfo
));
547 pktinfo
.data_rate
= pstatus
->rate
;
549 if (rtlpriv
->mac80211
.opmode
== NL80211_IFTYPE_STATION
) {
550 pktinfo
.station_id
= 0;
552 /* TODO: use rtl_find_sta() to find ID */
553 pktinfo
.station_id
= 0xFF;
556 pktinfo
.is_packet_match_bssid
=
557 (!ieee80211_is_ctl(fc
) &&
558 (ether_addr_equal(mac
->bssid
,
559 ieee80211_has_tods(fc
) ?
561 ieee80211_has_fromds(fc
) ?
564 (!pstatus
->hwerror
) && (!pstatus
->crc
) && (!pstatus
->icv
));
565 pktinfo
.is_packet_to_self
=
566 pktinfo
.is_packet_match_bssid
&&
567 (ether_addr_equal(hdr
->addr1
, rtlefuse
->dev_addr
));
568 pktinfo
.is_to_self
= (!pstatus
->icv
) && (!pstatus
->crc
) &&
569 (ether_addr_equal(hdr
->addr1
, rtlefuse
->dev_addr
));
570 pktinfo
.is_packet_beacon
= (ieee80211_is_beacon(fc
) ? true : false);
572 /* query phy status */
574 odm_phy_status_query(dm
, &phy_info
, phystrpt
, &pktinfo
);
576 memset(&phy_info
, 0, sizeof(phy_info
));
578 /* copy phy_info from phydm to driver */
579 pstatus
->rx_pwdb_all
= phy_info
.rx_pwdb_all
;
580 pstatus
->bt_rx_rssi_percentage
= phy_info
.bt_rx_rssi_percentage
;
581 pstatus
->recvsignalpower
= phy_info
.recv_signal_power
;
582 pstatus
->signalquality
= phy_info
.signal_quality
;
583 pstatus
->rx_mimo_signalquality
[0] = phy_info
.rx_mimo_signal_quality
[0];
584 pstatus
->rx_mimo_signalquality
[1] = phy_info
.rx_mimo_signal_quality
[1];
585 pstatus
->rx_packet_bw
=
586 phy_info
.band_width
; /* HT_CHANNEL_WIDTH_20 <- ODM_BW20M */
588 /* fill driver pstatus */
589 pstatus
->packet_matchbssid
= pktinfo
.is_packet_match_bssid
;
590 pstatus
->packet_toself
= pktinfo
.is_packet_to_self
;
591 pstatus
->packet_beacon
= pktinfo
.is_packet_beacon
;
596 static u8
rtl_phydm_rate_id_mapping(struct rtl_priv
*rtlpriv
,
597 enum wireless_mode wireless_mode
,
598 enum rf_type rf_type
,
599 enum ht_channel_width bw
)
601 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
603 return phydm_rate_id_mapping(dm
, wireless_mode
, rf_type
, bw
);
606 static bool rtl_phydm_get_ra_bitmap(struct rtl_priv
*rtlpriv
,
607 enum wireless_mode wireless_mode
,
608 enum rf_type rf_type
,
609 enum ht_channel_width bw
,
610 u8 tx_rate_level
, /* 0~6 */
614 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
615 const u8 mimo_ps_enable
= 0;
616 const u8 disable_cck_rate
= 0;
618 phydm_update_hal_ra_mask(dm
, wireless_mode
, rf_type
, bw
, mimo_ps_enable
,
619 disable_cck_rate
, tx_bitmap_msb
, tx_bitmap_lsb
,
625 static u8
_rtl_phydm_get_macid(struct rtl_priv
*rtlpriv
,
626 struct ieee80211_sta
*sta
)
628 struct rtl_mac
*mac
= rtl_mac(rtlpriv
);
630 if (mac
->opmode
== NL80211_IFTYPE_STATION
||
631 mac
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
633 } else if (mac
->opmode
== NL80211_IFTYPE_AP
||
634 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
640 static bool rtl_phydm_add_sta(struct rtl_priv
*rtlpriv
,
641 struct ieee80211_sta
*sta
)
643 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
644 struct rtl_sta_info
*sta_entry
= (struct rtl_sta_info
*)sta
->drv_priv
;
645 u8 mac_id
= _rtl_phydm_get_macid(rtlpriv
, sta
);
647 odm_cmn_info_ptr_array_hook(dm
, ODM_CMNINFO_STA_STATUS
, mac_id
,
653 static bool rtl_phydm_del_sta(struct rtl_priv
*rtlpriv
,
654 struct ieee80211_sta
*sta
)
656 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
657 u8 mac_id
= _rtl_phydm_get_macid(rtlpriv
, sta
);
659 odm_cmn_info_ptr_array_hook(dm
, ODM_CMNINFO_STA_STATUS
, mac_id
, NULL
);
664 static u32
rtl_phydm_get_version(struct rtl_priv
*rtlpriv
)
668 if (IS_HARDWARE_TYPE_8822B(rtlpriv
))
669 ver
= RELEASE_VERSION_8822B
;
674 static bool rtl_phydm_modify_ra_pcr_threshold(struct rtl_priv
*rtlpriv
,
675 u8 ra_offset_direction
,
676 u8 ra_threshold_offset
)
678 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
680 phydm_modify_RA_PCR_threshold(dm
, ra_offset_direction
,
681 ra_threshold_offset
);
686 static u32
rtl_phydm_query_counter(struct rtl_priv
*rtlpriv
,
687 const char *info_type
)
689 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
690 static const struct query_entry
{
691 const char *query_name
;
692 enum phydm_info_query query_id
;
694 #define QUERY_ENTRY(name) {#name, name}
695 QUERY_ENTRY(PHYDM_INFO_FA_OFDM
),
696 QUERY_ENTRY(PHYDM_INFO_FA_CCK
),
697 QUERY_ENTRY(PHYDM_INFO_CCA_OFDM
),
698 QUERY_ENTRY(PHYDM_INFO_CCA_CCK
),
699 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_CCK
),
700 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_LEGACY
),
701 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_HT
),
702 QUERY_ENTRY(PHYDM_INFO_CRC32_OK_VHT
),
703 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_CCK
),
704 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_LEGACY
),
705 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_HT
),
706 QUERY_ENTRY(PHYDM_INFO_CRC32_ERROR_VHT
),
708 #define QUERY_TABLE_SIZE ARRAY_SIZE(query_table)
711 const struct query_entry
*entry
;
713 if (!strcmp(info_type
, "IQK_TOTAL"))
714 return dm
->n_iqk_cnt
;
716 if (!strcmp(info_type
, "IQK_OK"))
717 return dm
->n_iqk_ok_cnt
;
719 if (!strcmp(info_type
, "IQK_FAIL"))
720 return dm
->n_iqk_fail_cnt
;
722 for (i
= 0; i
< QUERY_TABLE_SIZE
; i
++) {
723 entry
= &query_table
[i
];
725 if (!strcmp(info_type
, entry
->query_name
))
726 return phydm_cmn_info_query(dm
, entry
->query_id
);
729 pr_err("Unrecognized info_type:%s!!!!:\n", info_type
);
734 static bool rtl_phydm_debug_cmd(struct rtl_priv
*rtlpriv
, char *in
, u32 in_len
,
735 char *out
, u32 out_len
)
737 struct phy_dm_struct
*dm
= rtlpriv_to_phydm(rtlpriv
);
739 phydm_cmd(dm
, in
, in_len
, 1, out
, out_len
);
744 static struct rtl_phydm_ops rtl_phydm_operation
= {
745 /* init/deinit priv */
746 .phydm_init_priv
= rtl_phydm_init_priv
,
747 .phydm_deinit_priv
= rtl_phydm_deinit_priv
,
748 .phydm_load_txpower_by_rate
= rtl_phydm_load_txpower_by_rate
,
749 .phydm_load_txpower_limit
= rtl_phydm_load_txpower_limit
,
752 .phydm_init_dm
= rtl_phydm_init_dm
,
753 .phydm_deinit_dm
= rtl_phydm_deinit_dm
,
754 .phydm_reset_dm
= rtl_phydm_reset_dm
,
755 .phydm_parameter_init
= rtl_phydm_parameter_init
,
756 .phydm_phy_bb_config
= rtl_phydm_phy_bb_config
,
757 .phydm_phy_rf_config
= rtl_phydm_phy_rf_config
,
758 .phydm_phy_mac_config
= rtl_phydm_phy_mac_config
,
759 .phydm_trx_mode
= rtl_phydm_trx_mode
,
762 .phydm_watchdog
= rtl_phydm_watchdog
,
765 .phydm_switch_band
= rtl_phydm_switch_band
,
766 .phydm_switch_channel
= rtl_phydm_switch_channel
,
767 .phydm_switch_bandwidth
= rtl_phydm_switch_bandwidth
,
768 .phydm_iq_calibrate
= rtl_phydm_iq_calibrate
,
769 .phydm_clear_txpowertracking_state
=
770 rtl_phydm_clear_txpowertracking_state
,
771 .phydm_pause_dig
= rtl_phydm_pause_dig
,
774 .phydm_read_rf_reg
= rtl_phydm_read_rf_reg
,
775 .phydm_write_rf_reg
= rtl_phydm_write_rf_reg
,
776 .phydm_read_txagc
= rtl_phydm_read_txagc
,
777 .phydm_write_txagc
= rtl_phydm_write_txagc
,
780 .phydm_c2h_content_parsing
= rtl_phydm_c2h_content_parsing
,
781 .phydm_query_phy_status
= rtl_phydm_query_phy_status
,
784 .phydm_rate_id_mapping
= rtl_phydm_rate_id_mapping
,
785 .phydm_get_ra_bitmap
= rtl_phydm_get_ra_bitmap
,
788 .phydm_add_sta
= rtl_phydm_add_sta
,
789 .phydm_del_sta
= rtl_phydm_del_sta
,
792 .phydm_get_version
= rtl_phydm_get_version
,
793 .phydm_modify_ra_pcr_threshold
= rtl_phydm_modify_ra_pcr_threshold
,
794 .phydm_query_counter
= rtl_phydm_query_counter
,
797 .phydm_debug_cmd
= rtl_phydm_debug_cmd
,
800 struct rtl_phydm_ops
*rtl_phydm_get_ops_pointer(void)
802 return &rtl_phydm_operation
;
804 EXPORT_SYMBOL(rtl_phydm_get_ops_pointer
);
806 /* ********************************************************
807 * Define phydm callout function in below
808 * ********************************************************
811 u8
phy_get_tx_power_index(void *adapter
, u8 rf_path
, u8 rate
,
812 enum ht_channel_width bandwidth
, u8 channel
)
814 /* rate: DESC_RATE1M */
815 struct rtl_priv
*rtlpriv
= (struct rtl_priv
*)adapter
;
817 return rtlpriv
->cfg
->ops
->get_txpower_index(rtlpriv
->hw
, rf_path
, rate
,
821 void phy_set_tx_power_index_by_rs(void *adapter
, u8 ch
, u8 path
, u8 rs
)
823 struct rtl_priv
*rtlpriv
= (struct rtl_priv
*)adapter
;
825 return rtlpriv
->cfg
->ops
->set_tx_power_index_by_rs(rtlpriv
->hw
, ch
,
829 void phy_store_tx_power_by_rate(void *adapter
, u32 band
, u32 rfpath
, u32 txnum
,
830 u32 regaddr
, u32 bitmask
, u32 data
)
832 struct rtl_priv
*rtlpriv
= (struct rtl_priv
*)adapter
;
834 rtlpriv
->cfg
->ops
->store_tx_power_by_rate(
835 rtlpriv
->hw
, band
, rfpath
, txnum
, regaddr
, bitmask
, data
);
838 void phy_set_tx_power_limit(void *dm
, u8
*regulation
, u8
*band
, u8
*bandwidth
,
839 u8
*rate_section
, u8
*rf_path
, u8
*channel
,
842 struct rtl_priv
*rtlpriv
=
843 (struct rtl_priv
*)((struct phy_dm_struct
*)dm
)->adapter
;
845 rtlpriv
->cfg
->ops
->phy_set_txpower_limit(rtlpriv
->hw
, regulation
, band
,
846 bandwidth
, rate_section
,
847 rf_path
, channel
, power_limit
);
850 void rtl_hal_update_ra_mask(void *adapter
, struct rtl_sta_info
*psta
,
853 struct rtl_priv
*rtlpriv
= (struct rtl_priv
*)adapter
;
854 struct ieee80211_sta
*sta
=
855 container_of((void *)psta
, struct ieee80211_sta
, drv_priv
);
857 rtlpriv
->cfg
->ops
->update_rate_tbl(rtlpriv
->hw
, sta
, rssi_level
, false);
860 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
861 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
862 MODULE_LICENSE("GPL");
863 MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");