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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12
13 #include "tb.h"
14
15 #define USB4_DATA_DWORDS 16
16 #define USB4_DATA_RETRIES 3
17
18 enum usb4_switch_op {
19 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10,
20 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11,
21 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12,
22 USB4_SWITCH_OP_NVM_WRITE = 0x20,
23 USB4_SWITCH_OP_NVM_AUTH = 0x21,
24 USB4_SWITCH_OP_NVM_READ = 0x22,
25 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23,
26 USB4_SWITCH_OP_DROM_READ = 0x24,
27 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25,
28 };
29
30 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
31 #define USB4_NVM_READ_OFFSET_SHIFT 2
32 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
33 #define USB4_NVM_READ_LENGTH_SHIFT 24
34
35 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
36 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
37
38 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
39 #define USB4_DROM_ADDRESS_SHIFT 2
40 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
41 #define USB4_DROM_SIZE_SHIFT 15
42
43 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
44
45 typedef int (*read_block_fn)(struct tb_switch *, unsigned int, void *, size_t);
46 typedef int (*write_block_fn)(struct tb_switch *, const void *, size_t);
47
48 static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
49 u32 value, int timeout_msec)
50 {
51 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
52
53 do {
54 u32 val;
55 int ret;
56
57 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
58 if (ret)
59 return ret;
60
61 if ((val & bit) == value)
62 return 0;
63
64 usleep_range(50, 100);
65 } while (ktime_before(ktime_get(), timeout));
66
67 return -ETIMEDOUT;
68 }
69
70 static int usb4_switch_op_read_data(struct tb_switch *sw, void *data,
71 size_t dwords)
72 {
73 if (dwords > USB4_DATA_DWORDS)
74 return -EINVAL;
75
76 return tb_sw_read(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
77 }
78
79 static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data,
80 size_t dwords)
81 {
82 if (dwords > USB4_DATA_DWORDS)
83 return -EINVAL;
84
85 return tb_sw_write(sw, data, TB_CFG_SWITCH, ROUTER_CS_9, dwords);
86 }
87
88 static int usb4_switch_op_read_metadata(struct tb_switch *sw, u32 *metadata)
89 {
90 return tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
91 }
92
93 static int usb4_switch_op_write_metadata(struct tb_switch *sw, u32 metadata)
94 {
95 return tb_sw_write(sw, &metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
96 }
97
98 static int usb4_switch_do_read_data(struct tb_switch *sw, u16 address,
99 void *buf, size_t size, read_block_fn read_block)
100 {
101 unsigned int retries = USB4_DATA_RETRIES;
102 unsigned int offset;
103
104 offset = address & 3;
105 address = address & ~3;
106
107 do {
108 size_t nbytes = min_t(size_t, size, USB4_DATA_DWORDS * 4);
109 unsigned int dwaddress, dwords;
110 u8 data[USB4_DATA_DWORDS * 4];
111 int ret;
112
113 dwaddress = address / 4;
114 dwords = ALIGN(nbytes, 4) / 4;
115
116 ret = read_block(sw, dwaddress, data, dwords);
117 if (ret) {
118 if (ret == -ETIMEDOUT) {
119 if (retries--)
120 continue;
121 ret = -EIO;
122 }
123 return ret;
124 }
125
126 memcpy(buf, data + offset, nbytes);
127
128 size -= nbytes;
129 address += nbytes;
130 buf += nbytes;
131 } while (size > 0);
132
133 return 0;
134 }
135
136 static int usb4_switch_do_write_data(struct tb_switch *sw, u16 address,
137 const void *buf, size_t size, write_block_fn write_next_block)
138 {
139 unsigned int retries = USB4_DATA_RETRIES;
140 unsigned int offset;
141
142 offset = address & 3;
143 address = address & ~3;
144
145 do {
146 u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4);
147 u8 data[USB4_DATA_DWORDS * 4];
148 int ret;
149
150 memcpy(data + offset, buf, nbytes);
151
152 ret = write_next_block(sw, data, nbytes / 4);
153 if (ret) {
154 if (ret == -ETIMEDOUT) {
155 if (retries--)
156 continue;
157 ret = -EIO;
158 }
159 return ret;
160 }
161
162 size -= nbytes;
163 address += nbytes;
164 buf += nbytes;
165 } while (size > 0);
166
167 return 0;
168 }
169
170 static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u8 *status)
171 {
172 u32 val;
173 int ret;
174
175 val = opcode | ROUTER_CS_26_OV;
176 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
177 if (ret)
178 return ret;
179
180 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
181 if (ret)
182 return ret;
183
184 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
185 if (val & ROUTER_CS_26_ONS)
186 return -EOPNOTSUPP;
187
188 *status = (val & ROUTER_CS_26_STATUS_MASK) >> ROUTER_CS_26_STATUS_SHIFT;
189 return 0;
190 }
191
192 /**
193 * usb4_switch_setup() - Additional setup for USB4 device
194 * @sw: USB4 router to setup
195 *
196 * USB4 routers need additional settings in order to enable all the
197 * tunneling. This function enables USB and PCIe tunneling if it can be
198 * enabled (e.g the parent switch also supports them). If USB tunneling
199 * is not available for some reason (like that there is Thunderbolt 3
200 * switch upstream) then the internal xHCI controller is enabled
201 * instead.
202 */
203 int usb4_switch_setup(struct tb_switch *sw)
204 {
205 struct tb_switch *parent;
206 bool tbt3, xhci;
207 u32 val = 0;
208 int ret;
209
210 if (!tb_route(sw))
211 return 0;
212
213 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
214 if (ret)
215 return ret;
216
217 xhci = val & ROUTER_CS_6_HCI;
218 tbt3 = !(val & ROUTER_CS_6_TNS);
219
220 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
221 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
222
223 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
224 if (ret)
225 return ret;
226
227 parent = tb_switch_parent(sw);
228
229 if (tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
230 val |= ROUTER_CS_5_UTO;
231 xhci = false;
232 }
233
234 /* Only enable PCIe tunneling if the parent router supports it */
235 if (tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
236 val |= ROUTER_CS_5_PTO;
237 /*
238 * xHCI can be enabled if PCIe tunneling is supported
239 * and the parent does not have any USB3 dowstream
240 * adapters (so we cannot do USB 3.x tunneling).
241 */
242 if (xhci)
243 val |= ROUTER_CS_5_HCO;
244 }
245
246 /* TBT3 supported by the CM */
247 val |= ROUTER_CS_5_C3S;
248 /* Tunneling configuration is ready now */
249 val |= ROUTER_CS_5_CV;
250
251 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
252 if (ret)
253 return ret;
254
255 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
256 ROUTER_CS_6_CR, 50);
257 }
258
259 /**
260 * usb4_switch_read_uid() - Read UID from USB4 router
261 * @sw: USB4 router
262 * @uid: UID is stored here
263 *
264 * Reads 64-bit UID from USB4 router config space.
265 */
266 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
267 {
268 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
269 }
270
271 static int usb4_switch_drom_read_block(struct tb_switch *sw,
272 unsigned int dwaddress, void *buf,
273 size_t dwords)
274 {
275 u8 status = 0;
276 u32 metadata;
277 int ret;
278
279 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
280 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
281 USB4_DROM_ADDRESS_MASK;
282
283 ret = usb4_switch_op_write_metadata(sw, metadata);
284 if (ret)
285 return ret;
286
287 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DROM_READ, &status);
288 if (ret)
289 return ret;
290
291 if (status)
292 return -EIO;
293
294 return usb4_switch_op_read_data(sw, buf, dwords);
295 }
296
297 /**
298 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
299 * @sw: USB4 router
300 * @address: Byte address inside DROM to start reading
301 * @buf: Buffer where the DROM content is stored
302 * @size: Number of bytes to read from DROM
303 *
304 * Uses USB4 router operations to read router DROM. For devices this
305 * should always work but for hosts it may return %-EOPNOTSUPP in which
306 * case the host router does not have DROM.
307 */
308 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
309 size_t size)
310 {
311 return usb4_switch_do_read_data(sw, address, buf, size,
312 usb4_switch_drom_read_block);
313 }
314
315 static int usb4_set_port_configured(struct tb_port *port, bool configured)
316 {
317 int ret;
318 u32 val;
319
320 ret = tb_port_read(port, &val, TB_CFG_PORT,
321 port->cap_usb4 + PORT_CS_19, 1);
322 if (ret)
323 return ret;
324
325 if (configured)
326 val |= PORT_CS_19_PC;
327 else
328 val &= ~PORT_CS_19_PC;
329
330 return tb_port_write(port, &val, TB_CFG_PORT,
331 port->cap_usb4 + PORT_CS_19, 1);
332 }
333
334 /**
335 * usb4_switch_configure_link() - Set upstream USB4 link configured
336 * @sw: USB4 router
337 *
338 * Sets the upstream USB4 link to be configured for power management
339 * purposes.
340 */
341 int usb4_switch_configure_link(struct tb_switch *sw)
342 {
343 struct tb_port *up;
344
345 if (!tb_route(sw))
346 return 0;
347
348 up = tb_upstream_port(sw);
349 return usb4_set_port_configured(up, true);
350 }
351
352 /**
353 * usb4_switch_unconfigure_link() - Un-set upstream USB4 link configuration
354 * @sw: USB4 router
355 *
356 * Reverse of usb4_switch_configure_link().
357 */
358 void usb4_switch_unconfigure_link(struct tb_switch *sw)
359 {
360 struct tb_port *up;
361
362 if (sw->is_unplugged || !tb_route(sw))
363 return;
364
365 up = tb_upstream_port(sw);
366 usb4_set_port_configured(up, false);
367 }
368
369 /**
370 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
371 * @sw: USB4 router
372 *
373 * Checks whether conditions are met so that lane bonding can be
374 * established with the upstream router. Call only for device routers.
375 */
376 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
377 {
378 struct tb_port *up;
379 int ret;
380 u32 val;
381
382 up = tb_upstream_port(sw);
383 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
384 if (ret)
385 return false;
386
387 return !!(val & PORT_CS_18_BE);
388 }
389
390 /**
391 * usb4_switch_set_sleep() - Prepare the router to enter sleep
392 * @sw: USB4 router
393 *
394 * Enables wakes and sets sleep bit for the router. Returns when the
395 * router sleep ready bit has been asserted.
396 */
397 int usb4_switch_set_sleep(struct tb_switch *sw)
398 {
399 int ret;
400 u32 val;
401
402 /* Set sleep bit and wait for sleep ready to be asserted */
403 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
404 if (ret)
405 return ret;
406
407 val |= ROUTER_CS_5_SLP;
408
409 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
410 if (ret)
411 return ret;
412
413 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
414 ROUTER_CS_6_SLPR, 500);
415 }
416
417 /**
418 * usb4_switch_nvm_sector_size() - Return router NVM sector size
419 * @sw: USB4 router
420 *
421 * If the router supports NVM operations this function returns the NVM
422 * sector size in bytes. If NVM operations are not supported returns
423 * %-EOPNOTSUPP.
424 */
425 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
426 {
427 u32 metadata;
428 u8 status;
429 int ret;
430
431 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &status);
432 if (ret)
433 return ret;
434
435 if (status)
436 return status == 0x2 ? -EOPNOTSUPP : -EIO;
437
438 ret = usb4_switch_op_read_metadata(sw, &metadata);
439 if (ret)
440 return ret;
441
442 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
443 }
444
445 static int usb4_switch_nvm_read_block(struct tb_switch *sw,
446 unsigned int dwaddress, void *buf, size_t dwords)
447 {
448 u8 status = 0;
449 u32 metadata;
450 int ret;
451
452 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
453 USB4_NVM_READ_LENGTH_MASK;
454 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
455 USB4_NVM_READ_OFFSET_MASK;
456
457 ret = usb4_switch_op_write_metadata(sw, metadata);
458 if (ret)
459 return ret;
460
461 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_READ, &status);
462 if (ret)
463 return ret;
464
465 if (status)
466 return -EIO;
467
468 return usb4_switch_op_read_data(sw, buf, dwords);
469 }
470
471 /**
472 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
473 * @sw: USB4 router
474 * @address: Starting address in bytes
475 * @buf: Read data is placed here
476 * @size: How many bytes to read
477 *
478 * Reads NVM contents of the router. If NVM is not supported returns
479 * %-EOPNOTSUPP.
480 */
481 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
482 size_t size)
483 {
484 return usb4_switch_do_read_data(sw, address, buf, size,
485 usb4_switch_nvm_read_block);
486 }
487
488 static int usb4_switch_nvm_set_offset(struct tb_switch *sw,
489 unsigned int address)
490 {
491 u32 metadata, dwaddress;
492 u8 status = 0;
493 int ret;
494
495 dwaddress = address / 4;
496 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
497 USB4_NVM_SET_OFFSET_MASK;
498
499 ret = usb4_switch_op_write_metadata(sw, metadata);
500 if (ret)
501 return ret;
502
503 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &status);
504 if (ret)
505 return ret;
506
507 return status ? -EIO : 0;
508 }
509
510 static int usb4_switch_nvm_write_next_block(struct tb_switch *sw,
511 const void *buf, size_t dwords)
512 {
513 u8 status;
514 int ret;
515
516 ret = usb4_switch_op_write_data(sw, buf, dwords);
517 if (ret)
518 return ret;
519
520 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_WRITE, &status);
521 if (ret)
522 return ret;
523
524 return status ? -EIO : 0;
525 }
526
527 /**
528 * usb4_switch_nvm_write() - Write to the router NVM
529 * @sw: USB4 router
530 * @address: Start address where to write in bytes
531 * @buf: Pointer to the data to write
532 * @size: Size of @buf in bytes
533 *
534 * Writes @buf to the router NVM using USB4 router operations. If NVM
535 * write is not supported returns %-EOPNOTSUPP.
536 */
537 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
538 const void *buf, size_t size)
539 {
540 int ret;
541
542 ret = usb4_switch_nvm_set_offset(sw, address);
543 if (ret)
544 return ret;
545
546 return usb4_switch_do_write_data(sw, address, buf, size,
547 usb4_switch_nvm_write_next_block);
548 }
549
550 /**
551 * usb4_switch_nvm_authenticate() - Authenticate new NVM
552 * @sw: USB4 router
553 *
554 * After the new NVM has been written via usb4_switch_nvm_write(), this
555 * function triggers NVM authentication process. If the authentication
556 * is successful the router is power cycled and the new NVM starts
557 * running. In case of failure returns negative errno.
558 */
559 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
560 {
561 u8 status = 0;
562 int ret;
563
564 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, &status);
565 if (ret)
566 return ret;
567
568 switch (status) {
569 case 0x0:
570 tb_sw_dbg(sw, "NVM authentication successful\n");
571 return 0;
572 case 0x1:
573 return -EINVAL;
574 case 0x2:
575 return -EAGAIN;
576 case 0x3:
577 return -EOPNOTSUPP;
578 default:
579 return -EIO;
580 }
581 }
582
583 /**
584 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
585 * @sw: USB4 router
586 * @in: DP IN adapter
587 *
588 * For DP tunneling this function can be used to query availability of
589 * DP IN resource. Returns true if the resource is available for DP
590 * tunneling, false otherwise.
591 */
592 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
593 {
594 u8 status;
595 int ret;
596
597 ret = usb4_switch_op_write_metadata(sw, in->port);
598 if (ret)
599 return false;
600
601 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &status);
602 /*
603 * If DP resource allocation is not supported assume it is
604 * always available.
605 */
606 if (ret == -EOPNOTSUPP)
607 return true;
608 else if (ret)
609 return false;
610
611 return !status;
612 }
613
614 /**
615 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
616 * @sw: USB4 router
617 * @in: DP IN adapter
618 *
619 * Allocates DP IN resource for DP tunneling using USB4 router
620 * operations. If the resource was allocated returns %0. Otherwise
621 * returns negative errno, in particular %-EBUSY if the resource is
622 * already allocated.
623 */
624 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
625 {
626 u8 status;
627 int ret;
628
629 ret = usb4_switch_op_write_metadata(sw, in->port);
630 if (ret)
631 return ret;
632
633 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &status);
634 if (ret == -EOPNOTSUPP)
635 return 0;
636 else if (ret)
637 return ret;
638
639 return status ? -EBUSY : 0;
640 }
641
642 /**
643 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
644 * @sw: USB4 router
645 * @in: DP IN adapter
646 *
647 * Releases the previously allocated DP IN resource.
648 */
649 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
650 {
651 u8 status;
652 int ret;
653
654 ret = usb4_switch_op_write_metadata(sw, in->port);
655 if (ret)
656 return ret;
657
658 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &status);
659 if (ret == -EOPNOTSUPP)
660 return 0;
661 else if (ret)
662 return ret;
663
664 return status ? -EIO : 0;
665 }
666
667 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
668 {
669 struct tb_port *p;
670 int usb4_idx = 0;
671
672 /* Assume port is primary */
673 tb_switch_for_each_port(sw, p) {
674 if (!tb_port_is_null(p))
675 continue;
676 if (tb_is_upstream_port(p))
677 continue;
678 if (!p->link_nr) {
679 if (p == port)
680 break;
681 usb4_idx++;
682 }
683 }
684
685 return usb4_idx;
686 }
687
688 /**
689 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
690 * @sw: USB4 router
691 * @port: USB4 port
692 *
693 * USB4 routers have direct mapping between USB4 ports and PCIe
694 * downstream adapters where the PCIe topology is extended. This
695 * function returns the corresponding downstream PCIe adapter or %NULL
696 * if no such mapping was possible.
697 */
698 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
699 const struct tb_port *port)
700 {
701 int usb4_idx = usb4_port_idx(sw, port);
702 struct tb_port *p;
703 int pcie_idx = 0;
704
705 /* Find PCIe down port matching usb4_port */
706 tb_switch_for_each_port(sw, p) {
707 if (!tb_port_is_pcie_down(p))
708 continue;
709
710 if (pcie_idx == usb4_idx && !tb_pci_port_is_enabled(p))
711 return p;
712
713 pcie_idx++;
714 }
715
716 return NULL;
717 }
718
719 /**
720 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
721 * @sw: USB4 router
722 * @port: USB4 port
723 *
724 * USB4 routers have direct mapping between USB4 ports and USB 3.x
725 * downstream adapters where the USB 3.x topology is extended. This
726 * function returns the corresponding downstream USB 3.x adapter or
727 * %NULL if no such mapping was possible.
728 */
729 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
730 const struct tb_port *port)
731 {
732 int usb4_idx = usb4_port_idx(sw, port);
733 struct tb_port *p;
734 int usb_idx = 0;
735
736 /* Find USB3 down port matching usb4_port */
737 tb_switch_for_each_port(sw, p) {
738 if (!tb_port_is_usb3_down(p))
739 continue;
740
741 if (usb_idx == usb4_idx && !tb_usb3_port_is_enabled(p))
742 return p;
743
744 usb_idx++;
745 }
746
747 return NULL;
748 }
749
750 /**
751 * usb4_port_unlock() - Unlock USB4 downstream port
752 * @port: USB4 port to unlock
753 *
754 * Unlocks USB4 downstream port so that the connection manager can
755 * access the router below this port.
756 */
757 int usb4_port_unlock(struct tb_port *port)
758 {
759 int ret;
760 u32 val;
761
762 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
763 if (ret)
764 return ret;
765
766 val &= ~ADP_CS_4_LCK;
767 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
768 }