4 bool "Enable driver model for timer drivers"
7 Enable driver model for timer access. It uses the same API as
8 lib/time.c, but now implemented by the uclass. The first timer
9 will be used. The timer is usually a 32 bits free-running up
10 counter. There may be no real tick, and no timer interrupt.
13 bool "Enable driver model for timer drivers in SPL"
14 depends on TIMER && SPL
16 Enable support for timer drivers in SPL. These can be used to get
17 a timer value when in SPL, or perhaps for implementing a delay
18 function. This enables the drivers in drivers/timer as part of an
22 bool "Enable driver model for timer drivers in TPL"
23 depends on TIMER && TPL
25 Enable support for timer drivers in TPL. These can be used to get
26 a timer value when in TPL, or perhaps for implementing a delay
27 function. This enables the drivers in drivers/timer as part of an
31 bool "Enable driver model for timer drivers in VPL"
32 depends on TIMER && VPL
33 default y if TPL_TIMER
35 Enable support for timer drivers in VPL. These can be used to get
36 a timer value when in VPL, or perhaps for implementing a delay
37 function. This enables the drivers in drivers/timer as part of an
41 bool "Allow timer to be used early in U-Boot"
43 # initr_bootstage() requires a timer and is called before initr_dm()
44 # so only the early timer is available
45 default y if X86 && BOOTSTAGE
47 In some cases the timer must be accessible before driver model is
48 active. Examples include when using CONFIG_TRACE to trace U-Boot's
49 execution before driver model is set up. Enable this option to
50 use an early timer. These functions must be supported by your timer
51 driver: timer_early_get_count() and timer_early_get_rate().
54 bool "Altera timer support"
57 Select this to enable a timer for Altera devices. Please find
58 details on the "Embedded Peripherals IP User Guide" of Altera.
60 config ANDES_PLMT_TIMER
62 depends on RISCV_MMODE || SPL_RISCV_MMODE
64 The Andes PLMT block holds memory-mapped mtime register
65 associated with timer tick.
68 bool "ARC timer support"
69 depends on TIMER && ARC && CLK
71 Select this to enable built-in ARC timers.
72 ARC cores may have up to 2 built-in timers: timer0 and timer1,
73 usually at least one of them exists. Either of them is supported
77 bool "Aspeed ast2400/ast2500 timer support"
79 default y if ARCH_ASPEED
81 Select this to enable timer for Aspeed ast2400/ast2500 devices.
82 This is a simple sys timer driver, it is compatible with lib/time.c,
83 but does not support any interrupts. Even though SoC has 8 hardware
84 counters, they are all treated as a single device by this driver.
85 This is mostly because they all share several registers which
86 makes it difficult to completely separate them.
88 config ATCPIT100_TIMER
89 bool "ATCPIT100 timer support"
92 Select this to enable a ATCPIT100 timer which will be embedded
93 in AE3XX, AE250 boards.
95 config ATMEL_PIT_TIMER
96 bool "Atmel periodic interval timer support"
99 Select this to enable a periodic interval timer for Atmel devices,
100 it is designed to offer maximum accuracy and efficient management,
101 even for systems with long response time.
103 config SPL_ATMEL_PIT_TIMER
104 bool "Atmel periodic interval timer support in SPL"
107 Select this to enable a periodic interval timer for Atmel devices,
108 it is designed to offer maximum accuracy and efficient management,
109 even for systems with long response time.
110 Select this to be available in SPL.
112 config ATMEL_TCB_TIMER
113 bool "Atmel timer counter support"
117 Select this to enable the use of the timer counter as a monotonic
120 config SPL_ATMEL_TCB_TIMER
121 bool "Atmel timer counter support in SPL"
125 Select this to enable the use of the timer counter as a monotonic
128 config CADENCE_TTC_TIMER
129 bool "Cadence TTC (Triple Timer Counter)"
132 Enables support for the cadence ttc driver. This driver is present
133 on Xilinx Zynq and ZynqMP SoCs.
135 config DESIGNWARE_APB_TIMER
136 bool "Designware APB Timer"
139 Enables support for the Designware APB Timer driver. This timer is
140 present on Altera SoCFPGA SoCs.
146 Enables support for the GXP Timer driver. This timer is
147 present on HPE GXP SoCs.
150 bool "MPC83xx timer support"
153 Select this to enable support for the timer found on
154 devices based on the MPC83xx family of SoCs.
156 config RENESAS_OSTM_TIMER
157 bool "Renesas RZ/A1 R7S72100 OSTM Timer"
160 Enables support for the Renesas OSTM Timer driver.
161 This timer is present on Renesas RZ/A1 R7S72100 SoCs.
163 config X86_TSC_TIMER_FREQ
164 int "x86 TSC timer frequency in Hz"
165 depends on X86_TSC_TIMER
168 Sets the estimated CPU frequency in Hz when TSC is used as the
169 early timer and the frequency can neither be calibrated via some
170 hardware ways, nor got from device tree at the time when device
171 tree is not available yet.
173 config NOMADIK_MTU_TIMER
174 bool "Nomadik MTU Timer"
177 Enables support for the Nomadik Multi Timer Unit (MTU),
178 used in ST-Ericsson Ux500 SoCs.
179 The MTU provides 4 decrementing free-running timers.
180 At the moment, only the first timer is used by the driver.
183 bool "Nuvoton NPCM timer support"
186 Select this to enable a timer on Nuvoton NPCM SoCs.
187 NPCM timer module has 5 down-counting timers, only the first timer
188 is used to implement timer ops. No support for early timer and
192 bool "Omap timer support"
195 Select this to enable an timer for Omap devices.
198 bool "RISC-V timer support"
199 depends on TIMER && RISCV
201 Select this to enable support for a generic RISC-V S-Mode timer
204 config ROCKCHIP_TIMER
205 bool "Rockchip timer support"
208 Select this to enable support for the timer found on
212 bool "Sandbox timer support"
213 depends on SANDBOX && TIMER
215 Select this to enable an emulated timer for sandbox. It gets
219 bool "STi timer support"
221 default y if ARCH_STI
223 Select this to enable a timer for STi devices.
226 bool "STM32 timer support"
229 Select this to enable support for the timer found on
233 bool "x86 Time-Stamp Counter (TSC) timer support"
234 depends on TIMER && X86
236 Select this to enable Time-Stamp Counter (TSC) timer for x86.
238 config X86_TSC_READ_BASE
239 bool "Read the TSC timer base on start-up"
240 depends on X86_TSC_TIMER
242 On x86 platforms the TSC timer tick starts at the value 0 on reset.
243 This it makes no sense to read the timer on boot and use that as the
244 base, since we will miss some time taken to load U-Boot, etc. This
245 delay is controlled by the SoC and we cannot reduce it, but for
246 bootstage we want to record the time since reset as accurately as
249 The only exception is when U-Boot is used as a secondary bootloader,
250 where this option should be enabled.
252 config TPL_X86_TSC_TIMER_NATIVE
253 bool "x86 TSC timer uses native calibration"
254 depends on TPL && X86_TSC_TIMER
256 Selects native timer calibration for TPL and don't include the other
257 methods in the code. This helps to reduce code size in TPL and works
258 on fairly modern Intel chips. Code-size reductions is about 700
262 bool "MediaTek timer support"
265 Select this to enable support for the timer found on
268 config MCHP_PIT64B_TIMER
269 bool "Microchip 64-bit periodic interval timer support"
272 Select this to enable support for Microchip 64-bit periodic
276 bool "NXP i.MX GPT timer support"
279 Select this to enable support for the timer found on
283 bool "Xilinx timer support"
286 select SPL_REGMAP if SPL
288 Select this to enable support for the timer found on
289 any Xilinx boards (axi timer).