2 * Copyright (c) 2012 The Chromium OS Authors.
4 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/i8254.h>
17 #include <asm/ibmpc.h>
19 #include <asm/u-boot-x86.h>
21 #define MAX_NUM_FREQS 9
23 DECLARE_GLOBAL_DATA_PTR
;
26 * According to Intel 64 and IA-32 System Programming Guide,
27 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
28 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
29 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
30 * so we need manually differentiate SoC families. This is what the
31 * field msr_plat does.
34 u8 x86_family
; /* CPU family */
35 u8 x86_model
; /* model */
36 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
38 u32 freqs
[MAX_NUM_FREQS
];
41 static struct freq_desc freq_desc_tables
[] = {
43 { 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
45 { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
46 /* TNG - Intel Atom processor Z3400 series */
47 { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
48 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
49 { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
50 /* ANN - Intel Atom processor Z3500 series */
51 { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
52 /* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
53 { 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
54 80000, 93300, 90000, 88900, 87500 } },
56 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
59 static int match_cpu(u8 family
, u8 model
)
63 for (i
= 0; i
< ARRAY_SIZE(freq_desc_tables
); i
++) {
64 if ((family
== freq_desc_tables
[i
].x86_family
) &&
65 (model
== freq_desc_tables
[i
].x86_model
))
72 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
73 #define id_to_freq(cpu_index, freq_id) \
74 (freq_desc_tables[cpu_index].freqs[freq_id])
77 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
78 * reliable and the frequency is known (provided by HW).
80 * On these platforms PIT/HPET is generally not available so calibration won't
81 * work at all and there is no other clocksource to act as a watchdog for the
82 * TSC, so we have no other choice than to trust it.
84 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
86 static unsigned long __maybe_unused
cpu_mhz_from_msr(void)
88 u32 lo
, hi
, ratio
, freq_id
, freq
;
92 if (gd
->arch
.x86_vendor
!= X86_VENDOR_INTEL
)
95 cpu_index
= match_cpu(gd
->arch
.x86
, gd
->arch
.x86_model
);
99 if (freq_desc_tables
[cpu_index
].msr_plat
) {
100 rdmsr(MSR_PLATFORM_INFO
, lo
, hi
);
101 ratio
= (lo
>> 8) & 0xff;
103 rdmsr(MSR_IA32_PERF_STATUS
, lo
, hi
);
104 ratio
= (hi
>> 8) & 0x1f;
106 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio
);
108 if (freq_desc_tables
[cpu_index
].msr_plat
== 2) {
109 /* TODO: Figure out how best to deal with this */
111 debug("Using frequency: %u KHz\n", freq
);
113 /* Get FSB FREQ ID */
114 rdmsr(MSR_FSB_FREQ
, lo
, hi
);
116 freq
= id_to_freq(cpu_index
, freq_id
);
117 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
121 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
122 res
= freq
* ratio
/ 1000;
123 debug("TSC runs at %lu MHz\n", res
);
129 * This reads the current MSB of the PIT counter, and
130 * checks if we are running on sufficiently fast and
131 * non-virtualized hardware.
133 * Our expectations are:
135 * - the PIT is running at roughly 1.19MHz
137 * - each IO is going to take about 1us on real hardware,
138 * but we allow it to be much faster (by a factor of 10) or
139 * _slightly_ slower (ie we allow up to a 2us read+counter
140 * update - anything else implies a unacceptably slow CPU
141 * or PIT for the fast calibration to work.
143 * - with 256 PIT ticks to read the value, we have 214us to
144 * see the same MSB (and overhead like doing a single TSC
145 * read per MSB value etc).
147 * - We're doing 2 reads per loop (LSB, MSB), and we expect
148 * them each to take about a microsecond on real hardware.
149 * So we expect a count value of around 100. But we'll be
150 * generous, and accept anything over 50.
152 * - if the PIT is stuck, and we see *many* more reads, we
153 * return early (and the next caller of pit_expect_msb()
154 * then consider it a failure when they don't see the
155 * next expected value).
157 * These expectations mean that we know that we have seen the
158 * transition from one expected value to another with a fairly
159 * high accuracy, and we didn't miss any events. We can thus
160 * use the TSC value at the transitions to calculate a pretty
161 * good value for the TSC frequencty.
163 static inline int pit_verify_msb(unsigned char val
)
167 return inb(0x42) == val
;
170 static inline int pit_expect_msb(unsigned char val
, u64
*tscp
,
171 unsigned long *deltap
)
174 u64 tsc
= 0, prev_tsc
= 0;
176 for (count
= 0; count
< 50000; count
++) {
177 if (!pit_verify_msb(val
))
182 *deltap
= rdtsc() - prev_tsc
;
186 * We require _some_ success, but the quality control
187 * will be based on the error terms on the TSC values.
193 * How many MSB values do we want to see? We aim for
194 * a maximum error rate of 500ppm (in practice the
195 * real error is much smaller), but refuse to spend
196 * more than 50ms on it.
198 #define MAX_QUICK_PIT_MS 50
199 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
201 static unsigned long __maybe_unused
quick_pit_calibrate(void)
205 unsigned long d1
, d2
;
207 /* Set the Gate high, disable speaker */
208 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
211 * Counter 2, mode 0 (one-shot), binary count
213 * NOTE! Mode 2 decrements by two (and then the
214 * output is flipped each time, giving the same
215 * final output frequency as a decrement-by-one),
216 * so mode 0 is much better when looking at the
221 /* Start at 0xffff */
226 * The PIT starts counting at the next edge, so we
227 * need to delay for a microsecond. The easiest way
228 * to do that is to just read back the 16-bit counter
233 if (pit_expect_msb(0xff, &tsc
, &d1
)) {
234 for (i
= 1; i
<= MAX_QUICK_PIT_ITERATIONS
; i
++) {
235 if (!pit_expect_msb(0xff-i
, &delta
, &d2
))
239 * Iterate until the error is less than 500 ppm
242 if (d1
+d2
>= delta
>> 11)
246 * Check the PIT one more time to verify that
247 * all TSC reads were stable wrt the PIT.
249 * This also guarantees serialization of the
250 * last cycle read ('d2') in pit_expect_msb.
252 if (!pit_verify_msb(0xfe - i
))
257 debug("Fast TSC calibration failed\n");
262 * Ok, if we get here, then we've seen the
263 * MSB of the PIT decrement 'i' times, and the
264 * error has shrunk to less than 500 ppm.
266 * As a result, we can depend on there not being
267 * any odd delays anywhere, and the TSC reads are
268 * reliable (within the error).
270 * kHz = ticks / time-in-seconds / 1000;
271 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
272 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
274 delta
*= PIT_TICK_RATE
;
275 delta
/= (i
*256*1000);
276 debug("Fast TSC calibration using PIT\n");
280 /* Get the speed of the TSC timer in MHz */
281 unsigned notrace
long get_tbclk_mhz(void)
283 return get_tbclk() / 1000000;
286 static ulong
get_ms_timer(void)
288 return (get_ticks() * 1000) / get_tbclk();
291 ulong
get_timer(ulong base
)
293 return get_ms_timer() - base
;
296 ulong notrace
timer_get_us(void)
298 return get_ticks() / get_tbclk_mhz();
301 ulong
timer_get_boot_us(void)
303 return timer_get_us();
306 void __udelay(unsigned long usec
)
308 u64 now
= get_ticks();
311 stop
= now
+ usec
* get_tbclk_mhz();
313 while ((int64_t)(stop
- get_ticks()) > 0)
314 #if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
316 * Add a 'pause' instruction on qemu target,
317 * to give other VCPUs a chance to run.
319 asm volatile("pause");
325 static int tsc_timer_get_count(struct udevice
*dev
, u64
*count
)
327 u64 now_tick
= rdtsc();
329 *count
= now_tick
- gd
->arch
.tsc_base
;
334 static int tsc_timer_probe(struct udevice
*dev
)
336 struct timer_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
338 gd
->arch
.tsc_base
= rdtsc();
341 * If there is no clock frequency specified in the device tree,
342 * calibrate it by ourselves.
344 if (!uc_priv
->clock_rate
) {
345 unsigned long fast_calibrate
;
347 fast_calibrate
= cpu_mhz_from_msr();
348 if (!fast_calibrate
) {
349 fast_calibrate
= quick_pit_calibrate();
351 panic("TSC frequency is ZERO");
354 uc_priv
->clock_rate
= fast_calibrate
* 1000000;
360 static const struct timer_ops tsc_timer_ops
= {
361 .get_count
= tsc_timer_get_count
,
364 static const struct udevice_id tsc_timer_ids
[] = {
365 { .compatible
= "x86,tsc-timer", },
369 U_BOOT_DRIVER(tsc_timer
) = {
372 .of_match
= tsc_timer_ids
,
373 .probe
= tsc_timer_probe
,
374 .ops
= &tsc_timer_ops
,
375 .flags
= DM_FLAG_PRE_RELOC
,