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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/tsec.h
4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
27 #define TSEC_SIZE 0x01000
29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30 #if defined(CONFIG_MPC85xx)
31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32 #elif defined(CONFIG_MPC83XX)
33 #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
37 #define MAC_ADDR_LEN 6
39 /* #define TSEC_TIMEOUT 1000000 */
40 #define TSEC_TIMEOUT 1000
41 #define TOUT_LOOP 1000000
43 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
45 /* MAC register bits */
46 #define MACCFG1_SOFT_RESET 0x80000000
47 #define MACCFG1_RESET_RX_MC 0x00080000
48 #define MACCFG1_RESET_TX_MC 0x00040000
49 #define MACCFG1_RESET_RX_FUN 0x00020000
50 #define MACCFG1_RESET_TX_FUN 0x00010000
51 #define MACCFG1_LOOPBACK 0x00000100
52 #define MACCFG1_RX_FLOW 0x00000020
53 #define MACCFG1_TX_FLOW 0x00000010
54 #define MACCFG1_SYNCD_RX_EN 0x00000008
55 #define MACCFG1_RX_EN 0x00000004
56 #define MACCFG1_SYNCD_TX_EN 0x00000002
57 #define MACCFG1_TX_EN 0x00000001
59 #define MACCFG2_INIT_SETTINGS 0x00007205
60 #define MACCFG2_FULL_DUPLEX 0x00000001
61 #define MACCFG2_IF 0x00000300
62 #define MACCFG2_GMII 0x00000200
63 #define MACCFG2_MII 0x00000100
65 #define ECNTRL_INIT_SETTINGS 0x00001000
66 #define ECNTRL_TBI_MODE 0x00000020
67 #define ECNTRL_R100 0x00000008
72 #define TBIPA_VALUE 0x1f
73 #define MIIMCFG_INIT_VALUE 0x00000003
74 #define MIIMCFG_RESET 0x80000000
76 #define MIIMIND_BUSY 0x00000001
77 #define MIIMIND_NOTVALID 0x00000004
79 #define MIIM_CONTROL 0x00
80 #define MIIM_CONTROL_RESET 0x00009140
81 #define MIIM_CONTROL_INIT 0x00001140
82 #define MIIM_CONTROL_RESTART 0x00001340
83 #define MIIM_ANEN 0x00001000
86 #define MIIM_CR_RST 0x00008000
87 #define MIIM_CR_INIT 0x00001000
89 #define MIIM_STATUS 0x1
90 #define MIIM_STATUS_AN_DONE 0x00000020
91 #define MIIM_STATUS_LINK 0x0004
92 #define PHY_BMSR_AUTN_ABLE 0x0008
93 #define PHY_BMSR_AUTN_COMP 0x0020
95 #define MIIM_PHYIR1 0x2
96 #define MIIM_PHYIR2 0x3
99 #define MIIM_ANAR_INIT 0x1e1
101 #define MIIM_TBI_ANLPBPA 0x5
102 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
103 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
105 #define MIIM_TBI_ANEX 0x6
106 #define MIIM_TBI_ANEX_NP 0x00000004
107 #define MIIM_TBI_ANEX_PRX 0x00000002
109 #define MIIM_GBIT_CONTROL 0x9
110 #define MIIM_GBIT_CONTROL_INIT 0xe00
112 /* Cicada Auxiliary Control/Status Register */
113 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
114 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
115 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
116 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
117 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
118 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
120 /* Cicada Extended Control Register 1 */
121 #define MIIM_CIS8201_EXT_CON1 0x17
122 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
124 /* Cicada 8204 Extended PHY Control Register 1 */
125 #define MIIM_CIS8204_EPHY_CON 0x17
126 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
127 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
129 /* Cicada 8204 Serial LED Control Register */
130 #define MIIM_CIS8204_SLED_CON 0x1b
131 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
133 #define MIIM_GBIT_CON 0x09
134 #define MIIM_GBIT_CON_ADVERT 0x0e00
136 /* 88E1011 PHY Status Register */
137 #define MIIM_88E1011_PHY_STATUS 0x11
138 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
139 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
140 #define MIIM_88E1011_PHYSTAT_100 0x4000
141 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
142 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
143 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
145 /* DM9161 Control register values */
146 #define MIIM_DM9161_CR_STOP 0x0400
147 #define MIIM_DM9161_CR_RSTAN 0x1200
149 #define MIIM_DM9161_SCR 0x10
150 #define MIIM_DM9161_SCR_INIT 0x0610
152 /* DM9161 Specified Configuration and Status Register */
153 #define MIIM_DM9161_SCSR 0x11
154 #define MIIM_DM9161_SCSR_100F 0x8000
155 #define MIIM_DM9161_SCSR_100H 0x4000
156 #define MIIM_DM9161_SCSR_10F 0x2000
157 #define MIIM_DM9161_SCSR_10H 0x1000
159 /* DM9161 10BT Configuration/Status */
160 #define MIIM_DM9161_10BTCSR 0x12
161 #define MIIM_DM9161_10BTCSR_INIT 0x7800
163 /* LXT971 Status 2 registers */
164 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
165 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
166 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
167 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
168 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
169 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
171 /* DP83865 Control register values */
172 #define MIIM_DP83865_CR_INIT 0x9200
174 /* DP83865 Link and Auto-Neg Status Register */
175 #define MIIM_DP83865_LANR 0x11
176 #define MIIM_DP83865_SPD_MASK 0x0018
177 #define MIIM_DP83865_SPD_1000 0x0010
178 #define MIIM_DP83865_SPD_100 0x0008
179 #define MIIM_DP83865_DPX_FULL 0x0002
181 #define MIIM_READ_COMMAND 0x00000001
183 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
185 #define MINFLR_INIT_SETTINGS 0x00000040
187 #define DMACTRL_INIT_SETTINGS 0x000000c3
188 #define DMACTRL_GRS 0x00000010
189 #define DMACTRL_GTS 0x00000008
191 #define TSTAT_CLEAR_THALT 0x80000000
192 #define RSTAT_CLEAR_RHALT 0x00800000
195 #define IEVENT_INIT_CLEAR 0xffffffff
196 #define IEVENT_BABR 0x80000000
197 #define IEVENT_RXC 0x40000000
198 #define IEVENT_BSY 0x20000000
199 #define IEVENT_EBERR 0x10000000
200 #define IEVENT_MSRO 0x04000000
201 #define IEVENT_GTSC 0x02000000
202 #define IEVENT_BABT 0x01000000
203 #define IEVENT_TXC 0x00800000
204 #define IEVENT_TXE 0x00400000
205 #define IEVENT_TXB 0x00200000
206 #define IEVENT_TXF 0x00100000
207 #define IEVENT_IE 0x00080000
208 #define IEVENT_LC 0x00040000
209 #define IEVENT_CRL 0x00020000
210 #define IEVENT_XFUN 0x00010000
211 #define IEVENT_RXB0 0x00008000
212 #define IEVENT_GRSC 0x00000100
213 #define IEVENT_RXF0 0x00000080
215 #define IMASK_INIT_CLEAR 0x00000000
216 #define IMASK_TXEEN 0x00400000
217 #define IMASK_TXBEN 0x00200000
218 #define IMASK_TXFEN 0x00100000
219 #define IMASK_RXFEN0 0x00000080
222 /* Default Attribute fields */
223 #define ATTR_INIT_SETTINGS 0x000000c0
224 #define ATTRELI_INIT_SETTINGS 0x00000000
227 /* TxBD status field bits */
228 #define TXBD_READY 0x8000
229 #define TXBD_PADCRC 0x4000
230 #define TXBD_WRAP 0x2000
231 #define TXBD_INTERRUPT 0x1000
232 #define TXBD_LAST 0x0800
233 #define TXBD_CRC 0x0400
234 #define TXBD_DEF 0x0200
235 #define TXBD_HUGEFRAME 0x0080
236 #define TXBD_LATECOLLISION 0x0080
237 #define TXBD_RETRYLIMIT 0x0040
238 #define TXBD_RETRYCOUNTMASK 0x003c
239 #define TXBD_UNDERRUN 0x0002
240 #define TXBD_STATS 0x03ff
242 /* RxBD status field bits */
243 #define RXBD_EMPTY 0x8000
244 #define RXBD_RO1 0x4000
245 #define RXBD_WRAP 0x2000
246 #define RXBD_INTERRUPT 0x1000
247 #define RXBD_LAST 0x0800
248 #define RXBD_FIRST 0x0400
249 #define RXBD_MISS 0x0100
250 #define RXBD_BROADCAST 0x0080
251 #define RXBD_MULTICAST 0x0040
252 #define RXBD_LARGE 0x0020
253 #define RXBD_NONOCTET 0x0010
254 #define RXBD_SHORT 0x0008
255 #define RXBD_CRCERR 0x0004
256 #define RXBD_OVERRUN 0x0002
257 #define RXBD_TRUNCATED 0x0001
258 #define RXBD_STATS 0x003f
262 ushort status
; /* Status Fields */
263 ushort length
; /* Buffer length */
264 uint bufPtr
; /* Buffer Pointer */
269 ushort status
; /* Status Fields */
270 ushort length
; /* Buffer Length */
271 uint bufPtr
; /* Buffer Pointer */
274 typedef struct rmon_mib
276 /* Transmit and Receive Counters */
277 uint tr64
; /* Transmit and Receive 64-byte Frame Counter */
278 uint tr127
; /* Transmit and Receive 65-127 byte Frame Counter */
279 uint tr255
; /* Transmit and Receive 128-255 byte Frame Counter */
280 uint tr511
; /* Transmit and Receive 256-511 byte Frame Counter */
281 uint tr1k
; /* Transmit and Receive 512-1023 byte Frame Counter */
282 uint trmax
; /* Transmit and Receive 1024-1518 byte Frame Counter */
283 uint trmgv
; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
284 /* Receive Counters */
285 uint rbyt
; /* Receive Byte Counter */
286 uint rpkt
; /* Receive Packet Counter */
287 uint rfcs
; /* Receive FCS Error Counter */
288 uint rmca
; /* Receive Multicast Packet (Counter) */
289 uint rbca
; /* Receive Broadcast Packet */
290 uint rxcf
; /* Receive Control Frame Packet */
291 uint rxpf
; /* Receive Pause Frame Packet */
292 uint rxuo
; /* Receive Unknown OP Code */
293 uint raln
; /* Receive Alignment Error */
294 uint rflr
; /* Receive Frame Length Error */
295 uint rcde
; /* Receive Code Error */
296 uint rcse
; /* Receive Carrier Sense Error */
297 uint rund
; /* Receive Undersize Packet */
298 uint rovr
; /* Receive Oversize Packet */
299 uint rfrg
; /* Receive Fragments */
300 uint rjbr
; /* Receive Jabber */
301 uint rdrp
; /* Receive Drop */
302 /* Transmit Counters */
303 uint tbyt
; /* Transmit Byte Counter */
304 uint tpkt
; /* Transmit Packet */
305 uint tmca
; /* Transmit Multicast Packet */
306 uint tbca
; /* Transmit Broadcast Packet */
307 uint txpf
; /* Transmit Pause Control Frame */
308 uint tdfr
; /* Transmit Deferral Packet */
309 uint tedf
; /* Transmit Excessive Deferral Packet */
310 uint tscl
; /* Transmit Single Collision Packet */
312 uint tmcl
; /* Transmit Multiple Collision Packet */
313 uint tlcl
; /* Transmit Late Collision Packet */
314 uint txcl
; /* Transmit Excessive Collision Packet */
315 uint tncl
; /* Transmit Total Collision */
319 uint tdrp
; /* Transmit Drop Frame */
320 uint tjbr
; /* Transmit Jabber Frame */
321 uint tfcs
; /* Transmit FCS Error */
322 uint txcf
; /* Transmit Control Frame */
323 uint tovr
; /* Transmit Oversize Frame */
324 uint tund
; /* Transmit Undersize Frame */
325 uint tfrg
; /* Transmit Fragments Frame */
326 /* General Registers */
327 uint car1
; /* Carry Register One */
328 uint car2
; /* Carry Register Two */
329 uint cam1
; /* Carry Register One Mask */
330 uint cam2
; /* Carry Register Two Mask */
333 typedef struct tsec_hash_regs
335 uint iaddr0
; /* Individual Address Register 0 */
336 uint iaddr1
; /* Individual Address Register 1 */
337 uint iaddr2
; /* Individual Address Register 2 */
338 uint iaddr3
; /* Individual Address Register 3 */
339 uint iaddr4
; /* Individual Address Register 4 */
340 uint iaddr5
; /* Individual Address Register 5 */
341 uint iaddr6
; /* Individual Address Register 6 */
342 uint iaddr7
; /* Individual Address Register 7 */
344 uint gaddr0
; /* Group Address Register 0 */
345 uint gaddr1
; /* Group Address Register 1 */
346 uint gaddr2
; /* Group Address Register 2 */
347 uint gaddr3
; /* Group Address Register 3 */
348 uint gaddr4
; /* Group Address Register 4 */
349 uint gaddr5
; /* Group Address Register 5 */
350 uint gaddr6
; /* Group Address Register 6 */
351 uint gaddr7
; /* Group Address Register 7 */
357 /* General Control and Status Registers (0x2_n000) */
360 uint ievent
; /* Interrupt Event */
361 uint imask
; /* Interrupt Mask */
362 uint edis
; /* Error Disabled */
364 uint ecntrl
; /* Ethernet Control */
365 uint minflr
; /* Minimum Frame Length */
366 uint ptv
; /* Pause Time Value */
367 uint dmactrl
; /* DMA Control */
368 uint tbipa
; /* TBI PHY Address */
373 /* Transmit Control and Status Registers (0x2_n100) */
374 uint tctrl
; /* Transmit Control */
375 uint tstat
; /* Transmit Status */
377 uint tbdlen
; /* Tx BD Data Length */
379 uint ctbptr
; /* Current TxBD Pointer */
381 uint tbptr
; /* TxBD Pointer */
385 uint tbase
; /* TxBD Base Address */
387 uint ostbd
; /* Out of Sequence TxBD */
388 uint ostbdp
; /* Out of Sequence Tx Data Buffer Pointer */
391 /* Receive Control and Status Registers (0x2_n300) */
392 uint rctrl
; /* Receive Control */
393 uint rstat
; /* Receive Status */
395 uint rbdlen
; /* RxBD Data Length */
398 uint crbptr
; /* Current Receive Buffer Pointer */
400 uint mrblr
; /* Maximum Receive Buffer Length */
402 uint rbptr
; /* RxBD Pointer */
406 uint rbase
; /* RxBD Base Address */
409 /* MAC Registers (0x2_n500) */
410 uint maccfg1
; /* MAC Configuration #1 */
411 uint maccfg2
; /* MAC Configuration #2 */
412 uint ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
413 uint hafdup
; /* Half-duplex */
414 uint maxfrm
; /* Maximum Frame */
420 uint miimcfg
; /* MII Management: Configuration */
421 uint miimcom
; /* MII Management: Command */
422 uint miimadd
; /* MII Management: Address */
423 uint miimcon
; /* MII Management: Control */
424 uint miimstat
; /* MII Management: Status */
425 uint miimind
; /* MII Management: Indicators */
429 uint ifstat
; /* Interface Status */
430 uint macstnaddr1
; /* Station Address, part 1 */
431 uint macstnaddr2
; /* Station Address, part 2 */
437 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
441 /* Hash Function Registers (0x2_n800) */
446 /* Pattern Registers (0x2_nb00) */
448 uint attr
; /* Default Attribute Register */
449 uint attreli
; /* Default Attribute Extract Length and Index */
451 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
455 #define TSEC_GIGABIT (1)
457 /* This flag currently only has
458 * meaning if we're using the eTSEC */
459 #define TSEC_REDUCED (1 << 1)
461 struct tsec_private
{
462 volatile tsec_t
*regs
;
463 volatile tsec_t
*phyregs
;
464 struct phy_info
*phyinfo
;
474 * struct phy_cmd: A command for reading or writing a PHY register
476 * mii_reg: The register to read or write
478 * mii_data: For writes, the value to put in the register.
479 * A value of -1 indicates this is a read.
481 * funct: A function pointer which is invoked for each command.
482 * For reads, this function will be passed the value read
483 * from the PHY, and process it.
484 * For writes, the result of this function will be written
485 * to the PHY register
490 uint (*funct
) (uint mii_reg
, struct tsec_private
* priv
);
493 /* struct phy_info: a structure which defines attributes for a PHY
495 * id will contain a number which represents the PHY. During
496 * startup, the driver will poll the PHY to find out what its
497 * UID--as defined by registers 2 and 3--is. The 32-bit result
498 * gotten from the PHY will be shifted right by "shift" bits to
499 * discard any bits which may change based on revision numbers
500 * unimportant to functionality
502 * The struct phy_cmd entries represent pointers to an arrays of
503 * commands which tell the driver what to do to the PHY.
509 /* Called to configure the PHY, and modify the controller
510 * based on the results */
511 struct phy_cmd
*config
;
513 /* Called when starting up the controller */
514 struct phy_cmd
*startup
;
516 /* Called when bringing down the controller */
517 struct phy_cmd
*shutdown
;
520 #endif /* __TSEC_H */