drivers/tsec.h

   1 /*
   2  *  tsec.h
   3  *
   4  *  Driver for the Motorola Triple Speed Ethernet Controller
   5  *
   6  *  This software may be used and distributed according to the
   7  *  terms of the GNU Public License, Version 2, incorporated
   8  *  herein by reference.
   9  *
  10  * Copyright 2004 Freescale Semiconductor.
  11  * (C) Copyright 2003, Motorola, Inc.
  12  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  13  * author Andy Fleming
  14  *
  15  */
  16
  17 #ifndef __TSEC_H
  18 #define __TSEC_H
  19
  20 #include <net.h>
  21 #include <config.h>
  22
  23 #ifndef CFG_TSEC1_OFFSET
  24     #define CFG_TSEC1_OFFSET    (0x24000)
  25 #endif
  26
  27 #define TSEC_SIZE       0x01000
  28
  29 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
  30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
  31     #define TSEC_BASE_ADDR      (CFG_IMMR + CFG_TSEC1_OFFSET)
  32 #elif defined(CONFIG_MPC83XX)
  33     #define TSEC_BASE_ADDR      (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
  34 #endif
  35
  36
  37 #define MAC_ADDR_LEN 6
  38
  39 /* #define TSEC_TIMEOUT         1000000 */
  40 #define TSEC_TIMEOUT 1000
  41 #define TOUT_LOOP       1000000
  42
  43 #define PHY_AUTONEGOTIATE_TIMEOUT       5000 /* in ms */
  44
  45 /* MAC register bits */
  46 #define MACCFG1_SOFT_RESET      0x80000000
  47 #define MACCFG1_RESET_RX_MC     0x00080000
  48 #define MACCFG1_RESET_TX_MC     0x00040000
  49 #define MACCFG1_RESET_RX_FUN    0x00020000
  50 #define MACCFG1_RESET_TX_FUN    0x00010000
  51 #define MACCFG1_LOOPBACK        0x00000100
  52 #define MACCFG1_RX_FLOW         0x00000020
  53 #define MACCFG1_TX_FLOW         0x00000010
  54 #define MACCFG1_SYNCD_RX_EN     0x00000008
  55 #define MACCFG1_RX_EN           0x00000004
  56 #define MACCFG1_SYNCD_TX_EN     0x00000002
  57 #define MACCFG1_TX_EN           0x00000001
  58
  59 #define MACCFG2_INIT_SETTINGS   0x00007205
  60 #define MACCFG2_FULL_DUPLEX     0x00000001
  61 #define MACCFG2_IF              0x00000300
  62 #define MACCFG2_GMII            0x00000200
  63 #define MACCFG2_MII             0x00000100
  64
  65 #define ECNTRL_INIT_SETTINGS    0x00001000
  66 #define ECNTRL_TBI_MODE         0x00000020
  67 #define ECNTRL_R100             0x00000008
  68
  69 #define miim_end -2
  70 #define miim_read -1
  71
  72 #define TBIPA_VALUE             0x1f
  73 #define MIIMCFG_INIT_VALUE      0x00000003
  74 #define MIIMCFG_RESET           0x80000000
  75
  76 #define MIIMIND_BUSY            0x00000001
  77 #define MIIMIND_NOTVALID        0x00000004
  78
  79 #define MIIM_CONTROL            0x00
  80 #define MIIM_CONTROL_RESET      0x00009140
  81 #define MIIM_CONTROL_INIT       0x00001140
  82 #define MIIM_CONTROL_RESTART    0x00001340
  83 #define MIIM_ANEN               0x00001000
  84
  85 #define MIIM_CR                 0x00
  86 #define MIIM_CR_RST             0x00008000
  87 #define MIIM_CR_INIT            0x00001000
  88
  89 #define MIIM_STATUS             0x1
  90 #define MIIM_STATUS_AN_DONE     0x00000020
  91 #define MIIM_STATUS_LINK        0x0004
  92 #define PHY_BMSR_AUTN_ABLE      0x0008
  93 #define PHY_BMSR_AUTN_COMP      0x0020
  94
  95 #define MIIM_PHYIR1             0x2
  96 #define MIIM_PHYIR2             0x3
  97
  98 #define MIIM_ANAR               0x4
  99 #define MIIM_ANAR_INIT          0x1e1
 100
 101 #define MIIM_TBI_ANLPBPA        0x5
 102 #define MIIM_TBI_ANLPBPA_HALF   0x00000040
 103 #define MIIM_TBI_ANLPBPA_FULL   0x00000020
 104
 105 #define MIIM_TBI_ANEX           0x6
 106 #define MIIM_TBI_ANEX_NP        0x00000004
 107 #define MIIM_TBI_ANEX_PRX       0x00000002
 108
 109 #define MIIM_GBIT_CONTROL       0x9
 110 #define MIIM_GBIT_CONTROL_INIT  0xe00
 111
 112 /* Cicada Auxiliary Control/Status Register */
 113 #define MIIM_CIS8201_AUX_CONSTAT        0x1c
 114 #define MIIM_CIS8201_AUXCONSTAT_INIT    0x0004
 115 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX  0x0020
 116 #define MIIM_CIS8201_AUXCONSTAT_SPEED   0x0018
 117 #define MIIM_CIS8201_AUXCONSTAT_GBIT    0x0010
 118 #define MIIM_CIS8201_AUXCONSTAT_100     0x0008
 119
 120 /* Cicada Extended Control Register 1 */
 121 #define MIIM_CIS8201_EXT_CON1           0x17
 122 #define MIIM_CIS8201_EXTCON1_INIT       0x0000
 123
 124 /* Cicada 8204 Extended PHY Control Register 1 */
 125 #define MIIM_CIS8204_EPHY_CON           0x17
 126 #define MIIM_CIS8204_EPHYCON_INIT       0x0006
 127 #define MIIM_CIS8204_EPHYCON_RGMII      0x1100
 128
 129 /* Cicada 8204 Serial LED Control Register */
 130 #define MIIM_CIS8204_SLED_CON           0x1b
 131 #define MIIM_CIS8204_SLEDCON_INIT       0x1115
 132
 133 #define MIIM_GBIT_CON           0x09
 134 #define MIIM_GBIT_CON_ADVERT    0x0e00
 135
 136 /* Entry for Vitesse VSC8244 regs starts here */
 137 /* Vitesse VSC8244 Auxiliary Control/Status Register */
 138 #define MIIM_VSC8244_AUX_CONSTAT        0x1c
 139 #define MIIM_VSC8244_AUXCONSTAT_INIT    0x0000
 140 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX  0x0020
 141 #define MIIM_VSC8244_AUXCONSTAT_SPEED   0x0018
 142 #define MIIM_VSC8244_AUXCONSTAT_GBIT    0x0010
 143 #define MIIM_VSC8244_AUXCONSTAT_100     0x0008
 144 #define MIIM_CONTROL_INIT_LOOPBACK      0x4000
 145
 146 /* Vitesse VSC8244 Extended PHY Control Register 1 */
 147 #define MIIM_VSC8244_EPHY_CON           0x17
 148 #define MIIM_VSC8244_EPHYCON_INIT       0x0006
 149
 150 /* Vitesse VSC8244 Serial LED Control Register */
 151 #define MIIM_VSC8244_LED_CON            0x1b
 152 #define MIIM_VSC8244_LEDCON_INIT        0xF011
 153
 154 /* 88E1011 PHY Status Register */
 155 #define MIIM_88E1011_PHY_STATUS         0x11
 156 #define MIIM_88E1011_PHYSTAT_SPEED      0xc000
 157 #define MIIM_88E1011_PHYSTAT_GBIT       0x8000
 158 #define MIIM_88E1011_PHYSTAT_100        0x4000
 159 #define MIIM_88E1011_PHYSTAT_DUPLEX     0x2000
 160 #define MIIM_88E1011_PHYSTAT_SPDDONE    0x0800
 161 #define MIIM_88E1011_PHYSTAT_LINK       0x0400
 162
 163 /* DM9161 Control register values */
 164 #define MIIM_DM9161_CR_STOP     0x0400
 165 #define MIIM_DM9161_CR_RSTAN    0x1200
 166
 167 #define MIIM_DM9161_SCR         0x10
 168 #define MIIM_DM9161_SCR_INIT    0x0610
 169
 170 /* DM9161 Specified Configuration and Status Register */
 171 #define MIIM_DM9161_SCSR        0x11
 172 #define MIIM_DM9161_SCSR_100F   0x8000
 173 #define MIIM_DM9161_SCSR_100H   0x4000
 174 #define MIIM_DM9161_SCSR_10F    0x2000
 175 #define MIIM_DM9161_SCSR_10H    0x1000
 176
 177 /* DM9161 10BT Configuration/Status */
 178 #define MIIM_DM9161_10BTCSR     0x12
 179 #define MIIM_DM9161_10BTCSR_INIT        0x7800
 180
 181 /* LXT971 Status 2 registers */
 182 #define MIIM_LXT971_SR2              0x11  /* Status Register 2  */
 183 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
 184 #define MIIM_LXT971_SR2_10HDX      0x0000  /*  10 Mbit half duplex selected */
 185 #define MIIM_LXT971_SR2_10FDX      0x0200  /*  10 Mbit full duplex selected */
 186 #define MIIM_LXT971_SR2_100HDX     0x4000  /* 100 Mbit half duplex selected */
 187 #define MIIM_LXT971_SR2_100FDX     0x4200  /* 100 Mbit full duplex selected */
 188
 189 /* DP83865 Control register values */
 190 #define MIIM_DP83865_CR_INIT    0x9200
 191
 192 /* DP83865 Link and Auto-Neg Status Register */
 193 #define MIIM_DP83865_LANR       0x11
 194 #define MIIM_DP83865_SPD_MASK   0x0018
 195 #define MIIM_DP83865_SPD_1000   0x0010
 196 #define MIIM_DP83865_SPD_100    0x0008
 197 #define MIIM_DP83865_DPX_FULL   0x0002
 198
 199 #define MIIM_READ_COMMAND       0x00000001
 200
 201 #define MRBLR_INIT_SETTINGS     PKTSIZE_ALIGN
 202
 203 #define MINFLR_INIT_SETTINGS    0x00000040
 204
 205 #define DMACTRL_INIT_SETTINGS   0x000000c3
 206 #define DMACTRL_GRS             0x00000010
 207 #define DMACTRL_GTS             0x00000008
 208
 209 #define TSTAT_CLEAR_THALT       0x80000000
 210 #define RSTAT_CLEAR_RHALT       0x00800000
 211
 212
 213 #define IEVENT_INIT_CLEAR       0xffffffff
 214 #define IEVENT_BABR             0x80000000
 215 #define IEVENT_RXC              0x40000000
 216 #define IEVENT_BSY              0x20000000
 217 #define IEVENT_EBERR            0x10000000
 218 #define IEVENT_MSRO             0x04000000
 219 #define IEVENT_GTSC             0x02000000
 220 #define IEVENT_BABT             0x01000000
 221 #define IEVENT_TXC              0x00800000
 222 #define IEVENT_TXE              0x00400000
 223 #define IEVENT_TXB              0x00200000
 224 #define IEVENT_TXF              0x00100000
 225 #define IEVENT_IE               0x00080000
 226 #define IEVENT_LC               0x00040000
 227 #define IEVENT_CRL              0x00020000
 228 #define IEVENT_XFUN             0x00010000
 229 #define IEVENT_RXB0             0x00008000
 230 #define IEVENT_GRSC             0x00000100
 231 #define IEVENT_RXF0             0x00000080
 232
 233 #define IMASK_INIT_CLEAR        0x00000000
 234 #define IMASK_TXEEN             0x00400000
 235 #define IMASK_TXBEN             0x00200000
 236 #define IMASK_TXFEN             0x00100000
 237 #define IMASK_RXFEN0            0x00000080
 238
 239
 240 /* Default Attribute fields */
 241 #define ATTR_INIT_SETTINGS     0x000000c0
 242 #define ATTRELI_INIT_SETTINGS  0x00000000
 243
 244
 245 /* TxBD status field bits */
 246 #define TXBD_READY              0x8000
 247 #define TXBD_PADCRC             0x4000
 248 #define TXBD_WRAP               0x2000
 249 #define TXBD_INTERRUPT          0x1000
 250 #define TXBD_LAST               0x0800
 251 #define TXBD_CRC                0x0400
 252 #define TXBD_DEF                0x0200
 253 #define TXBD_HUGEFRAME          0x0080
 254 #define TXBD_LATECOLLISION      0x0080
 255 #define TXBD_RETRYLIMIT         0x0040
 256 #define TXBD_RETRYCOUNTMASK     0x003c
 257 #define TXBD_UNDERRUN           0x0002
 258 #define TXBD_STATS              0x03ff
 259
 260 /* RxBD status field bits */
 261 #define RXBD_EMPTY              0x8000
 262 #define RXBD_RO1                0x4000
 263 #define RXBD_WRAP               0x2000
 264 #define RXBD_INTERRUPT          0x1000
 265 #define RXBD_LAST               0x0800
 266 #define RXBD_FIRST              0x0400
 267 #define RXBD_MISS               0x0100
 268 #define RXBD_BROADCAST          0x0080
 269 #define RXBD_MULTICAST          0x0040
 270 #define RXBD_LARGE              0x0020
 271 #define RXBD_NONOCTET           0x0010
 272 #define RXBD_SHORT              0x0008
 273 #define RXBD_CRCERR             0x0004
 274 #define RXBD_OVERRUN            0x0002
 275 #define RXBD_TRUNCATED          0x0001
 276 #define RXBD_STATS              0x003f
 277
 278 typedef struct txbd8
 279 {
 280         ushort       status;         /* Status Fields */
 281         ushort       length;         /* Buffer length */
 282         uint         bufPtr;         /* Buffer Pointer */
 283 } txbd8_t;
 284
 285 typedef struct rxbd8
 286 {
 287         ushort       status;         /* Status Fields */
 288         ushort       length;         /* Buffer Length */
 289         uint         bufPtr;         /* Buffer Pointer */
 290 } rxbd8_t;
 291
 292 typedef struct rmon_mib
 293 {
 294         /* Transmit and Receive Counters */
 295         uint    tr64;           /* Transmit and Receive 64-byte Frame Counter */
 296         uint    tr127;          /* Transmit and Receive 65-127 byte Frame Counter */
 297         uint    tr255;          /* Transmit and Receive 128-255 byte Frame Counter */
 298         uint    tr511;          /* Transmit and Receive 256-511 byte Frame Counter */
 299         uint    tr1k;           /* Transmit and Receive 512-1023 byte Frame Counter */
 300         uint    trmax;          /* Transmit and Receive 1024-1518 byte Frame Counter */
 301         uint    trmgv;          /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
 302         /* Receive Counters */
 303         uint    rbyt;           /* Receive Byte Counter */
 304         uint    rpkt;           /* Receive Packet Counter */
 305         uint    rfcs;           /* Receive FCS Error Counter */
 306         uint    rmca;           /* Receive Multicast Packet (Counter) */
 307         uint    rbca;           /* Receive Broadcast Packet */
 308         uint    rxcf;           /* Receive Control Frame Packet */
 309         uint    rxpf;           /* Receive Pause Frame Packet */
 310         uint    rxuo;           /* Receive Unknown OP Code */
 311         uint    raln;           /* Receive Alignment Error */
 312         uint    rflr;           /* Receive Frame Length Error */
 313         uint    rcde;           /* Receive Code Error */
 314         uint    rcse;           /* Receive Carrier Sense Error */
 315         uint    rund;           /* Receive Undersize Packet */
 316         uint    rovr;           /* Receive Oversize Packet */
 317         uint    rfrg;           /* Receive Fragments */
 318         uint    rjbr;           /* Receive Jabber */
 319         uint    rdrp;           /* Receive Drop */
 320         /* Transmit Counters */
 321         uint    tbyt;           /* Transmit Byte Counter */
 322         uint    tpkt;           /* Transmit Packet */
 323         uint    tmca;           /* Transmit Multicast Packet */
 324         uint    tbca;           /* Transmit Broadcast Packet */
 325         uint    txpf;           /* Transmit Pause Control Frame */
 326         uint    tdfr;           /* Transmit Deferral Packet */
 327         uint    tedf;           /* Transmit Excessive Deferral Packet */
 328         uint    tscl;           /* Transmit Single Collision Packet */
 329         /* (0x2_n700) */
 330         uint    tmcl;           /* Transmit Multiple Collision Packet */
 331         uint    tlcl;           /* Transmit Late Collision Packet */
 332         uint    txcl;           /* Transmit Excessive Collision Packet */
 333         uint    tncl;           /* Transmit Total Collision */
 334
 335         uint    res2;
 336
 337         uint    tdrp;           /* Transmit Drop Frame */
 338         uint    tjbr;           /* Transmit Jabber Frame */
 339         uint    tfcs;           /* Transmit FCS Error */
 340         uint    txcf;           /* Transmit Control Frame */
 341         uint    tovr;           /* Transmit Oversize Frame */
 342         uint    tund;           /* Transmit Undersize Frame */
 343         uint    tfrg;           /* Transmit Fragments Frame */
 344         /* General Registers */
 345         uint    car1;           /* Carry Register One */
 346         uint    car2;           /* Carry Register Two */
 347         uint    cam1;           /* Carry Register One Mask */
 348         uint    cam2;           /* Carry Register Two Mask */
 349 } rmon_mib_t;
 350
 351 typedef struct tsec_hash_regs
 352 {
 353         uint    iaddr0;         /* Individual Address Register 0 */
 354         uint    iaddr1;         /* Individual Address Register 1 */
 355         uint    iaddr2;         /* Individual Address Register 2 */
 356         uint    iaddr3;         /* Individual Address Register 3 */
 357         uint    iaddr4;         /* Individual Address Register 4 */
 358         uint    iaddr5;         /* Individual Address Register 5 */
 359         uint    iaddr6;         /* Individual Address Register 6 */
 360         uint    iaddr7;         /* Individual Address Register 7 */
 361         uint    res1[24];
 362         uint    gaddr0;         /* Group Address Register 0 */
 363         uint    gaddr1;         /* Group Address Register 1 */
 364         uint    gaddr2;         /* Group Address Register 2 */
 365         uint    gaddr3;         /* Group Address Register 3 */
 366         uint    gaddr4;         /* Group Address Register 4 */
 367         uint    gaddr5;         /* Group Address Register 5 */
 368         uint    gaddr6;         /* Group Address Register 6 */
 369         uint    gaddr7;         /* Group Address Register 7 */
 370         uint    res2[24];
 371 } tsec_hash_t;
 372
 373 typedef struct tsec
 374 {
 375         /* General Control and Status Registers (0x2_n000) */
 376         uint    res000[4];
 377
 378         uint    ievent;         /* Interrupt Event */
 379         uint    imask;          /* Interrupt Mask */
 380         uint    edis;           /* Error Disabled */
 381         uint    res01c;
 382         uint    ecntrl;         /* Ethernet Control */
 383         uint    minflr;         /* Minimum Frame Length */
 384         uint    ptv;            /* Pause Time Value */
 385         uint    dmactrl;        /* DMA Control */
 386         uint    tbipa;          /* TBI PHY Address */
 387
 388         uint    res034[3];
 389         uint    res040[48];
 390
 391         /* Transmit Control and Status Registers (0x2_n100) */
 392         uint    tctrl;          /* Transmit Control */
 393         uint    tstat;          /* Transmit Status */
 394         uint    res108;
 395         uint    tbdlen;         /* Tx BD Data Length */
 396         uint    res110[5];
 397         uint    ctbptr;         /* Current TxBD Pointer */
 398         uint    res128[23];
 399         uint    tbptr;          /* TxBD Pointer */
 400         uint    res188[30];
 401         /* (0x2_n200) */
 402         uint        res200;
 403         uint    tbase;          /* TxBD Base Address */
 404         uint    res208[42];
 405         uint    ostbd;          /* Out of Sequence TxBD */
 406         uint    ostbdp;         /* Out of Sequence Tx Data Buffer Pointer */
 407         uint        res2b8[18];
 408
 409         /* Receive Control and Status Registers (0x2_n300) */
 410         uint    rctrl;          /* Receive Control */
 411         uint    rstat;          /* Receive Status */
 412         uint    res308;
 413         uint    rbdlen;         /* RxBD Data Length */
 414         uint    res310[4];
 415         uint        res320;
 416         uint    crbptr;         /* Current Receive Buffer Pointer */
 417         uint    res328[6];
 418         uint    mrblr;          /* Maximum Receive Buffer Length */
 419         uint    res344[16];
 420         uint    rbptr;          /* RxBD Pointer */
 421         uint        res388[30];
 422         /* (0x2_n400) */
 423         uint        res400;
 424         uint    rbase;          /* RxBD Base Address */
 425         uint        res408[62];
 426
 427         /* MAC Registers (0x2_n500) */
 428         uint    maccfg1;        /* MAC Configuration #1 */
 429         uint    maccfg2;        /* MAC Configuration #2 */
 430         uint    ipgifg;         /* Inter Packet Gap/Inter Frame Gap */
 431         uint    hafdup;         /* Half-duplex */
 432         uint    maxfrm;         /* Maximum Frame */
 433         uint    res514;
 434         uint    res518;
 435
 436         uint    res51c;
 437
 438         uint    miimcfg;        /* MII Management: Configuration */
 439         uint    miimcom;        /* MII Management: Command */
 440         uint    miimadd;        /* MII Management: Address */
 441         uint    miimcon;        /* MII Management: Control */
 442         uint    miimstat;       /* MII Management: Status */
 443         uint    miimind;        /* MII Management: Indicators */
 444
 445         uint    res538;
 446
 447         uint    ifstat;         /* Interface Status */
 448         uint    macstnaddr1;    /* Station Address, part 1 */
 449         uint    macstnaddr2;    /* Station Address, part 2 */
 450         uint    res548[46];
 451
 452         /* (0x2_n600) */
 453         uint    res600[32];
 454
 455         /* RMON MIB Registers (0x2_n680-0x2_n73c) */
 456         rmon_mib_t      rmon;
 457         uint    res740[48];
 458
 459         /* Hash Function Registers (0x2_n800) */
 460         tsec_hash_t     hash;
 461
 462         uint        res900[128];
 463
 464         /* Pattern Registers (0x2_nb00) */
 465         uint        resb00[62];
 466         uint        attr;          /* Default Attribute Register */
 467         uint        attreli;       /* Default Attribute Extract Length and Index */
 468
 469         /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
 470         uint    resc00[256];
 471 } tsec_t;
 472
 473 #define TSEC_GIGABIT (1)
 474
 475 /* This flag currently only has
 476  * meaning if we're using the eTSEC */
 477 #define TSEC_REDUCED (1 << 1)
 478
 479 struct tsec_private {
 480         volatile tsec_t *regs;
 481         volatile tsec_t *phyregs;
 482         struct phy_info *phyinfo;
 483         uint phyaddr;
 484         u32 flags;
 485         uint link;
 486         uint duplexity;
 487         uint speed;
 488 };
 489
 490
 491 /*
 492  * struct phy_cmd:  A command for reading or writing a PHY register
 493  *
 494  * mii_reg:  The register to read or write
 495  *
 496  * mii_data:  For writes, the value to put in the register.
 497  *      A value of -1 indicates this is a read.
 498  *
 499  * funct: A function pointer which is invoked for each command.
 500  *      For reads, this function will be passed the value read
 501  *      from the PHY, and process it.
 502  *      For writes, the result of this function will be written
 503  *      to the PHY register
 504  */
 505 struct phy_cmd {
 506     uint mii_reg;
 507     uint mii_data;
 508     uint (*funct) (uint mii_reg, struct tsec_private* priv);
 509 };
 510
 511 /* struct phy_info: a structure which defines attributes for a PHY
 512  *
 513  * id will contain a number which represents the PHY.  During
 514  * startup, the driver will poll the PHY to find out what its
 515  * UID--as defined by registers 2 and 3--is.  The 32-bit result
 516  * gotten from the PHY will be shifted right by "shift" bits to
 517  * discard any bits which may change based on revision numbers
 518  * unimportant to functionality
 519  *
 520  * The struct phy_cmd entries represent pointers to an arrays of
 521  * commands which tell the driver what to do to the PHY.
 522  */
 523 struct phy_info {
 524     uint id;
 525     char *name;
 526     uint shift;
 527     /* Called to configure the PHY, and modify the controller
 528      * based on the results */
 529     struct phy_cmd *config;
 530
 531     /* Called when starting up the controller */
 532     struct phy_cmd *startup;
 533
 534     /* Called when bringing down the controller */
 535     struct phy_cmd *shutdown;
 536 };
 537
 538 #endif /* __TSEC_H */