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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/tsec.h
4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
27 #define TSEC_SIZE 0x01000
29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30 #if defined(CONFIG_MPC85xx)
31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32 #elif defined(CONFIG_MPC83XX)
33 #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
37 #define MAC_ADDR_LEN 6
39 /* #define TSEC_TIMEOUT 1000000 */
40 #define TSEC_TIMEOUT 1000
41 #define TOUT_LOOP 1000000
43 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
45 /* MAC register bits */
46 #define MACCFG1_SOFT_RESET 0x80000000
47 #define MACCFG1_RESET_RX_MC 0x00080000
48 #define MACCFG1_RESET_TX_MC 0x00040000
49 #define MACCFG1_RESET_RX_FUN 0x00020000
50 #define MACCFG1_RESET_TX_FUN 0x00010000
51 #define MACCFG1_LOOPBACK 0x00000100
52 #define MACCFG1_RX_FLOW 0x00000020
53 #define MACCFG1_TX_FLOW 0x00000010
54 #define MACCFG1_SYNCD_RX_EN 0x00000008
55 #define MACCFG1_RX_EN 0x00000004
56 #define MACCFG1_SYNCD_TX_EN 0x00000002
57 #define MACCFG1_TX_EN 0x00000001
59 #define MACCFG2_INIT_SETTINGS 0x00007205
60 #define MACCFG2_FULL_DUPLEX 0x00000001
61 #define MACCFG2_IF 0x00000300
62 #define MACCFG2_GMII 0x00000200
63 #define MACCFG2_MII 0x00000100
65 #define ECNTRL_INIT_SETTINGS 0x00001000
66 #define ECNTRL_TBI_MODE 0x00000020
67 #define ECNTRL_R100 0x00000008
72 #define TBIPA_VALUE 0x1f
73 #define MIIMCFG_INIT_VALUE 0x00000003
74 #define MIIMCFG_RESET 0x80000000
76 #define MIIMIND_BUSY 0x00000001
77 #define MIIMIND_NOTVALID 0x00000004
79 #define MIIM_CONTROL 0x00
80 #define MIIM_CONTROL_RESET 0x00009140
81 #define MIIM_CONTROL_INIT 0x00001140
82 #define MIIM_CONTROL_RESTART 0x00001340
83 #define MIIM_ANEN 0x00001000
86 #define MIIM_CR_RST 0x00008000
87 #define MIIM_CR_INIT 0x00001000
89 #define MIIM_STATUS 0x1
90 #define MIIM_STATUS_AN_DONE 0x00000020
91 #define MIIM_STATUS_LINK 0x0004
92 #define PHY_BMSR_AUTN_ABLE 0x0008
93 #define PHY_BMSR_AUTN_COMP 0x0020
95 #define MIIM_PHYIR1 0x2
96 #define MIIM_PHYIR2 0x3
99 #define MIIM_ANAR_INIT 0x1e1
101 #define MIIM_TBI_ANLPBPA 0x5
102 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
103 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
105 #define MIIM_TBI_ANEX 0x6
106 #define MIIM_TBI_ANEX_NP 0x00000004
107 #define MIIM_TBI_ANEX_PRX 0x00000002
109 #define MIIM_GBIT_CONTROL 0x9
110 #define MIIM_GBIT_CONTROL_INIT 0xe00
112 /* Cicada Auxiliary Control/Status Register */
113 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
114 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
115 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
116 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
117 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
118 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
120 /* Cicada Extended Control Register 1 */
121 #define MIIM_CIS8201_EXT_CON1 0x17
122 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
124 /* Cicada 8204 Extended PHY Control Register 1 */
125 #define MIIM_CIS8204_EPHY_CON 0x17
126 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
127 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
129 /* Cicada 8204 Serial LED Control Register */
130 #define MIIM_CIS8204_SLED_CON 0x1b
131 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
133 #define MIIM_GBIT_CON 0x09
134 #define MIIM_GBIT_CON_ADVERT 0x0e00
136 /* 88E1011 PHY Status Register */
137 #define MIIM_88E1011_PHY_STATUS 0x11
138 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
139 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
140 #define MIIM_88E1011_PHYSTAT_100 0x4000
141 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
142 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
143 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
145 /* DM9161 Control register values */
146 #define MIIM_DM9161_CR_STOP 0x0400
147 #define MIIM_DM9161_CR_RSTAN 0x1200
149 #define MIIM_DM9161_SCR 0x10
150 #define MIIM_DM9161_SCR_INIT 0x0610
152 /* DM9161 Specified Configuration and Status Register */
153 #define MIIM_DM9161_SCSR 0x11
154 #define MIIM_DM9161_SCSR_100F 0x8000
155 #define MIIM_DM9161_SCSR_100H 0x4000
156 #define MIIM_DM9161_SCSR_10F 0x2000
157 #define MIIM_DM9161_SCSR_10H 0x1000
159 /* DM9161 10BT Configuration/Status */
160 #define MIIM_DM9161_10BTCSR 0x12
161 #define MIIM_DM9161_10BTCSR_INIT 0x7800
163 /* LXT971 Status 2 registers */
164 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
165 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
166 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
167 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
168 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
169 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
171 #define MIIM_READ_COMMAND 0x00000001
173 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
175 #define MINFLR_INIT_SETTINGS 0x00000040
177 #define DMACTRL_INIT_SETTINGS 0x000000c3
178 #define DMACTRL_GRS 0x00000010
179 #define DMACTRL_GTS 0x00000008
181 #define TSTAT_CLEAR_THALT 0x80000000
182 #define RSTAT_CLEAR_RHALT 0x00800000
185 #define IEVENT_INIT_CLEAR 0xffffffff
186 #define IEVENT_BABR 0x80000000
187 #define IEVENT_RXC 0x40000000
188 #define IEVENT_BSY 0x20000000
189 #define IEVENT_EBERR 0x10000000
190 #define IEVENT_MSRO 0x04000000
191 #define IEVENT_GTSC 0x02000000
192 #define IEVENT_BABT 0x01000000
193 #define IEVENT_TXC 0x00800000
194 #define IEVENT_TXE 0x00400000
195 #define IEVENT_TXB 0x00200000
196 #define IEVENT_TXF 0x00100000
197 #define IEVENT_IE 0x00080000
198 #define IEVENT_LC 0x00040000
199 #define IEVENT_CRL 0x00020000
200 #define IEVENT_XFUN 0x00010000
201 #define IEVENT_RXB0 0x00008000
202 #define IEVENT_GRSC 0x00000100
203 #define IEVENT_RXF0 0x00000080
205 #define IMASK_INIT_CLEAR 0x00000000
206 #define IMASK_TXEEN 0x00400000
207 #define IMASK_TXBEN 0x00200000
208 #define IMASK_TXFEN 0x00100000
209 #define IMASK_RXFEN0 0x00000080
212 /* Default Attribute fields */
213 #define ATTR_INIT_SETTINGS 0x000000c0
214 #define ATTRELI_INIT_SETTINGS 0x00000000
217 /* TxBD status field bits */
218 #define TXBD_READY 0x8000
219 #define TXBD_PADCRC 0x4000
220 #define TXBD_WRAP 0x2000
221 #define TXBD_INTERRUPT 0x1000
222 #define TXBD_LAST 0x0800
223 #define TXBD_CRC 0x0400
224 #define TXBD_DEF 0x0200
225 #define TXBD_HUGEFRAME 0x0080
226 #define TXBD_LATECOLLISION 0x0080
227 #define TXBD_RETRYLIMIT 0x0040
228 #define TXBD_RETRYCOUNTMASK 0x003c
229 #define TXBD_UNDERRUN 0x0002
230 #define TXBD_STATS 0x03ff
232 /* RxBD status field bits */
233 #define RXBD_EMPTY 0x8000
234 #define RXBD_RO1 0x4000
235 #define RXBD_WRAP 0x2000
236 #define RXBD_INTERRUPT 0x1000
237 #define RXBD_LAST 0x0800
238 #define RXBD_FIRST 0x0400
239 #define RXBD_MISS 0x0100
240 #define RXBD_BROADCAST 0x0080
241 #define RXBD_MULTICAST 0x0040
242 #define RXBD_LARGE 0x0020
243 #define RXBD_NONOCTET 0x0010
244 #define RXBD_SHORT 0x0008
245 #define RXBD_CRCERR 0x0004
246 #define RXBD_OVERRUN 0x0002
247 #define RXBD_TRUNCATED 0x0001
248 #define RXBD_STATS 0x003f
252 ushort status
; /* Status Fields */
253 ushort length
; /* Buffer length */
254 uint bufPtr
; /* Buffer Pointer */
259 ushort status
; /* Status Fields */
260 ushort length
; /* Buffer Length */
261 uint bufPtr
; /* Buffer Pointer */
264 typedef struct rmon_mib
266 /* Transmit and Receive Counters */
267 uint tr64
; /* Transmit and Receive 64-byte Frame Counter */
268 uint tr127
; /* Transmit and Receive 65-127 byte Frame Counter */
269 uint tr255
; /* Transmit and Receive 128-255 byte Frame Counter */
270 uint tr511
; /* Transmit and Receive 256-511 byte Frame Counter */
271 uint tr1k
; /* Transmit and Receive 512-1023 byte Frame Counter */
272 uint trmax
; /* Transmit and Receive 1024-1518 byte Frame Counter */
273 uint trmgv
; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
274 /* Receive Counters */
275 uint rbyt
; /* Receive Byte Counter */
276 uint rpkt
; /* Receive Packet Counter */
277 uint rfcs
; /* Receive FCS Error Counter */
278 uint rmca
; /* Receive Multicast Packet (Counter) */
279 uint rbca
; /* Receive Broadcast Packet */
280 uint rxcf
; /* Receive Control Frame Packet */
281 uint rxpf
; /* Receive Pause Frame Packet */
282 uint rxuo
; /* Receive Unknown OP Code */
283 uint raln
; /* Receive Alignment Error */
284 uint rflr
; /* Receive Frame Length Error */
285 uint rcde
; /* Receive Code Error */
286 uint rcse
; /* Receive Carrier Sense Error */
287 uint rund
; /* Receive Undersize Packet */
288 uint rovr
; /* Receive Oversize Packet */
289 uint rfrg
; /* Receive Fragments */
290 uint rjbr
; /* Receive Jabber */
291 uint rdrp
; /* Receive Drop */
292 /* Transmit Counters */
293 uint tbyt
; /* Transmit Byte Counter */
294 uint tpkt
; /* Transmit Packet */
295 uint tmca
; /* Transmit Multicast Packet */
296 uint tbca
; /* Transmit Broadcast Packet */
297 uint txpf
; /* Transmit Pause Control Frame */
298 uint tdfr
; /* Transmit Deferral Packet */
299 uint tedf
; /* Transmit Excessive Deferral Packet */
300 uint tscl
; /* Transmit Single Collision Packet */
302 uint tmcl
; /* Transmit Multiple Collision Packet */
303 uint tlcl
; /* Transmit Late Collision Packet */
304 uint txcl
; /* Transmit Excessive Collision Packet */
305 uint tncl
; /* Transmit Total Collision */
309 uint tdrp
; /* Transmit Drop Frame */
310 uint tjbr
; /* Transmit Jabber Frame */
311 uint tfcs
; /* Transmit FCS Error */
312 uint txcf
; /* Transmit Control Frame */
313 uint tovr
; /* Transmit Oversize Frame */
314 uint tund
; /* Transmit Undersize Frame */
315 uint tfrg
; /* Transmit Fragments Frame */
316 /* General Registers */
317 uint car1
; /* Carry Register One */
318 uint car2
; /* Carry Register Two */
319 uint cam1
; /* Carry Register One Mask */
320 uint cam2
; /* Carry Register Two Mask */
323 typedef struct tsec_hash_regs
325 uint iaddr0
; /* Individual Address Register 0 */
326 uint iaddr1
; /* Individual Address Register 1 */
327 uint iaddr2
; /* Individual Address Register 2 */
328 uint iaddr3
; /* Individual Address Register 3 */
329 uint iaddr4
; /* Individual Address Register 4 */
330 uint iaddr5
; /* Individual Address Register 5 */
331 uint iaddr6
; /* Individual Address Register 6 */
332 uint iaddr7
; /* Individual Address Register 7 */
334 uint gaddr0
; /* Group Address Register 0 */
335 uint gaddr1
; /* Group Address Register 1 */
336 uint gaddr2
; /* Group Address Register 2 */
337 uint gaddr3
; /* Group Address Register 3 */
338 uint gaddr4
; /* Group Address Register 4 */
339 uint gaddr5
; /* Group Address Register 5 */
340 uint gaddr6
; /* Group Address Register 6 */
341 uint gaddr7
; /* Group Address Register 7 */
347 /* General Control and Status Registers (0x2_n000) */
350 uint ievent
; /* Interrupt Event */
351 uint imask
; /* Interrupt Mask */
352 uint edis
; /* Error Disabled */
354 uint ecntrl
; /* Ethernet Control */
355 uint minflr
; /* Minimum Frame Length */
356 uint ptv
; /* Pause Time Value */
357 uint dmactrl
; /* DMA Control */
358 uint tbipa
; /* TBI PHY Address */
363 /* Transmit Control and Status Registers (0x2_n100) */
364 uint tctrl
; /* Transmit Control */
365 uint tstat
; /* Transmit Status */
367 uint tbdlen
; /* Tx BD Data Length */
369 uint ctbptr
; /* Current TxBD Pointer */
371 uint tbptr
; /* TxBD Pointer */
375 uint tbase
; /* TxBD Base Address */
377 uint ostbd
; /* Out of Sequence TxBD */
378 uint ostbdp
; /* Out of Sequence Tx Data Buffer Pointer */
381 /* Receive Control and Status Registers (0x2_n300) */
382 uint rctrl
; /* Receive Control */
383 uint rstat
; /* Receive Status */
385 uint rbdlen
; /* RxBD Data Length */
388 uint crbptr
; /* Current Receive Buffer Pointer */
390 uint mrblr
; /* Maximum Receive Buffer Length */
392 uint rbptr
; /* RxBD Pointer */
396 uint rbase
; /* RxBD Base Address */
399 /* MAC Registers (0x2_n500) */
400 uint maccfg1
; /* MAC Configuration #1 */
401 uint maccfg2
; /* MAC Configuration #2 */
402 uint ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
403 uint hafdup
; /* Half-duplex */
404 uint maxfrm
; /* Maximum Frame */
410 uint miimcfg
; /* MII Management: Configuration */
411 uint miimcom
; /* MII Management: Command */
412 uint miimadd
; /* MII Management: Address */
413 uint miimcon
; /* MII Management: Control */
414 uint miimstat
; /* MII Management: Status */
415 uint miimind
; /* MII Management: Indicators */
419 uint ifstat
; /* Interface Status */
420 uint macstnaddr1
; /* Station Address, part 1 */
421 uint macstnaddr2
; /* Station Address, part 2 */
427 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
431 /* Hash Function Registers (0x2_n800) */
436 /* Pattern Registers (0x2_nb00) */
438 uint attr
; /* Default Attribute Register */
439 uint attreli
; /* Default Attribute Extract Length and Index */
441 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
445 #define TSEC_GIGABIT (1)
447 /* This flag currently only has
448 * meaning if we're using the eTSEC */
449 #define TSEC_REDUCED (1 << 1)
451 struct tsec_private
{
452 volatile tsec_t
*regs
;
453 volatile tsec_t
*phyregs
;
454 struct phy_info
*phyinfo
;
464 * struct phy_cmd: A command for reading or writing a PHY register
466 * mii_reg: The register to read or write
468 * mii_data: For writes, the value to put in the register.
469 * A value of -1 indicates this is a read.
471 * funct: A function pointer which is invoked for each command.
472 * For reads, this function will be passed the value read
473 * from the PHY, and process it.
474 * For writes, the result of this function will be written
475 * to the PHY register
480 uint (*funct
) (uint mii_reg
, struct tsec_private
* priv
);
483 /* struct phy_info: a structure which defines attributes for a PHY
485 * id will contain a number which represents the PHY. During
486 * startup, the driver will poll the PHY to find out what its
487 * UID--as defined by registers 2 and 3--is. The 32-bit result
488 * gotten from the PHY will be shifted right by "shift" bits to
489 * discard any bits which may change based on revision numbers
490 * unimportant to functionality
492 * The struct phy_cmd entries represent pointers to an arrays of
493 * commands which tell the driver what to do to the PHY.
499 /* Called to configure the PHY, and modify the controller
500 * based on the results */
501 struct phy_cmd
*config
;
503 /* Called when starting up the controller */
504 struct phy_cmd
*startup
;
506 /* Called when bringing down the controller */
507 struct phy_cmd
*shutdown
;
510 #endif /* __TSEC_H */