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scsi: ufs: core: Fix an error handling path in ufshcd_read_desc_param()
[thirdparty/linux.git] / drivers / ufs / core / ufshcd.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Universal Flash Storage Host controller driver Core
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #include <linux/async.h>
13 #include <linux/devfreq.h>
14 #include <linux/nls.h>
15 #include <linux/of.h>
16 #include <linux/bitfield.h>
17 #include <linux/blk-pm.h>
18 #include <linux/blkdev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/sched/clock.h>
25 #include <scsi/scsi_cmnd.h>
26 #include <scsi/scsi_dbg.h>
27 #include <scsi/scsi_driver.h>
28 #include <scsi/scsi_eh.h>
29 #include "ufshcd-priv.h"
30 #include <ufs/ufs_quirks.h>
31 #include <ufs/unipro.h>
32 #include "ufs-sysfs.h"
33 #include "ufs-debugfs.h"
34 #include "ufs-fault-injection.h"
35 #include "ufs_bsg.h"
36 #include "ufshcd-crypto.h"
37 #include "ufshpb.h"
38 #include <asm/unaligned.h>
39
40 #define CREATE_TRACE_POINTS
41 #include <trace/events/ufs.h>
42
43 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
44 UTP_TASK_REQ_COMPL |\
45 UFSHCD_ERROR_MASK)
46
47 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK |\
49 MCQ_CQ_EVENT_STATUS)
50
51
52 /* UIC command timeout, unit: ms */
53 #define UIC_CMD_TIMEOUT 500
54
55 /* NOP OUT retries waiting for NOP IN response */
56 #define NOP_OUT_RETRIES 10
57 /* Timeout after 50 msecs if NOP OUT hangs without response */
58 #define NOP_OUT_TIMEOUT 50 /* msecs */
59
60 /* Query request retries */
61 #define QUERY_REQ_RETRIES 3
62 /* Query request timeout */
63 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
64
65 /* Advanced RPMB request timeout */
66 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */
67
68 /* Task management command timeout */
69 #define TM_CMD_TIMEOUT 100 /* msecs */
70
71 /* maximum number of retries for a general UIC command */
72 #define UFS_UIC_COMMAND_RETRIES 3
73
74 /* maximum number of link-startup retries */
75 #define DME_LINKSTARTUP_RETRIES 3
76
77 /* maximum number of reset retries before giving up */
78 #define MAX_HOST_RESET_RETRIES 5
79
80 /* Maximum number of error handler retries before giving up */
81 #define MAX_ERR_HANDLER_RETRIES 5
82
83 /* Expose the flag value from utp_upiu_query.value */
84 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
85
86 /* Interrupt aggregation default timeout, unit: 40us */
87 #define INT_AGGR_DEF_TO 0x02
88
89 /* default delay of autosuspend: 2000 ms */
90 #define RPM_AUTOSUSPEND_DELAY_MS 2000
91
92 /* Default delay of RPM device flush delayed work */
93 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
94
95 /* Default value of wait time before gating device ref clock */
96 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
97
98 /* Polling time to wait for fDeviceInit */
99 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
100
101 /* UFSHC 4.0 compliant HC support this mode, refer param_set_mcq_mode() */
102 static bool use_mcq_mode = true;
103
104 static bool is_mcq_supported(struct ufs_hba *hba)
105 {
106 return hba->mcq_sup && use_mcq_mode;
107 }
108
109 static int param_set_mcq_mode(const char *val, const struct kernel_param *kp)
110 {
111 int ret;
112
113 ret = param_set_bool(val, kp);
114 if (ret)
115 return ret;
116
117 return 0;
118 }
119
120 static const struct kernel_param_ops mcq_mode_ops = {
121 .set = param_set_mcq_mode,
122 .get = param_get_bool,
123 };
124
125 module_param_cb(use_mcq_mode, &mcq_mode_ops, &use_mcq_mode, 0644);
126 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
127
128 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
129 ({ \
130 int _ret; \
131 if (_on) \
132 _ret = ufshcd_enable_vreg(_dev, _vreg); \
133 else \
134 _ret = ufshcd_disable_vreg(_dev, _vreg); \
135 _ret; \
136 })
137
138 #define ufshcd_hex_dump(prefix_str, buf, len) do { \
139 size_t __len = (len); \
140 print_hex_dump(KERN_ERR, prefix_str, \
141 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
142 16, 4, buf, __len, false); \
143 } while (0)
144
145 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
146 const char *prefix)
147 {
148 u32 *regs;
149 size_t pos;
150
151 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
152 return -EINVAL;
153
154 regs = kzalloc(len, GFP_ATOMIC);
155 if (!regs)
156 return -ENOMEM;
157
158 for (pos = 0; pos < len; pos += 4) {
159 if (offset == 0 &&
160 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
161 pos <= REG_UIC_ERROR_CODE_DME)
162 continue;
163 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
164 }
165
166 ufshcd_hex_dump(prefix, regs, len);
167 kfree(regs);
168
169 return 0;
170 }
171 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
172
173 enum {
174 UFSHCD_MAX_CHANNEL = 0,
175 UFSHCD_MAX_ID = 1,
176 UFSHCD_NUM_RESERVED = 1,
177 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
178 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
179 };
180
181 static const char *const ufshcd_state_name[] = {
182 [UFSHCD_STATE_RESET] = "reset",
183 [UFSHCD_STATE_OPERATIONAL] = "operational",
184 [UFSHCD_STATE_ERROR] = "error",
185 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
186 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
187 };
188
189 /* UFSHCD error handling flags */
190 enum {
191 UFSHCD_EH_IN_PROGRESS = (1 << 0),
192 };
193
194 /* UFSHCD UIC layer error flags */
195 enum {
196 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
197 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
198 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
199 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
200 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
201 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
202 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
203 };
204
205 #define ufshcd_set_eh_in_progress(h) \
206 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
207 #define ufshcd_eh_in_progress(h) \
208 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
209 #define ufshcd_clear_eh_in_progress(h) \
210 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
211
212 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
213 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
214 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
215 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
216 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
217 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
218 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
219 /*
220 * For DeepSleep, the link is first put in hibern8 and then off.
221 * Leaving the link in hibern8 is not supported.
222 */
223 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
224 };
225
226 static inline enum ufs_dev_pwr_mode
227 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
228 {
229 return ufs_pm_lvl_states[lvl].dev_state;
230 }
231
232 static inline enum uic_link_state
233 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
234 {
235 return ufs_pm_lvl_states[lvl].link_state;
236 }
237
238 static inline enum ufs_pm_level
239 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
240 enum uic_link_state link_state)
241 {
242 enum ufs_pm_level lvl;
243
244 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
245 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
246 (ufs_pm_lvl_states[lvl].link_state == link_state))
247 return lvl;
248 }
249
250 /* if no match found, return the level 0 */
251 return UFS_PM_LVL_0;
252 }
253
254 static const struct ufs_dev_quirk ufs_fixups[] = {
255 /* UFS cards deviations table */
256 { .wmanufacturerid = UFS_VENDOR_MICRON,
257 .model = UFS_ANY_MODEL,
258 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
259 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ },
260 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
261 .model = UFS_ANY_MODEL,
262 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
263 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
264 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
265 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
266 .model = UFS_ANY_MODEL,
267 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
268 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
269 .model = "hB8aL1" /*H28U62301AMR*/,
270 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
271 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
272 .model = UFS_ANY_MODEL,
273 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
274 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
275 .model = "THGLF2G9C8KBADG",
276 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
277 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
278 .model = "THGLF2G9D8KBADG",
279 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
280 {}
281 };
282
283 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
284 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
285 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
286 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
287 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
288 static void ufshcd_hba_exit(struct ufs_hba *hba);
289 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
290 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
291 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
292 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
293 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
294 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
295 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
296 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
297 static irqreturn_t ufshcd_intr(int irq, void *__hba);
298 static int ufshcd_change_power_mode(struct ufs_hba *hba,
299 struct ufs_pa_layer_attr *pwr_mode);
300 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
301 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
302 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
303 struct ufs_vreg *vreg);
304 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
305 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
306 bool enable);
307 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
308 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
309
310 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
311 {
312 if (!hba->is_irq_enabled) {
313 enable_irq(hba->irq);
314 hba->is_irq_enabled = true;
315 }
316 }
317
318 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
319 {
320 if (hba->is_irq_enabled) {
321 disable_irq(hba->irq);
322 hba->is_irq_enabled = false;
323 }
324 }
325
326 static void ufshcd_configure_wb(struct ufs_hba *hba)
327 {
328 if (!ufshcd_is_wb_allowed(hba))
329 return;
330
331 ufshcd_wb_toggle(hba, true);
332
333 ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
334
335 if (ufshcd_is_wb_buf_flush_allowed(hba))
336 ufshcd_wb_toggle_buf_flush(hba, true);
337 }
338
339 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
340 {
341 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
342 scsi_unblock_requests(hba->host);
343 }
344
345 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
346 {
347 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
348 scsi_block_requests(hba->host);
349 }
350
351 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
352 enum ufs_trace_str_t str_t)
353 {
354 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
355 struct utp_upiu_header *header;
356
357 if (!trace_ufshcd_upiu_enabled())
358 return;
359
360 if (str_t == UFS_CMD_SEND)
361 header = &rq->header;
362 else
363 header = &hba->lrb[tag].ucd_rsp_ptr->header;
364
365 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
366 UFS_TSF_CDB);
367 }
368
369 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
370 enum ufs_trace_str_t str_t,
371 struct utp_upiu_req *rq_rsp)
372 {
373 if (!trace_ufshcd_upiu_enabled())
374 return;
375
376 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
377 &rq_rsp->qr, UFS_TSF_OSF);
378 }
379
380 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
381 enum ufs_trace_str_t str_t)
382 {
383 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
384
385 if (!trace_ufshcd_upiu_enabled())
386 return;
387
388 if (str_t == UFS_TM_SEND)
389 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
390 &descp->upiu_req.req_header,
391 &descp->upiu_req.input_param1,
392 UFS_TSF_TM_INPUT);
393 else
394 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
395 &descp->upiu_rsp.rsp_header,
396 &descp->upiu_rsp.output_param1,
397 UFS_TSF_TM_OUTPUT);
398 }
399
400 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
401 const struct uic_command *ucmd,
402 enum ufs_trace_str_t str_t)
403 {
404 u32 cmd;
405
406 if (!trace_ufshcd_uic_command_enabled())
407 return;
408
409 if (str_t == UFS_CMD_SEND)
410 cmd = ucmd->command;
411 else
412 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
413
414 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
415 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
416 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
417 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
418 }
419
420 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
421 enum ufs_trace_str_t str_t)
422 {
423 u64 lba = 0;
424 u8 opcode = 0, group_id = 0;
425 u32 intr, doorbell;
426 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
427 struct scsi_cmnd *cmd = lrbp->cmd;
428 struct request *rq = scsi_cmd_to_rq(cmd);
429 int transfer_len = -1;
430
431 if (!cmd)
432 return;
433
434 /* trace UPIU also */
435 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
436 if (!trace_ufshcd_command_enabled())
437 return;
438
439 opcode = cmd->cmnd[0];
440
441 if (opcode == READ_10 || opcode == WRITE_10) {
442 /*
443 * Currently we only fully trace read(10) and write(10) commands
444 */
445 transfer_len =
446 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
447 lba = scsi_get_lba(cmd);
448 if (opcode == WRITE_10)
449 group_id = lrbp->cmd->cmnd[6];
450 } else if (opcode == UNMAP) {
451 /*
452 * The number of Bytes to be unmapped beginning with the lba.
453 */
454 transfer_len = blk_rq_bytes(rq);
455 lba = scsi_get_lba(cmd);
456 }
457
458 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
459 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
460 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
461 doorbell, transfer_len, intr, lba, opcode, group_id);
462 }
463
464 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
465 {
466 struct ufs_clk_info *clki;
467 struct list_head *head = &hba->clk_list_head;
468
469 if (list_empty(head))
470 return;
471
472 list_for_each_entry(clki, head, list) {
473 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
474 clki->max_freq)
475 dev_err(hba->dev, "clk: %s, rate: %u\n",
476 clki->name, clki->curr_freq);
477 }
478 }
479
480 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
481 const char *err_name)
482 {
483 int i;
484 bool found = false;
485 const struct ufs_event_hist *e;
486
487 if (id >= UFS_EVT_CNT)
488 return;
489
490 e = &hba->ufs_stats.event[id];
491
492 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
493 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
494
495 if (e->tstamp[p] == 0)
496 continue;
497 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
498 e->val[p], div_u64(e->tstamp[p], 1000));
499 found = true;
500 }
501
502 if (!found)
503 dev_err(hba->dev, "No record of %s\n", err_name);
504 else
505 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
506 }
507
508 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
509 {
510 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
511
512 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
513 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
514 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
515 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
516 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
517 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
518 "auto_hibern8_err");
519 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
520 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
521 "link_startup_fail");
522 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
523 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
524 "suspend_fail");
525 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
526 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
527 "wlun suspend_fail");
528 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
529 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
530 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
531
532 ufshcd_vops_dbg_register_dump(hba);
533 }
534
535 static
536 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
537 {
538 const struct ufshcd_lrb *lrbp;
539 int prdt_length;
540 int tag;
541
542 for_each_set_bit(tag, &bitmap, hba->nutrs) {
543 lrbp = &hba->lrb[tag];
544
545 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
546 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
547 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
548 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
549 dev_err(hba->dev,
550 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
551 tag, (u64)lrbp->utrd_dma_addr);
552
553 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
554 sizeof(struct utp_transfer_req_desc));
555 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
556 (u64)lrbp->ucd_req_dma_addr);
557 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
558 sizeof(struct utp_upiu_req));
559 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
560 (u64)lrbp->ucd_rsp_dma_addr);
561 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
562 sizeof(struct utp_upiu_rsp));
563
564 prdt_length = le16_to_cpu(
565 lrbp->utr_descriptor_ptr->prd_table_length);
566 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
567 prdt_length /= ufshcd_sg_entry_size(hba);
568
569 dev_err(hba->dev,
570 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
571 tag, prdt_length,
572 (u64)lrbp->ucd_prdt_dma_addr);
573
574 if (pr_prdt)
575 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
576 ufshcd_sg_entry_size(hba) * prdt_length);
577 }
578 }
579
580 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
581 {
582 int tag;
583
584 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
585 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
586
587 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
588 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
589 }
590 }
591
592 static void ufshcd_print_host_state(struct ufs_hba *hba)
593 {
594 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
595
596 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
597 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
598 hba->outstanding_reqs, hba->outstanding_tasks);
599 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
600 hba->saved_err, hba->saved_uic_err);
601 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
602 hba->curr_dev_pwr_mode, hba->uic_link_state);
603 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
604 hba->pm_op_in_progress, hba->is_sys_suspended);
605 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
606 hba->auto_bkops_enabled, hba->host->host_self_blocked);
607 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
608 dev_err(hba->dev,
609 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
610 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
611 hba->ufs_stats.hibern8_exit_cnt);
612 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
613 div_u64(hba->ufs_stats.last_intr_ts, 1000),
614 hba->ufs_stats.last_intr_status);
615 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
616 hba->eh_flags, hba->req_abort_count);
617 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
618 hba->ufs_version, hba->capabilities, hba->caps);
619 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
620 hba->dev_quirks);
621 if (sdev_ufs)
622 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
623 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
624
625 ufshcd_print_clk_freqs(hba);
626 }
627
628 /**
629 * ufshcd_print_pwr_info - print power params as saved in hba
630 * power info
631 * @hba: per-adapter instance
632 */
633 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
634 {
635 static const char * const names[] = {
636 "INVALID MODE",
637 "FAST MODE",
638 "SLOW_MODE",
639 "INVALID MODE",
640 "FASTAUTO_MODE",
641 "SLOWAUTO_MODE",
642 "INVALID MODE",
643 };
644
645 /*
646 * Using dev_dbg to avoid messages during runtime PM to avoid
647 * never-ending cycles of messages written back to storage by user space
648 * causing runtime resume, causing more messages and so on.
649 */
650 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
651 __func__,
652 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
653 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
654 names[hba->pwr_info.pwr_rx],
655 names[hba->pwr_info.pwr_tx],
656 hba->pwr_info.hs_rate);
657 }
658
659 static void ufshcd_device_reset(struct ufs_hba *hba)
660 {
661 int err;
662
663 err = ufshcd_vops_device_reset(hba);
664
665 if (!err) {
666 ufshcd_set_ufs_dev_active(hba);
667 if (ufshcd_is_wb_allowed(hba)) {
668 hba->dev_info.wb_enabled = false;
669 hba->dev_info.wb_buf_flush_enabled = false;
670 }
671 }
672 if (err != -EOPNOTSUPP)
673 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
674 }
675
676 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
677 {
678 if (!us)
679 return;
680
681 if (us < 10)
682 udelay(us);
683 else
684 usleep_range(us, us + tolerance);
685 }
686 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
687
688 /**
689 * ufshcd_wait_for_register - wait for register value to change
690 * @hba: per-adapter interface
691 * @reg: mmio register offset
692 * @mask: mask to apply to the read register value
693 * @val: value to wait for
694 * @interval_us: polling interval in microseconds
695 * @timeout_ms: timeout in milliseconds
696 *
697 * Return:
698 * -ETIMEDOUT on error, zero on success.
699 */
700 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
701 u32 val, unsigned long interval_us,
702 unsigned long timeout_ms)
703 {
704 int err = 0;
705 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
706
707 /* ignore bits that we don't intend to wait on */
708 val = val & mask;
709
710 while ((ufshcd_readl(hba, reg) & mask) != val) {
711 usleep_range(interval_us, interval_us + 50);
712 if (time_after(jiffies, timeout)) {
713 if ((ufshcd_readl(hba, reg) & mask) != val)
714 err = -ETIMEDOUT;
715 break;
716 }
717 }
718
719 return err;
720 }
721
722 /**
723 * ufshcd_get_intr_mask - Get the interrupt bit mask
724 * @hba: Pointer to adapter instance
725 *
726 * Returns interrupt bit mask per version
727 */
728 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
729 {
730 if (hba->ufs_version == ufshci_version(1, 0))
731 return INTERRUPT_MASK_ALL_VER_10;
732 if (hba->ufs_version <= ufshci_version(2, 0))
733 return INTERRUPT_MASK_ALL_VER_11;
734
735 return INTERRUPT_MASK_ALL_VER_21;
736 }
737
738 /**
739 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
740 * @hba: Pointer to adapter instance
741 *
742 * Returns UFSHCI version supported by the controller
743 */
744 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
745 {
746 u32 ufshci_ver;
747
748 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
749 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
750 else
751 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
752
753 /*
754 * UFSHCI v1.x uses a different version scheme, in order
755 * to allow the use of comparisons with the ufshci_version
756 * function, we convert it to the same scheme as ufs 2.0+.
757 */
758 if (ufshci_ver & 0x00010000)
759 return ufshci_version(1, ufshci_ver & 0x00000100);
760
761 return ufshci_ver;
762 }
763
764 /**
765 * ufshcd_is_device_present - Check if any device connected to
766 * the host controller
767 * @hba: pointer to adapter instance
768 *
769 * Returns true if device present, false if no device detected
770 */
771 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
772 {
773 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
774 }
775
776 /**
777 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
778 * @lrbp: pointer to local command reference block
779 * @cqe: pointer to the completion queue entry
780 *
781 * This function is used to get the OCS field from UTRD
782 * Returns the OCS field in the UTRD
783 */
784 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
785 struct cq_entry *cqe)
786 {
787 if (cqe)
788 return le32_to_cpu(cqe->status) & MASK_OCS;
789
790 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
791 }
792
793 /**
794 * ufshcd_utrl_clear() - Clear requests from the controller request list.
795 * @hba: per adapter instance
796 * @mask: mask with one bit set for each request to be cleared
797 */
798 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
799 {
800 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
801 mask = ~mask;
802 /*
803 * From the UFSHCI specification: "UTP Transfer Request List CLear
804 * Register (UTRLCLR): This field is bit significant. Each bit
805 * corresponds to a slot in the UTP Transfer Request List, where bit 0
806 * corresponds to request slot 0. A bit in this field is set to ‘0’
807 * by host software to indicate to the host controller that a transfer
808 * request slot is cleared. The host controller
809 * shall free up any resources associated to the request slot
810 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
811 * host software indicates no change to request slots by setting the
812 * associated bits in this field to ‘1’. Bits in this field shall only
813 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
814 */
815 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
816 }
817
818 /**
819 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
820 * @hba: per adapter instance
821 * @pos: position of the bit to be cleared
822 */
823 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
824 {
825 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
826 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
827 else
828 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
829 }
830
831 /**
832 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
833 * @reg: Register value of host controller status
834 *
835 * Returns integer, 0 on Success and positive value if failed
836 */
837 static inline int ufshcd_get_lists_status(u32 reg)
838 {
839 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
840 }
841
842 /**
843 * ufshcd_get_uic_cmd_result - Get the UIC command result
844 * @hba: Pointer to adapter instance
845 *
846 * This function gets the result of UIC command completion
847 * Returns 0 on success, non zero value on error
848 */
849 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
850 {
851 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
852 MASK_UIC_COMMAND_RESULT;
853 }
854
855 /**
856 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
857 * @hba: Pointer to adapter instance
858 *
859 * This function gets UIC command argument3
860 * Returns 0 on success, non zero value on error
861 */
862 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
863 {
864 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
865 }
866
867 /**
868 * ufshcd_get_req_rsp - returns the TR response transaction type
869 * @ucd_rsp_ptr: pointer to response UPIU
870 */
871 static inline int
872 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
873 {
874 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
875 }
876
877 /**
878 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
879 * @ucd_rsp_ptr: pointer to response UPIU
880 *
881 * This function gets the response status and scsi_status from response UPIU
882 * Returns the response result code.
883 */
884 static inline int
885 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
886 {
887 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
888 }
889
890 /*
891 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
892 * from response UPIU
893 * @ucd_rsp_ptr: pointer to response UPIU
894 *
895 * Return the data segment length.
896 */
897 static inline unsigned int
898 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
899 {
900 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
901 MASK_RSP_UPIU_DATA_SEG_LEN;
902 }
903
904 /**
905 * ufshcd_is_exception_event - Check if the device raised an exception event
906 * @ucd_rsp_ptr: pointer to response UPIU
907 *
908 * The function checks if the device raised an exception event indicated in
909 * the Device Information field of response UPIU.
910 *
911 * Returns true if exception is raised, false otherwise.
912 */
913 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
914 {
915 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
916 MASK_RSP_EXCEPTION_EVENT;
917 }
918
919 /**
920 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
921 * @hba: per adapter instance
922 */
923 static inline void
924 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
925 {
926 ufshcd_writel(hba, INT_AGGR_ENABLE |
927 INT_AGGR_COUNTER_AND_TIMER_RESET,
928 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
929 }
930
931 /**
932 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
933 * @hba: per adapter instance
934 * @cnt: Interrupt aggregation counter threshold
935 * @tmout: Interrupt aggregation timeout value
936 */
937 static inline void
938 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
939 {
940 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
941 INT_AGGR_COUNTER_THLD_VAL(cnt) |
942 INT_AGGR_TIMEOUT_VAL(tmout),
943 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
944 }
945
946 /**
947 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
948 * @hba: per adapter instance
949 */
950 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
951 {
952 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
953 }
954
955 /**
956 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
957 * When run-stop registers are set to 1, it indicates the
958 * host controller that it can process the requests
959 * @hba: per adapter instance
960 */
961 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
962 {
963 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
964 REG_UTP_TASK_REQ_LIST_RUN_STOP);
965 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
966 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
967 }
968
969 /**
970 * ufshcd_hba_start - Start controller initialization sequence
971 * @hba: per adapter instance
972 */
973 static inline void ufshcd_hba_start(struct ufs_hba *hba)
974 {
975 u32 val = CONTROLLER_ENABLE;
976
977 if (ufshcd_crypto_enable(hba))
978 val |= CRYPTO_GENERAL_ENABLE;
979
980 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
981 }
982
983 /**
984 * ufshcd_is_hba_active - Get controller state
985 * @hba: per adapter instance
986 *
987 * Returns true if and only if the controller is active.
988 */
989 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
990 {
991 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
992 }
993
994 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
995 {
996 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
997 if (hba->ufs_version <= ufshci_version(1, 1))
998 return UFS_UNIPRO_VER_1_41;
999 else
1000 return UFS_UNIPRO_VER_1_6;
1001 }
1002 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
1003
1004 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
1005 {
1006 /*
1007 * If both host and device support UniPro ver1.6 or later, PA layer
1008 * parameters tuning happens during link startup itself.
1009 *
1010 * We can manually tune PA layer parameters if either host or device
1011 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
1012 * logic simple, we will only do manual tuning if local unipro version
1013 * doesn't support ver1.6 or later.
1014 */
1015 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
1016 }
1017
1018 /**
1019 * ufshcd_set_clk_freq - set UFS controller clock frequencies
1020 * @hba: per adapter instance
1021 * @scale_up: If True, set max possible frequency othewise set low frequency
1022 *
1023 * Returns 0 if successful
1024 * Returns < 0 for any other errors
1025 */
1026 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1027 {
1028 int ret = 0;
1029 struct ufs_clk_info *clki;
1030 struct list_head *head = &hba->clk_list_head;
1031
1032 if (list_empty(head))
1033 goto out;
1034
1035 list_for_each_entry(clki, head, list) {
1036 if (!IS_ERR_OR_NULL(clki->clk)) {
1037 if (scale_up && clki->max_freq) {
1038 if (clki->curr_freq == clki->max_freq)
1039 continue;
1040
1041 ret = clk_set_rate(clki->clk, clki->max_freq);
1042 if (ret) {
1043 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1044 __func__, clki->name,
1045 clki->max_freq, ret);
1046 break;
1047 }
1048 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1049 "scaled up", clki->name,
1050 clki->curr_freq,
1051 clki->max_freq);
1052
1053 clki->curr_freq = clki->max_freq;
1054
1055 } else if (!scale_up && clki->min_freq) {
1056 if (clki->curr_freq == clki->min_freq)
1057 continue;
1058
1059 ret = clk_set_rate(clki->clk, clki->min_freq);
1060 if (ret) {
1061 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1062 __func__, clki->name,
1063 clki->min_freq, ret);
1064 break;
1065 }
1066 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1067 "scaled down", clki->name,
1068 clki->curr_freq,
1069 clki->min_freq);
1070 clki->curr_freq = clki->min_freq;
1071 }
1072 }
1073 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1074 clki->name, clk_get_rate(clki->clk));
1075 }
1076
1077 out:
1078 return ret;
1079 }
1080
1081 /**
1082 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1083 * @hba: per adapter instance
1084 * @scale_up: True if scaling up and false if scaling down
1085 *
1086 * Returns 0 if successful
1087 * Returns < 0 for any other errors
1088 */
1089 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1090 {
1091 int ret = 0;
1092 ktime_t start = ktime_get();
1093
1094 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1095 if (ret)
1096 goto out;
1097
1098 ret = ufshcd_set_clk_freq(hba, scale_up);
1099 if (ret)
1100 goto out;
1101
1102 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1103 if (ret)
1104 ufshcd_set_clk_freq(hba, !scale_up);
1105
1106 out:
1107 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1108 (scale_up ? "up" : "down"),
1109 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1110 return ret;
1111 }
1112
1113 /**
1114 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1115 * @hba: per adapter instance
1116 * @scale_up: True if scaling up and false if scaling down
1117 *
1118 * Returns true if scaling is required, false otherwise.
1119 */
1120 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1121 bool scale_up)
1122 {
1123 struct ufs_clk_info *clki;
1124 struct list_head *head = &hba->clk_list_head;
1125
1126 if (list_empty(head))
1127 return false;
1128
1129 list_for_each_entry(clki, head, list) {
1130 if (!IS_ERR_OR_NULL(clki->clk)) {
1131 if (scale_up && clki->max_freq) {
1132 if (clki->curr_freq == clki->max_freq)
1133 continue;
1134 return true;
1135 } else if (!scale_up && clki->min_freq) {
1136 if (clki->curr_freq == clki->min_freq)
1137 continue;
1138 return true;
1139 }
1140 }
1141 }
1142
1143 return false;
1144 }
1145
1146 /*
1147 * Determine the number of pending commands by counting the bits in the SCSI
1148 * device budget maps. This approach has been selected because a bit is set in
1149 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1150 * flag. The host_self_blocked flag can be modified by calling
1151 * scsi_block_requests() or scsi_unblock_requests().
1152 */
1153 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1154 {
1155 const struct scsi_device *sdev;
1156 u32 pending = 0;
1157
1158 lockdep_assert_held(hba->host->host_lock);
1159 __shost_for_each_device(sdev, hba->host)
1160 pending += sbitmap_weight(&sdev->budget_map);
1161
1162 return pending;
1163 }
1164
1165 /*
1166 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1167 * has expired.
1168 *
1169 * Return: 0 upon success; -EBUSY upon timeout.
1170 */
1171 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1172 u64 wait_timeout_us)
1173 {
1174 unsigned long flags;
1175 int ret = 0;
1176 u32 tm_doorbell;
1177 u32 tr_pending;
1178 bool timeout = false, do_last_check = false;
1179 ktime_t start;
1180
1181 ufshcd_hold(hba, false);
1182 spin_lock_irqsave(hba->host->host_lock, flags);
1183 /*
1184 * Wait for all the outstanding tasks/transfer requests.
1185 * Verify by checking the doorbell registers are clear.
1186 */
1187 start = ktime_get();
1188 do {
1189 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1190 ret = -EBUSY;
1191 goto out;
1192 }
1193
1194 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1195 tr_pending = ufshcd_pending_cmds(hba);
1196 if (!tm_doorbell && !tr_pending) {
1197 timeout = false;
1198 break;
1199 } else if (do_last_check) {
1200 break;
1201 }
1202
1203 spin_unlock_irqrestore(hba->host->host_lock, flags);
1204 io_schedule_timeout(msecs_to_jiffies(20));
1205 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1206 wait_timeout_us) {
1207 timeout = true;
1208 /*
1209 * We might have scheduled out for long time so make
1210 * sure to check if doorbells are cleared by this time
1211 * or not.
1212 */
1213 do_last_check = true;
1214 }
1215 spin_lock_irqsave(hba->host->host_lock, flags);
1216 } while (tm_doorbell || tr_pending);
1217
1218 if (timeout) {
1219 dev_err(hba->dev,
1220 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1221 __func__, tm_doorbell, tr_pending);
1222 ret = -EBUSY;
1223 }
1224 out:
1225 spin_unlock_irqrestore(hba->host->host_lock, flags);
1226 ufshcd_release(hba);
1227 return ret;
1228 }
1229
1230 /**
1231 * ufshcd_scale_gear - scale up/down UFS gear
1232 * @hba: per adapter instance
1233 * @scale_up: True for scaling up gear and false for scaling down
1234 *
1235 * Returns 0 for success,
1236 * Returns -EBUSY if scaling can't happen at this time
1237 * Returns non-zero for any other errors
1238 */
1239 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1240 {
1241 int ret = 0;
1242 struct ufs_pa_layer_attr new_pwr_info;
1243
1244 if (scale_up) {
1245 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1246 sizeof(struct ufs_pa_layer_attr));
1247 } else {
1248 memcpy(&new_pwr_info, &hba->pwr_info,
1249 sizeof(struct ufs_pa_layer_attr));
1250
1251 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1252 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1253 /* save the current power mode */
1254 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1255 &hba->pwr_info,
1256 sizeof(struct ufs_pa_layer_attr));
1257
1258 /* scale down gear */
1259 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1260 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1261 }
1262 }
1263
1264 /* check if the power mode needs to be changed or not? */
1265 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1266 if (ret)
1267 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1268 __func__, ret,
1269 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1270 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1271
1272 return ret;
1273 }
1274
1275 /*
1276 * Wait until all pending SCSI commands and TMFs have finished or the timeout
1277 * has expired.
1278 *
1279 * Return: 0 upon success; -EBUSY upon timeout.
1280 */
1281 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1282 {
1283 int ret = 0;
1284 /*
1285 * make sure that there are no outstanding requests when
1286 * clock scaling is in progress
1287 */
1288 ufshcd_scsi_block_requests(hba);
1289 down_write(&hba->clk_scaling_lock);
1290
1291 if (!hba->clk_scaling.is_allowed ||
1292 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
1293 ret = -EBUSY;
1294 up_write(&hba->clk_scaling_lock);
1295 ufshcd_scsi_unblock_requests(hba);
1296 goto out;
1297 }
1298
1299 /* let's not get into low power until clock scaling is completed */
1300 ufshcd_hold(hba, false);
1301
1302 out:
1303 return ret;
1304 }
1305
1306 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1307 {
1308 if (writelock)
1309 up_write(&hba->clk_scaling_lock);
1310 else
1311 up_read(&hba->clk_scaling_lock);
1312 ufshcd_scsi_unblock_requests(hba);
1313 ufshcd_release(hba);
1314 }
1315
1316 /**
1317 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1318 * @hba: per adapter instance
1319 * @scale_up: True for scaling up and false for scalin down
1320 *
1321 * Returns 0 for success,
1322 * Returns -EBUSY if scaling can't happen at this time
1323 * Returns non-zero for any other errors
1324 */
1325 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1326 {
1327 int ret = 0;
1328 bool is_writelock = true;
1329
1330 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
1331 if (ret)
1332 return ret;
1333
1334 /* scale down the gear before scaling down clocks */
1335 if (!scale_up) {
1336 ret = ufshcd_scale_gear(hba, false);
1337 if (ret)
1338 goto out_unprepare;
1339 }
1340
1341 ret = ufshcd_scale_clks(hba, scale_up);
1342 if (ret) {
1343 if (!scale_up)
1344 ufshcd_scale_gear(hba, true);
1345 goto out_unprepare;
1346 }
1347
1348 /* scale up the gear after scaling up clocks */
1349 if (scale_up) {
1350 ret = ufshcd_scale_gear(hba, true);
1351 if (ret) {
1352 ufshcd_scale_clks(hba, false);
1353 goto out_unprepare;
1354 }
1355 }
1356
1357 /* Enable Write Booster if we have scaled up else disable it */
1358 if (ufshcd_enable_wb_if_scaling_up(hba)) {
1359 downgrade_write(&hba->clk_scaling_lock);
1360 is_writelock = false;
1361 ufshcd_wb_toggle(hba, scale_up);
1362 }
1363
1364 out_unprepare:
1365 ufshcd_clock_scaling_unprepare(hba, is_writelock);
1366 return ret;
1367 }
1368
1369 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1370 {
1371 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1372 clk_scaling.suspend_work);
1373 unsigned long irq_flags;
1374
1375 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1376 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1377 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1378 return;
1379 }
1380 hba->clk_scaling.is_suspended = true;
1381 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1382
1383 __ufshcd_suspend_clkscaling(hba);
1384 }
1385
1386 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1387 {
1388 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1389 clk_scaling.resume_work);
1390 unsigned long irq_flags;
1391
1392 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1393 if (!hba->clk_scaling.is_suspended) {
1394 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1395 return;
1396 }
1397 hba->clk_scaling.is_suspended = false;
1398 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1399
1400 devfreq_resume_device(hba->devfreq);
1401 }
1402
1403 static int ufshcd_devfreq_target(struct device *dev,
1404 unsigned long *freq, u32 flags)
1405 {
1406 int ret = 0;
1407 struct ufs_hba *hba = dev_get_drvdata(dev);
1408 ktime_t start;
1409 bool scale_up, sched_clk_scaling_suspend_work = false;
1410 struct list_head *clk_list = &hba->clk_list_head;
1411 struct ufs_clk_info *clki;
1412 unsigned long irq_flags;
1413
1414 if (!ufshcd_is_clkscaling_supported(hba))
1415 return -EINVAL;
1416
1417 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1418 /* Override with the closest supported frequency */
1419 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1420 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1421 if (ufshcd_eh_in_progress(hba)) {
1422 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1423 return 0;
1424 }
1425
1426 if (!hba->clk_scaling.active_reqs)
1427 sched_clk_scaling_suspend_work = true;
1428
1429 if (list_empty(clk_list)) {
1430 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1431 goto out;
1432 }
1433
1434 /* Decide based on the rounded-off frequency and update */
1435 scale_up = *freq == clki->max_freq;
1436 if (!scale_up)
1437 *freq = clki->min_freq;
1438 /* Update the frequency */
1439 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1440 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1441 ret = 0;
1442 goto out; /* no state change required */
1443 }
1444 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1445
1446 start = ktime_get();
1447 ret = ufshcd_devfreq_scale(hba, scale_up);
1448
1449 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1450 (scale_up ? "up" : "down"),
1451 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1452
1453 out:
1454 if (sched_clk_scaling_suspend_work)
1455 queue_work(hba->clk_scaling.workq,
1456 &hba->clk_scaling.suspend_work);
1457
1458 return ret;
1459 }
1460
1461 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1462 struct devfreq_dev_status *stat)
1463 {
1464 struct ufs_hba *hba = dev_get_drvdata(dev);
1465 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1466 unsigned long flags;
1467 struct list_head *clk_list = &hba->clk_list_head;
1468 struct ufs_clk_info *clki;
1469 ktime_t curr_t;
1470
1471 if (!ufshcd_is_clkscaling_supported(hba))
1472 return -EINVAL;
1473
1474 memset(stat, 0, sizeof(*stat));
1475
1476 spin_lock_irqsave(hba->host->host_lock, flags);
1477 curr_t = ktime_get();
1478 if (!scaling->window_start_t)
1479 goto start_window;
1480
1481 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1482 /*
1483 * If current frequency is 0, then the ondemand governor considers
1484 * there's no initial frequency set. And it always requests to set
1485 * to max. frequency.
1486 */
1487 stat->current_frequency = clki->curr_freq;
1488 if (scaling->is_busy_started)
1489 scaling->tot_busy_t += ktime_us_delta(curr_t,
1490 scaling->busy_start_t);
1491
1492 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1493 stat->busy_time = scaling->tot_busy_t;
1494 start_window:
1495 scaling->window_start_t = curr_t;
1496 scaling->tot_busy_t = 0;
1497
1498 if (hba->outstanding_reqs) {
1499 scaling->busy_start_t = curr_t;
1500 scaling->is_busy_started = true;
1501 } else {
1502 scaling->busy_start_t = 0;
1503 scaling->is_busy_started = false;
1504 }
1505 spin_unlock_irqrestore(hba->host->host_lock, flags);
1506 return 0;
1507 }
1508
1509 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1510 {
1511 struct list_head *clk_list = &hba->clk_list_head;
1512 struct ufs_clk_info *clki;
1513 struct devfreq *devfreq;
1514 int ret;
1515
1516 /* Skip devfreq if we don't have any clocks in the list */
1517 if (list_empty(clk_list))
1518 return 0;
1519
1520 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1521 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1522 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1523
1524 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1525 &hba->vps->ondemand_data);
1526 devfreq = devfreq_add_device(hba->dev,
1527 &hba->vps->devfreq_profile,
1528 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1529 &hba->vps->ondemand_data);
1530 if (IS_ERR(devfreq)) {
1531 ret = PTR_ERR(devfreq);
1532 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1533
1534 dev_pm_opp_remove(hba->dev, clki->min_freq);
1535 dev_pm_opp_remove(hba->dev, clki->max_freq);
1536 return ret;
1537 }
1538
1539 hba->devfreq = devfreq;
1540
1541 return 0;
1542 }
1543
1544 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1545 {
1546 struct list_head *clk_list = &hba->clk_list_head;
1547 struct ufs_clk_info *clki;
1548
1549 if (!hba->devfreq)
1550 return;
1551
1552 devfreq_remove_device(hba->devfreq);
1553 hba->devfreq = NULL;
1554
1555 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1556 dev_pm_opp_remove(hba->dev, clki->min_freq);
1557 dev_pm_opp_remove(hba->dev, clki->max_freq);
1558 }
1559
1560 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1561 {
1562 unsigned long flags;
1563
1564 devfreq_suspend_device(hba->devfreq);
1565 spin_lock_irqsave(hba->host->host_lock, flags);
1566 hba->clk_scaling.window_start_t = 0;
1567 spin_unlock_irqrestore(hba->host->host_lock, flags);
1568 }
1569
1570 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1571 {
1572 unsigned long flags;
1573 bool suspend = false;
1574
1575 cancel_work_sync(&hba->clk_scaling.suspend_work);
1576 cancel_work_sync(&hba->clk_scaling.resume_work);
1577
1578 spin_lock_irqsave(hba->host->host_lock, flags);
1579 if (!hba->clk_scaling.is_suspended) {
1580 suspend = true;
1581 hba->clk_scaling.is_suspended = true;
1582 }
1583 spin_unlock_irqrestore(hba->host->host_lock, flags);
1584
1585 if (suspend)
1586 __ufshcd_suspend_clkscaling(hba);
1587 }
1588
1589 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1590 {
1591 unsigned long flags;
1592 bool resume = false;
1593
1594 spin_lock_irqsave(hba->host->host_lock, flags);
1595 if (hba->clk_scaling.is_suspended) {
1596 resume = true;
1597 hba->clk_scaling.is_suspended = false;
1598 }
1599 spin_unlock_irqrestore(hba->host->host_lock, flags);
1600
1601 if (resume)
1602 devfreq_resume_device(hba->devfreq);
1603 }
1604
1605 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1606 struct device_attribute *attr, char *buf)
1607 {
1608 struct ufs_hba *hba = dev_get_drvdata(dev);
1609
1610 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1611 }
1612
1613 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1614 struct device_attribute *attr, const char *buf, size_t count)
1615 {
1616 struct ufs_hba *hba = dev_get_drvdata(dev);
1617 u32 value;
1618 int err = 0;
1619
1620 if (kstrtou32(buf, 0, &value))
1621 return -EINVAL;
1622
1623 down(&hba->host_sem);
1624 if (!ufshcd_is_user_access_allowed(hba)) {
1625 err = -EBUSY;
1626 goto out;
1627 }
1628
1629 value = !!value;
1630 if (value == hba->clk_scaling.is_enabled)
1631 goto out;
1632
1633 ufshcd_rpm_get_sync(hba);
1634 ufshcd_hold(hba, false);
1635
1636 hba->clk_scaling.is_enabled = value;
1637
1638 if (value) {
1639 ufshcd_resume_clkscaling(hba);
1640 } else {
1641 ufshcd_suspend_clkscaling(hba);
1642 err = ufshcd_devfreq_scale(hba, true);
1643 if (err)
1644 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1645 __func__, err);
1646 }
1647
1648 ufshcd_release(hba);
1649 ufshcd_rpm_put_sync(hba);
1650 out:
1651 up(&hba->host_sem);
1652 return err ? err : count;
1653 }
1654
1655 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1656 {
1657 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1658 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1659 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1660 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1661 hba->clk_scaling.enable_attr.attr.mode = 0644;
1662 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1663 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1664 }
1665
1666 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1667 {
1668 if (hba->clk_scaling.enable_attr.attr.name)
1669 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1670 }
1671
1672 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1673 {
1674 char wq_name[sizeof("ufs_clkscaling_00")];
1675
1676 if (!ufshcd_is_clkscaling_supported(hba))
1677 return;
1678
1679 if (!hba->clk_scaling.min_gear)
1680 hba->clk_scaling.min_gear = UFS_HS_G1;
1681
1682 INIT_WORK(&hba->clk_scaling.suspend_work,
1683 ufshcd_clk_scaling_suspend_work);
1684 INIT_WORK(&hba->clk_scaling.resume_work,
1685 ufshcd_clk_scaling_resume_work);
1686
1687 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1688 hba->host->host_no);
1689 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1690
1691 hba->clk_scaling.is_initialized = true;
1692 }
1693
1694 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1695 {
1696 if (!hba->clk_scaling.is_initialized)
1697 return;
1698
1699 ufshcd_remove_clk_scaling_sysfs(hba);
1700 destroy_workqueue(hba->clk_scaling.workq);
1701 ufshcd_devfreq_remove(hba);
1702 hba->clk_scaling.is_initialized = false;
1703 }
1704
1705 static void ufshcd_ungate_work(struct work_struct *work)
1706 {
1707 int ret;
1708 unsigned long flags;
1709 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1710 clk_gating.ungate_work);
1711
1712 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1713
1714 spin_lock_irqsave(hba->host->host_lock, flags);
1715 if (hba->clk_gating.state == CLKS_ON) {
1716 spin_unlock_irqrestore(hba->host->host_lock, flags);
1717 goto unblock_reqs;
1718 }
1719
1720 spin_unlock_irqrestore(hba->host->host_lock, flags);
1721 ufshcd_hba_vreg_set_hpm(hba);
1722 ufshcd_setup_clocks(hba, true);
1723
1724 ufshcd_enable_irq(hba);
1725
1726 /* Exit from hibern8 */
1727 if (ufshcd_can_hibern8_during_gating(hba)) {
1728 /* Prevent gating in this path */
1729 hba->clk_gating.is_suspended = true;
1730 if (ufshcd_is_link_hibern8(hba)) {
1731 ret = ufshcd_uic_hibern8_exit(hba);
1732 if (ret)
1733 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1734 __func__, ret);
1735 else
1736 ufshcd_set_link_active(hba);
1737 }
1738 hba->clk_gating.is_suspended = false;
1739 }
1740 unblock_reqs:
1741 ufshcd_scsi_unblock_requests(hba);
1742 }
1743
1744 /**
1745 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1746 * Also, exit from hibern8 mode and set the link as active.
1747 * @hba: per adapter instance
1748 * @async: This indicates whether caller should ungate clocks asynchronously.
1749 */
1750 int ufshcd_hold(struct ufs_hba *hba, bool async)
1751 {
1752 int rc = 0;
1753 bool flush_result;
1754 unsigned long flags;
1755
1756 if (!ufshcd_is_clkgating_allowed(hba) ||
1757 !hba->clk_gating.is_initialized)
1758 goto out;
1759 spin_lock_irqsave(hba->host->host_lock, flags);
1760 hba->clk_gating.active_reqs++;
1761
1762 start:
1763 switch (hba->clk_gating.state) {
1764 case CLKS_ON:
1765 /*
1766 * Wait for the ungate work to complete if in progress.
1767 * Though the clocks may be in ON state, the link could
1768 * still be in hibner8 state if hibern8 is allowed
1769 * during clock gating.
1770 * Make sure we exit hibern8 state also in addition to
1771 * clocks being ON.
1772 */
1773 if (ufshcd_can_hibern8_during_gating(hba) &&
1774 ufshcd_is_link_hibern8(hba)) {
1775 if (async) {
1776 rc = -EAGAIN;
1777 hba->clk_gating.active_reqs--;
1778 break;
1779 }
1780 spin_unlock_irqrestore(hba->host->host_lock, flags);
1781 flush_result = flush_work(&hba->clk_gating.ungate_work);
1782 if (hba->clk_gating.is_suspended && !flush_result)
1783 goto out;
1784 spin_lock_irqsave(hba->host->host_lock, flags);
1785 goto start;
1786 }
1787 break;
1788 case REQ_CLKS_OFF:
1789 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1790 hba->clk_gating.state = CLKS_ON;
1791 trace_ufshcd_clk_gating(dev_name(hba->dev),
1792 hba->clk_gating.state);
1793 break;
1794 }
1795 /*
1796 * If we are here, it means gating work is either done or
1797 * currently running. Hence, fall through to cancel gating
1798 * work and to enable clocks.
1799 */
1800 fallthrough;
1801 case CLKS_OFF:
1802 hba->clk_gating.state = REQ_CLKS_ON;
1803 trace_ufshcd_clk_gating(dev_name(hba->dev),
1804 hba->clk_gating.state);
1805 if (queue_work(hba->clk_gating.clk_gating_workq,
1806 &hba->clk_gating.ungate_work))
1807 ufshcd_scsi_block_requests(hba);
1808 /*
1809 * fall through to check if we should wait for this
1810 * work to be done or not.
1811 */
1812 fallthrough;
1813 case REQ_CLKS_ON:
1814 if (async) {
1815 rc = -EAGAIN;
1816 hba->clk_gating.active_reqs--;
1817 break;
1818 }
1819
1820 spin_unlock_irqrestore(hba->host->host_lock, flags);
1821 flush_work(&hba->clk_gating.ungate_work);
1822 /* Make sure state is CLKS_ON before returning */
1823 spin_lock_irqsave(hba->host->host_lock, flags);
1824 goto start;
1825 default:
1826 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1827 __func__, hba->clk_gating.state);
1828 break;
1829 }
1830 spin_unlock_irqrestore(hba->host->host_lock, flags);
1831 out:
1832 return rc;
1833 }
1834 EXPORT_SYMBOL_GPL(ufshcd_hold);
1835
1836 static void ufshcd_gate_work(struct work_struct *work)
1837 {
1838 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1839 clk_gating.gate_work.work);
1840 unsigned long flags;
1841 int ret;
1842
1843 spin_lock_irqsave(hba->host->host_lock, flags);
1844 /*
1845 * In case you are here to cancel this work the gating state
1846 * would be marked as REQ_CLKS_ON. In this case save time by
1847 * skipping the gating work and exit after changing the clock
1848 * state to CLKS_ON.
1849 */
1850 if (hba->clk_gating.is_suspended ||
1851 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1852 hba->clk_gating.state = CLKS_ON;
1853 trace_ufshcd_clk_gating(dev_name(hba->dev),
1854 hba->clk_gating.state);
1855 goto rel_lock;
1856 }
1857
1858 if (hba->clk_gating.active_reqs
1859 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1860 || hba->outstanding_reqs || hba->outstanding_tasks
1861 || hba->active_uic_cmd || hba->uic_async_done)
1862 goto rel_lock;
1863
1864 spin_unlock_irqrestore(hba->host->host_lock, flags);
1865
1866 /* put the link into hibern8 mode before turning off clocks */
1867 if (ufshcd_can_hibern8_during_gating(hba)) {
1868 ret = ufshcd_uic_hibern8_enter(hba);
1869 if (ret) {
1870 hba->clk_gating.state = CLKS_ON;
1871 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1872 __func__, ret);
1873 trace_ufshcd_clk_gating(dev_name(hba->dev),
1874 hba->clk_gating.state);
1875 goto out;
1876 }
1877 ufshcd_set_link_hibern8(hba);
1878 }
1879
1880 ufshcd_disable_irq(hba);
1881
1882 ufshcd_setup_clocks(hba, false);
1883
1884 /* Put the host controller in low power mode if possible */
1885 ufshcd_hba_vreg_set_lpm(hba);
1886 /*
1887 * In case you are here to cancel this work the gating state
1888 * would be marked as REQ_CLKS_ON. In this case keep the state
1889 * as REQ_CLKS_ON which would anyway imply that clocks are off
1890 * and a request to turn them on is pending. By doing this way,
1891 * we keep the state machine in tact and this would ultimately
1892 * prevent from doing cancel work multiple times when there are
1893 * new requests arriving before the current cancel work is done.
1894 */
1895 spin_lock_irqsave(hba->host->host_lock, flags);
1896 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1897 hba->clk_gating.state = CLKS_OFF;
1898 trace_ufshcd_clk_gating(dev_name(hba->dev),
1899 hba->clk_gating.state);
1900 }
1901 rel_lock:
1902 spin_unlock_irqrestore(hba->host->host_lock, flags);
1903 out:
1904 return;
1905 }
1906
1907 /* host lock must be held before calling this variant */
1908 static void __ufshcd_release(struct ufs_hba *hba)
1909 {
1910 if (!ufshcd_is_clkgating_allowed(hba))
1911 return;
1912
1913 hba->clk_gating.active_reqs--;
1914
1915 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1916 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1917 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
1918 hba->active_uic_cmd || hba->uic_async_done ||
1919 hba->clk_gating.state == CLKS_OFF)
1920 return;
1921
1922 hba->clk_gating.state = REQ_CLKS_OFF;
1923 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1924 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1925 &hba->clk_gating.gate_work,
1926 msecs_to_jiffies(hba->clk_gating.delay_ms));
1927 }
1928
1929 void ufshcd_release(struct ufs_hba *hba)
1930 {
1931 unsigned long flags;
1932
1933 spin_lock_irqsave(hba->host->host_lock, flags);
1934 __ufshcd_release(hba);
1935 spin_unlock_irqrestore(hba->host->host_lock, flags);
1936 }
1937 EXPORT_SYMBOL_GPL(ufshcd_release);
1938
1939 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1940 struct device_attribute *attr, char *buf)
1941 {
1942 struct ufs_hba *hba = dev_get_drvdata(dev);
1943
1944 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1945 }
1946
1947 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1948 {
1949 struct ufs_hba *hba = dev_get_drvdata(dev);
1950 unsigned long flags;
1951
1952 spin_lock_irqsave(hba->host->host_lock, flags);
1953 hba->clk_gating.delay_ms = value;
1954 spin_unlock_irqrestore(hba->host->host_lock, flags);
1955 }
1956 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1957
1958 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1959 struct device_attribute *attr, const char *buf, size_t count)
1960 {
1961 unsigned long value;
1962
1963 if (kstrtoul(buf, 0, &value))
1964 return -EINVAL;
1965
1966 ufshcd_clkgate_delay_set(dev, value);
1967 return count;
1968 }
1969
1970 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1971 struct device_attribute *attr, char *buf)
1972 {
1973 struct ufs_hba *hba = dev_get_drvdata(dev);
1974
1975 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1976 }
1977
1978 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1979 struct device_attribute *attr, const char *buf, size_t count)
1980 {
1981 struct ufs_hba *hba = dev_get_drvdata(dev);
1982 unsigned long flags;
1983 u32 value;
1984
1985 if (kstrtou32(buf, 0, &value))
1986 return -EINVAL;
1987
1988 value = !!value;
1989
1990 spin_lock_irqsave(hba->host->host_lock, flags);
1991 if (value == hba->clk_gating.is_enabled)
1992 goto out;
1993
1994 if (value)
1995 __ufshcd_release(hba);
1996 else
1997 hba->clk_gating.active_reqs++;
1998
1999 hba->clk_gating.is_enabled = value;
2000 out:
2001 spin_unlock_irqrestore(hba->host->host_lock, flags);
2002 return count;
2003 }
2004
2005 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
2006 {
2007 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
2008 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
2009 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
2010 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
2011 hba->clk_gating.delay_attr.attr.mode = 0644;
2012 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
2013 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
2014
2015 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
2016 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
2017 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
2018 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
2019 hba->clk_gating.enable_attr.attr.mode = 0644;
2020 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
2021 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
2022 }
2023
2024 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
2025 {
2026 if (hba->clk_gating.delay_attr.attr.name)
2027 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
2028 if (hba->clk_gating.enable_attr.attr.name)
2029 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
2030 }
2031
2032 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
2033 {
2034 char wq_name[sizeof("ufs_clk_gating_00")];
2035
2036 if (!ufshcd_is_clkgating_allowed(hba))
2037 return;
2038
2039 hba->clk_gating.state = CLKS_ON;
2040
2041 hba->clk_gating.delay_ms = 150;
2042 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2043 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2044
2045 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
2046 hba->host->host_no);
2047 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
2048 WQ_MEM_RECLAIM | WQ_HIGHPRI);
2049
2050 ufshcd_init_clk_gating_sysfs(hba);
2051
2052 hba->clk_gating.is_enabled = true;
2053 hba->clk_gating.is_initialized = true;
2054 }
2055
2056 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2057 {
2058 if (!hba->clk_gating.is_initialized)
2059 return;
2060
2061 ufshcd_remove_clk_gating_sysfs(hba);
2062
2063 /* Ungate the clock if necessary. */
2064 ufshcd_hold(hba, false);
2065 hba->clk_gating.is_initialized = false;
2066 ufshcd_release(hba);
2067
2068 destroy_workqueue(hba->clk_gating.clk_gating_workq);
2069 }
2070
2071 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2072 {
2073 bool queue_resume_work = false;
2074 ktime_t curr_t = ktime_get();
2075 unsigned long flags;
2076
2077 if (!ufshcd_is_clkscaling_supported(hba))
2078 return;
2079
2080 spin_lock_irqsave(hba->host->host_lock, flags);
2081 if (!hba->clk_scaling.active_reqs++)
2082 queue_resume_work = true;
2083
2084 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2085 spin_unlock_irqrestore(hba->host->host_lock, flags);
2086 return;
2087 }
2088
2089 if (queue_resume_work)
2090 queue_work(hba->clk_scaling.workq,
2091 &hba->clk_scaling.resume_work);
2092
2093 if (!hba->clk_scaling.window_start_t) {
2094 hba->clk_scaling.window_start_t = curr_t;
2095 hba->clk_scaling.tot_busy_t = 0;
2096 hba->clk_scaling.is_busy_started = false;
2097 }
2098
2099 if (!hba->clk_scaling.is_busy_started) {
2100 hba->clk_scaling.busy_start_t = curr_t;
2101 hba->clk_scaling.is_busy_started = true;
2102 }
2103 spin_unlock_irqrestore(hba->host->host_lock, flags);
2104 }
2105
2106 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2107 {
2108 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2109 unsigned long flags;
2110
2111 if (!ufshcd_is_clkscaling_supported(hba))
2112 return;
2113
2114 spin_lock_irqsave(hba->host->host_lock, flags);
2115 hba->clk_scaling.active_reqs--;
2116 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2117 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2118 scaling->busy_start_t));
2119 scaling->busy_start_t = 0;
2120 scaling->is_busy_started = false;
2121 }
2122 spin_unlock_irqrestore(hba->host->host_lock, flags);
2123 }
2124
2125 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2126 {
2127 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2128 return READ;
2129 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2130 return WRITE;
2131 else
2132 return -EINVAL;
2133 }
2134
2135 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2136 struct ufshcd_lrb *lrbp)
2137 {
2138 const struct ufs_hba_monitor *m = &hba->monitor;
2139
2140 return (m->enabled && lrbp && lrbp->cmd &&
2141 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2142 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2143 }
2144
2145 static void ufshcd_start_monitor(struct ufs_hba *hba,
2146 const struct ufshcd_lrb *lrbp)
2147 {
2148 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2149 unsigned long flags;
2150
2151 spin_lock_irqsave(hba->host->host_lock, flags);
2152 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2153 hba->monitor.busy_start_ts[dir] = ktime_get();
2154 spin_unlock_irqrestore(hba->host->host_lock, flags);
2155 }
2156
2157 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
2158 {
2159 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2160 unsigned long flags;
2161
2162 spin_lock_irqsave(hba->host->host_lock, flags);
2163 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2164 const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2165 struct ufs_hba_monitor *m = &hba->monitor;
2166 ktime_t now, inc, lat;
2167
2168 now = lrbp->compl_time_stamp;
2169 inc = ktime_sub(now, m->busy_start_ts[dir]);
2170 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2171 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2172
2173 /* Update latencies */
2174 m->nr_req[dir]++;
2175 lat = ktime_sub(now, lrbp->issue_time_stamp);
2176 m->lat_sum[dir] += lat;
2177 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2178 m->lat_max[dir] = lat;
2179 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2180 m->lat_min[dir] = lat;
2181
2182 m->nr_queued[dir]--;
2183 /* Push forward the busy start of monitor */
2184 m->busy_start_ts[dir] = now;
2185 }
2186 spin_unlock_irqrestore(hba->host->host_lock, flags);
2187 }
2188
2189 /**
2190 * ufshcd_send_command - Send SCSI or device management commands
2191 * @hba: per adapter instance
2192 * @task_tag: Task tag of the command
2193 * @hwq: pointer to hardware queue instance
2194 */
2195 static inline
2196 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag,
2197 struct ufs_hw_queue *hwq)
2198 {
2199 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2200 unsigned long flags;
2201
2202 lrbp->issue_time_stamp = ktime_get();
2203 lrbp->issue_time_stamp_local_clock = local_clock();
2204 lrbp->compl_time_stamp = ktime_set(0, 0);
2205 lrbp->compl_time_stamp_local_clock = 0;
2206 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2207 ufshcd_clk_scaling_start_busy(hba);
2208 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2209 ufshcd_start_monitor(hba, lrbp);
2210
2211 if (is_mcq_enabled(hba)) {
2212 int utrd_size = sizeof(struct utp_transfer_req_desc);
2213
2214 spin_lock(&hwq->sq_lock);
2215 memcpy(hwq->sqe_base_addr + (hwq->sq_tail_slot * utrd_size),
2216 lrbp->utr_descriptor_ptr, utrd_size);
2217 ufshcd_inc_sq_tail(hwq);
2218 spin_unlock(&hwq->sq_lock);
2219 } else {
2220 spin_lock_irqsave(&hba->outstanding_lock, flags);
2221 if (hba->vops && hba->vops->setup_xfer_req)
2222 hba->vops->setup_xfer_req(hba, lrbp->task_tag,
2223 !!lrbp->cmd);
2224 __set_bit(lrbp->task_tag, &hba->outstanding_reqs);
2225 ufshcd_writel(hba, 1 << lrbp->task_tag,
2226 REG_UTP_TRANSFER_REQ_DOOR_BELL);
2227 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2228 }
2229 }
2230
2231 /**
2232 * ufshcd_copy_sense_data - Copy sense data in case of check condition
2233 * @lrbp: pointer to local reference block
2234 */
2235 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2236 {
2237 u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2238 int len;
2239
2240 if (sense_buffer &&
2241 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2242 int len_to_copy;
2243
2244 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2245 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2246
2247 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2248 len_to_copy);
2249 }
2250 }
2251
2252 /**
2253 * ufshcd_copy_query_response() - Copy the Query Response and the data
2254 * descriptor
2255 * @hba: per adapter instance
2256 * @lrbp: pointer to local reference block
2257 */
2258 static
2259 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2260 {
2261 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2262
2263 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2264
2265 /* Get the descriptor */
2266 if (hba->dev_cmd.query.descriptor &&
2267 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2268 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2269 GENERAL_UPIU_REQUEST_SIZE;
2270 u16 resp_len;
2271 u16 buf_len;
2272
2273 /* data segment length */
2274 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2275 MASK_QUERY_DATA_SEG_LEN;
2276 buf_len = be16_to_cpu(
2277 hba->dev_cmd.query.request.upiu_req.length);
2278 if (likely(buf_len >= resp_len)) {
2279 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2280 } else {
2281 dev_warn(hba->dev,
2282 "%s: rsp size %d is bigger than buffer size %d",
2283 __func__, resp_len, buf_len);
2284 return -EINVAL;
2285 }
2286 }
2287
2288 return 0;
2289 }
2290
2291 /**
2292 * ufshcd_hba_capabilities - Read controller capabilities
2293 * @hba: per adapter instance
2294 *
2295 * Return: 0 on success, negative on error.
2296 */
2297 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2298 {
2299 int err;
2300
2301 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2302 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
2303 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
2304
2305 /* nutrs and nutmrs are 0 based values */
2306 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2307 hba->nutmrs =
2308 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2309 hba->reserved_slot = hba->nutrs - 1;
2310
2311 /* Read crypto capabilities */
2312 err = ufshcd_hba_init_crypto_capabilities(hba);
2313 if (err)
2314 dev_err(hba->dev, "crypto setup failed\n");
2315
2316 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2317 if (!hba->mcq_sup)
2318 return err;
2319
2320 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2321 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT,
2322 hba->mcq_capabilities);
2323
2324 return err;
2325 }
2326
2327 /**
2328 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2329 * to accept UIC commands
2330 * @hba: per adapter instance
2331 * Return true on success, else false
2332 */
2333 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2334 {
2335 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
2336 }
2337
2338 /**
2339 * ufshcd_get_upmcrs - Get the power mode change request status
2340 * @hba: Pointer to adapter instance
2341 *
2342 * This function gets the UPMCRS field of HCS register
2343 * Returns value of UPMCRS field
2344 */
2345 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2346 {
2347 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2348 }
2349
2350 /**
2351 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2352 * @hba: per adapter instance
2353 * @uic_cmd: UIC command
2354 */
2355 static inline void
2356 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2357 {
2358 lockdep_assert_held(&hba->uic_cmd_mutex);
2359
2360 WARN_ON(hba->active_uic_cmd);
2361
2362 hba->active_uic_cmd = uic_cmd;
2363
2364 /* Write Args */
2365 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2366 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2367 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2368
2369 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2370
2371 /* Write UIC Cmd */
2372 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2373 REG_UIC_COMMAND);
2374 }
2375
2376 /**
2377 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2378 * @hba: per adapter instance
2379 * @uic_cmd: UIC command
2380 *
2381 * Returns 0 only if success.
2382 */
2383 static int
2384 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2385 {
2386 int ret;
2387 unsigned long flags;
2388
2389 lockdep_assert_held(&hba->uic_cmd_mutex);
2390
2391 if (wait_for_completion_timeout(&uic_cmd->done,
2392 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2393 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2394 } else {
2395 ret = -ETIMEDOUT;
2396 dev_err(hba->dev,
2397 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2398 uic_cmd->command, uic_cmd->argument3);
2399
2400 if (!uic_cmd->cmd_active) {
2401 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2402 __func__);
2403 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2404 }
2405 }
2406
2407 spin_lock_irqsave(hba->host->host_lock, flags);
2408 hba->active_uic_cmd = NULL;
2409 spin_unlock_irqrestore(hba->host->host_lock, flags);
2410
2411 return ret;
2412 }
2413
2414 /**
2415 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2416 * @hba: per adapter instance
2417 * @uic_cmd: UIC command
2418 * @completion: initialize the completion only if this is set to true
2419 *
2420 * Returns 0 only if success.
2421 */
2422 static int
2423 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2424 bool completion)
2425 {
2426 lockdep_assert_held(&hba->uic_cmd_mutex);
2427 lockdep_assert_held(hba->host->host_lock);
2428
2429 if (!ufshcd_ready_for_uic_cmd(hba)) {
2430 dev_err(hba->dev,
2431 "Controller not ready to accept UIC commands\n");
2432 return -EIO;
2433 }
2434
2435 if (completion)
2436 init_completion(&uic_cmd->done);
2437
2438 uic_cmd->cmd_active = 1;
2439 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2440
2441 return 0;
2442 }
2443
2444 /**
2445 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2446 * @hba: per adapter instance
2447 * @uic_cmd: UIC command
2448 *
2449 * Returns 0 only if success.
2450 */
2451 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2452 {
2453 int ret;
2454 unsigned long flags;
2455
2456 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2457 return 0;
2458
2459 ufshcd_hold(hba, false);
2460 mutex_lock(&hba->uic_cmd_mutex);
2461 ufshcd_add_delay_before_dme_cmd(hba);
2462
2463 spin_lock_irqsave(hba->host->host_lock, flags);
2464 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2465 spin_unlock_irqrestore(hba->host->host_lock, flags);
2466 if (!ret)
2467 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2468
2469 mutex_unlock(&hba->uic_cmd_mutex);
2470
2471 ufshcd_release(hba);
2472 return ret;
2473 }
2474
2475 /**
2476 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2477 * @hba: per-adapter instance
2478 * @lrbp: pointer to local reference block
2479 * @sg_entries: The number of sg lists actually used
2480 * @sg_list: Pointer to SG list
2481 */
2482 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2483 struct scatterlist *sg_list)
2484 {
2485 struct ufshcd_sg_entry *prd;
2486 struct scatterlist *sg;
2487 int i;
2488
2489 if (sg_entries) {
2490
2491 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2492 lrbp->utr_descriptor_ptr->prd_table_length =
2493 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2494 else
2495 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2496
2497 prd = lrbp->ucd_prdt_ptr;
2498
2499 for_each_sg(sg_list, sg, sg_entries, i) {
2500 const unsigned int len = sg_dma_len(sg);
2501
2502 /*
2503 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2504 * based value that indicates the length, in bytes, of
2505 * the data block. A maximum of length of 256KB may
2506 * exist for any entry. Bits 1:0 of this field shall be
2507 * 11b to indicate Dword granularity. A value of '3'
2508 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2509 */
2510 WARN_ONCE(len > 256 * 1024, "len = %#x\n", len);
2511 prd->size = cpu_to_le32(len - 1);
2512 prd->addr = cpu_to_le64(sg->dma_address);
2513 prd->reserved = 0;
2514 prd = (void *)prd + ufshcd_sg_entry_size(hba);
2515 }
2516 } else {
2517 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2518 }
2519 }
2520
2521 /**
2522 * ufshcd_map_sg - Map scatter-gather list to prdt
2523 * @hba: per adapter instance
2524 * @lrbp: pointer to local reference block
2525 *
2526 * Returns 0 in case of success, non-zero value in case of failure
2527 */
2528 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2529 {
2530 struct scsi_cmnd *cmd = lrbp->cmd;
2531 int sg_segments = scsi_dma_map(cmd);
2532
2533 if (sg_segments < 0)
2534 return sg_segments;
2535
2536 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
2537
2538 return 0;
2539 }
2540
2541 /**
2542 * ufshcd_enable_intr - enable interrupts
2543 * @hba: per adapter instance
2544 * @intrs: interrupt bits
2545 */
2546 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2547 {
2548 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2549
2550 if (hba->ufs_version == ufshci_version(1, 0)) {
2551 u32 rw;
2552 rw = set & INTERRUPT_MASK_RW_VER_10;
2553 set = rw | ((set ^ intrs) & intrs);
2554 } else {
2555 set |= intrs;
2556 }
2557
2558 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2559 }
2560
2561 /**
2562 * ufshcd_disable_intr - disable interrupts
2563 * @hba: per adapter instance
2564 * @intrs: interrupt bits
2565 */
2566 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2567 {
2568 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2569
2570 if (hba->ufs_version == ufshci_version(1, 0)) {
2571 u32 rw;
2572 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2573 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2574 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2575
2576 } else {
2577 set &= ~intrs;
2578 }
2579
2580 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2581 }
2582
2583 /**
2584 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2585 * descriptor according to request
2586 * @lrbp: pointer to local reference block
2587 * @upiu_flags: flags required in the header
2588 * @cmd_dir: requests data direction
2589 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2590 */
2591 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags,
2592 enum dma_data_direction cmd_dir, int ehs_length)
2593 {
2594 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2595 u32 data_direction;
2596 u32 dword_0;
2597 u32 dword_1 = 0;
2598 u32 dword_3 = 0;
2599
2600 if (cmd_dir == DMA_FROM_DEVICE) {
2601 data_direction = UTP_DEVICE_TO_HOST;
2602 *upiu_flags = UPIU_CMD_FLAGS_READ;
2603 } else if (cmd_dir == DMA_TO_DEVICE) {
2604 data_direction = UTP_HOST_TO_DEVICE;
2605 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2606 } else {
2607 data_direction = UTP_NO_DATA_TRANSFER;
2608 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2609 }
2610
2611 dword_0 = data_direction | (lrbp->command_type << UPIU_COMMAND_TYPE_OFFSET) |
2612 ehs_length << 8;
2613 if (lrbp->intr_cmd)
2614 dword_0 |= UTP_REQ_DESC_INT_CMD;
2615
2616 /* Prepare crypto related dwords */
2617 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2618
2619 /* Transfer request descriptor header fields */
2620 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2621 req_desc->header.dword_1 = cpu_to_le32(dword_1);
2622 /*
2623 * assigning invalid value for command status. Controller
2624 * updates OCS on command completion, with the command
2625 * status
2626 */
2627 req_desc->header.dword_2 =
2628 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2629 req_desc->header.dword_3 = cpu_to_le32(dword_3);
2630
2631 req_desc->prd_table_length = 0;
2632 }
2633
2634 /**
2635 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2636 * for scsi commands
2637 * @lrbp: local reference block pointer
2638 * @upiu_flags: flags
2639 */
2640 static
2641 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2642 {
2643 struct scsi_cmnd *cmd = lrbp->cmd;
2644 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2645 unsigned short cdb_len;
2646
2647 /* command descriptor fields */
2648 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2649 UPIU_TRANSACTION_COMMAND, upiu_flags,
2650 lrbp->lun, lrbp->task_tag);
2651 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2652 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2653
2654 /* Total EHS length and Data segment length will be zero */
2655 ucd_req_ptr->header.dword_2 = 0;
2656
2657 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2658
2659 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2660 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2661 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2662
2663 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2664 }
2665
2666 /**
2667 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2668 * @hba: UFS hba
2669 * @lrbp: local reference block pointer
2670 * @upiu_flags: flags
2671 */
2672 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2673 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2674 {
2675 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2676 struct ufs_query *query = &hba->dev_cmd.query;
2677 u16 len = be16_to_cpu(query->request.upiu_req.length);
2678
2679 /* Query request header */
2680 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2681 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2682 lrbp->lun, lrbp->task_tag);
2683 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2684 0, query->request.query_func, 0, 0);
2685
2686 /* Data segment length only need for WRITE_DESC */
2687 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2688 ucd_req_ptr->header.dword_2 =
2689 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2690 else
2691 ucd_req_ptr->header.dword_2 = 0;
2692
2693 /* Copy the Query Request buffer as is */
2694 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2695 QUERY_OSF_SIZE);
2696
2697 /* Copy the Descriptor */
2698 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2699 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2700
2701 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2702 }
2703
2704 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2705 {
2706 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2707
2708 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2709
2710 /* command descriptor fields */
2711 ucd_req_ptr->header.dword_0 =
2712 UPIU_HEADER_DWORD(
2713 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2714 /* clear rest of the fields of basic header */
2715 ucd_req_ptr->header.dword_1 = 0;
2716 ucd_req_ptr->header.dword_2 = 0;
2717
2718 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2719 }
2720
2721 /**
2722 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2723 * for Device Management Purposes
2724 * @hba: per adapter instance
2725 * @lrbp: pointer to local reference block
2726 */
2727 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2728 struct ufshcd_lrb *lrbp)
2729 {
2730 u8 upiu_flags;
2731 int ret = 0;
2732
2733 if (hba->ufs_version <= ufshci_version(1, 1))
2734 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2735 else
2736 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2737
2738 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
2739 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2740 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2741 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2742 ufshcd_prepare_utp_nop_upiu(lrbp);
2743 else
2744 ret = -EINVAL;
2745
2746 return ret;
2747 }
2748
2749 /**
2750 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2751 * for SCSI Purposes
2752 * @hba: per adapter instance
2753 * @lrbp: pointer to local reference block
2754 */
2755 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2756 {
2757 u8 upiu_flags;
2758 int ret = 0;
2759
2760 if (hba->ufs_version <= ufshci_version(1, 1))
2761 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2762 else
2763 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2764
2765 if (likely(lrbp->cmd)) {
2766 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, lrbp->cmd->sc_data_direction, 0);
2767 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2768 } else {
2769 ret = -EINVAL;
2770 }
2771
2772 return ret;
2773 }
2774
2775 /**
2776 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2777 * @upiu_wlun_id: UPIU W-LUN id
2778 *
2779 * Returns SCSI W-LUN id
2780 */
2781 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2782 {
2783 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2784 }
2785
2786 static inline bool is_device_wlun(struct scsi_device *sdev)
2787 {
2788 return sdev->lun ==
2789 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2790 }
2791
2792 /*
2793 * Associate the UFS controller queue with the default and poll HCTX types.
2794 * Initialize the mq_map[] arrays.
2795 */
2796 static void ufshcd_map_queues(struct Scsi_Host *shost)
2797 {
2798 struct ufs_hba *hba = shost_priv(shost);
2799 int i, queue_offset = 0;
2800
2801 if (!is_mcq_supported(hba)) {
2802 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2803 hba->nr_queues[HCTX_TYPE_READ] = 0;
2804 hba->nr_queues[HCTX_TYPE_POLL] = 1;
2805 hba->nr_hw_queues = 1;
2806 }
2807
2808 for (i = 0; i < shost->nr_maps; i++) {
2809 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2810
2811 map->nr_queues = hba->nr_queues[i];
2812 if (!map->nr_queues)
2813 continue;
2814 map->queue_offset = queue_offset;
2815 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
2816 map->queue_offset = 0;
2817
2818 blk_mq_map_queues(map);
2819 queue_offset += map->nr_queues;
2820 }
2821 }
2822
2823 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2824 {
2825 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2826 i * sizeof_utp_transfer_cmd_desc(hba);
2827 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2828 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2829 i * sizeof_utp_transfer_cmd_desc(hba);
2830 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2831 response_upiu);
2832 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2833
2834 lrb->utr_descriptor_ptr = utrdlp + i;
2835 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2836 i * sizeof(struct utp_transfer_req_desc);
2837 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2838 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2839 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2840 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2841 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2842 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2843 }
2844
2845 /**
2846 * ufshcd_queuecommand - main entry point for SCSI requests
2847 * @host: SCSI host pointer
2848 * @cmd: command from SCSI Midlayer
2849 *
2850 * Returns 0 for success, non-zero in case of failure
2851 */
2852 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2853 {
2854 struct ufs_hba *hba = shost_priv(host);
2855 int tag = scsi_cmd_to_rq(cmd)->tag;
2856 struct ufshcd_lrb *lrbp;
2857 int err = 0;
2858 struct ufs_hw_queue *hwq = NULL;
2859
2860 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
2861
2862 /*
2863 * Allows the UFS error handler to wait for prior ufshcd_queuecommand()
2864 * calls.
2865 */
2866 rcu_read_lock();
2867
2868 switch (hba->ufshcd_state) {
2869 case UFSHCD_STATE_OPERATIONAL:
2870 break;
2871 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2872 /*
2873 * SCSI error handler can call ->queuecommand() while UFS error
2874 * handler is in progress. Error interrupts could change the
2875 * state from UFSHCD_STATE_RESET to
2876 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2877 * being issued in that case.
2878 */
2879 if (ufshcd_eh_in_progress(hba)) {
2880 err = SCSI_MLQUEUE_HOST_BUSY;
2881 goto out;
2882 }
2883 break;
2884 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2885 /*
2886 * pm_runtime_get_sync() is used at error handling preparation
2887 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2888 * PM ops, it can never be finished if we let SCSI layer keep
2889 * retrying it, which gets err handler stuck forever. Neither
2890 * can we let the scsi cmd pass through, because UFS is in bad
2891 * state, the scsi cmd may eventually time out, which will get
2892 * err handler blocked for too long. So, just fail the scsi cmd
2893 * sent from PM ops, err handler can recover PM error anyways.
2894 */
2895 if (hba->pm_op_in_progress) {
2896 hba->force_reset = true;
2897 set_host_byte(cmd, DID_BAD_TARGET);
2898 scsi_done(cmd);
2899 goto out;
2900 }
2901 fallthrough;
2902 case UFSHCD_STATE_RESET:
2903 err = SCSI_MLQUEUE_HOST_BUSY;
2904 goto out;
2905 case UFSHCD_STATE_ERROR:
2906 set_host_byte(cmd, DID_ERROR);
2907 scsi_done(cmd);
2908 goto out;
2909 }
2910
2911 hba->req_abort_count = 0;
2912
2913 err = ufshcd_hold(hba, true);
2914 if (err) {
2915 err = SCSI_MLQUEUE_HOST_BUSY;
2916 goto out;
2917 }
2918 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2919 (hba->clk_gating.state != CLKS_ON));
2920
2921 lrbp = &hba->lrb[tag];
2922 WARN_ON(lrbp->cmd);
2923 lrbp->cmd = cmd;
2924 lrbp->task_tag = tag;
2925 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2926 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2927
2928 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
2929
2930 lrbp->req_abort_skip = false;
2931
2932 ufshpb_prep(hba, lrbp);
2933
2934 ufshcd_comp_scsi_upiu(hba, lrbp);
2935
2936 err = ufshcd_map_sg(hba, lrbp);
2937 if (err) {
2938 lrbp->cmd = NULL;
2939 ufshcd_release(hba);
2940 goto out;
2941 }
2942
2943 if (is_mcq_enabled(hba))
2944 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
2945
2946 ufshcd_send_command(hba, tag, hwq);
2947
2948 out:
2949 rcu_read_unlock();
2950
2951 if (ufs_trigger_eh()) {
2952 unsigned long flags;
2953
2954 spin_lock_irqsave(hba->host->host_lock, flags);
2955 ufshcd_schedule_eh_work(hba);
2956 spin_unlock_irqrestore(hba->host->host_lock, flags);
2957 }
2958
2959 return err;
2960 }
2961
2962 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2963 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2964 {
2965 lrbp->cmd = NULL;
2966 lrbp->task_tag = tag;
2967 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2968 lrbp->intr_cmd = true; /* No interrupt aggregation */
2969 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2970 hba->dev_cmd.type = cmd_type;
2971
2972 return ufshcd_compose_devman_upiu(hba, lrbp);
2973 }
2974
2975 /*
2976 * Clear all the requests from the controller for which a bit has been set in
2977 * @mask and wait until the controller confirms that these requests have been
2978 * cleared.
2979 */
2980 static int ufshcd_clear_cmds(struct ufs_hba *hba, u32 mask)
2981 {
2982 unsigned long flags;
2983
2984 /* clear outstanding transaction before retry */
2985 spin_lock_irqsave(hba->host->host_lock, flags);
2986 ufshcd_utrl_clear(hba, mask);
2987 spin_unlock_irqrestore(hba->host->host_lock, flags);
2988
2989 /*
2990 * wait for h/w to clear corresponding bit in door-bell.
2991 * max. wait is 1 sec.
2992 */
2993 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
2994 mask, ~mask, 1000, 1000);
2995 }
2996
2997 static int
2998 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2999 {
3000 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
3001
3002 /* Get the UPIU response */
3003 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
3004 UPIU_RSP_CODE_OFFSET;
3005 return query_res->response;
3006 }
3007
3008 /**
3009 * ufshcd_dev_cmd_completion() - handles device management command responses
3010 * @hba: per adapter instance
3011 * @lrbp: pointer to local reference block
3012 */
3013 static int
3014 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3015 {
3016 int resp;
3017 int err = 0;
3018
3019 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
3020 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3021
3022 switch (resp) {
3023 case UPIU_TRANSACTION_NOP_IN:
3024 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3025 err = -EINVAL;
3026 dev_err(hba->dev, "%s: unexpected response %x\n",
3027 __func__, resp);
3028 }
3029 break;
3030 case UPIU_TRANSACTION_QUERY_RSP:
3031 err = ufshcd_check_query_response(hba, lrbp);
3032 if (!err)
3033 err = ufshcd_copy_query_response(hba, lrbp);
3034 break;
3035 case UPIU_TRANSACTION_REJECT_UPIU:
3036 /* TODO: handle Reject UPIU Response */
3037 err = -EPERM;
3038 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3039 __func__);
3040 break;
3041 case UPIU_TRANSACTION_RESPONSE:
3042 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3043 err = -EINVAL;
3044 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3045 }
3046 break;
3047 default:
3048 err = -EINVAL;
3049 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3050 __func__, resp);
3051 break;
3052 }
3053
3054 return err;
3055 }
3056
3057 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
3058 struct ufshcd_lrb *lrbp, int max_timeout)
3059 {
3060 unsigned long time_left = msecs_to_jiffies(max_timeout);
3061 unsigned long flags;
3062 bool pending;
3063 int err;
3064
3065 retry:
3066 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
3067 time_left);
3068
3069 if (likely(time_left)) {
3070 /*
3071 * The completion handler called complete() and the caller of
3072 * this function still owns the @lrbp tag so the code below does
3073 * not trigger any race conditions.
3074 */
3075 hba->dev_cmd.complete = NULL;
3076 err = ufshcd_get_tr_ocs(lrbp, hba->dev_cmd.cqe);
3077 if (!err)
3078 err = ufshcd_dev_cmd_completion(hba, lrbp);
3079 } else {
3080 err = -ETIMEDOUT;
3081 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3082 __func__, lrbp->task_tag);
3083 if (ufshcd_clear_cmds(hba, 1U << lrbp->task_tag) == 0) {
3084 /* successfully cleared the command, retry if needed */
3085 err = -EAGAIN;
3086 /*
3087 * Since clearing the command succeeded we also need to
3088 * clear the task tag bit from the outstanding_reqs
3089 * variable.
3090 */
3091 spin_lock_irqsave(&hba->outstanding_lock, flags);
3092 pending = test_bit(lrbp->task_tag,
3093 &hba->outstanding_reqs);
3094 if (pending) {
3095 hba->dev_cmd.complete = NULL;
3096 __clear_bit(lrbp->task_tag,
3097 &hba->outstanding_reqs);
3098 }
3099 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3100
3101 if (!pending) {
3102 /*
3103 * The completion handler ran while we tried to
3104 * clear the command.
3105 */
3106 time_left = 1;
3107 goto retry;
3108 }
3109 } else {
3110 dev_err(hba->dev, "%s: failed to clear tag %d\n",
3111 __func__, lrbp->task_tag);
3112
3113 spin_lock_irqsave(&hba->outstanding_lock, flags);
3114 pending = test_bit(lrbp->task_tag,
3115 &hba->outstanding_reqs);
3116 if (pending)
3117 hba->dev_cmd.complete = NULL;
3118 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3119
3120 if (!pending) {
3121 /*
3122 * The completion handler ran while we tried to
3123 * clear the command.
3124 */
3125 time_left = 1;
3126 goto retry;
3127 }
3128 }
3129 }
3130
3131 return err;
3132 }
3133
3134 /**
3135 * ufshcd_exec_dev_cmd - API for sending device management requests
3136 * @hba: UFS hba
3137 * @cmd_type: specifies the type (NOP, Query...)
3138 * @timeout: timeout in milliseconds
3139 *
3140 * NOTE: Since there is only one available tag for device management commands,
3141 * it is expected you hold the hba->dev_cmd.lock mutex.
3142 */
3143 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3144 enum dev_cmd_type cmd_type, int timeout)
3145 {
3146 DECLARE_COMPLETION_ONSTACK(wait);
3147 const u32 tag = hba->reserved_slot;
3148 struct ufshcd_lrb *lrbp;
3149 int err;
3150
3151 /* Protects use of hba->reserved_slot. */
3152 lockdep_assert_held(&hba->dev_cmd.lock);
3153
3154 down_read(&hba->clk_scaling_lock);
3155
3156 lrbp = &hba->lrb[tag];
3157 WARN_ON(lrbp->cmd);
3158 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3159 if (unlikely(err))
3160 goto out;
3161
3162 hba->dev_cmd.complete = &wait;
3163 hba->dev_cmd.cqe = NULL;
3164
3165 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3166
3167 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
3168 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3169 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3170 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3171
3172 out:
3173 up_read(&hba->clk_scaling_lock);
3174 return err;
3175 }
3176
3177 /**
3178 * ufshcd_init_query() - init the query response and request parameters
3179 * @hba: per-adapter instance
3180 * @request: address of the request pointer to be initialized
3181 * @response: address of the response pointer to be initialized
3182 * @opcode: operation to perform
3183 * @idn: flag idn to access
3184 * @index: LU number to access
3185 * @selector: query/flag/descriptor further identification
3186 */
3187 static inline void ufshcd_init_query(struct ufs_hba *hba,
3188 struct ufs_query_req **request, struct ufs_query_res **response,
3189 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3190 {
3191 *request = &hba->dev_cmd.query.request;
3192 *response = &hba->dev_cmd.query.response;
3193 memset(*request, 0, sizeof(struct ufs_query_req));
3194 memset(*response, 0, sizeof(struct ufs_query_res));
3195 (*request)->upiu_req.opcode = opcode;
3196 (*request)->upiu_req.idn = idn;
3197 (*request)->upiu_req.index = index;
3198 (*request)->upiu_req.selector = selector;
3199 }
3200
3201 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3202 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3203 {
3204 int ret;
3205 int retries;
3206
3207 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3208 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3209 if (ret)
3210 dev_dbg(hba->dev,
3211 "%s: failed with error %d, retries %d\n",
3212 __func__, ret, retries);
3213 else
3214 break;
3215 }
3216
3217 if (ret)
3218 dev_err(hba->dev,
3219 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3220 __func__, opcode, idn, ret, retries);
3221 return ret;
3222 }
3223
3224 /**
3225 * ufshcd_query_flag() - API function for sending flag query requests
3226 * @hba: per-adapter instance
3227 * @opcode: flag query to perform
3228 * @idn: flag idn to access
3229 * @index: flag index to access
3230 * @flag_res: the flag value after the query request completes
3231 *
3232 * Returns 0 for success, non-zero in case of failure
3233 */
3234 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3235 enum flag_idn idn, u8 index, bool *flag_res)
3236 {
3237 struct ufs_query_req *request = NULL;
3238 struct ufs_query_res *response = NULL;
3239 int err, selector = 0;
3240 int timeout = QUERY_REQ_TIMEOUT;
3241
3242 BUG_ON(!hba);
3243
3244 ufshcd_hold(hba, false);
3245 mutex_lock(&hba->dev_cmd.lock);
3246 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3247 selector);
3248
3249 switch (opcode) {
3250 case UPIU_QUERY_OPCODE_SET_FLAG:
3251 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3252 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3253 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3254 break;
3255 case UPIU_QUERY_OPCODE_READ_FLAG:
3256 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3257 if (!flag_res) {
3258 /* No dummy reads */
3259 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3260 __func__);
3261 err = -EINVAL;
3262 goto out_unlock;
3263 }
3264 break;
3265 default:
3266 dev_err(hba->dev,
3267 "%s: Expected query flag opcode but got = %d\n",
3268 __func__, opcode);
3269 err = -EINVAL;
3270 goto out_unlock;
3271 }
3272
3273 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3274
3275 if (err) {
3276 dev_err(hba->dev,
3277 "%s: Sending flag query for idn %d failed, err = %d\n",
3278 __func__, idn, err);
3279 goto out_unlock;
3280 }
3281
3282 if (flag_res)
3283 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3284 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3285
3286 out_unlock:
3287 mutex_unlock(&hba->dev_cmd.lock);
3288 ufshcd_release(hba);
3289 return err;
3290 }
3291
3292 /**
3293 * ufshcd_query_attr - API function for sending attribute requests
3294 * @hba: per-adapter instance
3295 * @opcode: attribute opcode
3296 * @idn: attribute idn to access
3297 * @index: index field
3298 * @selector: selector field
3299 * @attr_val: the attribute value after the query request completes
3300 *
3301 * Returns 0 for success, non-zero in case of failure
3302 */
3303 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3304 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3305 {
3306 struct ufs_query_req *request = NULL;
3307 struct ufs_query_res *response = NULL;
3308 int err;
3309
3310 BUG_ON(!hba);
3311
3312 if (!attr_val) {
3313 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3314 __func__, opcode);
3315 return -EINVAL;
3316 }
3317
3318 ufshcd_hold(hba, false);
3319
3320 mutex_lock(&hba->dev_cmd.lock);
3321 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3322 selector);
3323
3324 switch (opcode) {
3325 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3326 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3327 request->upiu_req.value = cpu_to_be32(*attr_val);
3328 break;
3329 case UPIU_QUERY_OPCODE_READ_ATTR:
3330 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3331 break;
3332 default:
3333 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3334 __func__, opcode);
3335 err = -EINVAL;
3336 goto out_unlock;
3337 }
3338
3339 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3340
3341 if (err) {
3342 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3343 __func__, opcode, idn, index, err);
3344 goto out_unlock;
3345 }
3346
3347 *attr_val = be32_to_cpu(response->upiu_res.value);
3348
3349 out_unlock:
3350 mutex_unlock(&hba->dev_cmd.lock);
3351 ufshcd_release(hba);
3352 return err;
3353 }
3354
3355 /**
3356 * ufshcd_query_attr_retry() - API function for sending query
3357 * attribute with retries
3358 * @hba: per-adapter instance
3359 * @opcode: attribute opcode
3360 * @idn: attribute idn to access
3361 * @index: index field
3362 * @selector: selector field
3363 * @attr_val: the attribute value after the query request
3364 * completes
3365 *
3366 * Returns 0 for success, non-zero in case of failure
3367 */
3368 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3369 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3370 u32 *attr_val)
3371 {
3372 int ret = 0;
3373 u32 retries;
3374
3375 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3376 ret = ufshcd_query_attr(hba, opcode, idn, index,
3377 selector, attr_val);
3378 if (ret)
3379 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3380 __func__, ret, retries);
3381 else
3382 break;
3383 }
3384
3385 if (ret)
3386 dev_err(hba->dev,
3387 "%s: query attribute, idn %d, failed with error %d after %d retries\n",
3388 __func__, idn, ret, QUERY_REQ_RETRIES);
3389 return ret;
3390 }
3391
3392 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3393 enum query_opcode opcode, enum desc_idn idn, u8 index,
3394 u8 selector, u8 *desc_buf, int *buf_len)
3395 {
3396 struct ufs_query_req *request = NULL;
3397 struct ufs_query_res *response = NULL;
3398 int err;
3399
3400 BUG_ON(!hba);
3401
3402 if (!desc_buf) {
3403 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3404 __func__, opcode);
3405 return -EINVAL;
3406 }
3407
3408 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3409 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3410 __func__, *buf_len);
3411 return -EINVAL;
3412 }
3413
3414 ufshcd_hold(hba, false);
3415
3416 mutex_lock(&hba->dev_cmd.lock);
3417 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3418 selector);
3419 hba->dev_cmd.query.descriptor = desc_buf;
3420 request->upiu_req.length = cpu_to_be16(*buf_len);
3421
3422 switch (opcode) {
3423 case UPIU_QUERY_OPCODE_WRITE_DESC:
3424 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3425 break;
3426 case UPIU_QUERY_OPCODE_READ_DESC:
3427 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3428 break;
3429 default:
3430 dev_err(hba->dev,
3431 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3432 __func__, opcode);
3433 err = -EINVAL;
3434 goto out_unlock;
3435 }
3436
3437 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3438
3439 if (err) {
3440 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3441 __func__, opcode, idn, index, err);
3442 goto out_unlock;
3443 }
3444
3445 *buf_len = be16_to_cpu(response->upiu_res.length);
3446
3447 out_unlock:
3448 hba->dev_cmd.query.descriptor = NULL;
3449 mutex_unlock(&hba->dev_cmd.lock);
3450 ufshcd_release(hba);
3451 return err;
3452 }
3453
3454 /**
3455 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3456 * @hba: per-adapter instance
3457 * @opcode: attribute opcode
3458 * @idn: attribute idn to access
3459 * @index: index field
3460 * @selector: selector field
3461 * @desc_buf: the buffer that contains the descriptor
3462 * @buf_len: length parameter passed to the device
3463 *
3464 * Returns 0 for success, non-zero in case of failure.
3465 * The buf_len parameter will contain, on return, the length parameter
3466 * received on the response.
3467 */
3468 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3469 enum query_opcode opcode,
3470 enum desc_idn idn, u8 index,
3471 u8 selector,
3472 u8 *desc_buf, int *buf_len)
3473 {
3474 int err;
3475 int retries;
3476
3477 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3478 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3479 selector, desc_buf, buf_len);
3480 if (!err || err == -EINVAL)
3481 break;
3482 }
3483
3484 return err;
3485 }
3486
3487 /**
3488 * ufshcd_read_desc_param - read the specified descriptor parameter
3489 * @hba: Pointer to adapter instance
3490 * @desc_id: descriptor idn value
3491 * @desc_index: descriptor index
3492 * @param_offset: offset of the parameter to read
3493 * @param_read_buf: pointer to buffer where parameter would be read
3494 * @param_size: sizeof(param_read_buf)
3495 *
3496 * Return 0 in case of success, non-zero otherwise
3497 */
3498 int ufshcd_read_desc_param(struct ufs_hba *hba,
3499 enum desc_idn desc_id,
3500 int desc_index,
3501 u8 param_offset,
3502 u8 *param_read_buf,
3503 u8 param_size)
3504 {
3505 int ret;
3506 u8 *desc_buf;
3507 int buff_len = QUERY_DESC_MAX_SIZE;
3508 bool is_kmalloc = true;
3509
3510 /* Safety check */
3511 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3512 return -EINVAL;
3513
3514 /* Check whether we need temp memory */
3515 if (param_offset != 0 || param_size < buff_len) {
3516 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3517 if (!desc_buf)
3518 return -ENOMEM;
3519 } else {
3520 desc_buf = param_read_buf;
3521 is_kmalloc = false;
3522 }
3523
3524 /* Request for full descriptor */
3525 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3526 desc_id, desc_index, 0,
3527 desc_buf, &buff_len);
3528 if (ret) {
3529 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3530 __func__, desc_id, desc_index, param_offset, ret);
3531 goto out;
3532 }
3533
3534 /* Update descriptor length */
3535 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3536
3537 if (param_offset >= buff_len) {
3538 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3539 __func__, param_offset, desc_id, buff_len);
3540 ret = -EINVAL;
3541 goto out;
3542 }
3543
3544 /* Sanity check */
3545 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3546 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3547 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3548 ret = -EINVAL;
3549 goto out;
3550 }
3551
3552 if (is_kmalloc) {
3553 /* Make sure we don't copy more data than available */
3554 if (param_offset >= buff_len)
3555 ret = -EINVAL;
3556 else
3557 memcpy(param_read_buf, &desc_buf[param_offset],
3558 min_t(u32, param_size, buff_len - param_offset));
3559 }
3560 out:
3561 if (is_kmalloc)
3562 kfree(desc_buf);
3563 return ret;
3564 }
3565
3566 /**
3567 * struct uc_string_id - unicode string
3568 *
3569 * @len: size of this descriptor inclusive
3570 * @type: descriptor type
3571 * @uc: unicode string character
3572 */
3573 struct uc_string_id {
3574 u8 len;
3575 u8 type;
3576 wchar_t uc[];
3577 } __packed;
3578
3579 /* replace non-printable or non-ASCII characters with spaces */
3580 static inline char ufshcd_remove_non_printable(u8 ch)
3581 {
3582 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3583 }
3584
3585 /**
3586 * ufshcd_read_string_desc - read string descriptor
3587 * @hba: pointer to adapter instance
3588 * @desc_index: descriptor index
3589 * @buf: pointer to buffer where descriptor would be read,
3590 * the caller should free the memory.
3591 * @ascii: if true convert from unicode to ascii characters
3592 * null terminated string.
3593 *
3594 * Return:
3595 * * string size on success.
3596 * * -ENOMEM: on allocation failure
3597 * * -EINVAL: on a wrong parameter
3598 */
3599 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3600 u8 **buf, bool ascii)
3601 {
3602 struct uc_string_id *uc_str;
3603 u8 *str;
3604 int ret;
3605
3606 if (!buf)
3607 return -EINVAL;
3608
3609 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3610 if (!uc_str)
3611 return -ENOMEM;
3612
3613 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3614 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3615 if (ret < 0) {
3616 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3617 QUERY_REQ_RETRIES, ret);
3618 str = NULL;
3619 goto out;
3620 }
3621
3622 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3623 dev_dbg(hba->dev, "String Desc is of zero length\n");
3624 str = NULL;
3625 ret = 0;
3626 goto out;
3627 }
3628
3629 if (ascii) {
3630 ssize_t ascii_len;
3631 int i;
3632 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3633 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3634 str = kzalloc(ascii_len, GFP_KERNEL);
3635 if (!str) {
3636 ret = -ENOMEM;
3637 goto out;
3638 }
3639
3640 /*
3641 * the descriptor contains string in UTF16 format
3642 * we need to convert to utf-8 so it can be displayed
3643 */
3644 ret = utf16s_to_utf8s(uc_str->uc,
3645 uc_str->len - QUERY_DESC_HDR_SIZE,
3646 UTF16_BIG_ENDIAN, str, ascii_len);
3647
3648 /* replace non-printable or non-ASCII characters with spaces */
3649 for (i = 0; i < ret; i++)
3650 str[i] = ufshcd_remove_non_printable(str[i]);
3651
3652 str[ret++] = '\0';
3653
3654 } else {
3655 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3656 if (!str) {
3657 ret = -ENOMEM;
3658 goto out;
3659 }
3660 ret = uc_str->len;
3661 }
3662 out:
3663 *buf = str;
3664 kfree(uc_str);
3665 return ret;
3666 }
3667
3668 /**
3669 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3670 * @hba: Pointer to adapter instance
3671 * @lun: lun id
3672 * @param_offset: offset of the parameter to read
3673 * @param_read_buf: pointer to buffer where parameter would be read
3674 * @param_size: sizeof(param_read_buf)
3675 *
3676 * Return 0 in case of success, non-zero otherwise
3677 */
3678 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3679 int lun,
3680 enum unit_desc_param param_offset,
3681 u8 *param_read_buf,
3682 u32 param_size)
3683 {
3684 /*
3685 * Unit descriptors are only available for general purpose LUs (LUN id
3686 * from 0 to 7) and RPMB Well known LU.
3687 */
3688 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3689 return -EOPNOTSUPP;
3690
3691 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3692 param_offset, param_read_buf, param_size);
3693 }
3694
3695 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3696 {
3697 int err = 0;
3698 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3699
3700 if (hba->dev_info.wspecversion >= 0x300) {
3701 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3702 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3703 &gating_wait);
3704 if (err)
3705 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3706 err, gating_wait);
3707
3708 if (gating_wait == 0) {
3709 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3710 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3711 gating_wait);
3712 }
3713
3714 hba->dev_info.clk_gating_wait_us = gating_wait;
3715 }
3716
3717 return err;
3718 }
3719
3720 /**
3721 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3722 * @hba: per adapter instance
3723 *
3724 * 1. Allocate DMA memory for Command Descriptor array
3725 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3726 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3727 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3728 * (UTMRDL)
3729 * 4. Allocate memory for local reference block(lrb).
3730 *
3731 * Returns 0 for success, non-zero in case of failure
3732 */
3733 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3734 {
3735 size_t utmrdl_size, utrdl_size, ucdl_size;
3736
3737 /* Allocate memory for UTP command descriptors */
3738 ucdl_size = sizeof_utp_transfer_cmd_desc(hba) * hba->nutrs;
3739 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3740 ucdl_size,
3741 &hba->ucdl_dma_addr,
3742 GFP_KERNEL);
3743
3744 /*
3745 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3746 */
3747 if (!hba->ucdl_base_addr ||
3748 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3749 dev_err(hba->dev,
3750 "Command Descriptor Memory allocation failed\n");
3751 goto out;
3752 }
3753
3754 /*
3755 * Allocate memory for UTP Transfer descriptors
3756 * UFSHCI requires 1024 byte alignment of UTRD
3757 */
3758 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3759 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3760 utrdl_size,
3761 &hba->utrdl_dma_addr,
3762 GFP_KERNEL);
3763 if (!hba->utrdl_base_addr ||
3764 WARN_ON(hba->utrdl_dma_addr & (1024 - 1))) {
3765 dev_err(hba->dev,
3766 "Transfer Descriptor Memory allocation failed\n");
3767 goto out;
3768 }
3769
3770 /*
3771 * Skip utmrdl allocation; it may have been
3772 * allocated during first pass and not released during
3773 * MCQ memory allocation.
3774 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3775 */
3776 if (hba->utmrdl_base_addr)
3777 goto skip_utmrdl;
3778 /*
3779 * Allocate memory for UTP Task Management descriptors
3780 * UFSHCI requires 1024 byte alignment of UTMRD
3781 */
3782 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3783 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3784 utmrdl_size,
3785 &hba->utmrdl_dma_addr,
3786 GFP_KERNEL);
3787 if (!hba->utmrdl_base_addr ||
3788 WARN_ON(hba->utmrdl_dma_addr & (1024 - 1))) {
3789 dev_err(hba->dev,
3790 "Task Management Descriptor Memory allocation failed\n");
3791 goto out;
3792 }
3793
3794 skip_utmrdl:
3795 /* Allocate memory for local reference block */
3796 hba->lrb = devm_kcalloc(hba->dev,
3797 hba->nutrs, sizeof(struct ufshcd_lrb),
3798 GFP_KERNEL);
3799 if (!hba->lrb) {
3800 dev_err(hba->dev, "LRB Memory allocation failed\n");
3801 goto out;
3802 }
3803 return 0;
3804 out:
3805 return -ENOMEM;
3806 }
3807
3808 /**
3809 * ufshcd_host_memory_configure - configure local reference block with
3810 * memory offsets
3811 * @hba: per adapter instance
3812 *
3813 * Configure Host memory space
3814 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3815 * address.
3816 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3817 * and PRDT offset.
3818 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3819 * into local reference block.
3820 */
3821 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3822 {
3823 struct utp_transfer_req_desc *utrdlp;
3824 dma_addr_t cmd_desc_dma_addr;
3825 dma_addr_t cmd_desc_element_addr;
3826 u16 response_offset;
3827 u16 prdt_offset;
3828 int cmd_desc_size;
3829 int i;
3830
3831 utrdlp = hba->utrdl_base_addr;
3832
3833 response_offset =
3834 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3835 prdt_offset =
3836 offsetof(struct utp_transfer_cmd_desc, prd_table);
3837
3838 cmd_desc_size = sizeof_utp_transfer_cmd_desc(hba);
3839 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3840
3841 for (i = 0; i < hba->nutrs; i++) {
3842 /* Configure UTRD with command descriptor base address */
3843 cmd_desc_element_addr =
3844 (cmd_desc_dma_addr + (cmd_desc_size * i));
3845 utrdlp[i].command_desc_base_addr_lo =
3846 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3847 utrdlp[i].command_desc_base_addr_hi =
3848 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3849
3850 /* Response upiu and prdt offset should be in double words */
3851 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3852 utrdlp[i].response_upiu_offset =
3853 cpu_to_le16(response_offset);
3854 utrdlp[i].prd_table_offset =
3855 cpu_to_le16(prdt_offset);
3856 utrdlp[i].response_upiu_length =
3857 cpu_to_le16(ALIGNED_UPIU_SIZE);
3858 } else {
3859 utrdlp[i].response_upiu_offset =
3860 cpu_to_le16(response_offset >> 2);
3861 utrdlp[i].prd_table_offset =
3862 cpu_to_le16(prdt_offset >> 2);
3863 utrdlp[i].response_upiu_length =
3864 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3865 }
3866
3867 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3868 }
3869 }
3870
3871 /**
3872 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3873 * @hba: per adapter instance
3874 *
3875 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3876 * in order to initialize the Unipro link startup procedure.
3877 * Once the Unipro links are up, the device connected to the controller
3878 * is detected.
3879 *
3880 * Returns 0 on success, non-zero value on failure
3881 */
3882 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3883 {
3884 struct uic_command uic_cmd = {0};
3885 int ret;
3886
3887 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3888
3889 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3890 if (ret)
3891 dev_dbg(hba->dev,
3892 "dme-link-startup: error code %d\n", ret);
3893 return ret;
3894 }
3895 /**
3896 * ufshcd_dme_reset - UIC command for DME_RESET
3897 * @hba: per adapter instance
3898 *
3899 * DME_RESET command is issued in order to reset UniPro stack.
3900 * This function now deals with cold reset.
3901 *
3902 * Returns 0 on success, non-zero value on failure
3903 */
3904 static int ufshcd_dme_reset(struct ufs_hba *hba)
3905 {
3906 struct uic_command uic_cmd = {0};
3907 int ret;
3908
3909 uic_cmd.command = UIC_CMD_DME_RESET;
3910
3911 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3912 if (ret)
3913 dev_err(hba->dev,
3914 "dme-reset: error code %d\n", ret);
3915
3916 return ret;
3917 }
3918
3919 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3920 int agreed_gear,
3921 int adapt_val)
3922 {
3923 int ret;
3924
3925 if (agreed_gear < UFS_HS_G4)
3926 adapt_val = PA_NO_ADAPT;
3927
3928 ret = ufshcd_dme_set(hba,
3929 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3930 adapt_val);
3931 return ret;
3932 }
3933 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3934
3935 /**
3936 * ufshcd_dme_enable - UIC command for DME_ENABLE
3937 * @hba: per adapter instance
3938 *
3939 * DME_ENABLE command is issued in order to enable UniPro stack.
3940 *
3941 * Returns 0 on success, non-zero value on failure
3942 */
3943 static int ufshcd_dme_enable(struct ufs_hba *hba)
3944 {
3945 struct uic_command uic_cmd = {0};
3946 int ret;
3947
3948 uic_cmd.command = UIC_CMD_DME_ENABLE;
3949
3950 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3951 if (ret)
3952 dev_err(hba->dev,
3953 "dme-enable: error code %d\n", ret);
3954
3955 return ret;
3956 }
3957
3958 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3959 {
3960 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3961 unsigned long min_sleep_time_us;
3962
3963 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3964 return;
3965
3966 /*
3967 * last_dme_cmd_tstamp will be 0 only for 1st call to
3968 * this function
3969 */
3970 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3971 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3972 } else {
3973 unsigned long delta =
3974 (unsigned long) ktime_to_us(
3975 ktime_sub(ktime_get(),
3976 hba->last_dme_cmd_tstamp));
3977
3978 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3979 min_sleep_time_us =
3980 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3981 else
3982 return; /* no more delay required */
3983 }
3984
3985 /* allow sleep for extra 50us if needed */
3986 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3987 }
3988
3989 /**
3990 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3991 * @hba: per adapter instance
3992 * @attr_sel: uic command argument1
3993 * @attr_set: attribute set type as uic command argument2
3994 * @mib_val: setting value as uic command argument3
3995 * @peer: indicate whether peer or local
3996 *
3997 * Returns 0 on success, non-zero value on failure
3998 */
3999 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
4000 u8 attr_set, u32 mib_val, u8 peer)
4001 {
4002 struct uic_command uic_cmd = {0};
4003 static const char *const action[] = {
4004 "dme-set",
4005 "dme-peer-set"
4006 };
4007 const char *set = action[!!peer];
4008 int ret;
4009 int retries = UFS_UIC_COMMAND_RETRIES;
4010
4011 uic_cmd.command = peer ?
4012 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
4013 uic_cmd.argument1 = attr_sel;
4014 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
4015 uic_cmd.argument3 = mib_val;
4016
4017 do {
4018 /* for peer attributes we retry upon failure */
4019 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4020 if (ret)
4021 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4022 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4023 } while (ret && peer && --retries);
4024
4025 if (ret)
4026 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4027 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4028 UFS_UIC_COMMAND_RETRIES - retries);
4029
4030 return ret;
4031 }
4032 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4033
4034 /**
4035 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4036 * @hba: per adapter instance
4037 * @attr_sel: uic command argument1
4038 * @mib_val: the value of the attribute as returned by the UIC command
4039 * @peer: indicate whether peer or local
4040 *
4041 * Returns 0 on success, non-zero value on failure
4042 */
4043 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4044 u32 *mib_val, u8 peer)
4045 {
4046 struct uic_command uic_cmd = {0};
4047 static const char *const action[] = {
4048 "dme-get",
4049 "dme-peer-get"
4050 };
4051 const char *get = action[!!peer];
4052 int ret;
4053 int retries = UFS_UIC_COMMAND_RETRIES;
4054 struct ufs_pa_layer_attr orig_pwr_info;
4055 struct ufs_pa_layer_attr temp_pwr_info;
4056 bool pwr_mode_change = false;
4057
4058 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4059 orig_pwr_info = hba->pwr_info;
4060 temp_pwr_info = orig_pwr_info;
4061
4062 if (orig_pwr_info.pwr_tx == FAST_MODE ||
4063 orig_pwr_info.pwr_rx == FAST_MODE) {
4064 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4065 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4066 pwr_mode_change = true;
4067 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4068 orig_pwr_info.pwr_rx == SLOW_MODE) {
4069 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4070 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4071 pwr_mode_change = true;
4072 }
4073 if (pwr_mode_change) {
4074 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
4075 if (ret)
4076 goto out;
4077 }
4078 }
4079
4080 uic_cmd.command = peer ?
4081 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
4082 uic_cmd.argument1 = attr_sel;
4083
4084 do {
4085 /* for peer attributes we retry upon failure */
4086 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4087 if (ret)
4088 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4089 get, UIC_GET_ATTR_ID(attr_sel), ret);
4090 } while (ret && peer && --retries);
4091
4092 if (ret)
4093 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4094 get, UIC_GET_ATTR_ID(attr_sel),
4095 UFS_UIC_COMMAND_RETRIES - retries);
4096
4097 if (mib_val && !ret)
4098 *mib_val = uic_cmd.argument3;
4099
4100 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4101 && pwr_mode_change)
4102 ufshcd_change_power_mode(hba, &orig_pwr_info);
4103 out:
4104 return ret;
4105 }
4106 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4107
4108 /**
4109 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4110 * state) and waits for it to take effect.
4111 *
4112 * @hba: per adapter instance
4113 * @cmd: UIC command to execute
4114 *
4115 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4116 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4117 * and device UniPro link and hence it's final completion would be indicated by
4118 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4119 * addition to normal UIC command completion Status (UCCS). This function only
4120 * returns after the relevant status bits indicate the completion.
4121 *
4122 * Returns 0 on success, non-zero value on failure
4123 */
4124 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4125 {
4126 DECLARE_COMPLETION_ONSTACK(uic_async_done);
4127 unsigned long flags;
4128 u8 status;
4129 int ret;
4130 bool reenable_intr = false;
4131
4132 mutex_lock(&hba->uic_cmd_mutex);
4133 ufshcd_add_delay_before_dme_cmd(hba);
4134
4135 spin_lock_irqsave(hba->host->host_lock, flags);
4136 if (ufshcd_is_link_broken(hba)) {
4137 ret = -ENOLINK;
4138 goto out_unlock;
4139 }
4140 hba->uic_async_done = &uic_async_done;
4141 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4142 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4143 /*
4144 * Make sure UIC command completion interrupt is disabled before
4145 * issuing UIC command.
4146 */
4147 wmb();
4148 reenable_intr = true;
4149 }
4150 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4151 spin_unlock_irqrestore(hba->host->host_lock, flags);
4152 if (ret) {
4153 dev_err(hba->dev,
4154 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4155 cmd->command, cmd->argument3, ret);
4156 goto out;
4157 }
4158
4159 if (!wait_for_completion_timeout(hba->uic_async_done,
4160 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4161 dev_err(hba->dev,
4162 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4163 cmd->command, cmd->argument3);
4164
4165 if (!cmd->cmd_active) {
4166 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4167 __func__);
4168 goto check_upmcrs;
4169 }
4170
4171 ret = -ETIMEDOUT;
4172 goto out;
4173 }
4174
4175 check_upmcrs:
4176 status = ufshcd_get_upmcrs(hba);
4177 if (status != PWR_LOCAL) {
4178 dev_err(hba->dev,
4179 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4180 cmd->command, status);
4181 ret = (status != PWR_OK) ? status : -1;
4182 }
4183 out:
4184 if (ret) {
4185 ufshcd_print_host_state(hba);
4186 ufshcd_print_pwr_info(hba);
4187 ufshcd_print_evt_hist(hba);
4188 }
4189
4190 spin_lock_irqsave(hba->host->host_lock, flags);
4191 hba->active_uic_cmd = NULL;
4192 hba->uic_async_done = NULL;
4193 if (reenable_intr)
4194 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4195 if (ret) {
4196 ufshcd_set_link_broken(hba);
4197 ufshcd_schedule_eh_work(hba);
4198 }
4199 out_unlock:
4200 spin_unlock_irqrestore(hba->host->host_lock, flags);
4201 mutex_unlock(&hba->uic_cmd_mutex);
4202
4203 return ret;
4204 }
4205
4206 /**
4207 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4208 * using DME_SET primitives.
4209 * @hba: per adapter instance
4210 * @mode: powr mode value
4211 *
4212 * Returns 0 on success, non-zero value on failure
4213 */
4214 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4215 {
4216 struct uic_command uic_cmd = {0};
4217 int ret;
4218
4219 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4220 ret = ufshcd_dme_set(hba,
4221 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4222 if (ret) {
4223 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4224 __func__, ret);
4225 goto out;
4226 }
4227 }
4228
4229 uic_cmd.command = UIC_CMD_DME_SET;
4230 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4231 uic_cmd.argument3 = mode;
4232 ufshcd_hold(hba, false);
4233 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4234 ufshcd_release(hba);
4235
4236 out:
4237 return ret;
4238 }
4239 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4240
4241 int ufshcd_link_recovery(struct ufs_hba *hba)
4242 {
4243 int ret;
4244 unsigned long flags;
4245
4246 spin_lock_irqsave(hba->host->host_lock, flags);
4247 hba->ufshcd_state = UFSHCD_STATE_RESET;
4248 ufshcd_set_eh_in_progress(hba);
4249 spin_unlock_irqrestore(hba->host->host_lock, flags);
4250
4251 /* Reset the attached device */
4252 ufshcd_device_reset(hba);
4253
4254 ret = ufshcd_host_reset_and_restore(hba);
4255
4256 spin_lock_irqsave(hba->host->host_lock, flags);
4257 if (ret)
4258 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4259 ufshcd_clear_eh_in_progress(hba);
4260 spin_unlock_irqrestore(hba->host->host_lock, flags);
4261
4262 if (ret)
4263 dev_err(hba->dev, "%s: link recovery failed, err %d",
4264 __func__, ret);
4265
4266 return ret;
4267 }
4268 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4269
4270 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4271 {
4272 int ret;
4273 struct uic_command uic_cmd = {0};
4274 ktime_t start = ktime_get();
4275
4276 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4277
4278 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4279 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4280 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4281 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4282
4283 if (ret)
4284 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4285 __func__, ret);
4286 else
4287 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4288 POST_CHANGE);
4289
4290 return ret;
4291 }
4292 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4293
4294 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4295 {
4296 struct uic_command uic_cmd = {0};
4297 int ret;
4298 ktime_t start = ktime_get();
4299
4300 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4301
4302 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4303 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4304 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4305 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4306
4307 if (ret) {
4308 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4309 __func__, ret);
4310 } else {
4311 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4312 POST_CHANGE);
4313 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4314 hba->ufs_stats.hibern8_exit_cnt++;
4315 }
4316
4317 return ret;
4318 }
4319 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4320
4321 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4322 {
4323 unsigned long flags;
4324 bool update = false;
4325
4326 if (!ufshcd_is_auto_hibern8_supported(hba))
4327 return;
4328
4329 spin_lock_irqsave(hba->host->host_lock, flags);
4330 if (hba->ahit != ahit) {
4331 hba->ahit = ahit;
4332 update = true;
4333 }
4334 spin_unlock_irqrestore(hba->host->host_lock, flags);
4335
4336 if (update &&
4337 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4338 ufshcd_rpm_get_sync(hba);
4339 ufshcd_hold(hba, false);
4340 ufshcd_auto_hibern8_enable(hba);
4341 ufshcd_release(hba);
4342 ufshcd_rpm_put_sync(hba);
4343 }
4344 }
4345 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4346
4347 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4348 {
4349 if (!ufshcd_is_auto_hibern8_supported(hba))
4350 return;
4351
4352 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4353 }
4354
4355 /**
4356 * ufshcd_init_pwr_info - setting the POR (power on reset)
4357 * values in hba power info
4358 * @hba: per-adapter instance
4359 */
4360 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4361 {
4362 hba->pwr_info.gear_rx = UFS_PWM_G1;
4363 hba->pwr_info.gear_tx = UFS_PWM_G1;
4364 hba->pwr_info.lane_rx = 1;
4365 hba->pwr_info.lane_tx = 1;
4366 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4367 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4368 hba->pwr_info.hs_rate = 0;
4369 }
4370
4371 /**
4372 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4373 * @hba: per-adapter instance
4374 */
4375 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4376 {
4377 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4378
4379 if (hba->max_pwr_info.is_valid)
4380 return 0;
4381
4382 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4383 pwr_info->pwr_tx = FASTAUTO_MODE;
4384 pwr_info->pwr_rx = FASTAUTO_MODE;
4385 } else {
4386 pwr_info->pwr_tx = FAST_MODE;
4387 pwr_info->pwr_rx = FAST_MODE;
4388 }
4389 pwr_info->hs_rate = PA_HS_MODE_B;
4390
4391 /* Get the connected lane count */
4392 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4393 &pwr_info->lane_rx);
4394 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4395 &pwr_info->lane_tx);
4396
4397 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4398 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4399 __func__,
4400 pwr_info->lane_rx,
4401 pwr_info->lane_tx);
4402 return -EINVAL;
4403 }
4404
4405 /*
4406 * First, get the maximum gears of HS speed.
4407 * If a zero value, it means there is no HSGEAR capability.
4408 * Then, get the maximum gears of PWM speed.
4409 */
4410 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4411 if (!pwr_info->gear_rx) {
4412 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4413 &pwr_info->gear_rx);
4414 if (!pwr_info->gear_rx) {
4415 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4416 __func__, pwr_info->gear_rx);
4417 return -EINVAL;
4418 }
4419 pwr_info->pwr_rx = SLOW_MODE;
4420 }
4421
4422 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4423 &pwr_info->gear_tx);
4424 if (!pwr_info->gear_tx) {
4425 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4426 &pwr_info->gear_tx);
4427 if (!pwr_info->gear_tx) {
4428 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4429 __func__, pwr_info->gear_tx);
4430 return -EINVAL;
4431 }
4432 pwr_info->pwr_tx = SLOW_MODE;
4433 }
4434
4435 hba->max_pwr_info.is_valid = true;
4436 return 0;
4437 }
4438
4439 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4440 struct ufs_pa_layer_attr *pwr_mode)
4441 {
4442 int ret;
4443
4444 /* if already configured to the requested pwr_mode */
4445 if (!hba->force_pmc &&
4446 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4447 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4448 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4449 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4450 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4451 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4452 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4453 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4454 return 0;
4455 }
4456
4457 /*
4458 * Configure attributes for power mode change with below.
4459 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4460 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4461 * - PA_HSSERIES
4462 */
4463 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4464 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4465 pwr_mode->lane_rx);
4466 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4467 pwr_mode->pwr_rx == FAST_MODE)
4468 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4469 else
4470 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4471
4472 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4473 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4474 pwr_mode->lane_tx);
4475 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4476 pwr_mode->pwr_tx == FAST_MODE)
4477 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4478 else
4479 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4480
4481 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4482 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4483 pwr_mode->pwr_rx == FAST_MODE ||
4484 pwr_mode->pwr_tx == FAST_MODE)
4485 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4486 pwr_mode->hs_rate);
4487
4488 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4489 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4490 DL_FC0ProtectionTimeOutVal_Default);
4491 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4492 DL_TC0ReplayTimeOutVal_Default);
4493 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4494 DL_AFC0ReqTimeOutVal_Default);
4495 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4496 DL_FC1ProtectionTimeOutVal_Default);
4497 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4498 DL_TC1ReplayTimeOutVal_Default);
4499 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4500 DL_AFC1ReqTimeOutVal_Default);
4501
4502 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4503 DL_FC0ProtectionTimeOutVal_Default);
4504 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4505 DL_TC0ReplayTimeOutVal_Default);
4506 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4507 DL_AFC0ReqTimeOutVal_Default);
4508 }
4509
4510 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4511 | pwr_mode->pwr_tx);
4512
4513 if (ret) {
4514 dev_err(hba->dev,
4515 "%s: power mode change failed %d\n", __func__, ret);
4516 } else {
4517 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4518 pwr_mode);
4519
4520 memcpy(&hba->pwr_info, pwr_mode,
4521 sizeof(struct ufs_pa_layer_attr));
4522 }
4523
4524 return ret;
4525 }
4526
4527 /**
4528 * ufshcd_config_pwr_mode - configure a new power mode
4529 * @hba: per-adapter instance
4530 * @desired_pwr_mode: desired power configuration
4531 */
4532 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4533 struct ufs_pa_layer_attr *desired_pwr_mode)
4534 {
4535 struct ufs_pa_layer_attr final_params = { 0 };
4536 int ret;
4537
4538 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4539 desired_pwr_mode, &final_params);
4540
4541 if (ret)
4542 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4543
4544 ret = ufshcd_change_power_mode(hba, &final_params);
4545
4546 return ret;
4547 }
4548 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4549
4550 /**
4551 * ufshcd_complete_dev_init() - checks device readiness
4552 * @hba: per-adapter instance
4553 *
4554 * Set fDeviceInit flag and poll until device toggles it.
4555 */
4556 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4557 {
4558 int err;
4559 bool flag_res = true;
4560 ktime_t timeout;
4561
4562 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4563 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4564 if (err) {
4565 dev_err(hba->dev,
4566 "%s: setting fDeviceInit flag failed with error %d\n",
4567 __func__, err);
4568 goto out;
4569 }
4570
4571 /* Poll fDeviceInit flag to be cleared */
4572 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4573 do {
4574 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4575 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4576 if (!flag_res)
4577 break;
4578 usleep_range(500, 1000);
4579 } while (ktime_before(ktime_get(), timeout));
4580
4581 if (err) {
4582 dev_err(hba->dev,
4583 "%s: reading fDeviceInit flag failed with error %d\n",
4584 __func__, err);
4585 } else if (flag_res) {
4586 dev_err(hba->dev,
4587 "%s: fDeviceInit was not cleared by the device\n",
4588 __func__);
4589 err = -EBUSY;
4590 }
4591 out:
4592 return err;
4593 }
4594
4595 /**
4596 * ufshcd_make_hba_operational - Make UFS controller operational
4597 * @hba: per adapter instance
4598 *
4599 * To bring UFS host controller to operational state,
4600 * 1. Enable required interrupts
4601 * 2. Configure interrupt aggregation
4602 * 3. Program UTRL and UTMRL base address
4603 * 4. Configure run-stop-registers
4604 *
4605 * Returns 0 on success, non-zero value on failure
4606 */
4607 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4608 {
4609 int err = 0;
4610 u32 reg;
4611
4612 /* Enable required interrupts */
4613 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4614
4615 /* Configure interrupt aggregation */
4616 if (ufshcd_is_intr_aggr_allowed(hba))
4617 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4618 else
4619 ufshcd_disable_intr_aggr(hba);
4620
4621 /* Configure UTRL and UTMRL base address registers */
4622 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4623 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4624 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4625 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4626 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4627 REG_UTP_TASK_REQ_LIST_BASE_L);
4628 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4629 REG_UTP_TASK_REQ_LIST_BASE_H);
4630
4631 /*
4632 * Make sure base address and interrupt setup are updated before
4633 * enabling the run/stop registers below.
4634 */
4635 wmb();
4636
4637 /*
4638 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4639 */
4640 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4641 if (!(ufshcd_get_lists_status(reg))) {
4642 ufshcd_enable_run_stop_reg(hba);
4643 } else {
4644 dev_err(hba->dev,
4645 "Host controller not ready to process requests");
4646 err = -EIO;
4647 }
4648
4649 return err;
4650 }
4651 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4652
4653 /**
4654 * ufshcd_hba_stop - Send controller to reset state
4655 * @hba: per adapter instance
4656 */
4657 void ufshcd_hba_stop(struct ufs_hba *hba)
4658 {
4659 unsigned long flags;
4660 int err;
4661
4662 /*
4663 * Obtain the host lock to prevent that the controller is disabled
4664 * while the UFS interrupt handler is active on another CPU.
4665 */
4666 spin_lock_irqsave(hba->host->host_lock, flags);
4667 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4668 spin_unlock_irqrestore(hba->host->host_lock, flags);
4669
4670 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4671 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4672 10, 1);
4673 if (err)
4674 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4675 }
4676 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4677
4678 /**
4679 * ufshcd_hba_execute_hce - initialize the controller
4680 * @hba: per adapter instance
4681 *
4682 * The controller resets itself and controller firmware initialization
4683 * sequence kicks off. When controller is ready it will set
4684 * the Host Controller Enable bit to 1.
4685 *
4686 * Returns 0 on success, non-zero value on failure
4687 */
4688 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4689 {
4690 int retry_outer = 3;
4691 int retry_inner;
4692
4693 start:
4694 if (ufshcd_is_hba_active(hba))
4695 /* change controller state to "reset state" */
4696 ufshcd_hba_stop(hba);
4697
4698 /* UniPro link is disabled at this point */
4699 ufshcd_set_link_off(hba);
4700
4701 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4702
4703 /* start controller initialization sequence */
4704 ufshcd_hba_start(hba);
4705
4706 /*
4707 * To initialize a UFS host controller HCE bit must be set to 1.
4708 * During initialization the HCE bit value changes from 1->0->1.
4709 * When the host controller completes initialization sequence
4710 * it sets the value of HCE bit to 1. The same HCE bit is read back
4711 * to check if the controller has completed initialization sequence.
4712 * So without this delay the value HCE = 1, set in the previous
4713 * instruction might be read back.
4714 * This delay can be changed based on the controller.
4715 */
4716 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4717
4718 /* wait for the host controller to complete initialization */
4719 retry_inner = 50;
4720 while (!ufshcd_is_hba_active(hba)) {
4721 if (retry_inner) {
4722 retry_inner--;
4723 } else {
4724 dev_err(hba->dev,
4725 "Controller enable failed\n");
4726 if (retry_outer) {
4727 retry_outer--;
4728 goto start;
4729 }
4730 return -EIO;
4731 }
4732 usleep_range(1000, 1100);
4733 }
4734
4735 /* enable UIC related interrupts */
4736 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4737
4738 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4739
4740 return 0;
4741 }
4742
4743 int ufshcd_hba_enable(struct ufs_hba *hba)
4744 {
4745 int ret;
4746
4747 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4748 ufshcd_set_link_off(hba);
4749 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4750
4751 /* enable UIC related interrupts */
4752 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4753 ret = ufshcd_dme_reset(hba);
4754 if (ret) {
4755 dev_err(hba->dev, "DME_RESET failed\n");
4756 return ret;
4757 }
4758
4759 ret = ufshcd_dme_enable(hba);
4760 if (ret) {
4761 dev_err(hba->dev, "Enabling DME failed\n");
4762 return ret;
4763 }
4764
4765 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4766 } else {
4767 ret = ufshcd_hba_execute_hce(hba);
4768 }
4769
4770 return ret;
4771 }
4772 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4773
4774 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4775 {
4776 int tx_lanes = 0, i, err = 0;
4777
4778 if (!peer)
4779 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4780 &tx_lanes);
4781 else
4782 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4783 &tx_lanes);
4784 for (i = 0; i < tx_lanes; i++) {
4785 if (!peer)
4786 err = ufshcd_dme_set(hba,
4787 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4788 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4789 0);
4790 else
4791 err = ufshcd_dme_peer_set(hba,
4792 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4793 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4794 0);
4795 if (err) {
4796 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4797 __func__, peer, i, err);
4798 break;
4799 }
4800 }
4801
4802 return err;
4803 }
4804
4805 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4806 {
4807 return ufshcd_disable_tx_lcc(hba, true);
4808 }
4809
4810 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4811 {
4812 struct ufs_event_hist *e;
4813
4814 if (id >= UFS_EVT_CNT)
4815 return;
4816
4817 e = &hba->ufs_stats.event[id];
4818 e->val[e->pos] = val;
4819 e->tstamp[e->pos] = local_clock();
4820 e->cnt += 1;
4821 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4822
4823 ufshcd_vops_event_notify(hba, id, &val);
4824 }
4825 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4826
4827 /**
4828 * ufshcd_link_startup - Initialize unipro link startup
4829 * @hba: per adapter instance
4830 *
4831 * Returns 0 for success, non-zero in case of failure
4832 */
4833 static int ufshcd_link_startup(struct ufs_hba *hba)
4834 {
4835 int ret;
4836 int retries = DME_LINKSTARTUP_RETRIES;
4837 bool link_startup_again = false;
4838
4839 /*
4840 * If UFS device isn't active then we will have to issue link startup
4841 * 2 times to make sure the device state move to active.
4842 */
4843 if (!ufshcd_is_ufs_dev_active(hba))
4844 link_startup_again = true;
4845
4846 link_startup:
4847 do {
4848 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4849
4850 ret = ufshcd_dme_link_startup(hba);
4851
4852 /* check if device is detected by inter-connect layer */
4853 if (!ret && !ufshcd_is_device_present(hba)) {
4854 ufshcd_update_evt_hist(hba,
4855 UFS_EVT_LINK_STARTUP_FAIL,
4856 0);
4857 dev_err(hba->dev, "%s: Device not present\n", __func__);
4858 ret = -ENXIO;
4859 goto out;
4860 }
4861
4862 /*
4863 * DME link lost indication is only received when link is up,
4864 * but we can't be sure if the link is up until link startup
4865 * succeeds. So reset the local Uni-Pro and try again.
4866 */
4867 if (ret && retries && ufshcd_hba_enable(hba)) {
4868 ufshcd_update_evt_hist(hba,
4869 UFS_EVT_LINK_STARTUP_FAIL,
4870 (u32)ret);
4871 goto out;
4872 }
4873 } while (ret && retries--);
4874
4875 if (ret) {
4876 /* failed to get the link up... retire */
4877 ufshcd_update_evt_hist(hba,
4878 UFS_EVT_LINK_STARTUP_FAIL,
4879 (u32)ret);
4880 goto out;
4881 }
4882
4883 if (link_startup_again) {
4884 link_startup_again = false;
4885 retries = DME_LINKSTARTUP_RETRIES;
4886 goto link_startup;
4887 }
4888
4889 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4890 ufshcd_init_pwr_info(hba);
4891 ufshcd_print_pwr_info(hba);
4892
4893 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4894 ret = ufshcd_disable_device_tx_lcc(hba);
4895 if (ret)
4896 goto out;
4897 }
4898
4899 /* Include any host controller configuration via UIC commands */
4900 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4901 if (ret)
4902 goto out;
4903
4904 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4905 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4906 ret = ufshcd_make_hba_operational(hba);
4907 out:
4908 if (ret) {
4909 dev_err(hba->dev, "link startup failed %d\n", ret);
4910 ufshcd_print_host_state(hba);
4911 ufshcd_print_pwr_info(hba);
4912 ufshcd_print_evt_hist(hba);
4913 }
4914 return ret;
4915 }
4916
4917 /**
4918 * ufshcd_verify_dev_init() - Verify device initialization
4919 * @hba: per-adapter instance
4920 *
4921 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4922 * device Transport Protocol (UTP) layer is ready after a reset.
4923 * If the UTP layer at the device side is not initialized, it may
4924 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4925 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4926 */
4927 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4928 {
4929 int err = 0;
4930 int retries;
4931
4932 ufshcd_hold(hba, false);
4933 mutex_lock(&hba->dev_cmd.lock);
4934 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4935 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4936 hba->nop_out_timeout);
4937
4938 if (!err || err == -ETIMEDOUT)
4939 break;
4940
4941 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4942 }
4943 mutex_unlock(&hba->dev_cmd.lock);
4944 ufshcd_release(hba);
4945
4946 if (err)
4947 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4948 return err;
4949 }
4950
4951 /**
4952 * ufshcd_setup_links - associate link b/w device wlun and other luns
4953 * @sdev: pointer to SCSI device
4954 * @hba: pointer to ufs hba
4955 */
4956 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4957 {
4958 struct device_link *link;
4959
4960 /*
4961 * Device wlun is the supplier & rest of the luns are consumers.
4962 * This ensures that device wlun suspends after all other luns.
4963 */
4964 if (hba->ufs_device_wlun) {
4965 link = device_link_add(&sdev->sdev_gendev,
4966 &hba->ufs_device_wlun->sdev_gendev,
4967 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4968 if (!link) {
4969 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4970 dev_name(&hba->ufs_device_wlun->sdev_gendev));
4971 return;
4972 }
4973 hba->luns_avail--;
4974 /* Ignore REPORT_LUN wlun probing */
4975 if (hba->luns_avail == 1) {
4976 ufshcd_rpm_put(hba);
4977 return;
4978 }
4979 } else {
4980 /*
4981 * Device wlun is probed. The assumption is that WLUNs are
4982 * scanned before other LUNs.
4983 */
4984 hba->luns_avail--;
4985 }
4986 }
4987
4988 /**
4989 * ufshcd_lu_init - Initialize the relevant parameters of the LU
4990 * @hba: per-adapter instance
4991 * @sdev: pointer to SCSI device
4992 */
4993 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
4994 {
4995 int len = QUERY_DESC_MAX_SIZE;
4996 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
4997 u8 lun_qdepth = hba->nutrs;
4998 u8 *desc_buf;
4999 int ret;
5000
5001 desc_buf = kzalloc(len, GFP_KERNEL);
5002 if (!desc_buf)
5003 goto set_qdepth;
5004
5005 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
5006 if (ret < 0) {
5007 if (ret == -EOPNOTSUPP)
5008 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5009 lun_qdepth = 1;
5010 kfree(desc_buf);
5011 goto set_qdepth;
5012 }
5013
5014 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5015 /*
5016 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5017 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5018 */
5019 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5020 }
5021 /*
5022 * According to UFS device specification, the write protection mode is only supported by
5023 * normal LU, not supported by WLUN.
5024 */
5025 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5026 !hba->dev_info.is_lu_power_on_wp &&
5027 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5028 hba->dev_info.is_lu_power_on_wp = true;
5029
5030 /* In case of RPMB LU, check if advanced RPMB mode is enabled */
5031 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
5032 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5033 hba->dev_info.b_advanced_rpmb_en = true;
5034
5035
5036 kfree(desc_buf);
5037 set_qdepth:
5038 /*
5039 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5040 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5041 */
5042 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5043 scsi_change_queue_depth(sdev, lun_qdepth);
5044 }
5045
5046 /**
5047 * ufshcd_slave_alloc - handle initial SCSI device configurations
5048 * @sdev: pointer to SCSI device
5049 *
5050 * Returns success
5051 */
5052 static int ufshcd_slave_alloc(struct scsi_device *sdev)
5053 {
5054 struct ufs_hba *hba;
5055
5056 hba = shost_priv(sdev->host);
5057
5058 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5059 sdev->use_10_for_ms = 1;
5060
5061 /* DBD field should be set to 1 in mode sense(10) */
5062 sdev->set_dbd_for_ms = 1;
5063
5064 /* allow SCSI layer to restart the device in case of errors */
5065 sdev->allow_restart = 1;
5066
5067 /* REPORT SUPPORTED OPERATION CODES is not supported */
5068 sdev->no_report_opcodes = 1;
5069
5070 /* WRITE_SAME command is not supported */
5071 sdev->no_write_same = 1;
5072
5073 ufshcd_lu_init(hba, sdev);
5074
5075 ufshcd_setup_links(hba, sdev);
5076
5077 return 0;
5078 }
5079
5080 /**
5081 * ufshcd_change_queue_depth - change queue depth
5082 * @sdev: pointer to SCSI device
5083 * @depth: required depth to set
5084 *
5085 * Change queue depth and make sure the max. limits are not crossed.
5086 */
5087 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5088 {
5089 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5090 }
5091
5092 static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
5093 {
5094 /* skip well-known LU */
5095 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5096 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5097 return;
5098
5099 ufshpb_destroy_lu(hba, sdev);
5100 }
5101
5102 static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
5103 {
5104 /* skip well-known LU */
5105 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5106 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5107 return;
5108
5109 ufshpb_init_hpb_lu(hba, sdev);
5110 }
5111
5112 /**
5113 * ufshcd_slave_configure - adjust SCSI device configurations
5114 * @sdev: pointer to SCSI device
5115 */
5116 static int ufshcd_slave_configure(struct scsi_device *sdev)
5117 {
5118 struct ufs_hba *hba = shost_priv(sdev->host);
5119 struct request_queue *q = sdev->request_queue;
5120
5121 ufshcd_hpb_configure(hba, sdev);
5122
5123 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5124 if (hba->quirks & UFSHCD_QUIRK_4KB_DMA_ALIGNMENT)
5125 blk_queue_update_dma_alignment(q, 4096 - 1);
5126 /*
5127 * Block runtime-pm until all consumers are added.
5128 * Refer ufshcd_setup_links().
5129 */
5130 if (is_device_wlun(sdev))
5131 pm_runtime_get_noresume(&sdev->sdev_gendev);
5132 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5133 sdev->rpm_autosuspend = 1;
5134 /*
5135 * Do not print messages during runtime PM to avoid never-ending cycles
5136 * of messages written back to storage by user space causing runtime
5137 * resume, causing more messages and so on.
5138 */
5139 sdev->silence_suspend = 1;
5140
5141 ufshcd_crypto_register(hba, q);
5142
5143 return 0;
5144 }
5145
5146 /**
5147 * ufshcd_slave_destroy - remove SCSI device configurations
5148 * @sdev: pointer to SCSI device
5149 */
5150 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5151 {
5152 struct ufs_hba *hba;
5153 unsigned long flags;
5154
5155 hba = shost_priv(sdev->host);
5156
5157 ufshcd_hpb_destroy(hba, sdev);
5158
5159 /* Drop the reference as it won't be needed anymore */
5160 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5161 spin_lock_irqsave(hba->host->host_lock, flags);
5162 hba->ufs_device_wlun = NULL;
5163 spin_unlock_irqrestore(hba->host->host_lock, flags);
5164 } else if (hba->ufs_device_wlun) {
5165 struct device *supplier = NULL;
5166
5167 /* Ensure UFS Device WLUN exists and does not disappear */
5168 spin_lock_irqsave(hba->host->host_lock, flags);
5169 if (hba->ufs_device_wlun) {
5170 supplier = &hba->ufs_device_wlun->sdev_gendev;
5171 get_device(supplier);
5172 }
5173 spin_unlock_irqrestore(hba->host->host_lock, flags);
5174
5175 if (supplier) {
5176 /*
5177 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5178 * device will not have been registered but can still
5179 * have a device link holding a reference to the device.
5180 */
5181 device_link_remove(&sdev->sdev_gendev, supplier);
5182 put_device(supplier);
5183 }
5184 }
5185 }
5186
5187 /**
5188 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5189 * @lrbp: pointer to local reference block of completed command
5190 * @scsi_status: SCSI command status
5191 *
5192 * Returns value base on SCSI command status
5193 */
5194 static inline int
5195 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5196 {
5197 int result = 0;
5198
5199 switch (scsi_status) {
5200 case SAM_STAT_CHECK_CONDITION:
5201 ufshcd_copy_sense_data(lrbp);
5202 fallthrough;
5203 case SAM_STAT_GOOD:
5204 result |= DID_OK << 16 | scsi_status;
5205 break;
5206 case SAM_STAT_TASK_SET_FULL:
5207 case SAM_STAT_BUSY:
5208 case SAM_STAT_TASK_ABORTED:
5209 ufshcd_copy_sense_data(lrbp);
5210 result |= scsi_status;
5211 break;
5212 default:
5213 result |= DID_ERROR << 16;
5214 break;
5215 } /* end of switch */
5216
5217 return result;
5218 }
5219
5220 /**
5221 * ufshcd_transfer_rsp_status - Get overall status of the response
5222 * @hba: per adapter instance
5223 * @lrbp: pointer to local reference block of completed command
5224 * @cqe: pointer to the completion queue entry
5225 *
5226 * Returns result of the command to notify SCSI midlayer
5227 */
5228 static inline int
5229 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
5230 struct cq_entry *cqe)
5231 {
5232 int result = 0;
5233 int scsi_status;
5234 enum utp_ocs ocs;
5235
5236 /* overall command status of utrd */
5237 ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5238
5239 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5240 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5241 MASK_RSP_UPIU_RESULT)
5242 ocs = OCS_SUCCESS;
5243 }
5244
5245 switch (ocs) {
5246 case OCS_SUCCESS:
5247 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5248 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5249 switch (result) {
5250 case UPIU_TRANSACTION_RESPONSE:
5251 /*
5252 * get the response UPIU result to extract
5253 * the SCSI command status
5254 */
5255 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5256
5257 /*
5258 * get the result based on SCSI status response
5259 * to notify the SCSI midlayer of the command status
5260 */
5261 scsi_status = result & MASK_SCSI_STATUS;
5262 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5263
5264 /*
5265 * Currently we are only supporting BKOPs exception
5266 * events hence we can ignore BKOPs exception event
5267 * during power management callbacks. BKOPs exception
5268 * event is not expected to be raised in runtime suspend
5269 * callback as it allows the urgent bkops.
5270 * During system suspend, we are anyway forcefully
5271 * disabling the bkops and if urgent bkops is needed
5272 * it will be enabled on system resume. Long term
5273 * solution could be to abort the system suspend if
5274 * UFS device needs urgent BKOPs.
5275 */
5276 if (!hba->pm_op_in_progress &&
5277 !ufshcd_eh_in_progress(hba) &&
5278 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5279 /* Flushed in suspend */
5280 schedule_work(&hba->eeh_work);
5281
5282 if (scsi_status == SAM_STAT_GOOD)
5283 ufshpb_rsp_upiu(hba, lrbp);
5284 break;
5285 case UPIU_TRANSACTION_REJECT_UPIU:
5286 /* TODO: handle Reject UPIU Response */
5287 result = DID_ERROR << 16;
5288 dev_err(hba->dev,
5289 "Reject UPIU not fully implemented\n");
5290 break;
5291 default:
5292 dev_err(hba->dev,
5293 "Unexpected request response code = %x\n",
5294 result);
5295 result = DID_ERROR << 16;
5296 break;
5297 }
5298 break;
5299 case OCS_ABORTED:
5300 result |= DID_ABORT << 16;
5301 break;
5302 case OCS_INVALID_COMMAND_STATUS:
5303 result |= DID_REQUEUE << 16;
5304 break;
5305 case OCS_INVALID_CMD_TABLE_ATTR:
5306 case OCS_INVALID_PRDT_ATTR:
5307 case OCS_MISMATCH_DATA_BUF_SIZE:
5308 case OCS_MISMATCH_RESP_UPIU_SIZE:
5309 case OCS_PEER_COMM_FAILURE:
5310 case OCS_FATAL_ERROR:
5311 case OCS_DEVICE_FATAL_ERROR:
5312 case OCS_INVALID_CRYPTO_CONFIG:
5313 case OCS_GENERAL_CRYPTO_ERROR:
5314 default:
5315 result |= DID_ERROR << 16;
5316 dev_err(hba->dev,
5317 "OCS error from controller = %x for tag %d\n",
5318 ocs, lrbp->task_tag);
5319 ufshcd_print_evt_hist(hba);
5320 ufshcd_print_host_state(hba);
5321 break;
5322 } /* end of switch */
5323
5324 if ((host_byte(result) != DID_OK) &&
5325 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5326 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5327 return result;
5328 }
5329
5330 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5331 u32 intr_mask)
5332 {
5333 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5334 !ufshcd_is_auto_hibern8_enabled(hba))
5335 return false;
5336
5337 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5338 return false;
5339
5340 if (hba->active_uic_cmd &&
5341 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5342 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5343 return false;
5344
5345 return true;
5346 }
5347
5348 /**
5349 * ufshcd_uic_cmd_compl - handle completion of uic command
5350 * @hba: per adapter instance
5351 * @intr_status: interrupt status generated by the controller
5352 *
5353 * Returns
5354 * IRQ_HANDLED - If interrupt is valid
5355 * IRQ_NONE - If invalid interrupt
5356 */
5357 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5358 {
5359 irqreturn_t retval = IRQ_NONE;
5360
5361 spin_lock(hba->host->host_lock);
5362 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5363 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5364
5365 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5366 hba->active_uic_cmd->argument2 |=
5367 ufshcd_get_uic_cmd_result(hba);
5368 hba->active_uic_cmd->argument3 =
5369 ufshcd_get_dme_attr_val(hba);
5370 if (!hba->uic_async_done)
5371 hba->active_uic_cmd->cmd_active = 0;
5372 complete(&hba->active_uic_cmd->done);
5373 retval = IRQ_HANDLED;
5374 }
5375
5376 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5377 hba->active_uic_cmd->cmd_active = 0;
5378 complete(hba->uic_async_done);
5379 retval = IRQ_HANDLED;
5380 }
5381
5382 if (retval == IRQ_HANDLED)
5383 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5384 UFS_CMD_COMP);
5385 spin_unlock(hba->host->host_lock);
5386 return retval;
5387 }
5388
5389 /* Release the resources allocated for processing a SCSI command. */
5390 static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5391 struct ufshcd_lrb *lrbp)
5392 {
5393 struct scsi_cmnd *cmd = lrbp->cmd;
5394
5395 scsi_dma_unmap(cmd);
5396 lrbp->cmd = NULL; /* Mark the command as completed. */
5397 ufshcd_release(hba);
5398 ufshcd_clk_scaling_update_busy(hba);
5399 }
5400
5401 /**
5402 * ufshcd_compl_one_cqe - handle a completion queue entry
5403 * @hba: per adapter instance
5404 * @task_tag: the task tag of the request to be completed
5405 * @cqe: pointer to the completion queue entry
5406 */
5407 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5408 struct cq_entry *cqe)
5409 {
5410 struct ufshcd_lrb *lrbp;
5411 struct scsi_cmnd *cmd;
5412
5413 lrbp = &hba->lrb[task_tag];
5414 lrbp->compl_time_stamp = ktime_get();
5415 cmd = lrbp->cmd;
5416 if (cmd) {
5417 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5418 ufshcd_update_monitor(hba, lrbp);
5419 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP);
5420 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe);
5421 ufshcd_release_scsi_cmd(hba, lrbp);
5422 /* Do not touch lrbp after scsi done */
5423 scsi_done(cmd);
5424 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5425 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5426 if (hba->dev_cmd.complete) {
5427 hba->dev_cmd.cqe = cqe;
5428 ufshcd_add_command_trace(hba, task_tag, UFS_DEV_COMP);
5429 complete(hba->dev_cmd.complete);
5430 ufshcd_clk_scaling_update_busy(hba);
5431 }
5432 }
5433 }
5434
5435 /**
5436 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5437 * @hba: per adapter instance
5438 * @completed_reqs: bitmask that indicates which requests to complete
5439 */
5440 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5441 unsigned long completed_reqs)
5442 {
5443 int tag;
5444
5445 for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5446 ufshcd_compl_one_cqe(hba, tag, NULL);
5447 }
5448
5449 /* Any value that is not an existing queue number is fine for this constant. */
5450 enum {
5451 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5452 };
5453
5454 static void ufshcd_clear_polled(struct ufs_hba *hba,
5455 unsigned long *completed_reqs)
5456 {
5457 int tag;
5458
5459 for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5460 struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5461
5462 if (!cmd)
5463 continue;
5464 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5465 __clear_bit(tag, completed_reqs);
5466 }
5467 }
5468
5469 /*
5470 * Returns > 0 if one or more commands have been completed or 0 if no
5471 * requests have been completed.
5472 */
5473 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5474 {
5475 struct ufs_hba *hba = shost_priv(shost);
5476 unsigned long completed_reqs, flags;
5477 u32 tr_doorbell;
5478 struct ufs_hw_queue *hwq;
5479
5480 if (is_mcq_enabled(hba)) {
5481 hwq = &hba->uhq[queue_num + UFSHCD_MCQ_IO_QUEUE_OFFSET];
5482
5483 return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5484 }
5485
5486 spin_lock_irqsave(&hba->outstanding_lock, flags);
5487 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5488 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5489 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5490 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5491 hba->outstanding_reqs);
5492 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5493 /* Do not complete polled requests from interrupt context. */
5494 ufshcd_clear_polled(hba, &completed_reqs);
5495 }
5496 hba->outstanding_reqs &= ~completed_reqs;
5497 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5498
5499 if (completed_reqs)
5500 __ufshcd_transfer_req_compl(hba, completed_reqs);
5501
5502 return completed_reqs != 0;
5503 }
5504
5505 /**
5506 * ufshcd_transfer_req_compl - handle SCSI and query command completion
5507 * @hba: per adapter instance
5508 *
5509 * Returns
5510 * IRQ_HANDLED - If interrupt is valid
5511 * IRQ_NONE - If invalid interrupt
5512 */
5513 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5514 {
5515 /* Resetting interrupt aggregation counters first and reading the
5516 * DOOR_BELL afterward allows us to handle all the completed requests.
5517 * In order to prevent other interrupts starvation the DB is read once
5518 * after reset. The down side of this solution is the possibility of
5519 * false interrupt if device completes another request after resetting
5520 * aggregation and before reading the DB.
5521 */
5522 if (ufshcd_is_intr_aggr_allowed(hba) &&
5523 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5524 ufshcd_reset_intr_aggr(hba);
5525
5526 if (ufs_fail_completion())
5527 return IRQ_HANDLED;
5528
5529 /*
5530 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5531 * do not want polling to trigger spurious interrupt complaints.
5532 */
5533 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5534
5535 return IRQ_HANDLED;
5536 }
5537
5538 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5539 {
5540 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5541 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5542 &ee_ctrl_mask);
5543 }
5544
5545 int ufshcd_write_ee_control(struct ufs_hba *hba)
5546 {
5547 int err;
5548
5549 mutex_lock(&hba->ee_ctrl_mutex);
5550 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5551 mutex_unlock(&hba->ee_ctrl_mutex);
5552 if (err)
5553 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5554 __func__, err);
5555 return err;
5556 }
5557
5558 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5559 const u16 *other_mask, u16 set, u16 clr)
5560 {
5561 u16 new_mask, ee_ctrl_mask;
5562 int err = 0;
5563
5564 mutex_lock(&hba->ee_ctrl_mutex);
5565 new_mask = (*mask & ~clr) | set;
5566 ee_ctrl_mask = new_mask | *other_mask;
5567 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5568 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5569 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5570 if (!err) {
5571 hba->ee_ctrl_mask = ee_ctrl_mask;
5572 *mask = new_mask;
5573 }
5574 mutex_unlock(&hba->ee_ctrl_mutex);
5575 return err;
5576 }
5577
5578 /**
5579 * ufshcd_disable_ee - disable exception event
5580 * @hba: per-adapter instance
5581 * @mask: exception event to disable
5582 *
5583 * Disables exception event in the device so that the EVENT_ALERT
5584 * bit is not set.
5585 *
5586 * Returns zero on success, non-zero error value on failure.
5587 */
5588 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5589 {
5590 return ufshcd_update_ee_drv_mask(hba, 0, mask);
5591 }
5592
5593 /**
5594 * ufshcd_enable_ee - enable exception event
5595 * @hba: per-adapter instance
5596 * @mask: exception event to enable
5597 *
5598 * Enable corresponding exception event in the device to allow
5599 * device to alert host in critical scenarios.
5600 *
5601 * Returns zero on success, non-zero error value on failure.
5602 */
5603 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5604 {
5605 return ufshcd_update_ee_drv_mask(hba, mask, 0);
5606 }
5607
5608 /**
5609 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5610 * @hba: per-adapter instance
5611 *
5612 * Allow device to manage background operations on its own. Enabling
5613 * this might lead to inconsistent latencies during normal data transfers
5614 * as the device is allowed to manage its own way of handling background
5615 * operations.
5616 *
5617 * Returns zero on success, non-zero on failure.
5618 */
5619 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5620 {
5621 int err = 0;
5622
5623 if (hba->auto_bkops_enabled)
5624 goto out;
5625
5626 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5627 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5628 if (err) {
5629 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5630 __func__, err);
5631 goto out;
5632 }
5633
5634 hba->auto_bkops_enabled = true;
5635 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5636
5637 /* No need of URGENT_BKOPS exception from the device */
5638 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5639 if (err)
5640 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5641 __func__, err);
5642 out:
5643 return err;
5644 }
5645
5646 /**
5647 * ufshcd_disable_auto_bkops - block device in doing background operations
5648 * @hba: per-adapter instance
5649 *
5650 * Disabling background operations improves command response latency but
5651 * has drawback of device moving into critical state where the device is
5652 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5653 * host is idle so that BKOPS are managed effectively without any negative
5654 * impacts.
5655 *
5656 * Returns zero on success, non-zero on failure.
5657 */
5658 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5659 {
5660 int err = 0;
5661
5662 if (!hba->auto_bkops_enabled)
5663 goto out;
5664
5665 /*
5666 * If host assisted BKOPs is to be enabled, make sure
5667 * urgent bkops exception is allowed.
5668 */
5669 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5670 if (err) {
5671 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5672 __func__, err);
5673 goto out;
5674 }
5675
5676 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5677 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5678 if (err) {
5679 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5680 __func__, err);
5681 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5682 goto out;
5683 }
5684
5685 hba->auto_bkops_enabled = false;
5686 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5687 hba->is_urgent_bkops_lvl_checked = false;
5688 out:
5689 return err;
5690 }
5691
5692 /**
5693 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5694 * @hba: per adapter instance
5695 *
5696 * After a device reset the device may toggle the BKOPS_EN flag
5697 * to default value. The s/w tracking variables should be updated
5698 * as well. This function would change the auto-bkops state based on
5699 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5700 */
5701 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5702 {
5703 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5704 hba->auto_bkops_enabled = false;
5705 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5706 ufshcd_enable_auto_bkops(hba);
5707 } else {
5708 hba->auto_bkops_enabled = true;
5709 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5710 ufshcd_disable_auto_bkops(hba);
5711 }
5712 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5713 hba->is_urgent_bkops_lvl_checked = false;
5714 }
5715
5716 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5717 {
5718 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5719 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5720 }
5721
5722 /**
5723 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5724 * @hba: per-adapter instance
5725 * @status: bkops_status value
5726 *
5727 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5728 * flag in the device to permit background operations if the device
5729 * bkops_status is greater than or equal to "status" argument passed to
5730 * this function, disable otherwise.
5731 *
5732 * Returns 0 for success, non-zero in case of failure.
5733 *
5734 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5735 * to know whether auto bkops is enabled or disabled after this function
5736 * returns control to it.
5737 */
5738 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5739 enum bkops_status status)
5740 {
5741 int err;
5742 u32 curr_status = 0;
5743
5744 err = ufshcd_get_bkops_status(hba, &curr_status);
5745 if (err) {
5746 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5747 __func__, err);
5748 goto out;
5749 } else if (curr_status > BKOPS_STATUS_MAX) {
5750 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5751 __func__, curr_status);
5752 err = -EINVAL;
5753 goto out;
5754 }
5755
5756 if (curr_status >= status)
5757 err = ufshcd_enable_auto_bkops(hba);
5758 else
5759 err = ufshcd_disable_auto_bkops(hba);
5760 out:
5761 return err;
5762 }
5763
5764 /**
5765 * ufshcd_urgent_bkops - handle urgent bkops exception event
5766 * @hba: per-adapter instance
5767 *
5768 * Enable fBackgroundOpsEn flag in the device to permit background
5769 * operations.
5770 *
5771 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5772 * and negative error value for any other failure.
5773 */
5774 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5775 {
5776 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5777 }
5778
5779 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5780 {
5781 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5782 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5783 }
5784
5785 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5786 {
5787 int err;
5788 u32 curr_status = 0;
5789
5790 if (hba->is_urgent_bkops_lvl_checked)
5791 goto enable_auto_bkops;
5792
5793 err = ufshcd_get_bkops_status(hba, &curr_status);
5794 if (err) {
5795 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5796 __func__, err);
5797 goto out;
5798 }
5799
5800 /*
5801 * We are seeing that some devices are raising the urgent bkops
5802 * exception events even when BKOPS status doesn't indicate performace
5803 * impacted or critical. Handle these device by determining their urgent
5804 * bkops status at runtime.
5805 */
5806 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5807 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5808 __func__, curr_status);
5809 /* update the current status as the urgent bkops level */
5810 hba->urgent_bkops_lvl = curr_status;
5811 hba->is_urgent_bkops_lvl_checked = true;
5812 }
5813
5814 enable_auto_bkops:
5815 err = ufshcd_enable_auto_bkops(hba);
5816 out:
5817 if (err < 0)
5818 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5819 __func__, err);
5820 }
5821
5822 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5823 {
5824 u32 value;
5825
5826 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5827 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5828 return;
5829
5830 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5831
5832 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5833
5834 /*
5835 * A placeholder for the platform vendors to add whatever additional
5836 * steps required
5837 */
5838 }
5839
5840 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5841 {
5842 u8 index;
5843 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5844 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5845
5846 index = ufshcd_wb_get_query_index(hba);
5847 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5848 }
5849
5850 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5851 {
5852 int ret;
5853
5854 if (!ufshcd_is_wb_allowed(hba) ||
5855 hba->dev_info.wb_enabled == enable)
5856 return 0;
5857
5858 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5859 if (ret) {
5860 dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
5861 __func__, enable ? "enabling" : "disabling", ret);
5862 return ret;
5863 }
5864
5865 hba->dev_info.wb_enabled = enable;
5866 dev_dbg(hba->dev, "%s: Write Booster %s\n",
5867 __func__, enable ? "enabled" : "disabled");
5868
5869 return ret;
5870 }
5871
5872 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
5873 bool enable)
5874 {
5875 int ret;
5876
5877 ret = __ufshcd_wb_toggle(hba, enable,
5878 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5879 if (ret) {
5880 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
5881 __func__, enable ? "enabling" : "disabling", ret);
5882 return;
5883 }
5884 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
5885 __func__, enable ? "enabled" : "disabled");
5886 }
5887
5888 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
5889 {
5890 int ret;
5891
5892 if (!ufshcd_is_wb_allowed(hba) ||
5893 hba->dev_info.wb_buf_flush_enabled == enable)
5894 return 0;
5895
5896 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5897 if (ret) {
5898 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
5899 __func__, enable ? "enabling" : "disabling", ret);
5900 return ret;
5901 }
5902
5903 hba->dev_info.wb_buf_flush_enabled = enable;
5904 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
5905 __func__, enable ? "enabled" : "disabled");
5906
5907 return ret;
5908 }
5909
5910 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5911 u32 avail_buf)
5912 {
5913 u32 cur_buf;
5914 int ret;
5915 u8 index;
5916
5917 index = ufshcd_wb_get_query_index(hba);
5918 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5919 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5920 index, 0, &cur_buf);
5921 if (ret) {
5922 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
5923 __func__, ret);
5924 return false;
5925 }
5926
5927 if (!cur_buf) {
5928 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5929 cur_buf);
5930 return false;
5931 }
5932 /* Let it continue to flush when available buffer exceeds threshold */
5933 return avail_buf < hba->vps->wb_flush_threshold;
5934 }
5935
5936 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5937 {
5938 if (ufshcd_is_wb_buf_flush_allowed(hba))
5939 ufshcd_wb_toggle_buf_flush(hba, false);
5940
5941 ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
5942 ufshcd_wb_toggle(hba, false);
5943 hba->caps &= ~UFSHCD_CAP_WB_EN;
5944
5945 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5946 }
5947
5948 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5949 {
5950 u32 lifetime;
5951 int ret;
5952 u8 index;
5953
5954 index = ufshcd_wb_get_query_index(hba);
5955 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5956 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5957 index, 0, &lifetime);
5958 if (ret) {
5959 dev_err(hba->dev,
5960 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
5961 __func__, ret);
5962 return false;
5963 }
5964
5965 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
5966 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
5967 __func__, lifetime);
5968 return false;
5969 }
5970
5971 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
5972 __func__, lifetime);
5973
5974 return true;
5975 }
5976
5977 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5978 {
5979 int ret;
5980 u32 avail_buf;
5981 u8 index;
5982
5983 if (!ufshcd_is_wb_allowed(hba))
5984 return false;
5985
5986 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
5987 ufshcd_wb_force_disable(hba);
5988 return false;
5989 }
5990
5991 /*
5992 * The ufs device needs the vcc to be ON to flush.
5993 * With user-space reduction enabled, it's enough to enable flush
5994 * by checking only the available buffer. The threshold
5995 * defined here is > 90% full.
5996 * With user-space preserved enabled, the current-buffer
5997 * should be checked too because the wb buffer size can reduce
5998 * when disk tends to be full. This info is provided by current
5999 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
6000 * keeping vcc on when current buffer is empty.
6001 */
6002 index = ufshcd_wb_get_query_index(hba);
6003 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6004 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6005 index, 0, &avail_buf);
6006 if (ret) {
6007 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6008 __func__, ret);
6009 return false;
6010 }
6011
6012 if (!hba->dev_info.b_presrv_uspc_en)
6013 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6014
6015 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
6016 }
6017
6018 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6019 {
6020 struct ufs_hba *hba = container_of(to_delayed_work(work),
6021 struct ufs_hba,
6022 rpm_dev_flush_recheck_work);
6023 /*
6024 * To prevent unnecessary VCC power drain after device finishes
6025 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
6026 * after a certain delay to recheck the threshold by next runtime
6027 * suspend.
6028 */
6029 ufshcd_rpm_get_sync(hba);
6030 ufshcd_rpm_put_sync(hba);
6031 }
6032
6033 /**
6034 * ufshcd_exception_event_handler - handle exceptions raised by device
6035 * @work: pointer to work data
6036 *
6037 * Read bExceptionEventStatus attribute from the device and handle the
6038 * exception event accordingly.
6039 */
6040 static void ufshcd_exception_event_handler(struct work_struct *work)
6041 {
6042 struct ufs_hba *hba;
6043 int err;
6044 u32 status = 0;
6045 hba = container_of(work, struct ufs_hba, eeh_work);
6046
6047 ufshcd_scsi_block_requests(hba);
6048 err = ufshcd_get_ee_status(hba, &status);
6049 if (err) {
6050 dev_err(hba->dev, "%s: failed to get exception status %d\n",
6051 __func__, err);
6052 goto out;
6053 }
6054
6055 trace_ufshcd_exception_event(dev_name(hba->dev), status);
6056
6057 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6058 ufshcd_bkops_exception_event_handler(hba);
6059
6060 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6061 ufshcd_temp_exception_event_handler(hba, status);
6062
6063 ufs_debugfs_exception_event(hba, status);
6064 out:
6065 ufshcd_scsi_unblock_requests(hba);
6066 }
6067
6068 /* Complete requests that have door-bell cleared */
6069 static void ufshcd_complete_requests(struct ufs_hba *hba)
6070 {
6071 ufshcd_transfer_req_compl(hba);
6072 ufshcd_tmc_handler(hba);
6073 }
6074
6075 /**
6076 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6077 * to recover from the DL NAC errors or not.
6078 * @hba: per-adapter instance
6079 *
6080 * Returns true if error handling is required, false otherwise
6081 */
6082 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6083 {
6084 unsigned long flags;
6085 bool err_handling = true;
6086
6087 spin_lock_irqsave(hba->host->host_lock, flags);
6088 /*
6089 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6090 * device fatal error and/or DL NAC & REPLAY timeout errors.
6091 */
6092 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6093 goto out;
6094
6095 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6096 ((hba->saved_err & UIC_ERROR) &&
6097 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6098 goto out;
6099
6100 if ((hba->saved_err & UIC_ERROR) &&
6101 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6102 int err;
6103 /*
6104 * wait for 50ms to see if we can get any other errors or not.
6105 */
6106 spin_unlock_irqrestore(hba->host->host_lock, flags);
6107 msleep(50);
6108 spin_lock_irqsave(hba->host->host_lock, flags);
6109
6110 /*
6111 * now check if we have got any other severe errors other than
6112 * DL NAC error?
6113 */
6114 if ((hba->saved_err & INT_FATAL_ERRORS) ||
6115 ((hba->saved_err & UIC_ERROR) &&
6116 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6117 goto out;
6118
6119 /*
6120 * As DL NAC is the only error received so far, send out NOP
6121 * command to confirm if link is still active or not.
6122 * - If we don't get any response then do error recovery.
6123 * - If we get response then clear the DL NAC error bit.
6124 */
6125
6126 spin_unlock_irqrestore(hba->host->host_lock, flags);
6127 err = ufshcd_verify_dev_init(hba);
6128 spin_lock_irqsave(hba->host->host_lock, flags);
6129
6130 if (err)
6131 goto out;
6132
6133 /* Link seems to be alive hence ignore the DL NAC errors */
6134 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6135 hba->saved_err &= ~UIC_ERROR;
6136 /* clear NAC error */
6137 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6138 if (!hba->saved_uic_err)
6139 err_handling = false;
6140 }
6141 out:
6142 spin_unlock_irqrestore(hba->host->host_lock, flags);
6143 return err_handling;
6144 }
6145
6146 /* host lock must be held before calling this func */
6147 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6148 {
6149 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6150 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6151 }
6152
6153 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6154 {
6155 lockdep_assert_held(hba->host->host_lock);
6156
6157 /* handle fatal errors only when link is not in error state */
6158 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6159 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6160 ufshcd_is_saved_err_fatal(hba))
6161 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6162 else
6163 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6164 queue_work(hba->eh_wq, &hba->eh_work);
6165 }
6166 }
6167
6168 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6169 {
6170 down_write(&hba->clk_scaling_lock);
6171 hba->clk_scaling.is_allowed = allow;
6172 up_write(&hba->clk_scaling_lock);
6173 }
6174
6175 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6176 {
6177 if (suspend) {
6178 if (hba->clk_scaling.is_enabled)
6179 ufshcd_suspend_clkscaling(hba);
6180 ufshcd_clk_scaling_allow(hba, false);
6181 } else {
6182 ufshcd_clk_scaling_allow(hba, true);
6183 if (hba->clk_scaling.is_enabled)
6184 ufshcd_resume_clkscaling(hba);
6185 }
6186 }
6187
6188 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6189 {
6190 ufshcd_rpm_get_sync(hba);
6191 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6192 hba->is_sys_suspended) {
6193 enum ufs_pm_op pm_op;
6194
6195 /*
6196 * Don't assume anything of resume, if
6197 * resume fails, irq and clocks can be OFF, and powers
6198 * can be OFF or in LPM.
6199 */
6200 ufshcd_setup_hba_vreg(hba, true);
6201 ufshcd_enable_irq(hba);
6202 ufshcd_setup_vreg(hba, true);
6203 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6204 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6205 ufshcd_hold(hba, false);
6206 if (!ufshcd_is_clkgating_allowed(hba))
6207 ufshcd_setup_clocks(hba, true);
6208 ufshcd_release(hba);
6209 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6210 ufshcd_vops_resume(hba, pm_op);
6211 } else {
6212 ufshcd_hold(hba, false);
6213 if (ufshcd_is_clkscaling_supported(hba) &&
6214 hba->clk_scaling.is_enabled)
6215 ufshcd_suspend_clkscaling(hba);
6216 ufshcd_clk_scaling_allow(hba, false);
6217 }
6218 ufshcd_scsi_block_requests(hba);
6219 /* Drain ufshcd_queuecommand() */
6220 synchronize_rcu();
6221 cancel_work_sync(&hba->eeh_work);
6222 }
6223
6224 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6225 {
6226 ufshcd_scsi_unblock_requests(hba);
6227 ufshcd_release(hba);
6228 if (ufshcd_is_clkscaling_supported(hba))
6229 ufshcd_clk_scaling_suspend(hba, false);
6230 ufshcd_rpm_put(hba);
6231 }
6232
6233 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6234 {
6235 return (!hba->is_powered || hba->shutting_down ||
6236 !hba->ufs_device_wlun ||
6237 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6238 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6239 ufshcd_is_link_broken(hba))));
6240 }
6241
6242 #ifdef CONFIG_PM
6243 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6244 {
6245 struct Scsi_Host *shost = hba->host;
6246 struct scsi_device *sdev;
6247 struct request_queue *q;
6248 int ret;
6249
6250 hba->is_sys_suspended = false;
6251 /*
6252 * Set RPM status of wlun device to RPM_ACTIVE,
6253 * this also clears its runtime error.
6254 */
6255 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6256
6257 /* hba device might have a runtime error otherwise */
6258 if (ret)
6259 ret = pm_runtime_set_active(hba->dev);
6260 /*
6261 * If wlun device had runtime error, we also need to resume those
6262 * consumer scsi devices in case any of them has failed to be
6263 * resumed due to supplier runtime resume failure. This is to unblock
6264 * blk_queue_enter in case there are bios waiting inside it.
6265 */
6266 if (!ret) {
6267 shost_for_each_device(sdev, shost) {
6268 q = sdev->request_queue;
6269 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6270 q->rpm_status == RPM_SUSPENDING))
6271 pm_request_resume(q->dev);
6272 }
6273 }
6274 }
6275 #else
6276 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6277 {
6278 }
6279 #endif
6280
6281 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6282 {
6283 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6284 u32 mode;
6285
6286 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6287
6288 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6289 return true;
6290
6291 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6292 return true;
6293
6294 return false;
6295 }
6296
6297 static bool ufshcd_abort_all(struct ufs_hba *hba)
6298 {
6299 bool needs_reset = false;
6300 int tag, ret;
6301
6302 /* Clear pending transfer requests */
6303 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6304 ret = ufshcd_try_to_abort_task(hba, tag);
6305 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6306 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6307 ret ? "failed" : "succeeded");
6308 if (ret) {
6309 needs_reset = true;
6310 goto out;
6311 }
6312 }
6313
6314 /* Clear pending task management requests */
6315 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6316 if (ufshcd_clear_tm_cmd(hba, tag)) {
6317 needs_reset = true;
6318 goto out;
6319 }
6320 }
6321
6322 out:
6323 /* Complete the requests that are cleared by s/w */
6324 ufshcd_complete_requests(hba);
6325
6326 return needs_reset;
6327 }
6328
6329 /**
6330 * ufshcd_err_handler - handle UFS errors that require s/w attention
6331 * @work: pointer to work structure
6332 */
6333 static void ufshcd_err_handler(struct work_struct *work)
6334 {
6335 int retries = MAX_ERR_HANDLER_RETRIES;
6336 struct ufs_hba *hba;
6337 unsigned long flags;
6338 bool needs_restore;
6339 bool needs_reset;
6340 int pmc_err;
6341
6342 hba = container_of(work, struct ufs_hba, eh_work);
6343
6344 dev_info(hba->dev,
6345 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6346 __func__, ufshcd_state_name[hba->ufshcd_state],
6347 hba->is_powered, hba->shutting_down, hba->saved_err,
6348 hba->saved_uic_err, hba->force_reset,
6349 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6350
6351 down(&hba->host_sem);
6352 spin_lock_irqsave(hba->host->host_lock, flags);
6353 if (ufshcd_err_handling_should_stop(hba)) {
6354 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6355 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6356 spin_unlock_irqrestore(hba->host->host_lock, flags);
6357 up(&hba->host_sem);
6358 return;
6359 }
6360 ufshcd_set_eh_in_progress(hba);
6361 spin_unlock_irqrestore(hba->host->host_lock, flags);
6362 ufshcd_err_handling_prepare(hba);
6363 /* Complete requests that have door-bell cleared by h/w */
6364 ufshcd_complete_requests(hba);
6365 spin_lock_irqsave(hba->host->host_lock, flags);
6366 again:
6367 needs_restore = false;
6368 needs_reset = false;
6369
6370 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6371 hba->ufshcd_state = UFSHCD_STATE_RESET;
6372 /*
6373 * A full reset and restore might have happened after preparation
6374 * is finished, double check whether we should stop.
6375 */
6376 if (ufshcd_err_handling_should_stop(hba))
6377 goto skip_err_handling;
6378
6379 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6380 bool ret;
6381
6382 spin_unlock_irqrestore(hba->host->host_lock, flags);
6383 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6384 ret = ufshcd_quirk_dl_nac_errors(hba);
6385 spin_lock_irqsave(hba->host->host_lock, flags);
6386 if (!ret && ufshcd_err_handling_should_stop(hba))
6387 goto skip_err_handling;
6388 }
6389
6390 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6391 (hba->saved_uic_err &&
6392 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6393 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6394
6395 spin_unlock_irqrestore(hba->host->host_lock, flags);
6396 ufshcd_print_host_state(hba);
6397 ufshcd_print_pwr_info(hba);
6398 ufshcd_print_evt_hist(hba);
6399 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6400 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6401 spin_lock_irqsave(hba->host->host_lock, flags);
6402 }
6403
6404 /*
6405 * if host reset is required then skip clearing the pending
6406 * transfers forcefully because they will get cleared during
6407 * host reset and restore
6408 */
6409 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6410 ufshcd_is_saved_err_fatal(hba) ||
6411 ((hba->saved_err & UIC_ERROR) &&
6412 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6413 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6414 needs_reset = true;
6415 goto do_reset;
6416 }
6417
6418 /*
6419 * If LINERESET was caught, UFS might have been put to PWM mode,
6420 * check if power mode restore is needed.
6421 */
6422 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6423 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6424 if (!hba->saved_uic_err)
6425 hba->saved_err &= ~UIC_ERROR;
6426 spin_unlock_irqrestore(hba->host->host_lock, flags);
6427 if (ufshcd_is_pwr_mode_restore_needed(hba))
6428 needs_restore = true;
6429 spin_lock_irqsave(hba->host->host_lock, flags);
6430 if (!hba->saved_err && !needs_restore)
6431 goto skip_err_handling;
6432 }
6433
6434 hba->silence_err_logs = true;
6435 /* release lock as clear command might sleep */
6436 spin_unlock_irqrestore(hba->host->host_lock, flags);
6437
6438 needs_reset = ufshcd_abort_all(hba);
6439
6440 spin_lock_irqsave(hba->host->host_lock, flags);
6441 hba->silence_err_logs = false;
6442 if (needs_reset)
6443 goto do_reset;
6444
6445 /*
6446 * After all reqs and tasks are cleared from doorbell,
6447 * now it is safe to retore power mode.
6448 */
6449 if (needs_restore) {
6450 spin_unlock_irqrestore(hba->host->host_lock, flags);
6451 /*
6452 * Hold the scaling lock just in case dev cmds
6453 * are sent via bsg and/or sysfs.
6454 */
6455 down_write(&hba->clk_scaling_lock);
6456 hba->force_pmc = true;
6457 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6458 if (pmc_err) {
6459 needs_reset = true;
6460 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6461 __func__, pmc_err);
6462 }
6463 hba->force_pmc = false;
6464 ufshcd_print_pwr_info(hba);
6465 up_write(&hba->clk_scaling_lock);
6466 spin_lock_irqsave(hba->host->host_lock, flags);
6467 }
6468
6469 do_reset:
6470 /* Fatal errors need reset */
6471 if (needs_reset) {
6472 int err;
6473
6474 hba->force_reset = false;
6475 spin_unlock_irqrestore(hba->host->host_lock, flags);
6476 err = ufshcd_reset_and_restore(hba);
6477 if (err)
6478 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6479 __func__, err);
6480 else
6481 ufshcd_recover_pm_error(hba);
6482 spin_lock_irqsave(hba->host->host_lock, flags);
6483 }
6484
6485 skip_err_handling:
6486 if (!needs_reset) {
6487 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6488 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6489 if (hba->saved_err || hba->saved_uic_err)
6490 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6491 __func__, hba->saved_err, hba->saved_uic_err);
6492 }
6493 /* Exit in an operational state or dead */
6494 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6495 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6496 if (--retries)
6497 goto again;
6498 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6499 }
6500 ufshcd_clear_eh_in_progress(hba);
6501 spin_unlock_irqrestore(hba->host->host_lock, flags);
6502 ufshcd_err_handling_unprepare(hba);
6503 up(&hba->host_sem);
6504
6505 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6506 ufshcd_state_name[hba->ufshcd_state]);
6507 }
6508
6509 /**
6510 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6511 * @hba: per-adapter instance
6512 *
6513 * Returns
6514 * IRQ_HANDLED - If interrupt is valid
6515 * IRQ_NONE - If invalid interrupt
6516 */
6517 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6518 {
6519 u32 reg;
6520 irqreturn_t retval = IRQ_NONE;
6521
6522 /* PHY layer error */
6523 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6524 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6525 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6526 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6527 /*
6528 * To know whether this error is fatal or not, DB timeout
6529 * must be checked but this error is handled separately.
6530 */
6531 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6532 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6533 __func__);
6534
6535 /* Got a LINERESET indication. */
6536 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6537 struct uic_command *cmd = NULL;
6538
6539 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6540 if (hba->uic_async_done && hba->active_uic_cmd)
6541 cmd = hba->active_uic_cmd;
6542 /*
6543 * Ignore the LINERESET during power mode change
6544 * operation via DME_SET command.
6545 */
6546 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6547 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6548 }
6549 retval |= IRQ_HANDLED;
6550 }
6551
6552 /* PA_INIT_ERROR is fatal and needs UIC reset */
6553 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6554 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6555 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6556 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6557
6558 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6559 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6560 else if (hba->dev_quirks &
6561 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6562 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6563 hba->uic_error |=
6564 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6565 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6566 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6567 }
6568 retval |= IRQ_HANDLED;
6569 }
6570
6571 /* UIC NL/TL/DME errors needs software retry */
6572 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6573 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6574 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6575 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6576 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6577 retval |= IRQ_HANDLED;
6578 }
6579
6580 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6581 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6582 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6583 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6584 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6585 retval |= IRQ_HANDLED;
6586 }
6587
6588 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6589 if ((reg & UIC_DME_ERROR) &&
6590 (reg & UIC_DME_ERROR_CODE_MASK)) {
6591 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6592 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6593 retval |= IRQ_HANDLED;
6594 }
6595
6596 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6597 __func__, hba->uic_error);
6598 return retval;
6599 }
6600
6601 /**
6602 * ufshcd_check_errors - Check for errors that need s/w attention
6603 * @hba: per-adapter instance
6604 * @intr_status: interrupt status generated by the controller
6605 *
6606 * Returns
6607 * IRQ_HANDLED - If interrupt is valid
6608 * IRQ_NONE - If invalid interrupt
6609 */
6610 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6611 {
6612 bool queue_eh_work = false;
6613 irqreturn_t retval = IRQ_NONE;
6614
6615 spin_lock(hba->host->host_lock);
6616 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6617
6618 if (hba->errors & INT_FATAL_ERRORS) {
6619 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6620 hba->errors);
6621 queue_eh_work = true;
6622 }
6623
6624 if (hba->errors & UIC_ERROR) {
6625 hba->uic_error = 0;
6626 retval = ufshcd_update_uic_error(hba);
6627 if (hba->uic_error)
6628 queue_eh_work = true;
6629 }
6630
6631 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6632 dev_err(hba->dev,
6633 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6634 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6635 "Enter" : "Exit",
6636 hba->errors, ufshcd_get_upmcrs(hba));
6637 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6638 hba->errors);
6639 ufshcd_set_link_broken(hba);
6640 queue_eh_work = true;
6641 }
6642
6643 if (queue_eh_work) {
6644 /*
6645 * update the transfer error masks to sticky bits, let's do this
6646 * irrespective of current ufshcd_state.
6647 */
6648 hba->saved_err |= hba->errors;
6649 hba->saved_uic_err |= hba->uic_error;
6650
6651 /* dump controller state before resetting */
6652 if ((hba->saved_err &
6653 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6654 (hba->saved_uic_err &&
6655 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6656 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6657 __func__, hba->saved_err,
6658 hba->saved_uic_err);
6659 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6660 "host_regs: ");
6661 ufshcd_print_pwr_info(hba);
6662 }
6663 ufshcd_schedule_eh_work(hba);
6664 retval |= IRQ_HANDLED;
6665 }
6666 /*
6667 * if (!queue_eh_work) -
6668 * Other errors are either non-fatal where host recovers
6669 * itself without s/w intervention or errors that will be
6670 * handled by the SCSI core layer.
6671 */
6672 hba->errors = 0;
6673 hba->uic_error = 0;
6674 spin_unlock(hba->host->host_lock);
6675 return retval;
6676 }
6677
6678 /**
6679 * ufshcd_tmc_handler - handle task management function completion
6680 * @hba: per adapter instance
6681 *
6682 * Returns
6683 * IRQ_HANDLED - If interrupt is valid
6684 * IRQ_NONE - If invalid interrupt
6685 */
6686 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6687 {
6688 unsigned long flags, pending, issued;
6689 irqreturn_t ret = IRQ_NONE;
6690 int tag;
6691
6692 spin_lock_irqsave(hba->host->host_lock, flags);
6693 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6694 issued = hba->outstanding_tasks & ~pending;
6695 for_each_set_bit(tag, &issued, hba->nutmrs) {
6696 struct request *req = hba->tmf_rqs[tag];
6697 struct completion *c = req->end_io_data;
6698
6699 complete(c);
6700 ret = IRQ_HANDLED;
6701 }
6702 spin_unlock_irqrestore(hba->host->host_lock, flags);
6703
6704 return ret;
6705 }
6706
6707 /**
6708 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
6709 * @hba: per adapter instance
6710 *
6711 * Returns IRQ_HANDLED if interrupt is handled
6712 */
6713 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
6714 {
6715 struct ufs_hw_queue *hwq;
6716 unsigned long outstanding_cqs;
6717 unsigned int nr_queues;
6718 int i, ret;
6719 u32 events;
6720
6721 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs);
6722 if (ret)
6723 outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
6724
6725 /* Exclude the poll queues */
6726 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
6727 for_each_set_bit(i, &outstanding_cqs, nr_queues) {
6728 hwq = &hba->uhq[i];
6729
6730 events = ufshcd_mcq_read_cqis(hba, i);
6731 if (events)
6732 ufshcd_mcq_write_cqis(hba, events, i);
6733
6734 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
6735 ufshcd_mcq_poll_cqe_nolock(hba, hwq);
6736 }
6737
6738 return IRQ_HANDLED;
6739 }
6740
6741 /**
6742 * ufshcd_sl_intr - Interrupt service routine
6743 * @hba: per adapter instance
6744 * @intr_status: contains interrupts generated by the controller
6745 *
6746 * Returns
6747 * IRQ_HANDLED - If interrupt is valid
6748 * IRQ_NONE - If invalid interrupt
6749 */
6750 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6751 {
6752 irqreturn_t retval = IRQ_NONE;
6753
6754 if (intr_status & UFSHCD_UIC_MASK)
6755 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6756
6757 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6758 retval |= ufshcd_check_errors(hba, intr_status);
6759
6760 if (intr_status & UTP_TASK_REQ_COMPL)
6761 retval |= ufshcd_tmc_handler(hba);
6762
6763 if (intr_status & UTP_TRANSFER_REQ_COMPL)
6764 retval |= ufshcd_transfer_req_compl(hba);
6765
6766 if (intr_status & MCQ_CQ_EVENT_STATUS)
6767 retval |= ufshcd_handle_mcq_cq_events(hba);
6768
6769 return retval;
6770 }
6771
6772 /**
6773 * ufshcd_intr - Main interrupt service routine
6774 * @irq: irq number
6775 * @__hba: pointer to adapter instance
6776 *
6777 * Returns
6778 * IRQ_HANDLED - If interrupt is valid
6779 * IRQ_NONE - If invalid interrupt
6780 */
6781 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6782 {
6783 u32 intr_status, enabled_intr_status = 0;
6784 irqreturn_t retval = IRQ_NONE;
6785 struct ufs_hba *hba = __hba;
6786 int retries = hba->nutrs;
6787
6788 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6789 hba->ufs_stats.last_intr_status = intr_status;
6790 hba->ufs_stats.last_intr_ts = local_clock();
6791
6792 /*
6793 * There could be max of hba->nutrs reqs in flight and in worst case
6794 * if the reqs get finished 1 by 1 after the interrupt status is
6795 * read, make sure we handle them by checking the interrupt status
6796 * again in a loop until we process all of the reqs before returning.
6797 */
6798 while (intr_status && retries--) {
6799 enabled_intr_status =
6800 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6801 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6802 if (enabled_intr_status)
6803 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6804
6805 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6806 }
6807
6808 if (enabled_intr_status && retval == IRQ_NONE &&
6809 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6810 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6811 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6812 __func__,
6813 intr_status,
6814 hba->ufs_stats.last_intr_status,
6815 enabled_intr_status);
6816 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6817 }
6818
6819 return retval;
6820 }
6821
6822 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6823 {
6824 int err = 0;
6825 u32 mask = 1 << tag;
6826 unsigned long flags;
6827
6828 if (!test_bit(tag, &hba->outstanding_tasks))
6829 goto out;
6830
6831 spin_lock_irqsave(hba->host->host_lock, flags);
6832 ufshcd_utmrl_clear(hba, tag);
6833 spin_unlock_irqrestore(hba->host->host_lock, flags);
6834
6835 /* poll for max. 1 sec to clear door bell register by h/w */
6836 err = ufshcd_wait_for_register(hba,
6837 REG_UTP_TASK_REQ_DOOR_BELL,
6838 mask, 0, 1000, 1000);
6839
6840 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6841 tag, err ? "succeeded" : "failed");
6842
6843 out:
6844 return err;
6845 }
6846
6847 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6848 struct utp_task_req_desc *treq, u8 tm_function)
6849 {
6850 struct request_queue *q = hba->tmf_queue;
6851 struct Scsi_Host *host = hba->host;
6852 DECLARE_COMPLETION_ONSTACK(wait);
6853 struct request *req;
6854 unsigned long flags;
6855 int task_tag, err;
6856
6857 /*
6858 * blk_mq_alloc_request() is used here only to get a free tag.
6859 */
6860 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
6861 if (IS_ERR(req))
6862 return PTR_ERR(req);
6863
6864 req->end_io_data = &wait;
6865 ufshcd_hold(hba, false);
6866
6867 spin_lock_irqsave(host->host_lock, flags);
6868
6869 task_tag = req->tag;
6870 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6871 task_tag);
6872 hba->tmf_rqs[req->tag] = req;
6873 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6874
6875 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6876 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6877
6878 /* send command to the controller */
6879 __set_bit(task_tag, &hba->outstanding_tasks);
6880
6881 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6882 /* Make sure that doorbell is committed immediately */
6883 wmb();
6884
6885 spin_unlock_irqrestore(host->host_lock, flags);
6886
6887 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6888
6889 /* wait until the task management command is completed */
6890 err = wait_for_completion_io_timeout(&wait,
6891 msecs_to_jiffies(TM_CMD_TIMEOUT));
6892 if (!err) {
6893 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6894 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6895 __func__, tm_function);
6896 if (ufshcd_clear_tm_cmd(hba, task_tag))
6897 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6898 __func__, task_tag);
6899 err = -ETIMEDOUT;
6900 } else {
6901 err = 0;
6902 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6903
6904 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6905 }
6906
6907 spin_lock_irqsave(hba->host->host_lock, flags);
6908 hba->tmf_rqs[req->tag] = NULL;
6909 __clear_bit(task_tag, &hba->outstanding_tasks);
6910 spin_unlock_irqrestore(hba->host->host_lock, flags);
6911
6912 ufshcd_release(hba);
6913 blk_mq_free_request(req);
6914
6915 return err;
6916 }
6917
6918 /**
6919 * ufshcd_issue_tm_cmd - issues task management commands to controller
6920 * @hba: per adapter instance
6921 * @lun_id: LUN ID to which TM command is sent
6922 * @task_id: task ID to which the TM command is applicable
6923 * @tm_function: task management function opcode
6924 * @tm_response: task management service response return value
6925 *
6926 * Returns non-zero value on error, zero on success.
6927 */
6928 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6929 u8 tm_function, u8 *tm_response)
6930 {
6931 struct utp_task_req_desc treq = { { 0 }, };
6932 enum utp_ocs ocs_value;
6933 int err;
6934
6935 /* Configure task request descriptor */
6936 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6937 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6938
6939 /* Configure task request UPIU */
6940 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6941 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6942 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6943
6944 /*
6945 * The host shall provide the same value for LUN field in the basic
6946 * header and for Input Parameter.
6947 */
6948 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6949 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6950
6951 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6952 if (err == -ETIMEDOUT)
6953 return err;
6954
6955 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6956 if (ocs_value != OCS_SUCCESS)
6957 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6958 __func__, ocs_value);
6959 else if (tm_response)
6960 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6961 MASK_TM_SERVICE_RESP;
6962 return err;
6963 }
6964
6965 /**
6966 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6967 * @hba: per-adapter instance
6968 * @req_upiu: upiu request
6969 * @rsp_upiu: upiu reply
6970 * @desc_buff: pointer to descriptor buffer, NULL if NA
6971 * @buff_len: descriptor size, 0 if NA
6972 * @cmd_type: specifies the type (NOP, Query...)
6973 * @desc_op: descriptor operation
6974 *
6975 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6976 * Therefore, it "rides" the device management infrastructure: uses its tag and
6977 * tasks work queues.
6978 *
6979 * Since there is only one available tag for device management commands,
6980 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6981 */
6982 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6983 struct utp_upiu_req *req_upiu,
6984 struct utp_upiu_req *rsp_upiu,
6985 u8 *desc_buff, int *buff_len,
6986 enum dev_cmd_type cmd_type,
6987 enum query_opcode desc_op)
6988 {
6989 DECLARE_COMPLETION_ONSTACK(wait);
6990 const u32 tag = hba->reserved_slot;
6991 struct ufshcd_lrb *lrbp;
6992 int err = 0;
6993 u8 upiu_flags;
6994
6995 /* Protects use of hba->reserved_slot. */
6996 lockdep_assert_held(&hba->dev_cmd.lock);
6997
6998 down_read(&hba->clk_scaling_lock);
6999
7000 lrbp = &hba->lrb[tag];
7001 WARN_ON(lrbp->cmd);
7002 lrbp->cmd = NULL;
7003 lrbp->task_tag = tag;
7004 lrbp->lun = 0;
7005 lrbp->intr_cmd = true;
7006 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7007 hba->dev_cmd.type = cmd_type;
7008
7009 if (hba->ufs_version <= ufshci_version(1, 1))
7010 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
7011 else
7012 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7013
7014 /* update the task tag in the request upiu */
7015 req_upiu->header.dword_0 |= cpu_to_be32(tag);
7016
7017 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
7018
7019 /* just copy the upiu request as it is */
7020 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7021 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7022 /* The Data Segment Area is optional depending upon the query
7023 * function value. for WRITE DESCRIPTOR, the data segment
7024 * follows right after the tsf.
7025 */
7026 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7027 *buff_len = 0;
7028 }
7029
7030 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7031
7032 hba->dev_cmd.complete = &wait;
7033
7034 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
7035
7036 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7037 /*
7038 * ignore the returning value here - ufshcd_check_query_response is
7039 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
7040 * read the response directly ignoring all errors.
7041 */
7042 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
7043
7044 /* just copy the upiu response as it is */
7045 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7046 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7047 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7048 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
7049 MASK_QUERY_DATA_SEG_LEN;
7050
7051 if (*buff_len >= resp_len) {
7052 memcpy(desc_buff, descp, resp_len);
7053 *buff_len = resp_len;
7054 } else {
7055 dev_warn(hba->dev,
7056 "%s: rsp size %d is bigger than buffer size %d",
7057 __func__, resp_len, *buff_len);
7058 *buff_len = 0;
7059 err = -EINVAL;
7060 }
7061 }
7062 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
7063 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
7064
7065 up_read(&hba->clk_scaling_lock);
7066 return err;
7067 }
7068
7069 /**
7070 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7071 * @hba: per-adapter instance
7072 * @req_upiu: upiu request
7073 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
7074 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
7075 * @desc_buff: pointer to descriptor buffer, NULL if NA
7076 * @buff_len: descriptor size, 0 if NA
7077 * @desc_op: descriptor operation
7078 *
7079 * Supports UTP Transfer requests (nop and query), and UTP Task
7080 * Management requests.
7081 * It is up to the caller to fill the upiu conent properly, as it will
7082 * be copied without any further input validations.
7083 */
7084 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7085 struct utp_upiu_req *req_upiu,
7086 struct utp_upiu_req *rsp_upiu,
7087 int msgcode,
7088 u8 *desc_buff, int *buff_len,
7089 enum query_opcode desc_op)
7090 {
7091 int err;
7092 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7093 struct utp_task_req_desc treq = { { 0 }, };
7094 enum utp_ocs ocs_value;
7095 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
7096
7097 switch (msgcode) {
7098 case UPIU_TRANSACTION_NOP_OUT:
7099 cmd_type = DEV_CMD_TYPE_NOP;
7100 fallthrough;
7101 case UPIU_TRANSACTION_QUERY_REQ:
7102 ufshcd_hold(hba, false);
7103 mutex_lock(&hba->dev_cmd.lock);
7104 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7105 desc_buff, buff_len,
7106 cmd_type, desc_op);
7107 mutex_unlock(&hba->dev_cmd.lock);
7108 ufshcd_release(hba);
7109
7110 break;
7111 case UPIU_TRANSACTION_TASK_REQ:
7112 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
7113 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
7114
7115 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7116
7117 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
7118 if (err == -ETIMEDOUT)
7119 break;
7120
7121 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
7122 if (ocs_value != OCS_SUCCESS) {
7123 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7124 ocs_value);
7125 break;
7126 }
7127
7128 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7129
7130 break;
7131 default:
7132 err = -EINVAL;
7133
7134 break;
7135 }
7136
7137 return err;
7138 }
7139
7140 /**
7141 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7142 * @hba: per adapter instance
7143 * @req_upiu: upiu request
7144 * @rsp_upiu: upiu reply
7145 * @req_ehs: EHS field which contains Advanced RPMB Request Message
7146 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message
7147 * @sg_cnt: The number of sg lists actually used
7148 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7149 * @dir: DMA direction
7150 *
7151 * Returns zero on success, non-zero on failure
7152 */
7153 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7154 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7155 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7156 enum dma_data_direction dir)
7157 {
7158 DECLARE_COMPLETION_ONSTACK(wait);
7159 const u32 tag = hba->reserved_slot;
7160 struct ufshcd_lrb *lrbp;
7161 int err = 0;
7162 int result;
7163 u8 upiu_flags;
7164 u8 *ehs_data;
7165 u16 ehs_len;
7166
7167 /* Protects use of hba->reserved_slot. */
7168 ufshcd_hold(hba, false);
7169 mutex_lock(&hba->dev_cmd.lock);
7170 down_read(&hba->clk_scaling_lock);
7171
7172 lrbp = &hba->lrb[tag];
7173 WARN_ON(lrbp->cmd);
7174 lrbp->cmd = NULL;
7175 lrbp->task_tag = tag;
7176 lrbp->lun = UFS_UPIU_RPMB_WLUN;
7177
7178 lrbp->intr_cmd = true;
7179 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7180 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB;
7181
7182 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */
7183 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7184
7185 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2);
7186
7187 /* update the task tag and LUN in the request upiu */
7188 req_upiu->header.dword_0 |= cpu_to_be32(upiu_flags << 16 | UFS_UPIU_RPMB_WLUN << 8 | tag);
7189
7190 /* copy the UPIU(contains CDB) request as it is */
7191 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7192 /* Copy EHS, starting with byte32, immediately after the CDB package */
7193 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7194
7195 if (dir != DMA_NONE && sg_list)
7196 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7197
7198 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7199
7200 hba->dev_cmd.complete = &wait;
7201
7202 ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7203
7204 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT);
7205
7206 if (!err) {
7207 /* Just copy the upiu response as it is */
7208 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7209 /* Get the response UPIU result */
7210 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
7211
7212 ehs_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) >> 24;
7213 /*
7214 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7215 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7216 * Message is 02h
7217 */
7218 if (ehs_len == 2 && rsp_ehs) {
7219 /*
7220 * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7221 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7222 */
7223 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7224 memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7225 }
7226 }
7227
7228 up_read(&hba->clk_scaling_lock);
7229 mutex_unlock(&hba->dev_cmd.lock);
7230 ufshcd_release(hba);
7231 return err ? : result;
7232 }
7233
7234 /**
7235 * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7236 * @cmd: SCSI command pointer
7237 *
7238 * Returns SUCCESS/FAILED
7239 */
7240 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7241 {
7242 unsigned long flags, pending_reqs = 0, not_cleared = 0;
7243 struct Scsi_Host *host;
7244 struct ufs_hba *hba;
7245 u32 pos;
7246 int err;
7247 u8 resp = 0xF, lun;
7248
7249 host = cmd->device->host;
7250 hba = shost_priv(host);
7251
7252 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7253 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7254 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7255 if (!err)
7256 err = resp;
7257 goto out;
7258 }
7259
7260 /* clear the commands that were pending for corresponding LUN */
7261 spin_lock_irqsave(&hba->outstanding_lock, flags);
7262 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7263 if (hba->lrb[pos].lun == lun)
7264 __set_bit(pos, &pending_reqs);
7265 hba->outstanding_reqs &= ~pending_reqs;
7266 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7267
7268 if (ufshcd_clear_cmds(hba, pending_reqs) < 0) {
7269 spin_lock_irqsave(&hba->outstanding_lock, flags);
7270 not_cleared = pending_reqs &
7271 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7272 hba->outstanding_reqs |= not_cleared;
7273 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7274
7275 dev_err(hba->dev, "%s: failed to clear requests %#lx\n",
7276 __func__, not_cleared);
7277 }
7278 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared);
7279
7280 out:
7281 hba->req_abort_count = 0;
7282 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7283 if (!err) {
7284 err = SUCCESS;
7285 } else {
7286 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7287 err = FAILED;
7288 }
7289 return err;
7290 }
7291
7292 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7293 {
7294 struct ufshcd_lrb *lrbp;
7295 int tag;
7296
7297 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7298 lrbp = &hba->lrb[tag];
7299 lrbp->req_abort_skip = true;
7300 }
7301 }
7302
7303 /**
7304 * ufshcd_try_to_abort_task - abort a specific task
7305 * @hba: Pointer to adapter instance
7306 * @tag: Task tag/index to be aborted
7307 *
7308 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7309 * command, and in host controller by clearing the door-bell register. There can
7310 * be race between controller sending the command to the device while abort is
7311 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7312 * really issued and then try to abort it.
7313 *
7314 * Returns zero on success, non-zero on failure
7315 */
7316 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7317 {
7318 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7319 int err = 0;
7320 int poll_cnt;
7321 u8 resp = 0xF;
7322 u32 reg;
7323
7324 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7325 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7326 UFS_QUERY_TASK, &resp);
7327 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7328 /* cmd pending in the device */
7329 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7330 __func__, tag);
7331 break;
7332 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7333 /*
7334 * cmd not pending in the device, check if it is
7335 * in transition.
7336 */
7337 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7338 __func__, tag);
7339 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7340 if (reg & (1 << tag)) {
7341 /* sleep for max. 200us to stabilize */
7342 usleep_range(100, 200);
7343 continue;
7344 }
7345 /* command completed already */
7346 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7347 __func__, tag);
7348 goto out;
7349 } else {
7350 dev_err(hba->dev,
7351 "%s: no response from device. tag = %d, err %d\n",
7352 __func__, tag, err);
7353 if (!err)
7354 err = resp; /* service response error */
7355 goto out;
7356 }
7357 }
7358
7359 if (!poll_cnt) {
7360 err = -EBUSY;
7361 goto out;
7362 }
7363
7364 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7365 UFS_ABORT_TASK, &resp);
7366 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7367 if (!err) {
7368 err = resp; /* service response error */
7369 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7370 __func__, tag, err);
7371 }
7372 goto out;
7373 }
7374
7375 err = ufshcd_clear_cmds(hba, 1U << tag);
7376 if (err)
7377 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7378 __func__, tag, err);
7379
7380 out:
7381 return err;
7382 }
7383
7384 /**
7385 * ufshcd_abort - scsi host template eh_abort_handler callback
7386 * @cmd: SCSI command pointer
7387 *
7388 * Returns SUCCESS/FAILED
7389 */
7390 static int ufshcd_abort(struct scsi_cmnd *cmd)
7391 {
7392 struct Scsi_Host *host = cmd->device->host;
7393 struct ufs_hba *hba = shost_priv(host);
7394 int tag = scsi_cmd_to_rq(cmd)->tag;
7395 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7396 unsigned long flags;
7397 int err = FAILED;
7398 bool outstanding;
7399 u32 reg;
7400
7401 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7402
7403 ufshcd_hold(hba, false);
7404 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7405 /* If command is already aborted/completed, return FAILED. */
7406 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7407 dev_err(hba->dev,
7408 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7409 __func__, tag, hba->outstanding_reqs, reg);
7410 goto release;
7411 }
7412
7413 /* Print Transfer Request of aborted task */
7414 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7415
7416 /*
7417 * Print detailed info about aborted request.
7418 * As more than one request might get aborted at the same time,
7419 * print full information only for the first aborted request in order
7420 * to reduce repeated printouts. For other aborted requests only print
7421 * basic details.
7422 */
7423 scsi_print_command(cmd);
7424 if (!hba->req_abort_count) {
7425 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7426 ufshcd_print_evt_hist(hba);
7427 ufshcd_print_host_state(hba);
7428 ufshcd_print_pwr_info(hba);
7429 ufshcd_print_trs(hba, 1 << tag, true);
7430 } else {
7431 ufshcd_print_trs(hba, 1 << tag, false);
7432 }
7433 hba->req_abort_count++;
7434
7435 if (!(reg & (1 << tag))) {
7436 dev_err(hba->dev,
7437 "%s: cmd was completed, but without a notifying intr, tag = %d",
7438 __func__, tag);
7439 __ufshcd_transfer_req_compl(hba, 1UL << tag);
7440 goto release;
7441 }
7442
7443 /*
7444 * Task abort to the device W-LUN is illegal. When this command
7445 * will fail, due to spec violation, scsi err handling next step
7446 * will be to send LU reset which, again, is a spec violation.
7447 * To avoid these unnecessary/illegal steps, first we clean up
7448 * the lrb taken by this cmd and re-set it in outstanding_reqs,
7449 * then queue the eh_work and bail.
7450 */
7451 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7452 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7453
7454 spin_lock_irqsave(host->host_lock, flags);
7455 hba->force_reset = true;
7456 ufshcd_schedule_eh_work(hba);
7457 spin_unlock_irqrestore(host->host_lock, flags);
7458 goto release;
7459 }
7460
7461 /* Skip task abort in case previous aborts failed and report failure */
7462 if (lrbp->req_abort_skip) {
7463 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7464 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7465 goto release;
7466 }
7467
7468 err = ufshcd_try_to_abort_task(hba, tag);
7469 if (err) {
7470 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7471 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7472 err = FAILED;
7473 goto release;
7474 }
7475
7476 /*
7477 * Clear the corresponding bit from outstanding_reqs since the command
7478 * has been aborted successfully.
7479 */
7480 spin_lock_irqsave(&hba->outstanding_lock, flags);
7481 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7482 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7483
7484 if (outstanding)
7485 ufshcd_release_scsi_cmd(hba, lrbp);
7486
7487 err = SUCCESS;
7488
7489 release:
7490 /* Matches the ufshcd_hold() call at the start of this function. */
7491 ufshcd_release(hba);
7492 return err;
7493 }
7494
7495 /**
7496 * ufshcd_host_reset_and_restore - reset and restore host controller
7497 * @hba: per-adapter instance
7498 *
7499 * Note that host controller reset may issue DME_RESET to
7500 * local and remote (device) Uni-Pro stack and the attributes
7501 * are reset to default state.
7502 *
7503 * Returns zero on success, non-zero on failure
7504 */
7505 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7506 {
7507 int err;
7508
7509 /*
7510 * Stop the host controller and complete the requests
7511 * cleared by h/w
7512 */
7513 ufshpb_toggle_state(hba, HPB_PRESENT, HPB_RESET);
7514 ufshcd_hba_stop(hba);
7515 hba->silence_err_logs = true;
7516 ufshcd_complete_requests(hba);
7517 hba->silence_err_logs = false;
7518
7519 /* scale up clocks to max frequency before full reinitialization */
7520 ufshcd_scale_clks(hba, true);
7521
7522 err = ufshcd_hba_enable(hba);
7523
7524 /* Establish the link again and restore the device */
7525 if (!err)
7526 err = ufshcd_probe_hba(hba, false);
7527
7528 if (err)
7529 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7530 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7531 return err;
7532 }
7533
7534 /**
7535 * ufshcd_reset_and_restore - reset and re-initialize host/device
7536 * @hba: per-adapter instance
7537 *
7538 * Reset and recover device, host and re-establish link. This
7539 * is helpful to recover the communication in fatal error conditions.
7540 *
7541 * Returns zero on success, non-zero on failure
7542 */
7543 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7544 {
7545 u32 saved_err = 0;
7546 u32 saved_uic_err = 0;
7547 int err = 0;
7548 unsigned long flags;
7549 int retries = MAX_HOST_RESET_RETRIES;
7550
7551 spin_lock_irqsave(hba->host->host_lock, flags);
7552 do {
7553 /*
7554 * This is a fresh start, cache and clear saved error first,
7555 * in case new error generated during reset and restore.
7556 */
7557 saved_err |= hba->saved_err;
7558 saved_uic_err |= hba->saved_uic_err;
7559 hba->saved_err = 0;
7560 hba->saved_uic_err = 0;
7561 hba->force_reset = false;
7562 hba->ufshcd_state = UFSHCD_STATE_RESET;
7563 spin_unlock_irqrestore(hba->host->host_lock, flags);
7564
7565 /* Reset the attached device */
7566 ufshcd_device_reset(hba);
7567
7568 err = ufshcd_host_reset_and_restore(hba);
7569
7570 spin_lock_irqsave(hba->host->host_lock, flags);
7571 if (err)
7572 continue;
7573 /* Do not exit unless operational or dead */
7574 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7575 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7576 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7577 err = -EAGAIN;
7578 } while (err && --retries);
7579
7580 /*
7581 * Inform scsi mid-layer that we did reset and allow to handle
7582 * Unit Attention properly.
7583 */
7584 scsi_report_bus_reset(hba->host, 0);
7585 if (err) {
7586 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7587 hba->saved_err |= saved_err;
7588 hba->saved_uic_err |= saved_uic_err;
7589 }
7590 spin_unlock_irqrestore(hba->host->host_lock, flags);
7591
7592 return err;
7593 }
7594
7595 /**
7596 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7597 * @cmd: SCSI command pointer
7598 *
7599 * Returns SUCCESS/FAILED
7600 */
7601 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7602 {
7603 int err = SUCCESS;
7604 unsigned long flags;
7605 struct ufs_hba *hba;
7606
7607 hba = shost_priv(cmd->device->host);
7608
7609 spin_lock_irqsave(hba->host->host_lock, flags);
7610 hba->force_reset = true;
7611 ufshcd_schedule_eh_work(hba);
7612 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7613 spin_unlock_irqrestore(hba->host->host_lock, flags);
7614
7615 flush_work(&hba->eh_work);
7616
7617 spin_lock_irqsave(hba->host->host_lock, flags);
7618 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7619 err = FAILED;
7620 spin_unlock_irqrestore(hba->host->host_lock, flags);
7621
7622 return err;
7623 }
7624
7625 /**
7626 * ufshcd_get_max_icc_level - calculate the ICC level
7627 * @sup_curr_uA: max. current supported by the regulator
7628 * @start_scan: row at the desc table to start scan from
7629 * @buff: power descriptor buffer
7630 *
7631 * Returns calculated max ICC level for specific regulator
7632 */
7633 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7634 const char *buff)
7635 {
7636 int i;
7637 int curr_uA;
7638 u16 data;
7639 u16 unit;
7640
7641 for (i = start_scan; i >= 0; i--) {
7642 data = get_unaligned_be16(&buff[2 * i]);
7643 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7644 ATTR_ICC_LVL_UNIT_OFFSET;
7645 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7646 switch (unit) {
7647 case UFSHCD_NANO_AMP:
7648 curr_uA = curr_uA / 1000;
7649 break;
7650 case UFSHCD_MILI_AMP:
7651 curr_uA = curr_uA * 1000;
7652 break;
7653 case UFSHCD_AMP:
7654 curr_uA = curr_uA * 1000 * 1000;
7655 break;
7656 case UFSHCD_MICRO_AMP:
7657 default:
7658 break;
7659 }
7660 if (sup_curr_uA >= curr_uA)
7661 break;
7662 }
7663 if (i < 0) {
7664 i = 0;
7665 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7666 }
7667
7668 return (u32)i;
7669 }
7670
7671 /**
7672 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7673 * In case regulators are not initialized we'll return 0
7674 * @hba: per-adapter instance
7675 * @desc_buf: power descriptor buffer to extract ICC levels from.
7676 *
7677 * Returns calculated ICC level
7678 */
7679 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7680 const u8 *desc_buf)
7681 {
7682 u32 icc_level = 0;
7683
7684 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7685 !hba->vreg_info.vccq2) {
7686 /*
7687 * Using dev_dbg to avoid messages during runtime PM to avoid
7688 * never-ending cycles of messages written back to storage by
7689 * user space causing runtime resume, causing more messages and
7690 * so on.
7691 */
7692 dev_dbg(hba->dev,
7693 "%s: Regulator capability was not set, actvIccLevel=%d",
7694 __func__, icc_level);
7695 goto out;
7696 }
7697
7698 if (hba->vreg_info.vcc->max_uA)
7699 icc_level = ufshcd_get_max_icc_level(
7700 hba->vreg_info.vcc->max_uA,
7701 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7702 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7703
7704 if (hba->vreg_info.vccq->max_uA)
7705 icc_level = ufshcd_get_max_icc_level(
7706 hba->vreg_info.vccq->max_uA,
7707 icc_level,
7708 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7709
7710 if (hba->vreg_info.vccq2->max_uA)
7711 icc_level = ufshcd_get_max_icc_level(
7712 hba->vreg_info.vccq2->max_uA,
7713 icc_level,
7714 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7715 out:
7716 return icc_level;
7717 }
7718
7719 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7720 {
7721 int ret;
7722 u8 *desc_buf;
7723 u32 icc_level;
7724
7725 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7726 if (!desc_buf)
7727 return;
7728
7729 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7730 desc_buf, QUERY_DESC_MAX_SIZE);
7731 if (ret) {
7732 dev_err(hba->dev,
7733 "%s: Failed reading power descriptor ret = %d",
7734 __func__, ret);
7735 goto out;
7736 }
7737
7738 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
7739 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7740
7741 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7742 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7743
7744 if (ret)
7745 dev_err(hba->dev,
7746 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7747 __func__, icc_level, ret);
7748
7749 out:
7750 kfree(desc_buf);
7751 }
7752
7753 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7754 {
7755 scsi_autopm_get_device(sdev);
7756 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7757 if (sdev->rpm_autosuspend)
7758 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7759 RPM_AUTOSUSPEND_DELAY_MS);
7760 scsi_autopm_put_device(sdev);
7761 }
7762
7763 /**
7764 * ufshcd_scsi_add_wlus - Adds required W-LUs
7765 * @hba: per-adapter instance
7766 *
7767 * UFS device specification requires the UFS devices to support 4 well known
7768 * logical units:
7769 * "REPORT_LUNS" (address: 01h)
7770 * "UFS Device" (address: 50h)
7771 * "RPMB" (address: 44h)
7772 * "BOOT" (address: 30h)
7773 * UFS device's power management needs to be controlled by "POWER CONDITION"
7774 * field of SSU (START STOP UNIT) command. But this "power condition" field
7775 * will take effect only when its sent to "UFS device" well known logical unit
7776 * hence we require the scsi_device instance to represent this logical unit in
7777 * order for the UFS host driver to send the SSU command for power management.
7778 *
7779 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7780 * Block) LU so user space process can control this LU. User space may also
7781 * want to have access to BOOT LU.
7782 *
7783 * This function adds scsi device instances for each of all well known LUs
7784 * (except "REPORT LUNS" LU).
7785 *
7786 * Returns zero on success (all required W-LUs are added successfully),
7787 * non-zero error value on failure (if failed to add any of the required W-LU).
7788 */
7789 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7790 {
7791 int ret = 0;
7792 struct scsi_device *sdev_boot, *sdev_rpmb;
7793
7794 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
7795 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7796 if (IS_ERR(hba->ufs_device_wlun)) {
7797 ret = PTR_ERR(hba->ufs_device_wlun);
7798 hba->ufs_device_wlun = NULL;
7799 goto out;
7800 }
7801 scsi_device_put(hba->ufs_device_wlun);
7802
7803 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7804 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7805 if (IS_ERR(sdev_rpmb)) {
7806 ret = PTR_ERR(sdev_rpmb);
7807 goto remove_ufs_device_wlun;
7808 }
7809 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7810 scsi_device_put(sdev_rpmb);
7811
7812 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7813 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7814 if (IS_ERR(sdev_boot)) {
7815 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7816 } else {
7817 ufshcd_blk_pm_runtime_init(sdev_boot);
7818 scsi_device_put(sdev_boot);
7819 }
7820 goto out;
7821
7822 remove_ufs_device_wlun:
7823 scsi_remove_device(hba->ufs_device_wlun);
7824 out:
7825 return ret;
7826 }
7827
7828 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
7829 {
7830 struct ufs_dev_info *dev_info = &hba->dev_info;
7831 u8 lun;
7832 u32 d_lu_wb_buf_alloc;
7833 u32 ext_ufs_feature;
7834
7835 if (!ufshcd_is_wb_allowed(hba))
7836 return;
7837
7838 /*
7839 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7840 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7841 * enabled
7842 */
7843 if (!(dev_info->wspecversion >= 0x310 ||
7844 dev_info->wspecversion == 0x220 ||
7845 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7846 goto wb_disabled;
7847
7848 ext_ufs_feature = get_unaligned_be32(desc_buf +
7849 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7850
7851 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7852 goto wb_disabled;
7853
7854 /*
7855 * WB may be supported but not configured while provisioning. The spec
7856 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7857 * buffer configured.
7858 */
7859 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7860
7861 dev_info->b_presrv_uspc_en =
7862 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7863
7864 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7865 if (!get_unaligned_be32(desc_buf +
7866 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7867 goto wb_disabled;
7868 } else {
7869 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7870 d_lu_wb_buf_alloc = 0;
7871 ufshcd_read_unit_desc_param(hba,
7872 lun,
7873 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7874 (u8 *)&d_lu_wb_buf_alloc,
7875 sizeof(d_lu_wb_buf_alloc));
7876 if (d_lu_wb_buf_alloc) {
7877 dev_info->wb_dedicated_lu = lun;
7878 break;
7879 }
7880 }
7881
7882 if (!d_lu_wb_buf_alloc)
7883 goto wb_disabled;
7884 }
7885
7886 if (!ufshcd_is_wb_buf_lifetime_available(hba))
7887 goto wb_disabled;
7888
7889 return;
7890
7891 wb_disabled:
7892 hba->caps &= ~UFSHCD_CAP_WB_EN;
7893 }
7894
7895 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
7896 {
7897 struct ufs_dev_info *dev_info = &hba->dev_info;
7898 u32 ext_ufs_feature;
7899 u8 mask = 0;
7900
7901 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7902 return;
7903
7904 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7905
7906 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7907 mask |= MASK_EE_TOO_LOW_TEMP;
7908
7909 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7910 mask |= MASK_EE_TOO_HIGH_TEMP;
7911
7912 if (mask) {
7913 ufshcd_enable_ee(hba, mask);
7914 ufs_hwmon_probe(hba, mask);
7915 }
7916 }
7917
7918 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf)
7919 {
7920 struct ufs_dev_info *dev_info = &hba->dev_info;
7921 u32 ext_ufs_feature;
7922 u32 ext_iid_en = 0;
7923 int err;
7924
7925 /* Only UFS-4.0 and above may support EXT_IID */
7926 if (dev_info->wspecversion < 0x400)
7927 goto out;
7928
7929 ext_ufs_feature = get_unaligned_be32(desc_buf +
7930 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7931 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP))
7932 goto out;
7933
7934 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7935 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en);
7936 if (err)
7937 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err);
7938
7939 out:
7940 dev_info->b_ext_iid_en = ext_iid_en;
7941 }
7942
7943 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
7944 const struct ufs_dev_quirk *fixups)
7945 {
7946 const struct ufs_dev_quirk *f;
7947 struct ufs_dev_info *dev_info = &hba->dev_info;
7948
7949 if (!fixups)
7950 return;
7951
7952 for (f = fixups; f->quirk; f++) {
7953 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7954 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7955 ((dev_info->model &&
7956 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7957 !strcmp(f->model, UFS_ANY_MODEL)))
7958 hba->dev_quirks |= f->quirk;
7959 }
7960 }
7961 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7962
7963 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7964 {
7965 /* fix by general quirk table */
7966 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7967
7968 /* allow vendors to fix quirks */
7969 ufshcd_vops_fixup_dev_quirks(hba);
7970 }
7971
7972 static int ufs_get_device_desc(struct ufs_hba *hba)
7973 {
7974 int err;
7975 u8 model_index;
7976 u8 b_ufs_feature_sup;
7977 u8 *desc_buf;
7978 struct ufs_dev_info *dev_info = &hba->dev_info;
7979
7980 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7981 if (!desc_buf) {
7982 err = -ENOMEM;
7983 goto out;
7984 }
7985
7986 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7987 QUERY_DESC_MAX_SIZE);
7988 if (err) {
7989 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7990 __func__, err);
7991 goto out;
7992 }
7993
7994 /*
7995 * getting vendor (manufacturerID) and Bank Index in big endian
7996 * format
7997 */
7998 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7999 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8000
8001 /* getting Specification Version in big endian format */
8002 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8003 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8004 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8005 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
8006
8007 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8008
8009 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
8010 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
8011 bool hpb_en = false;
8012
8013 ufshpb_get_dev_info(hba, desc_buf);
8014
8015 if (!ufshpb_is_legacy(hba))
8016 err = ufshcd_query_flag_retry(hba,
8017 UPIU_QUERY_OPCODE_READ_FLAG,
8018 QUERY_FLAG_IDN_HPB_EN, 0,
8019 &hpb_en);
8020
8021 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
8022 dev_info->hpb_enabled = true;
8023 }
8024
8025 err = ufshcd_read_string_desc(hba, model_index,
8026 &dev_info->model, SD_ASCII_STD);
8027 if (err < 0) {
8028 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8029 __func__, err);
8030 goto out;
8031 }
8032
8033 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8034 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8035
8036 ufs_fixup_device_setup(hba);
8037
8038 ufshcd_wb_probe(hba, desc_buf);
8039
8040 ufshcd_temp_notif_probe(hba, desc_buf);
8041
8042 if (hba->ext_iid_sup)
8043 ufshcd_ext_iid_probe(hba, desc_buf);
8044
8045 /*
8046 * ufshcd_read_string_desc returns size of the string
8047 * reset the error value
8048 */
8049 err = 0;
8050
8051 out:
8052 kfree(desc_buf);
8053 return err;
8054 }
8055
8056 static void ufs_put_device_desc(struct ufs_hba *hba)
8057 {
8058 struct ufs_dev_info *dev_info = &hba->dev_info;
8059
8060 kfree(dev_info->model);
8061 dev_info->model = NULL;
8062 }
8063
8064 /**
8065 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
8066 * @hba: per-adapter instance
8067 *
8068 * PA_TActivate parameter can be tuned manually if UniPro version is less than
8069 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
8070 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
8071 * the hibern8 exit latency.
8072 *
8073 * Returns zero on success, non-zero error value on failure.
8074 */
8075 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
8076 {
8077 int ret = 0;
8078 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
8079
8080 ret = ufshcd_dme_peer_get(hba,
8081 UIC_ARG_MIB_SEL(
8082 RX_MIN_ACTIVATETIME_CAPABILITY,
8083 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8084 &peer_rx_min_activatetime);
8085 if (ret)
8086 goto out;
8087
8088 /* make sure proper unit conversion is applied */
8089 tuned_pa_tactivate =
8090 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
8091 / PA_TACTIVATE_TIME_UNIT_US);
8092 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8093 tuned_pa_tactivate);
8094
8095 out:
8096 return ret;
8097 }
8098
8099 /**
8100 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
8101 * @hba: per-adapter instance
8102 *
8103 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
8104 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
8105 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
8106 * This optimal value can help reduce the hibern8 exit latency.
8107 *
8108 * Returns zero on success, non-zero error value on failure.
8109 */
8110 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
8111 {
8112 int ret = 0;
8113 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
8114 u32 max_hibern8_time, tuned_pa_hibern8time;
8115
8116 ret = ufshcd_dme_get(hba,
8117 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
8118 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
8119 &local_tx_hibern8_time_cap);
8120 if (ret)
8121 goto out;
8122
8123 ret = ufshcd_dme_peer_get(hba,
8124 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
8125 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8126 &peer_rx_hibern8_time_cap);
8127 if (ret)
8128 goto out;
8129
8130 max_hibern8_time = max(local_tx_hibern8_time_cap,
8131 peer_rx_hibern8_time_cap);
8132 /* make sure proper unit conversion is applied */
8133 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
8134 / PA_HIBERN8_TIME_UNIT_US);
8135 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
8136 tuned_pa_hibern8time);
8137 out:
8138 return ret;
8139 }
8140
8141 /**
8142 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8143 * less than device PA_TACTIVATE time.
8144 * @hba: per-adapter instance
8145 *
8146 * Some UFS devices require host PA_TACTIVATE to be lower than device
8147 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8148 * for such devices.
8149 *
8150 * Returns zero on success, non-zero error value on failure.
8151 */
8152 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8153 {
8154 int ret = 0;
8155 u32 granularity, peer_granularity;
8156 u32 pa_tactivate, peer_pa_tactivate;
8157 u32 pa_tactivate_us, peer_pa_tactivate_us;
8158 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8159
8160 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8161 &granularity);
8162 if (ret)
8163 goto out;
8164
8165 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8166 &peer_granularity);
8167 if (ret)
8168 goto out;
8169
8170 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8171 (granularity > PA_GRANULARITY_MAX_VAL)) {
8172 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8173 __func__, granularity);
8174 return -EINVAL;
8175 }
8176
8177 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8178 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8179 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8180 __func__, peer_granularity);
8181 return -EINVAL;
8182 }
8183
8184 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8185 if (ret)
8186 goto out;
8187
8188 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8189 &peer_pa_tactivate);
8190 if (ret)
8191 goto out;
8192
8193 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8194 peer_pa_tactivate_us = peer_pa_tactivate *
8195 gran_to_us_table[peer_granularity - 1];
8196
8197 if (pa_tactivate_us >= peer_pa_tactivate_us) {
8198 u32 new_peer_pa_tactivate;
8199
8200 new_peer_pa_tactivate = pa_tactivate_us /
8201 gran_to_us_table[peer_granularity - 1];
8202 new_peer_pa_tactivate++;
8203 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8204 new_peer_pa_tactivate);
8205 }
8206
8207 out:
8208 return ret;
8209 }
8210
8211 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8212 {
8213 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
8214 ufshcd_tune_pa_tactivate(hba);
8215 ufshcd_tune_pa_hibern8time(hba);
8216 }
8217
8218 ufshcd_vops_apply_dev_quirks(hba);
8219
8220 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8221 /* set 1ms timeout for PA_TACTIVATE */
8222 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
8223
8224 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8225 ufshcd_quirk_tune_host_pa_tactivate(hba);
8226 }
8227
8228 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8229 {
8230 hba->ufs_stats.hibern8_exit_cnt = 0;
8231 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
8232 hba->req_abort_count = 0;
8233 }
8234
8235 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8236 {
8237 int err;
8238 u8 *desc_buf;
8239
8240 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8241 if (!desc_buf) {
8242 err = -ENOMEM;
8243 goto out;
8244 }
8245
8246 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
8247 desc_buf, QUERY_DESC_MAX_SIZE);
8248 if (err) {
8249 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8250 __func__, err);
8251 goto out;
8252 }
8253
8254 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8255 hba->dev_info.max_lu_supported = 32;
8256 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8257 hba->dev_info.max_lu_supported = 8;
8258
8259 if (desc_buf[QUERY_DESC_LENGTH_OFFSET] >=
8260 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
8261 ufshpb_get_geo_info(hba, desc_buf);
8262
8263 out:
8264 kfree(desc_buf);
8265 return err;
8266 }
8267
8268 struct ufs_ref_clk {
8269 unsigned long freq_hz;
8270 enum ufs_ref_clk_freq val;
8271 };
8272
8273 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8274 {19200000, REF_CLK_FREQ_19_2_MHZ},
8275 {26000000, REF_CLK_FREQ_26_MHZ},
8276 {38400000, REF_CLK_FREQ_38_4_MHZ},
8277 {52000000, REF_CLK_FREQ_52_MHZ},
8278 {0, REF_CLK_FREQ_INVAL},
8279 };
8280
8281 static enum ufs_ref_clk_freq
8282 ufs_get_bref_clk_from_hz(unsigned long freq)
8283 {
8284 int i;
8285
8286 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8287 if (ufs_ref_clk_freqs[i].freq_hz == freq)
8288 return ufs_ref_clk_freqs[i].val;
8289
8290 return REF_CLK_FREQ_INVAL;
8291 }
8292
8293 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8294 {
8295 unsigned long freq;
8296
8297 freq = clk_get_rate(refclk);
8298
8299 hba->dev_ref_clk_freq =
8300 ufs_get_bref_clk_from_hz(freq);
8301
8302 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8303 dev_err(hba->dev,
8304 "invalid ref_clk setting = %ld\n", freq);
8305 }
8306
8307 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8308 {
8309 int err;
8310 u32 ref_clk;
8311 u32 freq = hba->dev_ref_clk_freq;
8312
8313 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8314 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8315
8316 if (err) {
8317 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8318 err);
8319 goto out;
8320 }
8321
8322 if (ref_clk == freq)
8323 goto out; /* nothing to update */
8324
8325 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8326 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8327
8328 if (err) {
8329 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8330 ufs_ref_clk_freqs[freq].freq_hz);
8331 goto out;
8332 }
8333
8334 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8335 ufs_ref_clk_freqs[freq].freq_hz);
8336
8337 out:
8338 return err;
8339 }
8340
8341 static int ufshcd_device_params_init(struct ufs_hba *hba)
8342 {
8343 bool flag;
8344 int ret;
8345
8346 /* Init UFS geometry descriptor related parameters */
8347 ret = ufshcd_device_geo_params_init(hba);
8348 if (ret)
8349 goto out;
8350
8351 /* Check and apply UFS device quirks */
8352 ret = ufs_get_device_desc(hba);
8353 if (ret) {
8354 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8355 __func__, ret);
8356 goto out;
8357 }
8358
8359 ufshcd_get_ref_clk_gating_wait(hba);
8360
8361 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8362 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8363 hba->dev_info.f_power_on_wp_en = flag;
8364
8365 /* Probe maximum power mode co-supported by both UFS host and device */
8366 if (ufshcd_get_max_pwr_mode(hba))
8367 dev_err(hba->dev,
8368 "%s: Failed getting max supported power mode\n",
8369 __func__);
8370 out:
8371 return ret;
8372 }
8373
8374 /**
8375 * ufshcd_add_lus - probe and add UFS logical units
8376 * @hba: per-adapter instance
8377 */
8378 static int ufshcd_add_lus(struct ufs_hba *hba)
8379 {
8380 int ret;
8381
8382 /* Add required well known logical units to scsi mid layer */
8383 ret = ufshcd_scsi_add_wlus(hba);
8384 if (ret)
8385 goto out;
8386
8387 /* Initialize devfreq after UFS device is detected */
8388 if (ufshcd_is_clkscaling_supported(hba)) {
8389 memcpy(&hba->clk_scaling.saved_pwr_info.info,
8390 &hba->pwr_info,
8391 sizeof(struct ufs_pa_layer_attr));
8392 hba->clk_scaling.saved_pwr_info.is_valid = true;
8393 hba->clk_scaling.is_allowed = true;
8394
8395 ret = ufshcd_devfreq_init(hba);
8396 if (ret)
8397 goto out;
8398
8399 hba->clk_scaling.is_enabled = true;
8400 ufshcd_init_clk_scaling_sysfs(hba);
8401 }
8402
8403 ufs_bsg_probe(hba);
8404 ufshpb_init(hba);
8405 scsi_scan_host(hba->host);
8406 pm_runtime_put_sync(hba->dev);
8407
8408 out:
8409 return ret;
8410 }
8411
8412 /* SDB - Single Doorbell */
8413 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
8414 {
8415 size_t ucdl_size, utrdl_size;
8416
8417 ucdl_size = sizeof(struct utp_transfer_cmd_desc) * nutrs;
8418 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr,
8419 hba->ucdl_dma_addr);
8420
8421 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
8422 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr,
8423 hba->utrdl_dma_addr);
8424
8425 devm_kfree(hba->dev, hba->lrb);
8426 }
8427
8428 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
8429 {
8430 int ret;
8431 int old_nutrs = hba->nutrs;
8432
8433 ret = ufshcd_mcq_decide_queue_depth(hba);
8434 if (ret < 0)
8435 return ret;
8436
8437 hba->nutrs = ret;
8438 ret = ufshcd_mcq_init(hba);
8439 if (ret)
8440 goto err;
8441
8442 /*
8443 * Previously allocated memory for nutrs may not be enough in MCQ mode.
8444 * Number of supported tags in MCQ mode may be larger than SDB mode.
8445 */
8446 if (hba->nutrs != old_nutrs) {
8447 ufshcd_release_sdb_queue(hba, old_nutrs);
8448 ret = ufshcd_memory_alloc(hba);
8449 if (ret)
8450 goto err;
8451 ufshcd_host_memory_configure(hba);
8452 }
8453
8454 ret = ufshcd_mcq_memory_alloc(hba);
8455 if (ret)
8456 goto err;
8457
8458 return 0;
8459 err:
8460 hba->nutrs = old_nutrs;
8461 return ret;
8462 }
8463
8464 static void ufshcd_config_mcq(struct ufs_hba *hba)
8465 {
8466 int ret;
8467
8468 ret = ufshcd_mcq_vops_config_esi(hba);
8469 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8470
8471 ufshcd_enable_intr(hba, UFSHCD_ENABLE_MCQ_INTRS);
8472 ufshcd_mcq_make_queues_operational(hba);
8473 ufshcd_mcq_config_mac(hba, hba->nutrs);
8474
8475 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
8476 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
8477
8478 /* Select MCQ mode */
8479 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
8480 REG_UFS_MEM_CFG);
8481 hba->mcq_enabled = true;
8482
8483 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
8484 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
8485 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
8486 hba->nutrs);
8487 }
8488
8489 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
8490 {
8491 int ret;
8492 struct Scsi_Host *host = hba->host;
8493
8494 hba->ufshcd_state = UFSHCD_STATE_RESET;
8495
8496 ret = ufshcd_link_startup(hba);
8497 if (ret)
8498 return ret;
8499
8500 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8501 return ret;
8502
8503 /* Debug counters initialization */
8504 ufshcd_clear_dbg_ufs_stats(hba);
8505
8506 /* UniPro link is active now */
8507 ufshcd_set_link_active(hba);
8508
8509 /* Reconfigure MCQ upon reset */
8510 if (is_mcq_enabled(hba) && !init_dev_params)
8511 ufshcd_config_mcq(hba);
8512
8513 /* Verify device initialization by sending NOP OUT UPIU */
8514 ret = ufshcd_verify_dev_init(hba);
8515 if (ret)
8516 return ret;
8517
8518 /* Initiate UFS initialization, and waiting until completion */
8519 ret = ufshcd_complete_dev_init(hba);
8520 if (ret)
8521 return ret;
8522
8523 /*
8524 * Initialize UFS device parameters used by driver, these
8525 * parameters are associated with UFS descriptors.
8526 */
8527 if (init_dev_params) {
8528 ret = ufshcd_device_params_init(hba);
8529 if (ret)
8530 return ret;
8531 if (is_mcq_supported(hba) && !hba->scsi_host_added) {
8532 ret = ufshcd_alloc_mcq(hba);
8533 if (ret) {
8534 /* Continue with SDB mode */
8535 use_mcq_mode = false;
8536 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
8537 ret);
8538 }
8539 ret = scsi_add_host(host, hba->dev);
8540 if (ret) {
8541 dev_err(hba->dev, "scsi_add_host failed\n");
8542 return ret;
8543 }
8544 hba->scsi_host_added = true;
8545 }
8546 /* MCQ may be disabled if ufshcd_alloc_mcq() fails */
8547 if (is_mcq_supported(hba) && use_mcq_mode)
8548 ufshcd_config_mcq(hba);
8549 }
8550
8551 ufshcd_tune_unipro_params(hba);
8552
8553 /* UFS device is also active now */
8554 ufshcd_set_ufs_dev_active(hba);
8555 ufshcd_force_reset_auto_bkops(hba);
8556
8557 /* Gear up to HS gear if supported */
8558 if (hba->max_pwr_info.is_valid) {
8559 /*
8560 * Set the right value to bRefClkFreq before attempting to
8561 * switch to HS gears.
8562 */
8563 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8564 ufshcd_set_dev_ref_clk(hba);
8565 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8566 if (ret) {
8567 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8568 __func__, ret);
8569 return ret;
8570 }
8571 }
8572
8573 return 0;
8574 }
8575
8576 /**
8577 * ufshcd_probe_hba - probe hba to detect device and initialize it
8578 * @hba: per-adapter instance
8579 * @init_dev_params: whether or not to call ufshcd_device_params_init().
8580 *
8581 * Execute link-startup and verify device initialization
8582 */
8583 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8584 {
8585 ktime_t start = ktime_get();
8586 unsigned long flags;
8587 int ret;
8588
8589 ret = ufshcd_device_init(hba, init_dev_params);
8590 if (ret)
8591 goto out;
8592
8593 if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) {
8594 /* Reset the device and controller before doing reinit */
8595 ufshcd_device_reset(hba);
8596 ufshcd_hba_stop(hba);
8597 ufshcd_vops_reinit_notify(hba);
8598 ret = ufshcd_hba_enable(hba);
8599 if (ret) {
8600 dev_err(hba->dev, "Host controller enable failed\n");
8601 ufshcd_print_evt_hist(hba);
8602 ufshcd_print_host_state(hba);
8603 goto out;
8604 }
8605
8606 /* Reinit the device */
8607 ret = ufshcd_device_init(hba, init_dev_params);
8608 if (ret)
8609 goto out;
8610 }
8611
8612 ufshcd_print_pwr_info(hba);
8613
8614 /*
8615 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8616 * and for removable UFS card as well, hence always set the parameter.
8617 * Note: Error handler may issue the device reset hence resetting
8618 * bActiveICCLevel as well so it is always safe to set this here.
8619 */
8620 ufshcd_set_active_icc_lvl(hba);
8621
8622 /* Enable UFS Write Booster if supported */
8623 ufshcd_configure_wb(hba);
8624
8625 if (hba->ee_usr_mask)
8626 ufshcd_write_ee_control(hba);
8627 /* Enable Auto-Hibernate if configured */
8628 ufshcd_auto_hibern8_enable(hba);
8629
8630 ufshpb_toggle_state(hba, HPB_RESET, HPB_PRESENT);
8631 out:
8632 spin_lock_irqsave(hba->host->host_lock, flags);
8633 if (ret)
8634 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8635 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8636 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8637 spin_unlock_irqrestore(hba->host->host_lock, flags);
8638
8639 trace_ufshcd_init(dev_name(hba->dev), ret,
8640 ktime_to_us(ktime_sub(ktime_get(), start)),
8641 hba->curr_dev_pwr_mode, hba->uic_link_state);
8642 return ret;
8643 }
8644
8645 /**
8646 * ufshcd_async_scan - asynchronous execution for probing hba
8647 * @data: data pointer to pass to this function
8648 * @cookie: cookie data
8649 */
8650 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8651 {
8652 struct ufs_hba *hba = (struct ufs_hba *)data;
8653 int ret;
8654
8655 down(&hba->host_sem);
8656 /* Initialize hba, detect and initialize UFS device */
8657 ret = ufshcd_probe_hba(hba, true);
8658 up(&hba->host_sem);
8659 if (ret)
8660 goto out;
8661
8662 /* Probe and add UFS logical units */
8663 ret = ufshcd_add_lus(hba);
8664 out:
8665 /*
8666 * If we failed to initialize the device or the device is not
8667 * present, turn off the power/clocks etc.
8668 */
8669 if (ret) {
8670 pm_runtime_put_sync(hba->dev);
8671 ufshcd_hba_exit(hba);
8672 }
8673 }
8674
8675 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
8676 {
8677 struct ufs_hba *hba = shost_priv(scmd->device->host);
8678
8679 if (!hba->system_suspending) {
8680 /* Activate the error handler in the SCSI core. */
8681 return SCSI_EH_NOT_HANDLED;
8682 }
8683
8684 /*
8685 * If we get here we know that no TMFs are outstanding and also that
8686 * the only pending command is a START STOP UNIT command. Handle the
8687 * timeout of that command directly to prevent a deadlock between
8688 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
8689 */
8690 ufshcd_link_recovery(hba);
8691 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
8692 __func__, hba->outstanding_tasks);
8693
8694 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
8695 }
8696
8697 static const struct attribute_group *ufshcd_driver_groups[] = {
8698 &ufs_sysfs_unit_descriptor_group,
8699 &ufs_sysfs_lun_attributes_group,
8700 #ifdef CONFIG_SCSI_UFS_HPB
8701 &ufs_sysfs_hpb_stat_group,
8702 &ufs_sysfs_hpb_param_group,
8703 #endif
8704 NULL,
8705 };
8706
8707 static struct ufs_hba_variant_params ufs_hba_vps = {
8708 .hba_enable_delay_us = 1000,
8709 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
8710 .devfreq_profile.polling_ms = 100,
8711 .devfreq_profile.target = ufshcd_devfreq_target,
8712 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8713 .ondemand_data.upthreshold = 70,
8714 .ondemand_data.downdifferential = 5,
8715 };
8716
8717 static struct scsi_host_template ufshcd_driver_template = {
8718 .module = THIS_MODULE,
8719 .name = UFSHCD,
8720 .proc_name = UFSHCD,
8721 .map_queues = ufshcd_map_queues,
8722 .queuecommand = ufshcd_queuecommand,
8723 .mq_poll = ufshcd_poll,
8724 .slave_alloc = ufshcd_slave_alloc,
8725 .slave_configure = ufshcd_slave_configure,
8726 .slave_destroy = ufshcd_slave_destroy,
8727 .change_queue_depth = ufshcd_change_queue_depth,
8728 .eh_abort_handler = ufshcd_abort,
8729 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8730 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
8731 .eh_timed_out = ufshcd_eh_timed_out,
8732 .this_id = -1,
8733 .sg_tablesize = SG_ALL,
8734 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8735 .can_queue = UFSHCD_CAN_QUEUE,
8736 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
8737 .max_sectors = (1 << 20) / SECTOR_SIZE, /* 1 MiB */
8738 .max_host_blocked = 1,
8739 .track_queue_depth = 1,
8740 .sdev_groups = ufshcd_driver_groups,
8741 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
8742 };
8743
8744 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8745 int ua)
8746 {
8747 int ret;
8748
8749 if (!vreg)
8750 return 0;
8751
8752 /*
8753 * "set_load" operation shall be required on those regulators
8754 * which specifically configured current limitation. Otherwise
8755 * zero max_uA may cause unexpected behavior when regulator is
8756 * enabled or set as high power mode.
8757 */
8758 if (!vreg->max_uA)
8759 return 0;
8760
8761 ret = regulator_set_load(vreg->reg, ua);
8762 if (ret < 0) {
8763 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8764 __func__, vreg->name, ua, ret);
8765 }
8766
8767 return ret;
8768 }
8769
8770 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8771 struct ufs_vreg *vreg)
8772 {
8773 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8774 }
8775
8776 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8777 struct ufs_vreg *vreg)
8778 {
8779 if (!vreg)
8780 return 0;
8781
8782 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8783 }
8784
8785 static int ufshcd_config_vreg(struct device *dev,
8786 struct ufs_vreg *vreg, bool on)
8787 {
8788 if (regulator_count_voltages(vreg->reg) <= 0)
8789 return 0;
8790
8791 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
8792 }
8793
8794 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8795 {
8796 int ret = 0;
8797
8798 if (!vreg || vreg->enabled)
8799 goto out;
8800
8801 ret = ufshcd_config_vreg(dev, vreg, true);
8802 if (!ret)
8803 ret = regulator_enable(vreg->reg);
8804
8805 if (!ret)
8806 vreg->enabled = true;
8807 else
8808 dev_err(dev, "%s: %s enable failed, err=%d\n",
8809 __func__, vreg->name, ret);
8810 out:
8811 return ret;
8812 }
8813
8814 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8815 {
8816 int ret = 0;
8817
8818 if (!vreg || !vreg->enabled || vreg->always_on)
8819 goto out;
8820
8821 ret = regulator_disable(vreg->reg);
8822
8823 if (!ret) {
8824 /* ignore errors on applying disable config */
8825 ufshcd_config_vreg(dev, vreg, false);
8826 vreg->enabled = false;
8827 } else {
8828 dev_err(dev, "%s: %s disable failed, err=%d\n",
8829 __func__, vreg->name, ret);
8830 }
8831 out:
8832 return ret;
8833 }
8834
8835 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8836 {
8837 int ret = 0;
8838 struct device *dev = hba->dev;
8839 struct ufs_vreg_info *info = &hba->vreg_info;
8840
8841 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8842 if (ret)
8843 goto out;
8844
8845 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8846 if (ret)
8847 goto out;
8848
8849 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8850
8851 out:
8852 if (ret) {
8853 ufshcd_toggle_vreg(dev, info->vccq2, false);
8854 ufshcd_toggle_vreg(dev, info->vccq, false);
8855 ufshcd_toggle_vreg(dev, info->vcc, false);
8856 }
8857 return ret;
8858 }
8859
8860 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8861 {
8862 struct ufs_vreg_info *info = &hba->vreg_info;
8863
8864 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8865 }
8866
8867 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8868 {
8869 int ret = 0;
8870
8871 if (!vreg)
8872 goto out;
8873
8874 vreg->reg = devm_regulator_get(dev, vreg->name);
8875 if (IS_ERR(vreg->reg)) {
8876 ret = PTR_ERR(vreg->reg);
8877 dev_err(dev, "%s: %s get failed, err=%d\n",
8878 __func__, vreg->name, ret);
8879 }
8880 out:
8881 return ret;
8882 }
8883 EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
8884
8885 static int ufshcd_init_vreg(struct ufs_hba *hba)
8886 {
8887 int ret = 0;
8888 struct device *dev = hba->dev;
8889 struct ufs_vreg_info *info = &hba->vreg_info;
8890
8891 ret = ufshcd_get_vreg(dev, info->vcc);
8892 if (ret)
8893 goto out;
8894
8895 ret = ufshcd_get_vreg(dev, info->vccq);
8896 if (!ret)
8897 ret = ufshcd_get_vreg(dev, info->vccq2);
8898 out:
8899 return ret;
8900 }
8901
8902 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8903 {
8904 struct ufs_vreg_info *info = &hba->vreg_info;
8905
8906 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8907 }
8908
8909 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8910 {
8911 int ret = 0;
8912 struct ufs_clk_info *clki;
8913 struct list_head *head = &hba->clk_list_head;
8914 unsigned long flags;
8915 ktime_t start = ktime_get();
8916 bool clk_state_changed = false;
8917
8918 if (list_empty(head))
8919 goto out;
8920
8921 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8922 if (ret)
8923 return ret;
8924
8925 list_for_each_entry(clki, head, list) {
8926 if (!IS_ERR_OR_NULL(clki->clk)) {
8927 /*
8928 * Don't disable clocks which are needed
8929 * to keep the link active.
8930 */
8931 if (ufshcd_is_link_active(hba) &&
8932 clki->keep_link_active)
8933 continue;
8934
8935 clk_state_changed = on ^ clki->enabled;
8936 if (on && !clki->enabled) {
8937 ret = clk_prepare_enable(clki->clk);
8938 if (ret) {
8939 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8940 __func__, clki->name, ret);
8941 goto out;
8942 }
8943 } else if (!on && clki->enabled) {
8944 clk_disable_unprepare(clki->clk);
8945 }
8946 clki->enabled = on;
8947 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8948 clki->name, on ? "en" : "dis");
8949 }
8950 }
8951
8952 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8953 if (ret)
8954 return ret;
8955
8956 out:
8957 if (ret) {
8958 list_for_each_entry(clki, head, list) {
8959 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8960 clk_disable_unprepare(clki->clk);
8961 }
8962 } else if (!ret && on) {
8963 spin_lock_irqsave(hba->host->host_lock, flags);
8964 hba->clk_gating.state = CLKS_ON;
8965 trace_ufshcd_clk_gating(dev_name(hba->dev),
8966 hba->clk_gating.state);
8967 spin_unlock_irqrestore(hba->host->host_lock, flags);
8968 }
8969
8970 if (clk_state_changed)
8971 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8972 (on ? "on" : "off"),
8973 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8974 return ret;
8975 }
8976
8977 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
8978 {
8979 u32 freq;
8980 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
8981
8982 if (ret) {
8983 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
8984 return REF_CLK_FREQ_INVAL;
8985 }
8986
8987 return ufs_get_bref_clk_from_hz(freq);
8988 }
8989
8990 static int ufshcd_init_clocks(struct ufs_hba *hba)
8991 {
8992 int ret = 0;
8993 struct ufs_clk_info *clki;
8994 struct device *dev = hba->dev;
8995 struct list_head *head = &hba->clk_list_head;
8996
8997 if (list_empty(head))
8998 goto out;
8999
9000 list_for_each_entry(clki, head, list) {
9001 if (!clki->name)
9002 continue;
9003
9004 clki->clk = devm_clk_get(dev, clki->name);
9005 if (IS_ERR(clki->clk)) {
9006 ret = PTR_ERR(clki->clk);
9007 dev_err(dev, "%s: %s clk get failed, %d\n",
9008 __func__, clki->name, ret);
9009 goto out;
9010 }
9011
9012 /*
9013 * Parse device ref clk freq as per device tree "ref_clk".
9014 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9015 * in ufshcd_alloc_host().
9016 */
9017 if (!strcmp(clki->name, "ref_clk"))
9018 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
9019
9020 if (clki->max_freq) {
9021 ret = clk_set_rate(clki->clk, clki->max_freq);
9022 if (ret) {
9023 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9024 __func__, clki->name,
9025 clki->max_freq, ret);
9026 goto out;
9027 }
9028 clki->curr_freq = clki->max_freq;
9029 }
9030 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9031 clki->name, clk_get_rate(clki->clk));
9032 }
9033 out:
9034 return ret;
9035 }
9036
9037 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9038 {
9039 int err = 0;
9040
9041 if (!hba->vops)
9042 goto out;
9043
9044 err = ufshcd_vops_init(hba);
9045 if (err)
9046 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
9047 __func__, ufshcd_get_var_name(hba), err);
9048 out:
9049 return err;
9050 }
9051
9052 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9053 {
9054 if (!hba->vops)
9055 return;
9056
9057 ufshcd_vops_exit(hba);
9058 }
9059
9060 static int ufshcd_hba_init(struct ufs_hba *hba)
9061 {
9062 int err;
9063
9064 /*
9065 * Handle host controller power separately from the UFS device power
9066 * rails as it will help controlling the UFS host controller power
9067 * collapse easily which is different than UFS device power collapse.
9068 * Also, enable the host controller power before we go ahead with rest
9069 * of the initialization here.
9070 */
9071 err = ufshcd_init_hba_vreg(hba);
9072 if (err)
9073 goto out;
9074
9075 err = ufshcd_setup_hba_vreg(hba, true);
9076 if (err)
9077 goto out;
9078
9079 err = ufshcd_init_clocks(hba);
9080 if (err)
9081 goto out_disable_hba_vreg;
9082
9083 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9084 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9085
9086 err = ufshcd_setup_clocks(hba, true);
9087 if (err)
9088 goto out_disable_hba_vreg;
9089
9090 err = ufshcd_init_vreg(hba);
9091 if (err)
9092 goto out_disable_clks;
9093
9094 err = ufshcd_setup_vreg(hba, true);
9095 if (err)
9096 goto out_disable_clks;
9097
9098 err = ufshcd_variant_hba_init(hba);
9099 if (err)
9100 goto out_disable_vreg;
9101
9102 ufs_debugfs_hba_init(hba);
9103
9104 hba->is_powered = true;
9105 goto out;
9106
9107 out_disable_vreg:
9108 ufshcd_setup_vreg(hba, false);
9109 out_disable_clks:
9110 ufshcd_setup_clocks(hba, false);
9111 out_disable_hba_vreg:
9112 ufshcd_setup_hba_vreg(hba, false);
9113 out:
9114 return err;
9115 }
9116
9117 static void ufshcd_hba_exit(struct ufs_hba *hba)
9118 {
9119 if (hba->is_powered) {
9120 ufshcd_exit_clk_scaling(hba);
9121 ufshcd_exit_clk_gating(hba);
9122 if (hba->eh_wq)
9123 destroy_workqueue(hba->eh_wq);
9124 ufs_debugfs_hba_exit(hba);
9125 ufshcd_variant_hba_exit(hba);
9126 ufshcd_setup_vreg(hba, false);
9127 ufshcd_setup_clocks(hba, false);
9128 ufshcd_setup_hba_vreg(hba, false);
9129 hba->is_powered = false;
9130 ufs_put_device_desc(hba);
9131 }
9132 }
9133
9134 static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9135 enum ufs_dev_pwr_mode pwr_mode,
9136 struct scsi_sense_hdr *sshdr)
9137 {
9138 unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9139 struct request *req;
9140 struct scsi_cmnd *scmd;
9141 int ret;
9142
9143 req = scsi_alloc_request(sdev->request_queue, REQ_OP_DRV_IN,
9144 BLK_MQ_REQ_PM);
9145 if (IS_ERR(req))
9146 return PTR_ERR(req);
9147
9148 scmd = blk_mq_rq_to_pdu(req);
9149 scmd->cmd_len = COMMAND_SIZE(cdb[0]);
9150 memcpy(scmd->cmnd, cdb, scmd->cmd_len);
9151 scmd->allowed = 0/*retries*/;
9152 scmd->flags |= SCMD_FAIL_IF_RECOVERING;
9153 req->timeout = 1 * HZ;
9154 req->rq_flags |= RQF_PM | RQF_QUIET;
9155
9156 blk_execute_rq(req, /*at_head=*/true);
9157
9158 if (sshdr)
9159 scsi_normalize_sense(scmd->sense_buffer, scmd->sense_len,
9160 sshdr);
9161 ret = scmd->result;
9162
9163 blk_mq_free_request(req);
9164
9165 return ret;
9166 }
9167
9168 /**
9169 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9170 * power mode
9171 * @hba: per adapter instance
9172 * @pwr_mode: device power mode to set
9173 *
9174 * Returns 0 if requested power mode is set successfully
9175 * Returns < 0 if failed to set the requested power mode
9176 */
9177 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9178 enum ufs_dev_pwr_mode pwr_mode)
9179 {
9180 struct scsi_sense_hdr sshdr;
9181 struct scsi_device *sdp;
9182 unsigned long flags;
9183 int ret, retries;
9184
9185 spin_lock_irqsave(hba->host->host_lock, flags);
9186 sdp = hba->ufs_device_wlun;
9187 if (sdp && scsi_device_online(sdp))
9188 ret = scsi_device_get(sdp);
9189 else
9190 ret = -ENODEV;
9191 spin_unlock_irqrestore(hba->host->host_lock, flags);
9192
9193 if (ret)
9194 return ret;
9195
9196 /*
9197 * If scsi commands fail, the scsi mid-layer schedules scsi error-
9198 * handling, which would wait for host to be resumed. Since we know
9199 * we are functional while we are here, skip host resume in error
9200 * handling context.
9201 */
9202 hba->host->eh_noresume = 1;
9203
9204 /*
9205 * Current function would be generally called from the power management
9206 * callbacks hence set the RQF_PM flag so that it doesn't resume the
9207 * already suspended childs.
9208 */
9209 for (retries = 3; retries > 0; --retries) {
9210 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
9211 /*
9212 * scsi_execute() only returns a negative value if the request
9213 * queue is dying.
9214 */
9215 if (ret <= 0)
9216 break;
9217 }
9218 if (ret) {
9219 sdev_printk(KERN_WARNING, sdp,
9220 "START_STOP failed for power mode: %d, result %x\n",
9221 pwr_mode, ret);
9222 if (ret > 0) {
9223 if (scsi_sense_valid(&sshdr))
9224 scsi_print_sense_hdr(sdp, NULL, &sshdr);
9225 ret = -EIO;
9226 }
9227 } else {
9228 hba->curr_dev_pwr_mode = pwr_mode;
9229 }
9230
9231 scsi_device_put(sdp);
9232 hba->host->eh_noresume = 0;
9233 return ret;
9234 }
9235
9236 static int ufshcd_link_state_transition(struct ufs_hba *hba,
9237 enum uic_link_state req_link_state,
9238 bool check_for_bkops)
9239 {
9240 int ret = 0;
9241
9242 if (req_link_state == hba->uic_link_state)
9243 return 0;
9244
9245 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9246 ret = ufshcd_uic_hibern8_enter(hba);
9247 if (!ret) {
9248 ufshcd_set_link_hibern8(hba);
9249 } else {
9250 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9251 __func__, ret);
9252 goto out;
9253 }
9254 }
9255 /*
9256 * If autobkops is enabled, link can't be turned off because
9257 * turning off the link would also turn off the device, except in the
9258 * case of DeepSleep where the device is expected to remain powered.
9259 */
9260 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9261 (!check_for_bkops || !hba->auto_bkops_enabled)) {
9262 /*
9263 * Let's make sure that link is in low power mode, we are doing
9264 * this currently by putting the link in Hibern8. Otherway to
9265 * put the link in low power mode is to send the DME end point
9266 * to device and then send the DME reset command to local
9267 * unipro. But putting the link in hibern8 is much faster.
9268 *
9269 * Note also that putting the link in Hibern8 is a requirement
9270 * for entering DeepSleep.
9271 */
9272 ret = ufshcd_uic_hibern8_enter(hba);
9273 if (ret) {
9274 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9275 __func__, ret);
9276 goto out;
9277 }
9278 /*
9279 * Change controller state to "reset state" which
9280 * should also put the link in off/reset state
9281 */
9282 ufshcd_hba_stop(hba);
9283 /*
9284 * TODO: Check if we need any delay to make sure that
9285 * controller is reset
9286 */
9287 ufshcd_set_link_off(hba);
9288 }
9289
9290 out:
9291 return ret;
9292 }
9293
9294 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9295 {
9296 bool vcc_off = false;
9297
9298 /*
9299 * It seems some UFS devices may keep drawing more than sleep current
9300 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9301 * To avoid this situation, add 2ms delay before putting these UFS
9302 * rails in LPM mode.
9303 */
9304 if (!ufshcd_is_link_active(hba) &&
9305 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9306 usleep_range(2000, 2100);
9307
9308 /*
9309 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9310 * power.
9311 *
9312 * If UFS device and link is in OFF state, all power supplies (VCC,
9313 * VCCQ, VCCQ2) can be turned off if power on write protect is not
9314 * required. If UFS link is inactive (Hibern8 or OFF state) and device
9315 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9316 *
9317 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9318 * in low power state which would save some power.
9319 *
9320 * If Write Booster is enabled and the device needs to flush the WB
9321 * buffer OR if bkops status is urgent for WB, keep Vcc on.
9322 */
9323 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9324 !hba->dev_info.is_lu_power_on_wp) {
9325 ufshcd_setup_vreg(hba, false);
9326 vcc_off = true;
9327 } else if (!ufshcd_is_ufs_dev_active(hba)) {
9328 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9329 vcc_off = true;
9330 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9331 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9332 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9333 }
9334 }
9335
9336 /*
9337 * Some UFS devices require delay after VCC power rail is turned-off.
9338 */
9339 if (vcc_off && hba->vreg_info.vcc &&
9340 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9341 usleep_range(5000, 5100);
9342 }
9343
9344 #ifdef CONFIG_PM
9345 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9346 {
9347 int ret = 0;
9348
9349 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9350 !hba->dev_info.is_lu_power_on_wp) {
9351 ret = ufshcd_setup_vreg(hba, true);
9352 } else if (!ufshcd_is_ufs_dev_active(hba)) {
9353 if (!ufshcd_is_link_active(hba)) {
9354 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9355 if (ret)
9356 goto vcc_disable;
9357 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9358 if (ret)
9359 goto vccq_lpm;
9360 }
9361 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9362 }
9363 goto out;
9364
9365 vccq_lpm:
9366 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9367 vcc_disable:
9368 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9369 out:
9370 return ret;
9371 }
9372 #endif /* CONFIG_PM */
9373
9374 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9375 {
9376 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9377 ufshcd_setup_hba_vreg(hba, false);
9378 }
9379
9380 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9381 {
9382 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9383 ufshcd_setup_hba_vreg(hba, true);
9384 }
9385
9386 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9387 {
9388 int ret = 0;
9389 bool check_for_bkops;
9390 enum ufs_pm_level pm_lvl;
9391 enum ufs_dev_pwr_mode req_dev_pwr_mode;
9392 enum uic_link_state req_link_state;
9393
9394 hba->pm_op_in_progress = true;
9395 if (pm_op != UFS_SHUTDOWN_PM) {
9396 pm_lvl = pm_op == UFS_RUNTIME_PM ?
9397 hba->rpm_lvl : hba->spm_lvl;
9398 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9399 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9400 } else {
9401 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9402 req_link_state = UIC_LINK_OFF_STATE;
9403 }
9404
9405 ufshpb_suspend(hba);
9406
9407 /*
9408 * If we can't transition into any of the low power modes
9409 * just gate the clocks.
9410 */
9411 ufshcd_hold(hba, false);
9412 hba->clk_gating.is_suspended = true;
9413
9414 if (ufshcd_is_clkscaling_supported(hba))
9415 ufshcd_clk_scaling_suspend(hba, true);
9416
9417 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9418 req_link_state == UIC_LINK_ACTIVE_STATE) {
9419 goto vops_suspend;
9420 }
9421
9422 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9423 (req_link_state == hba->uic_link_state))
9424 goto enable_scaling;
9425
9426 /* UFS device & link must be active before we enter in this function */
9427 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9428 ret = -EINVAL;
9429 goto enable_scaling;
9430 }
9431
9432 if (pm_op == UFS_RUNTIME_PM) {
9433 if (ufshcd_can_autobkops_during_suspend(hba)) {
9434 /*
9435 * The device is idle with no requests in the queue,
9436 * allow background operations if bkops status shows
9437 * that performance might be impacted.
9438 */
9439 ret = ufshcd_urgent_bkops(hba);
9440 if (ret)
9441 goto enable_scaling;
9442 } else {
9443 /* make sure that auto bkops is disabled */
9444 ufshcd_disable_auto_bkops(hba);
9445 }
9446 /*
9447 * If device needs to do BKOP or WB buffer flush during
9448 * Hibern8, keep device power mode as "active power mode"
9449 * and VCC supply.
9450 */
9451 hba->dev_info.b_rpm_dev_flush_capable =
9452 hba->auto_bkops_enabled ||
9453 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9454 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9455 ufshcd_is_auto_hibern8_enabled(hba))) &&
9456 ufshcd_wb_need_flush(hba));
9457 }
9458
9459 flush_work(&hba->eeh_work);
9460
9461 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9462 if (ret)
9463 goto enable_scaling;
9464
9465 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9466 if (pm_op != UFS_RUNTIME_PM)
9467 /* ensure that bkops is disabled */
9468 ufshcd_disable_auto_bkops(hba);
9469
9470 if (!hba->dev_info.b_rpm_dev_flush_capable) {
9471 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9472 if (ret)
9473 goto enable_scaling;
9474 }
9475 }
9476
9477 /*
9478 * In the case of DeepSleep, the device is expected to remain powered
9479 * with the link off, so do not check for bkops.
9480 */
9481 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9482 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9483 if (ret)
9484 goto set_dev_active;
9485
9486 vops_suspend:
9487 /*
9488 * Call vendor specific suspend callback. As these callbacks may access
9489 * vendor specific host controller register space call them before the
9490 * host clocks are ON.
9491 */
9492 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9493 if (ret)
9494 goto set_link_active;
9495 goto out;
9496
9497 set_link_active:
9498 /*
9499 * Device hardware reset is required to exit DeepSleep. Also, for
9500 * DeepSleep, the link is off so host reset and restore will be done
9501 * further below.
9502 */
9503 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9504 ufshcd_device_reset(hba);
9505 WARN_ON(!ufshcd_is_link_off(hba));
9506 }
9507 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9508 ufshcd_set_link_active(hba);
9509 else if (ufshcd_is_link_off(hba))
9510 ufshcd_host_reset_and_restore(hba);
9511 set_dev_active:
9512 /* Can also get here needing to exit DeepSleep */
9513 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9514 ufshcd_device_reset(hba);
9515 ufshcd_host_reset_and_restore(hba);
9516 }
9517 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9518 ufshcd_disable_auto_bkops(hba);
9519 enable_scaling:
9520 if (ufshcd_is_clkscaling_supported(hba))
9521 ufshcd_clk_scaling_suspend(hba, false);
9522
9523 hba->dev_info.b_rpm_dev_flush_capable = false;
9524 out:
9525 if (hba->dev_info.b_rpm_dev_flush_capable) {
9526 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9527 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9528 }
9529
9530 if (ret) {
9531 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9532 hba->clk_gating.is_suspended = false;
9533 ufshcd_release(hba);
9534 ufshpb_resume(hba);
9535 }
9536 hba->pm_op_in_progress = false;
9537 return ret;
9538 }
9539
9540 #ifdef CONFIG_PM
9541 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9542 {
9543 int ret;
9544 enum uic_link_state old_link_state = hba->uic_link_state;
9545
9546 hba->pm_op_in_progress = true;
9547
9548 /*
9549 * Call vendor specific resume callback. As these callbacks may access
9550 * vendor specific host controller register space call them when the
9551 * host clocks are ON.
9552 */
9553 ret = ufshcd_vops_resume(hba, pm_op);
9554 if (ret)
9555 goto out;
9556
9557 /* For DeepSleep, the only supported option is to have the link off */
9558 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9559
9560 if (ufshcd_is_link_hibern8(hba)) {
9561 ret = ufshcd_uic_hibern8_exit(hba);
9562 if (!ret) {
9563 ufshcd_set_link_active(hba);
9564 } else {
9565 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9566 __func__, ret);
9567 goto vendor_suspend;
9568 }
9569 } else if (ufshcd_is_link_off(hba)) {
9570 /*
9571 * A full initialization of the host and the device is
9572 * required since the link was put to off during suspend.
9573 * Note, in the case of DeepSleep, the device will exit
9574 * DeepSleep due to device reset.
9575 */
9576 ret = ufshcd_reset_and_restore(hba);
9577 /*
9578 * ufshcd_reset_and_restore() should have already
9579 * set the link state as active
9580 */
9581 if (ret || !ufshcd_is_link_active(hba))
9582 goto vendor_suspend;
9583 }
9584
9585 if (!ufshcd_is_ufs_dev_active(hba)) {
9586 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9587 if (ret)
9588 goto set_old_link_state;
9589 }
9590
9591 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9592 ufshcd_enable_auto_bkops(hba);
9593 else
9594 /*
9595 * If BKOPs operations are urgently needed at this moment then
9596 * keep auto-bkops enabled or else disable it.
9597 */
9598 ufshcd_urgent_bkops(hba);
9599
9600 if (hba->ee_usr_mask)
9601 ufshcd_write_ee_control(hba);
9602
9603 if (ufshcd_is_clkscaling_supported(hba))
9604 ufshcd_clk_scaling_suspend(hba, false);
9605
9606 if (hba->dev_info.b_rpm_dev_flush_capable) {
9607 hba->dev_info.b_rpm_dev_flush_capable = false;
9608 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9609 }
9610
9611 /* Enable Auto-Hibernate if configured */
9612 ufshcd_auto_hibern8_enable(hba);
9613
9614 ufshpb_resume(hba);
9615 goto out;
9616
9617 set_old_link_state:
9618 ufshcd_link_state_transition(hba, old_link_state, 0);
9619 vendor_suspend:
9620 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9621 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9622 out:
9623 if (ret)
9624 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9625 hba->clk_gating.is_suspended = false;
9626 ufshcd_release(hba);
9627 hba->pm_op_in_progress = false;
9628 return ret;
9629 }
9630
9631 static int ufshcd_wl_runtime_suspend(struct device *dev)
9632 {
9633 struct scsi_device *sdev = to_scsi_device(dev);
9634 struct ufs_hba *hba;
9635 int ret;
9636 ktime_t start = ktime_get();
9637
9638 hba = shost_priv(sdev->host);
9639
9640 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9641 if (ret)
9642 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9643
9644 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9645 ktime_to_us(ktime_sub(ktime_get(), start)),
9646 hba->curr_dev_pwr_mode, hba->uic_link_state);
9647
9648 return ret;
9649 }
9650
9651 static int ufshcd_wl_runtime_resume(struct device *dev)
9652 {
9653 struct scsi_device *sdev = to_scsi_device(dev);
9654 struct ufs_hba *hba;
9655 int ret = 0;
9656 ktime_t start = ktime_get();
9657
9658 hba = shost_priv(sdev->host);
9659
9660 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9661 if (ret)
9662 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9663
9664 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9665 ktime_to_us(ktime_sub(ktime_get(), start)),
9666 hba->curr_dev_pwr_mode, hba->uic_link_state);
9667
9668 return ret;
9669 }
9670 #endif
9671
9672 #ifdef CONFIG_PM_SLEEP
9673 static int ufshcd_wl_suspend(struct device *dev)
9674 {
9675 struct scsi_device *sdev = to_scsi_device(dev);
9676 struct ufs_hba *hba;
9677 int ret = 0;
9678 ktime_t start = ktime_get();
9679
9680 hba = shost_priv(sdev->host);
9681 down(&hba->host_sem);
9682 hba->system_suspending = true;
9683
9684 if (pm_runtime_suspended(dev))
9685 goto out;
9686
9687 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9688 if (ret) {
9689 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9690 up(&hba->host_sem);
9691 }
9692
9693 out:
9694 if (!ret)
9695 hba->is_sys_suspended = true;
9696 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9697 ktime_to_us(ktime_sub(ktime_get(), start)),
9698 hba->curr_dev_pwr_mode, hba->uic_link_state);
9699
9700 return ret;
9701 }
9702
9703 static int ufshcd_wl_resume(struct device *dev)
9704 {
9705 struct scsi_device *sdev = to_scsi_device(dev);
9706 struct ufs_hba *hba;
9707 int ret = 0;
9708 ktime_t start = ktime_get();
9709
9710 hba = shost_priv(sdev->host);
9711
9712 if (pm_runtime_suspended(dev))
9713 goto out;
9714
9715 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9716 if (ret)
9717 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9718 out:
9719 trace_ufshcd_wl_resume(dev_name(dev), ret,
9720 ktime_to_us(ktime_sub(ktime_get(), start)),
9721 hba->curr_dev_pwr_mode, hba->uic_link_state);
9722 if (!ret)
9723 hba->is_sys_suspended = false;
9724 hba->system_suspending = false;
9725 up(&hba->host_sem);
9726 return ret;
9727 }
9728 #endif
9729
9730 static void ufshcd_wl_shutdown(struct device *dev)
9731 {
9732 struct scsi_device *sdev = to_scsi_device(dev);
9733 struct ufs_hba *hba;
9734
9735 hba = shost_priv(sdev->host);
9736
9737 down(&hba->host_sem);
9738 hba->shutting_down = true;
9739 up(&hba->host_sem);
9740
9741 /* Turn on everything while shutting down */
9742 ufshcd_rpm_get_sync(hba);
9743 scsi_device_quiesce(sdev);
9744 shost_for_each_device(sdev, hba->host) {
9745 if (sdev == hba->ufs_device_wlun)
9746 continue;
9747 scsi_device_quiesce(sdev);
9748 }
9749 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9750 }
9751
9752 /**
9753 * ufshcd_suspend - helper function for suspend operations
9754 * @hba: per adapter instance
9755 *
9756 * This function will put disable irqs, turn off clocks
9757 * and set vreg and hba-vreg in lpm mode.
9758 */
9759 static int ufshcd_suspend(struct ufs_hba *hba)
9760 {
9761 int ret;
9762
9763 if (!hba->is_powered)
9764 return 0;
9765 /*
9766 * Disable the host irq as host controller as there won't be any
9767 * host controller transaction expected till resume.
9768 */
9769 ufshcd_disable_irq(hba);
9770 ret = ufshcd_setup_clocks(hba, false);
9771 if (ret) {
9772 ufshcd_enable_irq(hba);
9773 return ret;
9774 }
9775 if (ufshcd_is_clkgating_allowed(hba)) {
9776 hba->clk_gating.state = CLKS_OFF;
9777 trace_ufshcd_clk_gating(dev_name(hba->dev),
9778 hba->clk_gating.state);
9779 }
9780
9781 ufshcd_vreg_set_lpm(hba);
9782 /* Put the host controller in low power mode if possible */
9783 ufshcd_hba_vreg_set_lpm(hba);
9784 return ret;
9785 }
9786
9787 #ifdef CONFIG_PM
9788 /**
9789 * ufshcd_resume - helper function for resume operations
9790 * @hba: per adapter instance
9791 *
9792 * This function basically turns on the regulators, clocks and
9793 * irqs of the hba.
9794 *
9795 * Returns 0 for success and non-zero for failure
9796 */
9797 static int ufshcd_resume(struct ufs_hba *hba)
9798 {
9799 int ret;
9800
9801 if (!hba->is_powered)
9802 return 0;
9803
9804 ufshcd_hba_vreg_set_hpm(hba);
9805 ret = ufshcd_vreg_set_hpm(hba);
9806 if (ret)
9807 goto out;
9808
9809 /* Make sure clocks are enabled before accessing controller */
9810 ret = ufshcd_setup_clocks(hba, true);
9811 if (ret)
9812 goto disable_vreg;
9813
9814 /* enable the host irq as host controller would be active soon */
9815 ufshcd_enable_irq(hba);
9816
9817 goto out;
9818
9819 disable_vreg:
9820 ufshcd_vreg_set_lpm(hba);
9821 out:
9822 if (ret)
9823 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9824 return ret;
9825 }
9826 #endif /* CONFIG_PM */
9827
9828 #ifdef CONFIG_PM_SLEEP
9829 /**
9830 * ufshcd_system_suspend - system suspend callback
9831 * @dev: Device associated with the UFS controller.
9832 *
9833 * Executed before putting the system into a sleep state in which the contents
9834 * of main memory are preserved.
9835 *
9836 * Returns 0 for success and non-zero for failure
9837 */
9838 int ufshcd_system_suspend(struct device *dev)
9839 {
9840 struct ufs_hba *hba = dev_get_drvdata(dev);
9841 int ret = 0;
9842 ktime_t start = ktime_get();
9843
9844 if (pm_runtime_suspended(hba->dev))
9845 goto out;
9846
9847 ret = ufshcd_suspend(hba);
9848 out:
9849 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9850 ktime_to_us(ktime_sub(ktime_get(), start)),
9851 hba->curr_dev_pwr_mode, hba->uic_link_state);
9852 return ret;
9853 }
9854 EXPORT_SYMBOL(ufshcd_system_suspend);
9855
9856 /**
9857 * ufshcd_system_resume - system resume callback
9858 * @dev: Device associated with the UFS controller.
9859 *
9860 * Executed after waking the system up from a sleep state in which the contents
9861 * of main memory were preserved.
9862 *
9863 * Returns 0 for success and non-zero for failure
9864 */
9865 int ufshcd_system_resume(struct device *dev)
9866 {
9867 struct ufs_hba *hba = dev_get_drvdata(dev);
9868 ktime_t start = ktime_get();
9869 int ret = 0;
9870
9871 if (pm_runtime_suspended(hba->dev))
9872 goto out;
9873
9874 ret = ufshcd_resume(hba);
9875
9876 out:
9877 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9878 ktime_to_us(ktime_sub(ktime_get(), start)),
9879 hba->curr_dev_pwr_mode, hba->uic_link_state);
9880
9881 return ret;
9882 }
9883 EXPORT_SYMBOL(ufshcd_system_resume);
9884 #endif /* CONFIG_PM_SLEEP */
9885
9886 #ifdef CONFIG_PM
9887 /**
9888 * ufshcd_runtime_suspend - runtime suspend callback
9889 * @dev: Device associated with the UFS controller.
9890 *
9891 * Check the description of ufshcd_suspend() function for more details.
9892 *
9893 * Returns 0 for success and non-zero for failure
9894 */
9895 int ufshcd_runtime_suspend(struct device *dev)
9896 {
9897 struct ufs_hba *hba = dev_get_drvdata(dev);
9898 int ret;
9899 ktime_t start = ktime_get();
9900
9901 ret = ufshcd_suspend(hba);
9902
9903 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9904 ktime_to_us(ktime_sub(ktime_get(), start)),
9905 hba->curr_dev_pwr_mode, hba->uic_link_state);
9906 return ret;
9907 }
9908 EXPORT_SYMBOL(ufshcd_runtime_suspend);
9909
9910 /**
9911 * ufshcd_runtime_resume - runtime resume routine
9912 * @dev: Device associated with the UFS controller.
9913 *
9914 * This function basically brings controller
9915 * to active state. Following operations are done in this function:
9916 *
9917 * 1. Turn on all the controller related clocks
9918 * 2. Turn ON VCC rail
9919 */
9920 int ufshcd_runtime_resume(struct device *dev)
9921 {
9922 struct ufs_hba *hba = dev_get_drvdata(dev);
9923 int ret;
9924 ktime_t start = ktime_get();
9925
9926 ret = ufshcd_resume(hba);
9927
9928 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9929 ktime_to_us(ktime_sub(ktime_get(), start)),
9930 hba->curr_dev_pwr_mode, hba->uic_link_state);
9931 return ret;
9932 }
9933 EXPORT_SYMBOL(ufshcd_runtime_resume);
9934 #endif /* CONFIG_PM */
9935
9936 /**
9937 * ufshcd_shutdown - shutdown routine
9938 * @hba: per adapter instance
9939 *
9940 * This function would turn off both UFS device and UFS hba
9941 * regulators. It would also disable clocks.
9942 *
9943 * Returns 0 always to allow force shutdown even in case of errors.
9944 */
9945 int ufshcd_shutdown(struct ufs_hba *hba)
9946 {
9947 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9948 ufshcd_suspend(hba);
9949
9950 hba->is_powered = false;
9951 /* allow force shutdown even in case of errors */
9952 return 0;
9953 }
9954 EXPORT_SYMBOL(ufshcd_shutdown);
9955
9956 /**
9957 * ufshcd_remove - de-allocate SCSI host and host memory space
9958 * data structure memory
9959 * @hba: per adapter instance
9960 */
9961 void ufshcd_remove(struct ufs_hba *hba)
9962 {
9963 if (hba->ufs_device_wlun)
9964 ufshcd_rpm_get_sync(hba);
9965 ufs_hwmon_remove(hba);
9966 ufs_bsg_remove(hba);
9967 ufshpb_remove(hba);
9968 ufs_sysfs_remove_nodes(hba->dev);
9969 blk_mq_destroy_queue(hba->tmf_queue);
9970 blk_put_queue(hba->tmf_queue);
9971 blk_mq_free_tag_set(&hba->tmf_tag_set);
9972 scsi_remove_host(hba->host);
9973 /* disable interrupts */
9974 ufshcd_disable_intr(hba, hba->intr_mask);
9975 ufshcd_hba_stop(hba);
9976 ufshcd_hba_exit(hba);
9977 }
9978 EXPORT_SYMBOL_GPL(ufshcd_remove);
9979
9980 #ifdef CONFIG_PM_SLEEP
9981 int ufshcd_system_freeze(struct device *dev)
9982 {
9983
9984 return ufshcd_system_suspend(dev);
9985
9986 }
9987 EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
9988
9989 int ufshcd_system_restore(struct device *dev)
9990 {
9991
9992 struct ufs_hba *hba = dev_get_drvdata(dev);
9993 int ret;
9994
9995 ret = ufshcd_system_resume(dev);
9996 if (ret)
9997 return ret;
9998
9999 /* Configure UTRL and UTMRL base address registers */
10000 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10001 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10002 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10003 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10004 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10005 REG_UTP_TASK_REQ_LIST_BASE_L);
10006 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10007 REG_UTP_TASK_REQ_LIST_BASE_H);
10008 /*
10009 * Make sure that UTRL and UTMRL base address registers
10010 * are updated with the latest queue addresses. Only after
10011 * updating these addresses, we can queue the new commands.
10012 */
10013 mb();
10014
10015 /* Resuming from hibernate, assume that link was OFF */
10016 ufshcd_set_link_off(hba);
10017
10018 return 0;
10019
10020 }
10021 EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10022
10023 int ufshcd_system_thaw(struct device *dev)
10024 {
10025 return ufshcd_system_resume(dev);
10026 }
10027 EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10028 #endif /* CONFIG_PM_SLEEP */
10029
10030 /**
10031 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
10032 * @hba: pointer to Host Bus Adapter (HBA)
10033 */
10034 void ufshcd_dealloc_host(struct ufs_hba *hba)
10035 {
10036 scsi_host_put(hba->host);
10037 }
10038 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
10039
10040 /**
10041 * ufshcd_set_dma_mask - Set dma mask based on the controller
10042 * addressing capability
10043 * @hba: per adapter instance
10044 *
10045 * Returns 0 for success, non-zero for failure
10046 */
10047 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10048 {
10049 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10050 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
10051 return 0;
10052 }
10053 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
10054 }
10055
10056 /**
10057 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10058 * @dev: pointer to device handle
10059 * @hba_handle: driver private handle
10060 * Returns 0 on success, non-zero value on failure
10061 */
10062 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10063 {
10064 struct Scsi_Host *host;
10065 struct ufs_hba *hba;
10066 int err = 0;
10067
10068 if (!dev) {
10069 dev_err(dev,
10070 "Invalid memory reference for dev is NULL\n");
10071 err = -ENODEV;
10072 goto out_error;
10073 }
10074
10075 host = scsi_host_alloc(&ufshcd_driver_template,
10076 sizeof(struct ufs_hba));
10077 if (!host) {
10078 dev_err(dev, "scsi_host_alloc failed\n");
10079 err = -ENOMEM;
10080 goto out_error;
10081 }
10082 host->nr_maps = HCTX_TYPE_POLL + 1;
10083 hba = shost_priv(host);
10084 hba->host = host;
10085 hba->dev = dev;
10086 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10087 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10088 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
10089 INIT_LIST_HEAD(&hba->clk_list_head);
10090 spin_lock_init(&hba->outstanding_lock);
10091
10092 *hba_handle = hba;
10093
10094 out_error:
10095 return err;
10096 }
10097 EXPORT_SYMBOL(ufshcd_alloc_host);
10098
10099 /* This function exists because blk_mq_alloc_tag_set() requires this. */
10100 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10101 const struct blk_mq_queue_data *qd)
10102 {
10103 WARN_ON_ONCE(true);
10104 return BLK_STS_NOTSUPP;
10105 }
10106
10107 static const struct blk_mq_ops ufshcd_tmf_ops = {
10108 .queue_rq = ufshcd_queue_tmf,
10109 };
10110
10111 /**
10112 * ufshcd_init - Driver initialization routine
10113 * @hba: per-adapter instance
10114 * @mmio_base: base register address
10115 * @irq: Interrupt line of device
10116 * Returns 0 on success, non-zero value on failure
10117 */
10118 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10119 {
10120 int err;
10121 struct Scsi_Host *host = hba->host;
10122 struct device *dev = hba->dev;
10123 char eh_wq_name[sizeof("ufs_eh_wq_00")];
10124
10125 /*
10126 * dev_set_drvdata() must be called before any callbacks are registered
10127 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10128 * sysfs).
10129 */
10130 dev_set_drvdata(dev, hba);
10131
10132 if (!mmio_base) {
10133 dev_err(hba->dev,
10134 "Invalid memory reference for mmio_base is NULL\n");
10135 err = -ENODEV;
10136 goto out_error;
10137 }
10138
10139 hba->mmio_base = mmio_base;
10140 hba->irq = irq;
10141 hba->vps = &ufs_hba_vps;
10142
10143 err = ufshcd_hba_init(hba);
10144 if (err)
10145 goto out_error;
10146
10147 /* Read capabilities registers */
10148 err = ufshcd_hba_capabilities(hba);
10149 if (err)
10150 goto out_disable;
10151
10152 /* Get UFS version supported by the controller */
10153 hba->ufs_version = ufshcd_get_ufs_version(hba);
10154
10155 /* Get Interrupt bit mask per version */
10156 hba->intr_mask = ufshcd_get_intr_mask(hba);
10157
10158 err = ufshcd_set_dma_mask(hba);
10159 if (err) {
10160 dev_err(hba->dev, "set dma mask failed\n");
10161 goto out_disable;
10162 }
10163
10164 /* Allocate memory for host memory space */
10165 err = ufshcd_memory_alloc(hba);
10166 if (err) {
10167 dev_err(hba->dev, "Memory allocation failed\n");
10168 goto out_disable;
10169 }
10170
10171 /* Configure LRB */
10172 ufshcd_host_memory_configure(hba);
10173
10174 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10175 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
10176 host->max_id = UFSHCD_MAX_ID;
10177 host->max_lun = UFS_MAX_LUNS;
10178 host->max_channel = UFSHCD_MAX_CHANNEL;
10179 host->unique_id = host->host_no;
10180 host->max_cmd_len = UFS_CDB_SIZE;
10181
10182 hba->max_pwr_info.is_valid = false;
10183
10184 /* Initialize work queues */
10185 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
10186 hba->host->host_no);
10187 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
10188 if (!hba->eh_wq) {
10189 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10190 __func__);
10191 err = -ENOMEM;
10192 goto out_disable;
10193 }
10194 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10195 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10196
10197 sema_init(&hba->host_sem, 1);
10198
10199 /* Initialize UIC command mutex */
10200 mutex_init(&hba->uic_cmd_mutex);
10201
10202 /* Initialize mutex for device management commands */
10203 mutex_init(&hba->dev_cmd.lock);
10204
10205 /* Initialize mutex for exception event control */
10206 mutex_init(&hba->ee_ctrl_mutex);
10207
10208 init_rwsem(&hba->clk_scaling_lock);
10209
10210 ufshcd_init_clk_gating(hba);
10211
10212 ufshcd_init_clk_scaling(hba);
10213
10214 /*
10215 * In order to avoid any spurious interrupt immediately after
10216 * registering UFS controller interrupt handler, clear any pending UFS
10217 * interrupt status and disable all the UFS interrupts.
10218 */
10219 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10220 REG_INTERRUPT_STATUS);
10221 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10222 /*
10223 * Make sure that UFS interrupts are disabled and any pending interrupt
10224 * status is cleared before registering UFS interrupt handler.
10225 */
10226 mb();
10227
10228 /* IRQ registration */
10229 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
10230 if (err) {
10231 dev_err(hba->dev, "request irq failed\n");
10232 goto out_disable;
10233 } else {
10234 hba->is_irq_enabled = true;
10235 }
10236
10237 if (!is_mcq_supported(hba)) {
10238 err = scsi_add_host(host, hba->dev);
10239 if (err) {
10240 dev_err(hba->dev, "scsi_add_host failed\n");
10241 goto out_disable;
10242 }
10243 }
10244
10245 hba->tmf_tag_set = (struct blk_mq_tag_set) {
10246 .nr_hw_queues = 1,
10247 .queue_depth = hba->nutmrs,
10248 .ops = &ufshcd_tmf_ops,
10249 .flags = BLK_MQ_F_NO_SCHED,
10250 };
10251 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
10252 if (err < 0)
10253 goto out_remove_scsi_host;
10254 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
10255 if (IS_ERR(hba->tmf_queue)) {
10256 err = PTR_ERR(hba->tmf_queue);
10257 goto free_tmf_tag_set;
10258 }
10259 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
10260 sizeof(*hba->tmf_rqs), GFP_KERNEL);
10261 if (!hba->tmf_rqs) {
10262 err = -ENOMEM;
10263 goto free_tmf_queue;
10264 }
10265
10266 /* Reset the attached device */
10267 ufshcd_device_reset(hba);
10268
10269 ufshcd_init_crypto(hba);
10270
10271 /* Host controller enable */
10272 err = ufshcd_hba_enable(hba);
10273 if (err) {
10274 dev_err(hba->dev, "Host controller enable failed\n");
10275 ufshcd_print_evt_hist(hba);
10276 ufshcd_print_host_state(hba);
10277 goto free_tmf_queue;
10278 }
10279
10280 /*
10281 * Set the default power management level for runtime and system PM.
10282 * Default power saving mode is to keep UFS link in Hibern8 state
10283 * and UFS device in sleep state.
10284 */
10285 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10286 UFS_SLEEP_PWR_MODE,
10287 UIC_LINK_HIBERN8_STATE);
10288 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10289 UFS_SLEEP_PWR_MODE,
10290 UIC_LINK_HIBERN8_STATE);
10291
10292 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
10293 ufshcd_rpm_dev_flush_recheck_work);
10294
10295 /* Set the default auto-hiberate idle timer value to 150 ms */
10296 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10297 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10298 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10299 }
10300
10301 /* Hold auto suspend until async scan completes */
10302 pm_runtime_get_sync(dev);
10303 atomic_set(&hba->scsi_block_reqs_cnt, 0);
10304 /*
10305 * We are assuming that device wasn't put in sleep/power-down
10306 * state exclusively during the boot stage before kernel.
10307 * This assumption helps avoid doing link startup twice during
10308 * ufshcd_probe_hba().
10309 */
10310 ufshcd_set_ufs_dev_active(hba);
10311
10312 async_schedule(ufshcd_async_scan, hba);
10313 ufs_sysfs_add_nodes(hba->dev);
10314
10315 device_enable_async_suspend(dev);
10316 return 0;
10317
10318 free_tmf_queue:
10319 blk_mq_destroy_queue(hba->tmf_queue);
10320 blk_put_queue(hba->tmf_queue);
10321 free_tmf_tag_set:
10322 blk_mq_free_tag_set(&hba->tmf_tag_set);
10323 out_remove_scsi_host:
10324 scsi_remove_host(hba->host);
10325 out_disable:
10326 hba->is_irq_enabled = false;
10327 ufshcd_hba_exit(hba);
10328 out_error:
10329 return err;
10330 }
10331 EXPORT_SYMBOL_GPL(ufshcd_init);
10332
10333 void ufshcd_resume_complete(struct device *dev)
10334 {
10335 struct ufs_hba *hba = dev_get_drvdata(dev);
10336
10337 if (hba->complete_put) {
10338 ufshcd_rpm_put(hba);
10339 hba->complete_put = false;
10340 }
10341 }
10342 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10343
10344 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10345 {
10346 struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
10347 enum ufs_dev_pwr_mode dev_pwr_mode;
10348 enum uic_link_state link_state;
10349 unsigned long flags;
10350 bool res;
10351
10352 spin_lock_irqsave(&dev->power.lock, flags);
10353 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10354 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10355 res = pm_runtime_suspended(dev) &&
10356 hba->curr_dev_pwr_mode == dev_pwr_mode &&
10357 hba->uic_link_state == link_state &&
10358 !hba->dev_info.b_rpm_dev_flush_capable;
10359 spin_unlock_irqrestore(&dev->power.lock, flags);
10360
10361 return res;
10362 }
10363
10364 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
10365 {
10366 struct ufs_hba *hba = dev_get_drvdata(dev);
10367 int ret;
10368
10369 /*
10370 * SCSI assumes that runtime-pm and system-pm for scsi drivers
10371 * are same. And it doesn't wake up the device for system-suspend
10372 * if it's runtime suspended. But ufs doesn't follow that.
10373 * Refer ufshcd_resume_complete()
10374 */
10375 if (hba->ufs_device_wlun) {
10376 /* Prevent runtime suspend */
10377 ufshcd_rpm_get_noresume(hba);
10378 /*
10379 * Check if already runtime suspended in same state as system
10380 * suspend would be.
10381 */
10382 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10383 /* RPM state is not ok for SPM, so runtime resume */
10384 ret = ufshcd_rpm_resume(hba);
10385 if (ret < 0 && ret != -EACCES) {
10386 ufshcd_rpm_put(hba);
10387 return ret;
10388 }
10389 }
10390 hba->complete_put = true;
10391 }
10392 return 0;
10393 }
10394 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10395
10396 int ufshcd_suspend_prepare(struct device *dev)
10397 {
10398 return __ufshcd_suspend_prepare(dev, true);
10399 }
10400 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10401
10402 #ifdef CONFIG_PM_SLEEP
10403 static int ufshcd_wl_poweroff(struct device *dev)
10404 {
10405 struct scsi_device *sdev = to_scsi_device(dev);
10406 struct ufs_hba *hba = shost_priv(sdev->host);
10407
10408 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10409 return 0;
10410 }
10411 #endif
10412
10413 static int ufshcd_wl_probe(struct device *dev)
10414 {
10415 struct scsi_device *sdev = to_scsi_device(dev);
10416
10417 if (!is_device_wlun(sdev))
10418 return -ENODEV;
10419
10420 blk_pm_runtime_init(sdev->request_queue, dev);
10421 pm_runtime_set_autosuspend_delay(dev, 0);
10422 pm_runtime_allow(dev);
10423
10424 return 0;
10425 }
10426
10427 static int ufshcd_wl_remove(struct device *dev)
10428 {
10429 pm_runtime_forbid(dev);
10430 return 0;
10431 }
10432
10433 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10434 #ifdef CONFIG_PM_SLEEP
10435 .suspend = ufshcd_wl_suspend,
10436 .resume = ufshcd_wl_resume,
10437 .freeze = ufshcd_wl_suspend,
10438 .thaw = ufshcd_wl_resume,
10439 .poweroff = ufshcd_wl_poweroff,
10440 .restore = ufshcd_wl_resume,
10441 #endif
10442 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10443 };
10444
10445 /*
10446 * ufs_dev_wlun_template - describes ufs device wlun
10447 * ufs-device wlun - used to send pm commands
10448 * All luns are consumers of ufs-device wlun.
10449 *
10450 * Currently, no sd driver is present for wluns.
10451 * Hence the no specific pm operations are performed.
10452 * With ufs design, SSU should be sent to ufs-device wlun.
10453 * Hence register a scsi driver for ufs wluns only.
10454 */
10455 static struct scsi_driver ufs_dev_wlun_template = {
10456 .gendrv = {
10457 .name = "ufs_device_wlun",
10458 .owner = THIS_MODULE,
10459 .probe = ufshcd_wl_probe,
10460 .remove = ufshcd_wl_remove,
10461 .pm = &ufshcd_wl_pm_ops,
10462 .shutdown = ufshcd_wl_shutdown,
10463 },
10464 };
10465
10466 static int __init ufshcd_core_init(void)
10467 {
10468 int ret;
10469
10470 ufs_debugfs_init();
10471
10472 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10473 if (ret)
10474 ufs_debugfs_exit();
10475 return ret;
10476 }
10477
10478 static void __exit ufshcd_core_exit(void)
10479 {
10480 ufs_debugfs_exit();
10481 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
10482 }
10483
10484 module_init(ufshcd_core_init);
10485 module_exit(ufshcd_core_exit);
10486
10487 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10488 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
10489 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
10490 MODULE_LICENSE("GPL");