1 // SPDX-License-Identifier: GPL-2.0+
3 * ufs.c - Universal Flash Subsystem (UFS) driver
5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
11 #include <bouncebuf.h>
16 #include <dm/device_compat.h>
17 #include <dm/devres.h>
19 #include <dm/device-internal.h>
24 #include <asm/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
31 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
34 /* maximum number of link-startup retries */
35 #define DME_LINKSTARTUP_RETRIES 3
37 /* maximum number of retries for a general UIC command */
38 #define UFS_UIC_COMMAND_RETRIES 3
40 /* Query request retries */
41 #define QUERY_REQ_RETRIES 3
42 /* Query request timeout */
43 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
45 /* maximum timeout in ms for a general UIC command */
46 #define UFS_UIC_CMD_TIMEOUT 1000
47 /* NOP OUT retries waiting for NOP IN response */
48 #define NOP_OUT_RETRIES 10
49 /* Timeout after 30 msecs if NOP OUT hangs without response */
50 #define NOP_OUT_TIMEOUT 30 /* msecs */
52 /* Only use one Task Tag for all requests */
55 /* Expose the flag value from utp_upiu_query.value */
56 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
58 #define MAX_PRDT_ENTRY 262144
60 /* maximum bytes per request */
61 #define UFS_MAX_BYTES (128 * 256 * 1024)
63 static inline bool ufshcd_is_hba_active(struct ufs_hba
*hba
);
64 static inline void ufshcd_hba_stop(struct ufs_hba
*hba
);
65 static int ufshcd_hba_enable(struct ufs_hba
*hba
);
68 * ufshcd_wait_for_register - wait for register value to change
70 static int ufshcd_wait_for_register(struct ufs_hba
*hba
, u32 reg
, u32 mask
,
71 u32 val
, unsigned long timeout_ms
)
74 unsigned long start
= get_timer(0);
76 /* ignore bits that we don't intend to wait on */
79 while ((ufshcd_readl(hba
, reg
) & mask
) != val
) {
80 if (get_timer(start
) > timeout_ms
) {
81 if ((ufshcd_readl(hba
, reg
) & mask
) != val
)
91 * ufshcd_init_pwr_info - setting the POR (power on reset)
92 * values in hba power info
94 static void ufshcd_init_pwr_info(struct ufs_hba
*hba
)
96 hba
->pwr_info
.gear_rx
= UFS_PWM_G1
;
97 hba
->pwr_info
.gear_tx
= UFS_PWM_G1
;
98 hba
->pwr_info
.lane_rx
= 1;
99 hba
->pwr_info
.lane_tx
= 1;
100 hba
->pwr_info
.pwr_rx
= SLOWAUTO_MODE
;
101 hba
->pwr_info
.pwr_tx
= SLOWAUTO_MODE
;
102 hba
->pwr_info
.hs_rate
= 0;
106 * ufshcd_print_pwr_info - print power params as saved in hba
109 static void ufshcd_print_pwr_info(struct ufs_hba
*hba
)
111 static const char * const names
[] = {
121 dev_err(hba
->dev
, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
122 hba
->pwr_info
.gear_rx
, hba
->pwr_info
.gear_tx
,
123 hba
->pwr_info
.lane_rx
, hba
->pwr_info
.lane_tx
,
124 names
[hba
->pwr_info
.pwr_rx
],
125 names
[hba
->pwr_info
.pwr_tx
],
126 hba
->pwr_info
.hs_rate
);
130 * ufshcd_ready_for_uic_cmd - Check if controller is ready
131 * to accept UIC commands
133 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba
*hba
)
135 if (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) & UIC_COMMAND_READY
)
142 * ufshcd_get_uic_cmd_result - Get the UIC command result
144 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba
*hba
)
146 return ufshcd_readl(hba
, REG_UIC_COMMAND_ARG_2
) &
147 MASK_UIC_COMMAND_RESULT
;
151 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
153 static inline u32
ufshcd_get_dme_attr_val(struct ufs_hba
*hba
)
155 return ufshcd_readl(hba
, REG_UIC_COMMAND_ARG_3
);
159 * ufshcd_is_device_present - Check if any device connected to
160 * the host controller
162 static inline bool ufshcd_is_device_present(struct ufs_hba
*hba
)
164 return (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) &
165 DEVICE_PRESENT
) ? true : false;
169 * ufshcd_send_uic_cmd - UFS Interconnect layer command API
172 static int ufshcd_send_uic_cmd(struct ufs_hba
*hba
, struct uic_command
*uic_cmd
)
174 unsigned long start
= 0;
176 u32 enabled_intr_status
;
178 if (!ufshcd_ready_for_uic_cmd(hba
)) {
180 "Controller not ready to accept UIC commands\n");
184 debug("sending uic command:%d\n", uic_cmd
->command
);
187 ufshcd_writel(hba
, uic_cmd
->argument1
, REG_UIC_COMMAND_ARG_1
);
188 ufshcd_writel(hba
, uic_cmd
->argument2
, REG_UIC_COMMAND_ARG_2
);
189 ufshcd_writel(hba
, uic_cmd
->argument3
, REG_UIC_COMMAND_ARG_3
);
192 ufshcd_writel(hba
, uic_cmd
->command
& COMMAND_OPCODE_MASK
,
195 start
= get_timer(0);
197 intr_status
= ufshcd_readl(hba
, REG_INTERRUPT_STATUS
);
198 enabled_intr_status
= intr_status
& hba
->intr_mask
;
199 ufshcd_writel(hba
, intr_status
, REG_INTERRUPT_STATUS
);
201 if (get_timer(start
) > UFS_UIC_CMD_TIMEOUT
) {
203 "Timedout waiting for UIC response\n");
208 if (enabled_intr_status
& UFSHCD_ERROR_MASK
) {
209 dev_err(hba
->dev
, "Error in status:%08x\n",
210 enabled_intr_status
);
214 } while (!(enabled_intr_status
& UFSHCD_UIC_MASK
));
216 uic_cmd
->argument2
= ufshcd_get_uic_cmd_result(hba
);
217 uic_cmd
->argument3
= ufshcd_get_dme_attr_val(hba
);
219 debug("Sent successfully\n");
225 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
228 int ufshcd_dme_set_attr(struct ufs_hba
*hba
, u32 attr_sel
, u8 attr_set
,
229 u32 mib_val
, u8 peer
)
231 struct uic_command uic_cmd
= {0};
232 static const char *const action
[] = {
236 const char *set
= action
[!!peer
];
238 int retries
= UFS_UIC_COMMAND_RETRIES
;
240 uic_cmd
.command
= peer
?
241 UIC_CMD_DME_PEER_SET
: UIC_CMD_DME_SET
;
242 uic_cmd
.argument1
= attr_sel
;
243 uic_cmd
.argument2
= UIC_ARG_ATTR_TYPE(attr_set
);
244 uic_cmd
.argument3
= mib_val
;
247 /* for peer attributes we retry upon failure */
248 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
250 dev_dbg(hba
->dev
, "%s: attr-id 0x%x val 0x%x error code %d\n",
251 set
, UIC_GET_ATTR_ID(attr_sel
), mib_val
, ret
);
252 } while (ret
&& peer
&& --retries
);
255 dev_err(hba
->dev
, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
256 set
, UIC_GET_ATTR_ID(attr_sel
), mib_val
,
257 UFS_UIC_COMMAND_RETRIES
- retries
);
263 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
266 int ufshcd_dme_get_attr(struct ufs_hba
*hba
, u32 attr_sel
,
267 u32
*mib_val
, u8 peer
)
269 struct uic_command uic_cmd
= {0};
270 static const char *const action
[] = {
274 const char *get
= action
[!!peer
];
276 int retries
= UFS_UIC_COMMAND_RETRIES
;
278 uic_cmd
.command
= peer
?
279 UIC_CMD_DME_PEER_GET
: UIC_CMD_DME_GET
;
280 uic_cmd
.argument1
= attr_sel
;
283 /* for peer attributes we retry upon failure */
284 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
286 dev_dbg(hba
->dev
, "%s: attr-id 0x%x error code %d\n",
287 get
, UIC_GET_ATTR_ID(attr_sel
), ret
);
288 } while (ret
&& peer
&& --retries
);
291 dev_err(hba
->dev
, "%s: attr-id 0x%x failed %d retries\n",
292 get
, UIC_GET_ATTR_ID(attr_sel
),
293 UFS_UIC_COMMAND_RETRIES
- retries
);
296 *mib_val
= uic_cmd
.argument3
;
301 static int ufshcd_disable_tx_lcc(struct ufs_hba
*hba
, bool peer
)
303 u32 tx_lanes
, i
, err
= 0;
306 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
309 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
311 for (i
= 0; i
< tx_lanes
; i
++) {
313 err
= ufshcd_dme_set(hba
,
314 UIC_ARG_MIB_SEL(TX_LCC_ENABLE
,
315 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i
)),
318 err
= ufshcd_dme_peer_set(hba
,
319 UIC_ARG_MIB_SEL(TX_LCC_ENABLE
,
320 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i
)),
323 dev_err(hba
->dev
, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
324 __func__
, peer
, i
, err
);
332 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba
*hba
)
334 return ufshcd_disable_tx_lcc(hba
, true);
338 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
341 static int ufshcd_dme_link_startup(struct ufs_hba
*hba
)
343 struct uic_command uic_cmd
= {0};
346 uic_cmd
.command
= UIC_CMD_DME_LINK_STARTUP
;
348 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
351 "dme-link-startup: error code %d\n", ret
);
356 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
359 static inline void ufshcd_disable_intr_aggr(struct ufs_hba
*hba
)
361 ufshcd_writel(hba
, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL
);
365 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
367 static inline int ufshcd_get_lists_status(u32 reg
)
369 return !((reg
& UFSHCD_STATUS_READY
) == UFSHCD_STATUS_READY
);
373 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
374 * When run-stop registers are set to 1, it indicates the
375 * host controller that it can process the requests
377 static void ufshcd_enable_run_stop_reg(struct ufs_hba
*hba
)
379 ufshcd_writel(hba
, UTP_TASK_REQ_LIST_RUN_STOP_BIT
,
380 REG_UTP_TASK_REQ_LIST_RUN_STOP
);
381 ufshcd_writel(hba
, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT
,
382 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP
);
386 * ufshcd_enable_intr - enable interrupts
388 static void ufshcd_enable_intr(struct ufs_hba
*hba
, u32 intrs
)
390 u32 set
= ufshcd_readl(hba
, REG_INTERRUPT_ENABLE
);
393 if (hba
->version
== UFSHCI_VERSION_10
) {
394 rw
= set
& INTERRUPT_MASK_RW_VER_10
;
395 set
= rw
| ((set
^ intrs
) & intrs
);
400 ufshcd_writel(hba
, set
, REG_INTERRUPT_ENABLE
);
402 hba
->intr_mask
= set
;
406 * ufshcd_make_hba_operational - Make UFS controller operational
408 * To bring UFS host controller to operational state,
409 * 1. Enable required interrupts
410 * 2. Configure interrupt aggregation
411 * 3. Program UTRL and UTMRL base address
412 * 4. Configure run-stop-registers
415 static int ufshcd_make_hba_operational(struct ufs_hba
*hba
)
420 /* Enable required interrupts */
421 ufshcd_enable_intr(hba
, UFSHCD_ENABLE_INTRS
);
423 /* Disable interrupt aggregation */
424 ufshcd_disable_intr_aggr(hba
);
426 /* Configure UTRL and UTMRL base address registers */
427 ufshcd_writel(hba
, lower_32_bits((dma_addr_t
)hba
->utrdl
),
428 REG_UTP_TRANSFER_REQ_LIST_BASE_L
);
429 ufshcd_writel(hba
, upper_32_bits((dma_addr_t
)hba
->utrdl
),
430 REG_UTP_TRANSFER_REQ_LIST_BASE_H
);
431 ufshcd_writel(hba
, lower_32_bits((dma_addr_t
)hba
->utmrdl
),
432 REG_UTP_TASK_REQ_LIST_BASE_L
);
433 ufshcd_writel(hba
, upper_32_bits((dma_addr_t
)hba
->utmrdl
),
434 REG_UTP_TASK_REQ_LIST_BASE_H
);
437 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
439 reg
= ufshcd_readl(hba
, REG_CONTROLLER_STATUS
);
440 if (!(ufshcd_get_lists_status(reg
))) {
441 ufshcd_enable_run_stop_reg(hba
);
444 "Host controller not ready to process requests");
454 * ufshcd_link_startup - Initialize unipro link startup
456 static int ufshcd_link_startup(struct ufs_hba
*hba
)
459 int retries
= DME_LINKSTARTUP_RETRIES
;
460 bool link_startup_again
= true;
464 ufshcd_ops_link_startup_notify(hba
, PRE_CHANGE
);
466 ret
= ufshcd_dme_link_startup(hba
);
468 /* check if device is detected by inter-connect layer */
469 if (!ret
&& !ufshcd_is_device_present(hba
)) {
470 dev_err(hba
->dev
, "%s: Device not present\n", __func__
);
476 * DME link lost indication is only received when link is up,
477 * but we can't be sure if the link is up until link startup
478 * succeeds. So reset the local Uni-Pro and try again.
480 if (ret
&& ufshcd_hba_enable(hba
))
482 } while (ret
&& retries
--);
485 /* failed to get the link up... retire */
488 if (link_startup_again
) {
489 link_startup_again
= false;
490 retries
= DME_LINKSTARTUP_RETRIES
;
494 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
495 ufshcd_init_pwr_info(hba
);
497 if (hba
->quirks
& UFSHCD_QUIRK_BROKEN_LCC
) {
498 ret
= ufshcd_disable_device_tx_lcc(hba
);
503 /* Include any host controller configuration via UIC commands */
504 ret
= ufshcd_ops_link_startup_notify(hba
, POST_CHANGE
);
508 ret
= ufshcd_make_hba_operational(hba
);
511 dev_err(hba
->dev
, "link startup failed %d\n", ret
);
517 * ufshcd_hba_stop - Send controller to reset state
519 static inline void ufshcd_hba_stop(struct ufs_hba
*hba
)
523 ufshcd_writel(hba
, CONTROLLER_DISABLE
, REG_CONTROLLER_ENABLE
);
524 err
= ufshcd_wait_for_register(hba
, REG_CONTROLLER_ENABLE
,
525 CONTROLLER_ENABLE
, CONTROLLER_DISABLE
,
528 dev_err(hba
->dev
, "%s: Controller disable failed\n", __func__
);
532 * ufshcd_is_hba_active - Get controller state
534 static inline bool ufshcd_is_hba_active(struct ufs_hba
*hba
)
536 return (ufshcd_readl(hba
, REG_CONTROLLER_ENABLE
) & CONTROLLER_ENABLE
)
541 * ufshcd_hba_start - Start controller initialization sequence
543 static inline void ufshcd_hba_start(struct ufs_hba
*hba
)
545 ufshcd_writel(hba
, CONTROLLER_ENABLE
, REG_CONTROLLER_ENABLE
);
549 * ufshcd_hba_enable - initialize the controller
551 static int ufshcd_hba_enable(struct ufs_hba
*hba
)
555 if (!ufshcd_is_hba_active(hba
))
556 /* change controller state to "reset state" */
557 ufshcd_hba_stop(hba
);
559 ufshcd_ops_hce_enable_notify(hba
, PRE_CHANGE
);
561 /* start controller initialization sequence */
562 ufshcd_hba_start(hba
);
565 * To initialize a UFS host controller HCE bit must be set to 1.
566 * During initialization the HCE bit value changes from 1->0->1.
567 * When the host controller completes initialization sequence
568 * it sets the value of HCE bit to 1. The same HCE bit is read back
569 * to check if the controller has completed initialization sequence.
570 * So without this delay the value HCE = 1, set in the previous
571 * instruction might be read back.
572 * This delay can be changed based on the controller.
576 /* wait for the host controller to complete initialization */
578 while (ufshcd_is_hba_active(hba
)) {
582 dev_err(hba
->dev
, "Controller enable failed\n");
588 /* enable UIC related interrupts */
589 ufshcd_enable_intr(hba
, UFSHCD_UIC_MASK
);
591 ufshcd_ops_hce_enable_notify(hba
, POST_CHANGE
);
597 * ufshcd_host_memory_configure - configure local reference block with
600 static void ufshcd_host_memory_configure(struct ufs_hba
*hba
)
602 struct utp_transfer_req_desc
*utrdlp
;
603 dma_addr_t cmd_desc_dma_addr
;
608 cmd_desc_dma_addr
= (dma_addr_t
)hba
->ucdl
;
610 utrdlp
->command_desc_base_addr_lo
=
611 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr
));
612 utrdlp
->command_desc_base_addr_hi
=
613 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr
));
615 response_offset
= offsetof(struct utp_transfer_cmd_desc
, response_upiu
);
616 prdt_offset
= offsetof(struct utp_transfer_cmd_desc
, prd_table
);
618 utrdlp
->response_upiu_offset
= cpu_to_le16(response_offset
>> 2);
619 utrdlp
->prd_table_offset
= cpu_to_le16(prdt_offset
>> 2);
620 utrdlp
->response_upiu_length
= cpu_to_le16(ALIGNED_UPIU_SIZE
>> 2);
622 hba
->ucd_req_ptr
= (struct utp_upiu_req
*)hba
->ucdl
;
624 (struct utp_upiu_rsp
*)&hba
->ucdl
->response_upiu
;
626 (struct ufshcd_sg_entry
*)&hba
->ucdl
->prd_table
;
630 * ufshcd_memory_alloc - allocate memory for host memory space data structures
632 static int ufshcd_memory_alloc(struct ufs_hba
*hba
)
634 /* Allocate one Transfer Request Descriptor
635 * Should be aligned to 1k boundary.
637 hba
->utrdl
= memalign(1024, sizeof(struct utp_transfer_req_desc
));
639 dev_err(hba
->dev
, "Transfer Descriptor memory allocation failed\n");
643 /* Allocate one Command Descriptor
644 * Should be aligned to 1k boundary.
646 hba
->ucdl
= memalign(1024, sizeof(struct utp_transfer_cmd_desc
));
648 dev_err(hba
->dev
, "Command descriptor memory allocation failed\n");
656 * ufshcd_get_intr_mask - Get the interrupt bit mask
658 static inline u32
ufshcd_get_intr_mask(struct ufs_hba
*hba
)
662 switch (hba
->version
) {
663 case UFSHCI_VERSION_10
:
664 intr_mask
= INTERRUPT_MASK_ALL_VER_10
;
666 case UFSHCI_VERSION_11
:
667 case UFSHCI_VERSION_20
:
668 intr_mask
= INTERRUPT_MASK_ALL_VER_11
;
670 case UFSHCI_VERSION_21
:
672 intr_mask
= INTERRUPT_MASK_ALL_VER_21
;
680 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
682 static inline u32
ufshcd_get_ufs_version(struct ufs_hba
*hba
)
684 return ufshcd_readl(hba
, REG_UFS_VERSION
);
688 * ufshcd_get_upmcrs - Get the power mode change request status
690 static inline u8
ufshcd_get_upmcrs(struct ufs_hba
*hba
)
692 return (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) >> 8) & 0x7;
696 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
697 * descriptor according to request
699 static void ufshcd_prepare_req_desc_hdr(struct ufs_hba
*hba
,
701 enum dma_data_direction cmd_dir
)
703 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
707 if (cmd_dir
== DMA_FROM_DEVICE
) {
708 data_direction
= UTP_DEVICE_TO_HOST
;
709 *upiu_flags
= UPIU_CMD_FLAGS_READ
;
710 } else if (cmd_dir
== DMA_TO_DEVICE
) {
711 data_direction
= UTP_HOST_TO_DEVICE
;
712 *upiu_flags
= UPIU_CMD_FLAGS_WRITE
;
714 data_direction
= UTP_NO_DATA_TRANSFER
;
715 *upiu_flags
= UPIU_CMD_FLAGS_NONE
;
718 dword_0
= data_direction
| (0x1 << UPIU_COMMAND_TYPE_OFFSET
);
720 /* Enable Interrupt for command */
721 dword_0
|= UTP_REQ_DESC_INT_CMD
;
723 /* Transfer request descriptor header fields */
724 req_desc
->header
.dword_0
= cpu_to_le32(dword_0
);
725 /* dword_1 is reserved, hence it is set to 0 */
726 req_desc
->header
.dword_1
= 0;
728 * assigning invalid value for command status. Controller
729 * updates OCS on command completion, with the command
732 req_desc
->header
.dword_2
=
733 cpu_to_le32(OCS_INVALID_COMMAND_STATUS
);
734 /* dword_3 is reserved, hence it is set to 0 */
735 req_desc
->header
.dword_3
= 0;
737 req_desc
->prd_table_length
= 0;
740 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba
*hba
,
743 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
744 struct ufs_query
*query
= &hba
->dev_cmd
.query
;
745 u16 len
= be16_to_cpu(query
->request
.upiu_req
.length
);
747 /* Query request header */
748 ucd_req_ptr
->header
.dword_0
=
749 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ
,
750 upiu_flags
, 0, TASK_TAG
);
751 ucd_req_ptr
->header
.dword_1
=
752 UPIU_HEADER_DWORD(0, query
->request
.query_func
,
755 /* Data segment length only need for WRITE_DESC */
756 if (query
->request
.upiu_req
.opcode
== UPIU_QUERY_OPCODE_WRITE_DESC
)
757 ucd_req_ptr
->header
.dword_2
=
758 UPIU_HEADER_DWORD(0, 0, (len
>> 8), (u8
)len
);
760 ucd_req_ptr
->header
.dword_2
= 0;
762 /* Copy the Query Request buffer as is */
763 memcpy(&ucd_req_ptr
->qr
, &query
->request
.upiu_req
, QUERY_OSF_SIZE
);
765 /* Copy the Descriptor */
766 if (query
->request
.upiu_req
.opcode
== UPIU_QUERY_OPCODE_WRITE_DESC
)
767 memcpy(ucd_req_ptr
+ 1, query
->descriptor
, len
);
769 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
772 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba
*hba
)
774 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
776 memset(ucd_req_ptr
, 0, sizeof(struct utp_upiu_req
));
778 /* command descriptor fields */
779 ucd_req_ptr
->header
.dword_0
=
780 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT
, 0, 0, TASK_TAG
);
781 /* clear rest of the fields of basic header */
782 ucd_req_ptr
->header
.dword_1
= 0;
783 ucd_req_ptr
->header
.dword_2
= 0;
785 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
789 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
790 * for Device Management Purposes
792 static int ufshcd_comp_devman_upiu(struct ufs_hba
*hba
,
793 enum dev_cmd_type cmd_type
)
798 hba
->dev_cmd
.type
= cmd_type
;
800 ufshcd_prepare_req_desc_hdr(hba
, &upiu_flags
, DMA_NONE
);
802 case DEV_CMD_TYPE_QUERY
:
803 ufshcd_prepare_utp_query_req_upiu(hba
, upiu_flags
);
805 case DEV_CMD_TYPE_NOP
:
806 ufshcd_prepare_utp_nop_upiu(hba
);
815 static int ufshcd_send_command(struct ufs_hba
*hba
, unsigned int task_tag
)
819 u32 enabled_intr_status
;
821 ufshcd_writel(hba
, 1 << task_tag
, REG_UTP_TRANSFER_REQ_DOOR_BELL
);
823 start
= get_timer(0);
825 intr_status
= ufshcd_readl(hba
, REG_INTERRUPT_STATUS
);
826 enabled_intr_status
= intr_status
& hba
->intr_mask
;
827 ufshcd_writel(hba
, intr_status
, REG_INTERRUPT_STATUS
);
829 if (get_timer(start
) > QUERY_REQ_TIMEOUT
) {
831 "Timedout waiting for UTP response\n");
836 if (enabled_intr_status
& UFSHCD_ERROR_MASK
) {
837 dev_err(hba
->dev
, "Error in status:%08x\n",
838 enabled_intr_status
);
842 } while (!(enabled_intr_status
& UTP_TRANSFER_REQ_COMPL
));
848 * ufshcd_get_req_rsp - returns the TR response transaction type
850 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp
*ucd_rsp_ptr
)
852 return be32_to_cpu(ucd_rsp_ptr
->header
.dword_0
) >> 24;
856 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
859 static inline int ufshcd_get_tr_ocs(struct ufs_hba
*hba
)
861 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
863 return le32_to_cpu(req_desc
->header
.dword_2
) & MASK_OCS
;
866 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp
*ucd_rsp_ptr
)
868 return be32_to_cpu(ucd_rsp_ptr
->header
.dword_1
) & MASK_RSP_UPIU_RESULT
;
871 static int ufshcd_check_query_response(struct ufs_hba
*hba
)
873 struct ufs_query_res
*query_res
= &hba
->dev_cmd
.query
.response
;
875 /* Get the UPIU response */
876 query_res
->response
= ufshcd_get_rsp_upiu_result(hba
->ucd_rsp_ptr
) >>
877 UPIU_RSP_CODE_OFFSET
;
878 return query_res
->response
;
882 * ufshcd_copy_query_response() - Copy the Query Response and the data
885 static int ufshcd_copy_query_response(struct ufs_hba
*hba
)
887 struct ufs_query_res
*query_res
= &hba
->dev_cmd
.query
.response
;
889 memcpy(&query_res
->upiu_res
, &hba
->ucd_rsp_ptr
->qr
, QUERY_OSF_SIZE
);
891 /* Get the descriptor */
892 if (hba
->dev_cmd
.query
.descriptor
&&
893 hba
->ucd_rsp_ptr
->qr
.opcode
== UPIU_QUERY_OPCODE_READ_DESC
) {
894 u8
*descp
= (u8
*)hba
->ucd_rsp_ptr
+
895 GENERAL_UPIU_REQUEST_SIZE
;
899 /* data segment length */
900 resp_len
= be32_to_cpu(hba
->ucd_rsp_ptr
->header
.dword_2
) &
901 MASK_QUERY_DATA_SEG_LEN
;
903 be16_to_cpu(hba
->dev_cmd
.query
.request
.upiu_req
.length
);
904 if (likely(buf_len
>= resp_len
)) {
905 memcpy(hba
->dev_cmd
.query
.descriptor
, descp
, resp_len
);
908 "%s: Response size is bigger than buffer",
918 * ufshcd_exec_dev_cmd - API for sending device management requests
920 static int ufshcd_exec_dev_cmd(struct ufs_hba
*hba
, enum dev_cmd_type cmd_type
,
926 err
= ufshcd_comp_devman_upiu(hba
, cmd_type
);
930 err
= ufshcd_send_command(hba
, TASK_TAG
);
934 err
= ufshcd_get_tr_ocs(hba
);
936 dev_err(hba
->dev
, "Error in OCS:%d\n", err
);
940 resp
= ufshcd_get_req_rsp(hba
->ucd_rsp_ptr
);
942 case UPIU_TRANSACTION_NOP_IN
:
944 case UPIU_TRANSACTION_QUERY_RSP
:
945 err
= ufshcd_check_query_response(hba
);
947 err
= ufshcd_copy_query_response(hba
);
949 case UPIU_TRANSACTION_REJECT_UPIU
:
950 /* TODO: handle Reject UPIU Response */
952 dev_err(hba
->dev
, "%s: Reject UPIU not fully implemented\n",
957 dev_err(hba
->dev
, "%s: Invalid device management cmd response: %x\n",
965 * ufshcd_init_query() - init the query response and request parameters
967 static inline void ufshcd_init_query(struct ufs_hba
*hba
,
968 struct ufs_query_req
**request
,
969 struct ufs_query_res
**response
,
970 enum query_opcode opcode
,
971 u8 idn
, u8 index
, u8 selector
)
973 *request
= &hba
->dev_cmd
.query
.request
;
974 *response
= &hba
->dev_cmd
.query
.response
;
975 memset(*request
, 0, sizeof(struct ufs_query_req
));
976 memset(*response
, 0, sizeof(struct ufs_query_res
));
977 (*request
)->upiu_req
.opcode
= opcode
;
978 (*request
)->upiu_req
.idn
= idn
;
979 (*request
)->upiu_req
.index
= index
;
980 (*request
)->upiu_req
.selector
= selector
;
984 * ufshcd_query_flag() - API function for sending flag query requests
986 int ufshcd_query_flag(struct ufs_hba
*hba
, enum query_opcode opcode
,
987 enum flag_idn idn
, bool *flag_res
)
989 struct ufs_query_req
*request
= NULL
;
990 struct ufs_query_res
*response
= NULL
;
991 int err
, index
= 0, selector
= 0;
992 int timeout
= QUERY_REQ_TIMEOUT
;
994 ufshcd_init_query(hba
, &request
, &response
, opcode
, idn
, index
,
998 case UPIU_QUERY_OPCODE_SET_FLAG
:
999 case UPIU_QUERY_OPCODE_CLEAR_FLAG
:
1000 case UPIU_QUERY_OPCODE_TOGGLE_FLAG
:
1001 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST
;
1003 case UPIU_QUERY_OPCODE_READ_FLAG
:
1004 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_READ_REQUEST
;
1006 /* No dummy reads */
1007 dev_err(hba
->dev
, "%s: Invalid argument for read request\n",
1015 "%s: Expected query flag opcode but got = %d\n",
1021 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_QUERY
, timeout
);
1025 "%s: Sending flag query for idn %d failed, err = %d\n",
1026 __func__
, idn
, err
);
1031 *flag_res
= (be32_to_cpu(response
->upiu_res
.value
) &
1032 MASK_QUERY_UPIU_FLAG_LOC
) & 0x1;
1038 static int ufshcd_query_flag_retry(struct ufs_hba
*hba
,
1039 enum query_opcode opcode
,
1040 enum flag_idn idn
, bool *flag_res
)
1045 for (retries
= 0; retries
< QUERY_REQ_RETRIES
; retries
++) {
1046 ret
= ufshcd_query_flag(hba
, opcode
, idn
, flag_res
);
1049 "%s: failed with error %d, retries %d\n",
1050 __func__
, ret
, retries
);
1057 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1058 __func__
, opcode
, idn
, ret
, retries
);
1062 static int __ufshcd_query_descriptor(struct ufs_hba
*hba
,
1063 enum query_opcode opcode
,
1064 enum desc_idn idn
, u8 index
, u8 selector
,
1065 u8
*desc_buf
, int *buf_len
)
1067 struct ufs_query_req
*request
= NULL
;
1068 struct ufs_query_res
*response
= NULL
;
1072 dev_err(hba
->dev
, "%s: descriptor buffer required for opcode 0x%x\n",
1078 if (*buf_len
< QUERY_DESC_MIN_SIZE
|| *buf_len
> QUERY_DESC_MAX_SIZE
) {
1079 dev_err(hba
->dev
, "%s: descriptor buffer size (%d) is out of range\n",
1080 __func__
, *buf_len
);
1085 ufshcd_init_query(hba
, &request
, &response
, opcode
, idn
, index
,
1087 hba
->dev_cmd
.query
.descriptor
= desc_buf
;
1088 request
->upiu_req
.length
= cpu_to_be16(*buf_len
);
1091 case UPIU_QUERY_OPCODE_WRITE_DESC
:
1092 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST
;
1094 case UPIU_QUERY_OPCODE_READ_DESC
:
1095 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_READ_REQUEST
;
1098 dev_err(hba
->dev
, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1104 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_QUERY
, QUERY_REQ_TIMEOUT
);
1107 dev_err(hba
->dev
, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1108 __func__
, opcode
, idn
, index
, err
);
1112 hba
->dev_cmd
.query
.descriptor
= NULL
;
1113 *buf_len
= be16_to_cpu(response
->upiu_res
.length
);
1120 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
1122 int ufshcd_query_descriptor_retry(struct ufs_hba
*hba
, enum query_opcode opcode
,
1123 enum desc_idn idn
, u8 index
, u8 selector
,
1124 u8
*desc_buf
, int *buf_len
)
1129 for (retries
= QUERY_REQ_RETRIES
; retries
> 0; retries
--) {
1130 err
= __ufshcd_query_descriptor(hba
, opcode
, idn
, index
,
1131 selector
, desc_buf
, buf_len
);
1132 if (!err
|| err
== -EINVAL
)
1140 * ufshcd_read_desc_length - read the specified descriptor length from header
1142 static int ufshcd_read_desc_length(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1143 int desc_index
, int *desc_length
)
1146 u8 header
[QUERY_DESC_HDR_SIZE
];
1147 int header_len
= QUERY_DESC_HDR_SIZE
;
1149 if (desc_id
>= QUERY_DESC_IDN_MAX
)
1152 ret
= ufshcd_query_descriptor_retry(hba
, UPIU_QUERY_OPCODE_READ_DESC
,
1153 desc_id
, desc_index
, 0, header
,
1157 dev_err(hba
->dev
, "%s: Failed to get descriptor header id %d",
1160 } else if (desc_id
!= header
[QUERY_DESC_DESC_TYPE_OFFSET
]) {
1161 dev_warn(hba
->dev
, "%s: descriptor header id %d and desc_id %d mismatch",
1162 __func__
, header
[QUERY_DESC_DESC_TYPE_OFFSET
],
1167 *desc_length
= header
[QUERY_DESC_LENGTH_OFFSET
];
1172 static void ufshcd_init_desc_sizes(struct ufs_hba
*hba
)
1176 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_DEVICE
, 0,
1177 &hba
->desc_size
.dev_desc
);
1179 hba
->desc_size
.dev_desc
= QUERY_DESC_DEVICE_DEF_SIZE
;
1181 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_POWER
, 0,
1182 &hba
->desc_size
.pwr_desc
);
1184 hba
->desc_size
.pwr_desc
= QUERY_DESC_POWER_DEF_SIZE
;
1186 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_INTERCONNECT
, 0,
1187 &hba
->desc_size
.interc_desc
);
1189 hba
->desc_size
.interc_desc
= QUERY_DESC_INTERCONNECT_DEF_SIZE
;
1191 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_CONFIGURATION
, 0,
1192 &hba
->desc_size
.conf_desc
);
1194 hba
->desc_size
.conf_desc
= QUERY_DESC_CONFIGURATION_DEF_SIZE
;
1196 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_UNIT
, 0,
1197 &hba
->desc_size
.unit_desc
);
1199 hba
->desc_size
.unit_desc
= QUERY_DESC_UNIT_DEF_SIZE
;
1201 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_GEOMETRY
, 0,
1202 &hba
->desc_size
.geom_desc
);
1204 hba
->desc_size
.geom_desc
= QUERY_DESC_GEOMETRY_DEF_SIZE
;
1206 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_HEALTH
, 0,
1207 &hba
->desc_size
.hlth_desc
);
1209 hba
->desc_size
.hlth_desc
= QUERY_DESC_HEALTH_DEF_SIZE
;
1213 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
1216 int ufshcd_map_desc_id_to_length(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1220 case QUERY_DESC_IDN_DEVICE
:
1221 *desc_len
= hba
->desc_size
.dev_desc
;
1223 case QUERY_DESC_IDN_POWER
:
1224 *desc_len
= hba
->desc_size
.pwr_desc
;
1226 case QUERY_DESC_IDN_GEOMETRY
:
1227 *desc_len
= hba
->desc_size
.geom_desc
;
1229 case QUERY_DESC_IDN_CONFIGURATION
:
1230 *desc_len
= hba
->desc_size
.conf_desc
;
1232 case QUERY_DESC_IDN_UNIT
:
1233 *desc_len
= hba
->desc_size
.unit_desc
;
1235 case QUERY_DESC_IDN_INTERCONNECT
:
1236 *desc_len
= hba
->desc_size
.interc_desc
;
1238 case QUERY_DESC_IDN_STRING
:
1239 *desc_len
= QUERY_DESC_MAX_SIZE
;
1241 case QUERY_DESC_IDN_HEALTH
:
1242 *desc_len
= hba
->desc_size
.hlth_desc
;
1244 case QUERY_DESC_IDN_RFU_0
:
1245 case QUERY_DESC_IDN_RFU_1
:
1254 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length
);
1257 * ufshcd_read_desc_param - read the specified descriptor parameter
1260 int ufshcd_read_desc_param(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1261 int desc_index
, u8 param_offset
, u8
*param_read_buf
,
1267 bool is_kmalloc
= true;
1270 if (desc_id
>= QUERY_DESC_IDN_MAX
|| !param_size
)
1273 /* Get the max length of descriptor from structure filled up at probe
1276 ret
= ufshcd_map_desc_id_to_length(hba
, desc_id
, &buff_len
);
1279 if (ret
|| !buff_len
) {
1280 dev_err(hba
->dev
, "%s: Failed to get full descriptor length",
1285 /* Check whether we need temp memory */
1286 if (param_offset
!= 0 || param_size
< buff_len
) {
1287 desc_buf
= kmalloc(buff_len
, GFP_KERNEL
);
1291 desc_buf
= param_read_buf
;
1295 /* Request for full descriptor */
1296 ret
= ufshcd_query_descriptor_retry(hba
, UPIU_QUERY_OPCODE_READ_DESC
,
1297 desc_id
, desc_index
, 0, desc_buf
,
1301 dev_err(hba
->dev
, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
1302 __func__
, desc_id
, desc_index
, param_offset
, ret
);
1307 if (desc_buf
[QUERY_DESC_DESC_TYPE_OFFSET
] != desc_id
) {
1308 dev_err(hba
->dev
, "%s: invalid desc_id %d in descriptor header",
1309 __func__
, desc_buf
[QUERY_DESC_DESC_TYPE_OFFSET
]);
1314 /* Check wherher we will not copy more data, than available */
1315 if (is_kmalloc
&& param_size
> buff_len
)
1316 param_size
= buff_len
;
1319 memcpy(param_read_buf
, &desc_buf
[param_offset
], param_size
);
1326 /* replace non-printable or non-ASCII characters with spaces */
1327 static inline void ufshcd_remove_non_printable(uint8_t *val
)
1332 if (*val
< 0x20 || *val
> 0x7e)
1337 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
1338 * state) and waits for it to take effect.
1341 static int ufshcd_uic_pwr_ctrl(struct ufs_hba
*hba
, struct uic_command
*cmd
)
1343 unsigned long start
= 0;
1347 ret
= ufshcd_send_uic_cmd(hba
, cmd
);
1350 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
1351 cmd
->command
, cmd
->argument3
, ret
);
1356 start
= get_timer(0);
1358 status
= ufshcd_get_upmcrs(hba
);
1359 if (get_timer(start
) > UFS_UIC_CMD_TIMEOUT
) {
1361 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
1362 cmd
->command
, status
);
1363 ret
= (status
!= PWR_OK
) ? status
: -1;
1366 } while (status
!= PWR_LOCAL
);
1372 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
1373 * using DME_SET primitives.
1375 static int ufshcd_uic_change_pwr_mode(struct ufs_hba
*hba
, u8 mode
)
1377 struct uic_command uic_cmd
= {0};
1380 uic_cmd
.command
= UIC_CMD_DME_SET
;
1381 uic_cmd
.argument1
= UIC_ARG_MIB(PA_PWRMODE
);
1382 uic_cmd
.argument3
= mode
;
1383 ret
= ufshcd_uic_pwr_ctrl(hba
, &uic_cmd
);
1389 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba
*hba
,
1390 struct scsi_cmd
*pccb
, u32 upiu_flags
)
1392 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
1393 unsigned int cdb_len
;
1395 /* command descriptor fields */
1396 ucd_req_ptr
->header
.dword_0
=
1397 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND
, upiu_flags
,
1398 pccb
->lun
, TASK_TAG
);
1399 ucd_req_ptr
->header
.dword_1
=
1400 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI
, 0, 0, 0);
1402 /* Total EHS length and Data segment length will be zero */
1403 ucd_req_ptr
->header
.dword_2
= 0;
1405 ucd_req_ptr
->sc
.exp_data_transfer_len
= cpu_to_be32(pccb
->datalen
);
1407 cdb_len
= min_t(unsigned short, pccb
->cmdlen
, UFS_CDB_SIZE
);
1408 memset(ucd_req_ptr
->sc
.cdb
, 0, UFS_CDB_SIZE
);
1409 memcpy(ucd_req_ptr
->sc
.cdb
, pccb
->cmd
, cdb_len
);
1411 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
1414 static inline void prepare_prdt_desc(struct ufshcd_sg_entry
*entry
,
1415 unsigned char *buf
, ulong len
)
1417 entry
->size
= cpu_to_le32(len
) | GENMASK(1, 0);
1418 entry
->base_addr
= cpu_to_le32(lower_32_bits((unsigned long)buf
));
1419 entry
->upper_addr
= cpu_to_le32(upper_32_bits((unsigned long)buf
));
1422 static void prepare_prdt_table(struct ufs_hba
*hba
, struct scsi_cmd
*pccb
)
1424 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
1425 struct ufshcd_sg_entry
*prd_table
= hba
->ucd_prdt_ptr
;
1426 ulong datalen
= pccb
->datalen
;
1432 req_desc
->prd_table_length
= 0;
1436 table_length
= DIV_ROUND_UP(pccb
->datalen
, MAX_PRDT_ENTRY
);
1440 prepare_prdt_desc(&prd_table
[table_length
- i
- 1], buf
,
1441 MAX_PRDT_ENTRY
- 1);
1442 buf
+= MAX_PRDT_ENTRY
;
1443 datalen
-= MAX_PRDT_ENTRY
;
1446 prepare_prdt_desc(&prd_table
[table_length
- i
- 1], buf
, datalen
- 1);
1448 req_desc
->prd_table_length
= table_length
;
1451 static int ufs_scsi_exec(struct udevice
*scsi_dev
, struct scsi_cmd
*pccb
)
1453 struct ufs_hba
*hba
= dev_get_uclass_priv(scsi_dev
->parent
);
1455 int ocs
, result
= 0;
1458 ufshcd_prepare_req_desc_hdr(hba
, &upiu_flags
, pccb
->dma_dir
);
1459 ufshcd_prepare_utp_scsi_cmd_upiu(hba
, pccb
, upiu_flags
);
1460 prepare_prdt_table(hba
, pccb
);
1462 ufshcd_send_command(hba
, TASK_TAG
);
1464 ocs
= ufshcd_get_tr_ocs(hba
);
1467 result
= ufshcd_get_req_rsp(hba
->ucd_rsp_ptr
);
1469 case UPIU_TRANSACTION_RESPONSE
:
1470 result
= ufshcd_get_rsp_upiu_result(hba
->ucd_rsp_ptr
);
1472 scsi_status
= result
& MASK_SCSI_STATUS
;
1477 case UPIU_TRANSACTION_REJECT_UPIU
:
1478 /* TODO: handle Reject UPIU Response */
1480 "Reject UPIU not fully implemented\n");
1484 "Unexpected request response code = %x\n",
1490 dev_err(hba
->dev
, "OCS error from controller = %x\n", ocs
);
1497 static inline int ufshcd_read_desc(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1498 int desc_index
, u8
*buf
, u32 size
)
1500 return ufshcd_read_desc_param(hba
, desc_id
, desc_index
, 0, buf
, size
);
1503 static int ufshcd_read_device_desc(struct ufs_hba
*hba
, u8
*buf
, u32 size
)
1505 return ufshcd_read_desc(hba
, QUERY_DESC_IDN_DEVICE
, 0, buf
, size
);
1509 * ufshcd_read_string_desc - read string descriptor
1512 int ufshcd_read_string_desc(struct ufs_hba
*hba
, int desc_index
,
1513 u8
*buf
, u32 size
, bool ascii
)
1517 err
= ufshcd_read_desc(hba
, QUERY_DESC_IDN_STRING
, desc_index
, buf
,
1521 dev_err(hba
->dev
, "%s: reading String Desc failed after %d retries. err = %d\n",
1522 __func__
, QUERY_REQ_RETRIES
, err
);
1533 /* remove header and divide by 2 to move from UTF16 to UTF8 */
1534 ascii_len
= (desc_len
- QUERY_DESC_HDR_SIZE
) / 2 + 1;
1535 if (size
< ascii_len
+ QUERY_DESC_HDR_SIZE
) {
1536 dev_err(hba
->dev
, "%s: buffer allocated size is too small\n",
1542 buff_ascii
= kmalloc(ascii_len
, GFP_KERNEL
);
1549 * the descriptor contains string in UTF16 format
1550 * we need to convert to utf-8 so it can be displayed
1552 utf16_to_utf8(buff_ascii
,
1553 (uint16_t *)&buf
[QUERY_DESC_HDR_SIZE
], ascii_len
);
1555 /* replace non-printable or non-ASCII characters with spaces */
1556 for (i
= 0; i
< ascii_len
; i
++)
1557 ufshcd_remove_non_printable(&buff_ascii
[i
]);
1559 memset(buf
+ QUERY_DESC_HDR_SIZE
, 0,
1560 size
- QUERY_DESC_HDR_SIZE
);
1561 memcpy(buf
+ QUERY_DESC_HDR_SIZE
, buff_ascii
, ascii_len
);
1562 buf
[QUERY_DESC_LENGTH_OFFSET
] = ascii_len
+ QUERY_DESC_HDR_SIZE
;
1569 static int ufs_get_device_desc(struct ufs_hba
*hba
,
1570 struct ufs_dev_desc
*dev_desc
)
1577 buff_len
= max_t(size_t, hba
->desc_size
.dev_desc
,
1578 QUERY_DESC_MAX_SIZE
+ 1);
1579 desc_buf
= kmalloc(buff_len
, GFP_KERNEL
);
1585 err
= ufshcd_read_device_desc(hba
, desc_buf
, hba
->desc_size
.dev_desc
);
1587 dev_err(hba
->dev
, "%s: Failed reading Device Desc. err = %d\n",
1593 * getting vendor (manufacturerID) and Bank Index in big endian
1596 dev_desc
->wmanufacturerid
= desc_buf
[DEVICE_DESC_PARAM_MANF_ID
] << 8 |
1597 desc_buf
[DEVICE_DESC_PARAM_MANF_ID
+ 1];
1599 model_index
= desc_buf
[DEVICE_DESC_PARAM_PRDCT_NAME
];
1601 /* Zero-pad entire buffer for string termination. */
1602 memset(desc_buf
, 0, buff_len
);
1604 err
= ufshcd_read_string_desc(hba
, model_index
, desc_buf
,
1605 QUERY_DESC_MAX_SIZE
, true/*ASCII*/);
1607 dev_err(hba
->dev
, "%s: Failed reading Product Name. err = %d\n",
1612 desc_buf
[QUERY_DESC_MAX_SIZE
] = '\0';
1613 strlcpy(dev_desc
->model
, (char *)(desc_buf
+ QUERY_DESC_HDR_SIZE
),
1614 min_t(u8
, desc_buf
[QUERY_DESC_LENGTH_OFFSET
],
1617 /* Null terminate the model string */
1618 dev_desc
->model
[MAX_MODEL_LEN
] = '\0';
1626 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
1628 static int ufshcd_get_max_pwr_mode(struct ufs_hba
*hba
)
1630 struct ufs_pa_layer_attr
*pwr_info
= &hba
->max_pwr_info
.info
;
1632 if (hba
->max_pwr_info
.is_valid
)
1635 if (hba
->quirks
& UFSHCD_QUIRK_HIBERN_FASTAUTO
) {
1636 pwr_info
->pwr_tx
= FASTAUTO_MODE
;
1637 pwr_info
->pwr_rx
= FASTAUTO_MODE
;
1639 pwr_info
->pwr_tx
= FAST_MODE
;
1640 pwr_info
->pwr_rx
= FAST_MODE
;
1642 pwr_info
->hs_rate
= PA_HS_MODE_B
;
1644 /* Get the connected lane count */
1645 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES
),
1646 &pwr_info
->lane_rx
);
1647 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
1648 &pwr_info
->lane_tx
);
1650 if (!pwr_info
->lane_rx
|| !pwr_info
->lane_tx
) {
1651 dev_err(hba
->dev
, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
1652 __func__
, pwr_info
->lane_rx
, pwr_info
->lane_tx
);
1657 * First, get the maximum gears of HS speed.
1658 * If a zero value, it means there is no HSGEAR capability.
1659 * Then, get the maximum gears of PWM speed.
1661 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_MAXRXHSGEAR
), &pwr_info
->gear_rx
);
1662 if (!pwr_info
->gear_rx
) {
1663 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_MAXRXPWMGEAR
),
1664 &pwr_info
->gear_rx
);
1665 if (!pwr_info
->gear_rx
) {
1666 dev_err(hba
->dev
, "%s: invalid max pwm rx gear read = %d\n",
1667 __func__
, pwr_info
->gear_rx
);
1670 pwr_info
->pwr_rx
= SLOW_MODE
;
1673 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_MAXRXHSGEAR
),
1674 &pwr_info
->gear_tx
);
1675 if (!pwr_info
->gear_tx
) {
1676 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_MAXRXPWMGEAR
),
1677 &pwr_info
->gear_tx
);
1678 if (!pwr_info
->gear_tx
) {
1679 dev_err(hba
->dev
, "%s: invalid max pwm tx gear read = %d\n",
1680 __func__
, pwr_info
->gear_tx
);
1683 pwr_info
->pwr_tx
= SLOW_MODE
;
1686 hba
->max_pwr_info
.is_valid
= true;
1690 static int ufshcd_change_power_mode(struct ufs_hba
*hba
,
1691 struct ufs_pa_layer_attr
*pwr_mode
)
1695 /* if already configured to the requested pwr_mode */
1696 if (pwr_mode
->gear_rx
== hba
->pwr_info
.gear_rx
&&
1697 pwr_mode
->gear_tx
== hba
->pwr_info
.gear_tx
&&
1698 pwr_mode
->lane_rx
== hba
->pwr_info
.lane_rx
&&
1699 pwr_mode
->lane_tx
== hba
->pwr_info
.lane_tx
&&
1700 pwr_mode
->pwr_rx
== hba
->pwr_info
.pwr_rx
&&
1701 pwr_mode
->pwr_tx
== hba
->pwr_info
.pwr_tx
&&
1702 pwr_mode
->hs_rate
== hba
->pwr_info
.hs_rate
) {
1703 dev_dbg(hba
->dev
, "%s: power already configured\n", __func__
);
1708 * Configure attributes for power mode change with below.
1709 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1710 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1713 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXGEAR
), pwr_mode
->gear_rx
);
1714 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_ACTIVERXDATALANES
),
1716 if (pwr_mode
->pwr_rx
== FASTAUTO_MODE
|| pwr_mode
->pwr_rx
== FAST_MODE
)
1717 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXTERMINATION
), TRUE
);
1719 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXTERMINATION
), FALSE
);
1721 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXGEAR
), pwr_mode
->gear_tx
);
1722 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_ACTIVETXDATALANES
),
1724 if (pwr_mode
->pwr_tx
== FASTAUTO_MODE
|| pwr_mode
->pwr_tx
== FAST_MODE
)
1725 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXTERMINATION
), TRUE
);
1727 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXTERMINATION
), FALSE
);
1729 if (pwr_mode
->pwr_rx
== FASTAUTO_MODE
||
1730 pwr_mode
->pwr_tx
== FASTAUTO_MODE
||
1731 pwr_mode
->pwr_rx
== FAST_MODE
||
1732 pwr_mode
->pwr_tx
== FAST_MODE
)
1733 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_HSSERIES
),
1736 ret
= ufshcd_uic_change_pwr_mode(hba
, pwr_mode
->pwr_rx
<< 4 |
1741 "%s: power mode change failed %d\n", __func__
, ret
);
1746 /* Copy new Power Mode to power info */
1747 memcpy(&hba
->pwr_info
, pwr_mode
, sizeof(struct ufs_pa_layer_attr
));
1753 * ufshcd_verify_dev_init() - Verify device initialization
1756 static int ufshcd_verify_dev_init(struct ufs_hba
*hba
)
1761 for (retries
= NOP_OUT_RETRIES
; retries
> 0; retries
--) {
1762 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_NOP
,
1764 if (!err
|| err
== -ETIMEDOUT
)
1767 dev_dbg(hba
->dev
, "%s: error %d retrying\n", __func__
, err
);
1771 dev_err(hba
->dev
, "%s: NOP OUT failed %d\n", __func__
, err
);
1777 * ufshcd_complete_dev_init() - checks device readiness
1779 static int ufshcd_complete_dev_init(struct ufs_hba
*hba
)
1785 err
= ufshcd_query_flag_retry(hba
, UPIU_QUERY_OPCODE_SET_FLAG
,
1786 QUERY_FLAG_IDN_FDEVICEINIT
, NULL
);
1789 "%s setting fDeviceInit flag failed with error %d\n",
1794 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
1795 for (i
= 0; i
< 1000 && !err
&& flag_res
; i
++)
1796 err
= ufshcd_query_flag_retry(hba
, UPIU_QUERY_OPCODE_READ_FLAG
,
1797 QUERY_FLAG_IDN_FDEVICEINIT
,
1802 "%s reading fDeviceInit flag failed with error %d\n",
1806 "%s fDeviceInit was not cleared by the device\n",
1813 static void ufshcd_def_desc_sizes(struct ufs_hba
*hba
)
1815 hba
->desc_size
.dev_desc
= QUERY_DESC_DEVICE_DEF_SIZE
;
1816 hba
->desc_size
.pwr_desc
= QUERY_DESC_POWER_DEF_SIZE
;
1817 hba
->desc_size
.interc_desc
= QUERY_DESC_INTERCONNECT_DEF_SIZE
;
1818 hba
->desc_size
.conf_desc
= QUERY_DESC_CONFIGURATION_DEF_SIZE
;
1819 hba
->desc_size
.unit_desc
= QUERY_DESC_UNIT_DEF_SIZE
;
1820 hba
->desc_size
.geom_desc
= QUERY_DESC_GEOMETRY_DEF_SIZE
;
1821 hba
->desc_size
.hlth_desc
= QUERY_DESC_HEALTH_DEF_SIZE
;
1824 int ufs_start(struct ufs_hba
*hba
)
1826 struct ufs_dev_desc card
= {0};
1829 ret
= ufshcd_link_startup(hba
);
1833 ret
= ufshcd_verify_dev_init(hba
);
1837 ret
= ufshcd_complete_dev_init(hba
);
1841 /* Init check for device descriptor sizes */
1842 ufshcd_init_desc_sizes(hba
);
1844 ret
= ufs_get_device_desc(hba
, &card
);
1846 dev_err(hba
->dev
, "%s: Failed getting device info. err = %d\n",
1852 if (ufshcd_get_max_pwr_mode(hba
)) {
1854 "%s: Failed getting max supported power mode\n",
1857 ret
= ufshcd_change_power_mode(hba
, &hba
->max_pwr_info
.info
);
1859 dev_err(hba
->dev
, "%s: Failed setting power mode, err = %d\n",
1865 printf("Device at %s up at:", hba
->dev
->name
);
1866 ufshcd_print_pwr_info(hba
);
1872 int ufshcd_probe(struct udevice
*ufs_dev
, struct ufs_hba_ops
*hba_ops
)
1874 struct ufs_hba
*hba
= dev_get_uclass_priv(ufs_dev
);
1875 struct scsi_plat
*scsi_plat
;
1876 struct udevice
*scsi_dev
;
1879 device_find_first_child(ufs_dev
, &scsi_dev
);
1883 scsi_plat
= dev_get_uclass_plat(scsi_dev
);
1884 scsi_plat
->max_id
= UFSHCD_MAX_ID
;
1885 scsi_plat
->max_lun
= UFS_MAX_LUNS
;
1886 scsi_plat
->max_bytes_per_req
= UFS_MAX_BYTES
;
1890 hba
->mmio_base
= dev_read_addr_ptr(ufs_dev
);
1892 /* Set descriptor lengths to specification defaults */
1893 ufshcd_def_desc_sizes(hba
);
1895 ufshcd_ops_init(hba
);
1897 /* Read capabilties registers */
1898 hba
->capabilities
= ufshcd_readl(hba
, REG_CONTROLLER_CAPABILITIES
);
1899 if (hba
->quirks
& UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS
)
1900 hba
->capabilities
&= ~MASK_64_ADDRESSING_SUPPORT
;
1902 /* Get UFS version supported by the controller */
1903 hba
->version
= ufshcd_get_ufs_version(hba
);
1904 if (hba
->version
!= UFSHCI_VERSION_10
&&
1905 hba
->version
!= UFSHCI_VERSION_11
&&
1906 hba
->version
!= UFSHCI_VERSION_20
&&
1907 hba
->version
!= UFSHCI_VERSION_21
&&
1908 hba
->version
!= UFSHCI_VERSION_30
)
1909 dev_err(hba
->dev
, "invalid UFS version 0x%x\n",
1912 /* Get Interrupt bit mask per version */
1913 hba
->intr_mask
= ufshcd_get_intr_mask(hba
);
1915 /* Allocate memory for host memory space */
1916 err
= ufshcd_memory_alloc(hba
);
1918 dev_err(hba
->dev
, "Memory allocation failed\n");
1922 /* Configure Local data structures */
1923 ufshcd_host_memory_configure(hba
);
1926 * In order to avoid any spurious interrupt immediately after
1927 * registering UFS controller interrupt handler, clear any pending UFS
1928 * interrupt status and disable all the UFS interrupts.
1930 ufshcd_writel(hba
, ufshcd_readl(hba
, REG_INTERRUPT_STATUS
),
1931 REG_INTERRUPT_STATUS
);
1932 ufshcd_writel(hba
, 0, REG_INTERRUPT_ENABLE
);
1934 err
= ufshcd_hba_enable(hba
);
1936 dev_err(hba
->dev
, "Host controller enable failed\n");
1940 err
= ufs_start(hba
);
1947 int ufs_scsi_bind(struct udevice
*ufs_dev
, struct udevice
**scsi_devp
)
1949 int ret
= device_bind_driver(ufs_dev
, "ufs_scsi", "ufs_scsi",
1955 #if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
1956 static int ufs_scsi_buffer_aligned(struct udevice
*scsi_dev
, struct bounce_buffer
*state
)
1958 #ifdef CONFIG_PHYS_64BIT
1959 struct ufs_hba
*hba
= dev_get_uclass_priv(scsi_dev
->parent
);
1960 uintptr_t ubuf
= (uintptr_t)state
->user_buffer
;
1961 size_t len
= state
->len_aligned
;
1963 /* Check if below 32bit boundary */
1964 if ((hba
->quirks
& UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS
) &&
1965 ((ubuf
>> 32) || (ubuf
+ len
) >> 32)) {
1966 dev_dbg(scsi_dev
, "Buffer above 32bit boundary %lx-%lx\n",
1973 #endif /* CONFIG_BOUNCE_BUFFER */
1975 static struct scsi_ops ufs_ops
= {
1976 .exec
= ufs_scsi_exec
,
1977 #if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
1978 .buffer_aligned
= ufs_scsi_buffer_aligned
,
1979 #endif /* CONFIG_BOUNCE_BUFFER */
1982 int ufs_probe_dev(int index
)
1984 struct udevice
*dev
;
1986 return uclass_get_device(UCLASS_UFS
, index
, &dev
);
1991 struct udevice
*dev
;
1995 ret
= uclass_get_device(UCLASS_UFS
, i
, &dev
);
2003 U_BOOT_DRIVER(ufs_scsi
) = {