1 // SPDX-License-Identifier: GPL-2.0+
3 * ufs.c - Universal Flash Subsystem (UFS) driver
5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
15 #include <dm/device_compat.h>
16 #include <dm/devres.h>
18 #include <dm/device-internal.h>
22 #include <linux/bitops.h>
23 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
29 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
32 /* maximum number of link-startup retries */
33 #define DME_LINKSTARTUP_RETRIES 3
35 /* maximum number of retries for a general UIC command */
36 #define UFS_UIC_COMMAND_RETRIES 3
38 /* Query request retries */
39 #define QUERY_REQ_RETRIES 3
40 /* Query request timeout */
41 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
43 /* maximum timeout in ms for a general UIC command */
44 #define UFS_UIC_CMD_TIMEOUT 1000
45 /* NOP OUT retries waiting for NOP IN response */
46 #define NOP_OUT_RETRIES 10
47 /* Timeout after 30 msecs if NOP OUT hangs without response */
48 #define NOP_OUT_TIMEOUT 30 /* msecs */
50 /* Only use one Task Tag for all requests */
53 /* Expose the flag value from utp_upiu_query.value */
54 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
56 #define MAX_PRDT_ENTRY 262144
58 /* maximum bytes per request */
59 #define UFS_MAX_BYTES (128 * 256 * 1024)
61 static inline bool ufshcd_is_hba_active(struct ufs_hba
*hba
);
62 static inline void ufshcd_hba_stop(struct ufs_hba
*hba
);
63 static int ufshcd_hba_enable(struct ufs_hba
*hba
);
66 * ufshcd_wait_for_register - wait for register value to change
68 static int ufshcd_wait_for_register(struct ufs_hba
*hba
, u32 reg
, u32 mask
,
69 u32 val
, unsigned long timeout_ms
)
72 unsigned long start
= get_timer(0);
74 /* ignore bits that we don't intend to wait on */
77 while ((ufshcd_readl(hba
, reg
) & mask
) != val
) {
78 if (get_timer(start
) > timeout_ms
) {
79 if ((ufshcd_readl(hba
, reg
) & mask
) != val
)
89 * ufshcd_init_pwr_info - setting the POR (power on reset)
90 * values in hba power info
92 static void ufshcd_init_pwr_info(struct ufs_hba
*hba
)
94 hba
->pwr_info
.gear_rx
= UFS_PWM_G1
;
95 hba
->pwr_info
.gear_tx
= UFS_PWM_G1
;
96 hba
->pwr_info
.lane_rx
= 1;
97 hba
->pwr_info
.lane_tx
= 1;
98 hba
->pwr_info
.pwr_rx
= SLOWAUTO_MODE
;
99 hba
->pwr_info
.pwr_tx
= SLOWAUTO_MODE
;
100 hba
->pwr_info
.hs_rate
= 0;
104 * ufshcd_print_pwr_info - print power params as saved in hba
107 static void ufshcd_print_pwr_info(struct ufs_hba
*hba
)
109 static const char * const names
[] = {
119 dev_err(hba
->dev
, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
120 hba
->pwr_info
.gear_rx
, hba
->pwr_info
.gear_tx
,
121 hba
->pwr_info
.lane_rx
, hba
->pwr_info
.lane_tx
,
122 names
[hba
->pwr_info
.pwr_rx
],
123 names
[hba
->pwr_info
.pwr_tx
],
124 hba
->pwr_info
.hs_rate
);
128 * ufshcd_ready_for_uic_cmd - Check if controller is ready
129 * to accept UIC commands
131 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba
*hba
)
133 if (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) & UIC_COMMAND_READY
)
140 * ufshcd_get_uic_cmd_result - Get the UIC command result
142 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba
*hba
)
144 return ufshcd_readl(hba
, REG_UIC_COMMAND_ARG_2
) &
145 MASK_UIC_COMMAND_RESULT
;
149 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
151 static inline u32
ufshcd_get_dme_attr_val(struct ufs_hba
*hba
)
153 return ufshcd_readl(hba
, REG_UIC_COMMAND_ARG_3
);
157 * ufshcd_is_device_present - Check if any device connected to
158 * the host controller
160 static inline bool ufshcd_is_device_present(struct ufs_hba
*hba
)
162 return (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) &
163 DEVICE_PRESENT
) ? true : false;
167 * ufshcd_send_uic_cmd - UFS Interconnect layer command API
170 static int ufshcd_send_uic_cmd(struct ufs_hba
*hba
, struct uic_command
*uic_cmd
)
172 unsigned long start
= 0;
174 u32 enabled_intr_status
;
176 if (!ufshcd_ready_for_uic_cmd(hba
)) {
178 "Controller not ready to accept UIC commands\n");
182 debug("sending uic command:%d\n", uic_cmd
->command
);
185 ufshcd_writel(hba
, uic_cmd
->argument1
, REG_UIC_COMMAND_ARG_1
);
186 ufshcd_writel(hba
, uic_cmd
->argument2
, REG_UIC_COMMAND_ARG_2
);
187 ufshcd_writel(hba
, uic_cmd
->argument3
, REG_UIC_COMMAND_ARG_3
);
190 ufshcd_writel(hba
, uic_cmd
->command
& COMMAND_OPCODE_MASK
,
193 start
= get_timer(0);
195 intr_status
= ufshcd_readl(hba
, REG_INTERRUPT_STATUS
);
196 enabled_intr_status
= intr_status
& hba
->intr_mask
;
197 ufshcd_writel(hba
, intr_status
, REG_INTERRUPT_STATUS
);
199 if (get_timer(start
) > UFS_UIC_CMD_TIMEOUT
) {
201 "Timedout waiting for UIC response\n");
206 if (enabled_intr_status
& UFSHCD_ERROR_MASK
) {
207 dev_err(hba
->dev
, "Error in status:%08x\n",
208 enabled_intr_status
);
212 } while (!(enabled_intr_status
& UFSHCD_UIC_MASK
));
214 uic_cmd
->argument2
= ufshcd_get_uic_cmd_result(hba
);
215 uic_cmd
->argument3
= ufshcd_get_dme_attr_val(hba
);
217 debug("Sent successfully\n");
223 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
226 int ufshcd_dme_set_attr(struct ufs_hba
*hba
, u32 attr_sel
, u8 attr_set
,
227 u32 mib_val
, u8 peer
)
229 struct uic_command uic_cmd
= {0};
230 static const char *const action
[] = {
234 const char *set
= action
[!!peer
];
236 int retries
= UFS_UIC_COMMAND_RETRIES
;
238 uic_cmd
.command
= peer
?
239 UIC_CMD_DME_PEER_SET
: UIC_CMD_DME_SET
;
240 uic_cmd
.argument1
= attr_sel
;
241 uic_cmd
.argument2
= UIC_ARG_ATTR_TYPE(attr_set
);
242 uic_cmd
.argument3
= mib_val
;
245 /* for peer attributes we retry upon failure */
246 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
248 dev_dbg(hba
->dev
, "%s: attr-id 0x%x val 0x%x error code %d\n",
249 set
, UIC_GET_ATTR_ID(attr_sel
), mib_val
, ret
);
250 } while (ret
&& peer
&& --retries
);
253 dev_err(hba
->dev
, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
254 set
, UIC_GET_ATTR_ID(attr_sel
), mib_val
,
255 UFS_UIC_COMMAND_RETRIES
- retries
);
261 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
264 int ufshcd_dme_get_attr(struct ufs_hba
*hba
, u32 attr_sel
,
265 u32
*mib_val
, u8 peer
)
267 struct uic_command uic_cmd
= {0};
268 static const char *const action
[] = {
272 const char *get
= action
[!!peer
];
274 int retries
= UFS_UIC_COMMAND_RETRIES
;
276 uic_cmd
.command
= peer
?
277 UIC_CMD_DME_PEER_GET
: UIC_CMD_DME_GET
;
278 uic_cmd
.argument1
= attr_sel
;
281 /* for peer attributes we retry upon failure */
282 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
284 dev_dbg(hba
->dev
, "%s: attr-id 0x%x error code %d\n",
285 get
, UIC_GET_ATTR_ID(attr_sel
), ret
);
286 } while (ret
&& peer
&& --retries
);
289 dev_err(hba
->dev
, "%s: attr-id 0x%x failed %d retries\n",
290 get
, UIC_GET_ATTR_ID(attr_sel
),
291 UFS_UIC_COMMAND_RETRIES
- retries
);
294 *mib_val
= uic_cmd
.argument3
;
299 static int ufshcd_disable_tx_lcc(struct ufs_hba
*hba
, bool peer
)
301 u32 tx_lanes
, i
, err
= 0;
304 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
307 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
309 for (i
= 0; i
< tx_lanes
; i
++) {
311 err
= ufshcd_dme_set(hba
,
312 UIC_ARG_MIB_SEL(TX_LCC_ENABLE
,
313 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i
)),
316 err
= ufshcd_dme_peer_set(hba
,
317 UIC_ARG_MIB_SEL(TX_LCC_ENABLE
,
318 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i
)),
321 dev_err(hba
->dev
, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
322 __func__
, peer
, i
, err
);
330 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba
*hba
)
332 return ufshcd_disable_tx_lcc(hba
, true);
336 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
339 static int ufshcd_dme_link_startup(struct ufs_hba
*hba
)
341 struct uic_command uic_cmd
= {0};
344 uic_cmd
.command
= UIC_CMD_DME_LINK_STARTUP
;
346 ret
= ufshcd_send_uic_cmd(hba
, &uic_cmd
);
349 "dme-link-startup: error code %d\n", ret
);
354 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
357 static inline void ufshcd_disable_intr_aggr(struct ufs_hba
*hba
)
359 ufshcd_writel(hba
, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL
);
363 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
365 static inline int ufshcd_get_lists_status(u32 reg
)
367 return !((reg
& UFSHCD_STATUS_READY
) == UFSHCD_STATUS_READY
);
371 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
372 * When run-stop registers are set to 1, it indicates the
373 * host controller that it can process the requests
375 static void ufshcd_enable_run_stop_reg(struct ufs_hba
*hba
)
377 ufshcd_writel(hba
, UTP_TASK_REQ_LIST_RUN_STOP_BIT
,
378 REG_UTP_TASK_REQ_LIST_RUN_STOP
);
379 ufshcd_writel(hba
, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT
,
380 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP
);
384 * ufshcd_enable_intr - enable interrupts
386 static void ufshcd_enable_intr(struct ufs_hba
*hba
, u32 intrs
)
388 u32 set
= ufshcd_readl(hba
, REG_INTERRUPT_ENABLE
);
391 if (hba
->version
== UFSHCI_VERSION_10
) {
392 rw
= set
& INTERRUPT_MASK_RW_VER_10
;
393 set
= rw
| ((set
^ intrs
) & intrs
);
398 ufshcd_writel(hba
, set
, REG_INTERRUPT_ENABLE
);
400 hba
->intr_mask
= set
;
404 * ufshcd_make_hba_operational - Make UFS controller operational
406 * To bring UFS host controller to operational state,
407 * 1. Enable required interrupts
408 * 2. Configure interrupt aggregation
409 * 3. Program UTRL and UTMRL base address
410 * 4. Configure run-stop-registers
413 static int ufshcd_make_hba_operational(struct ufs_hba
*hba
)
418 /* Enable required interrupts */
419 ufshcd_enable_intr(hba
, UFSHCD_ENABLE_INTRS
);
421 /* Disable interrupt aggregation */
422 ufshcd_disable_intr_aggr(hba
);
424 /* Configure UTRL and UTMRL base address registers */
425 ufshcd_writel(hba
, lower_32_bits((dma_addr_t
)hba
->utrdl
),
426 REG_UTP_TRANSFER_REQ_LIST_BASE_L
);
427 ufshcd_writel(hba
, upper_32_bits((dma_addr_t
)hba
->utrdl
),
428 REG_UTP_TRANSFER_REQ_LIST_BASE_H
);
429 ufshcd_writel(hba
, lower_32_bits((dma_addr_t
)hba
->utmrdl
),
430 REG_UTP_TASK_REQ_LIST_BASE_L
);
431 ufshcd_writel(hba
, upper_32_bits((dma_addr_t
)hba
->utmrdl
),
432 REG_UTP_TASK_REQ_LIST_BASE_H
);
435 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
437 reg
= ufshcd_readl(hba
, REG_CONTROLLER_STATUS
);
438 if (!(ufshcd_get_lists_status(reg
))) {
439 ufshcd_enable_run_stop_reg(hba
);
442 "Host controller not ready to process requests");
452 * ufshcd_link_startup - Initialize unipro link startup
454 static int ufshcd_link_startup(struct ufs_hba
*hba
)
457 int retries
= DME_LINKSTARTUP_RETRIES
;
458 bool link_startup_again
= true;
462 ufshcd_ops_link_startup_notify(hba
, PRE_CHANGE
);
464 ret
= ufshcd_dme_link_startup(hba
);
466 /* check if device is detected by inter-connect layer */
467 if (!ret
&& !ufshcd_is_device_present(hba
)) {
468 dev_err(hba
->dev
, "%s: Device not present\n", __func__
);
474 * DME link lost indication is only received when link is up,
475 * but we can't be sure if the link is up until link startup
476 * succeeds. So reset the local Uni-Pro and try again.
478 if (ret
&& ufshcd_hba_enable(hba
))
480 } while (ret
&& retries
--);
483 /* failed to get the link up... retire */
486 if (link_startup_again
) {
487 link_startup_again
= false;
488 retries
= DME_LINKSTARTUP_RETRIES
;
492 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
493 ufshcd_init_pwr_info(hba
);
495 if (hba
->quirks
& UFSHCD_QUIRK_BROKEN_LCC
) {
496 ret
= ufshcd_disable_device_tx_lcc(hba
);
501 /* Include any host controller configuration via UIC commands */
502 ret
= ufshcd_ops_link_startup_notify(hba
, POST_CHANGE
);
506 ret
= ufshcd_make_hba_operational(hba
);
509 dev_err(hba
->dev
, "link startup failed %d\n", ret
);
515 * ufshcd_hba_stop - Send controller to reset state
517 static inline void ufshcd_hba_stop(struct ufs_hba
*hba
)
521 ufshcd_writel(hba
, CONTROLLER_DISABLE
, REG_CONTROLLER_ENABLE
);
522 err
= ufshcd_wait_for_register(hba
, REG_CONTROLLER_ENABLE
,
523 CONTROLLER_ENABLE
, CONTROLLER_DISABLE
,
526 dev_err(hba
->dev
, "%s: Controller disable failed\n", __func__
);
530 * ufshcd_is_hba_active - Get controller state
532 static inline bool ufshcd_is_hba_active(struct ufs_hba
*hba
)
534 return (ufshcd_readl(hba
, REG_CONTROLLER_ENABLE
) & CONTROLLER_ENABLE
)
539 * ufshcd_hba_start - Start controller initialization sequence
541 static inline void ufshcd_hba_start(struct ufs_hba
*hba
)
543 ufshcd_writel(hba
, CONTROLLER_ENABLE
, REG_CONTROLLER_ENABLE
);
547 * ufshcd_hba_enable - initialize the controller
549 static int ufshcd_hba_enable(struct ufs_hba
*hba
)
553 if (!ufshcd_is_hba_active(hba
))
554 /* change controller state to "reset state" */
555 ufshcd_hba_stop(hba
);
557 ufshcd_ops_hce_enable_notify(hba
, PRE_CHANGE
);
559 /* start controller initialization sequence */
560 ufshcd_hba_start(hba
);
563 * To initialize a UFS host controller HCE bit must be set to 1.
564 * During initialization the HCE bit value changes from 1->0->1.
565 * When the host controller completes initialization sequence
566 * it sets the value of HCE bit to 1. The same HCE bit is read back
567 * to check if the controller has completed initialization sequence.
568 * So without this delay the value HCE = 1, set in the previous
569 * instruction might be read back.
570 * This delay can be changed based on the controller.
574 /* wait for the host controller to complete initialization */
576 while (ufshcd_is_hba_active(hba
)) {
580 dev_err(hba
->dev
, "Controller enable failed\n");
586 /* enable UIC related interrupts */
587 ufshcd_enable_intr(hba
, UFSHCD_UIC_MASK
);
589 ufshcd_ops_hce_enable_notify(hba
, POST_CHANGE
);
595 * ufshcd_host_memory_configure - configure local reference block with
598 static void ufshcd_host_memory_configure(struct ufs_hba
*hba
)
600 struct utp_transfer_req_desc
*utrdlp
;
601 dma_addr_t cmd_desc_dma_addr
;
606 cmd_desc_dma_addr
= (dma_addr_t
)hba
->ucdl
;
608 utrdlp
->command_desc_base_addr_lo
=
609 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr
));
610 utrdlp
->command_desc_base_addr_hi
=
611 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr
));
613 response_offset
= offsetof(struct utp_transfer_cmd_desc
, response_upiu
);
614 prdt_offset
= offsetof(struct utp_transfer_cmd_desc
, prd_table
);
616 utrdlp
->response_upiu_offset
= cpu_to_le16(response_offset
>> 2);
617 utrdlp
->prd_table_offset
= cpu_to_le16(prdt_offset
>> 2);
618 utrdlp
->response_upiu_length
= cpu_to_le16(ALIGNED_UPIU_SIZE
>> 2);
620 hba
->ucd_req_ptr
= (struct utp_upiu_req
*)hba
->ucdl
;
622 (struct utp_upiu_rsp
*)&hba
->ucdl
->response_upiu
;
624 (struct ufshcd_sg_entry
*)&hba
->ucdl
->prd_table
;
628 * ufshcd_memory_alloc - allocate memory for host memory space data structures
630 static int ufshcd_memory_alloc(struct ufs_hba
*hba
)
632 /* Allocate one Transfer Request Descriptor
633 * Should be aligned to 1k boundary.
635 hba
->utrdl
= memalign(1024, sizeof(struct utp_transfer_req_desc
));
637 dev_err(hba
->dev
, "Transfer Descriptor memory allocation failed\n");
641 /* Allocate one Command Descriptor
642 * Should be aligned to 1k boundary.
644 hba
->ucdl
= memalign(1024, sizeof(struct utp_transfer_cmd_desc
));
646 dev_err(hba
->dev
, "Command descriptor memory allocation failed\n");
654 * ufshcd_get_intr_mask - Get the interrupt bit mask
656 static inline u32
ufshcd_get_intr_mask(struct ufs_hba
*hba
)
660 switch (hba
->version
) {
661 case UFSHCI_VERSION_10
:
662 intr_mask
= INTERRUPT_MASK_ALL_VER_10
;
664 case UFSHCI_VERSION_11
:
665 case UFSHCI_VERSION_20
:
666 intr_mask
= INTERRUPT_MASK_ALL_VER_11
;
668 case UFSHCI_VERSION_21
:
670 intr_mask
= INTERRUPT_MASK_ALL_VER_21
;
678 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
680 static inline u32
ufshcd_get_ufs_version(struct ufs_hba
*hba
)
682 return ufshcd_readl(hba
, REG_UFS_VERSION
);
686 * ufshcd_get_upmcrs - Get the power mode change request status
688 static inline u8
ufshcd_get_upmcrs(struct ufs_hba
*hba
)
690 return (ufshcd_readl(hba
, REG_CONTROLLER_STATUS
) >> 8) & 0x7;
694 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
695 * descriptor according to request
697 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc
*req_desc
,
699 enum dma_data_direction cmd_dir
)
704 if (cmd_dir
== DMA_FROM_DEVICE
) {
705 data_direction
= UTP_DEVICE_TO_HOST
;
706 *upiu_flags
= UPIU_CMD_FLAGS_READ
;
707 } else if (cmd_dir
== DMA_TO_DEVICE
) {
708 data_direction
= UTP_HOST_TO_DEVICE
;
709 *upiu_flags
= UPIU_CMD_FLAGS_WRITE
;
711 data_direction
= UTP_NO_DATA_TRANSFER
;
712 *upiu_flags
= UPIU_CMD_FLAGS_NONE
;
715 dword_0
= data_direction
| (0x1 << UPIU_COMMAND_TYPE_OFFSET
);
717 /* Enable Interrupt for command */
718 dword_0
|= UTP_REQ_DESC_INT_CMD
;
720 /* Transfer request descriptor header fields */
721 req_desc
->header
.dword_0
= cpu_to_le32(dword_0
);
722 /* dword_1 is reserved, hence it is set to 0 */
723 req_desc
->header
.dword_1
= 0;
725 * assigning invalid value for command status. Controller
726 * updates OCS on command completion, with the command
729 req_desc
->header
.dword_2
=
730 cpu_to_le32(OCS_INVALID_COMMAND_STATUS
);
731 /* dword_3 is reserved, hence it is set to 0 */
732 req_desc
->header
.dword_3
= 0;
734 req_desc
->prd_table_length
= 0;
737 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba
*hba
,
740 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
741 struct ufs_query
*query
= &hba
->dev_cmd
.query
;
742 u16 len
= be16_to_cpu(query
->request
.upiu_req
.length
);
744 /* Query request header */
745 ucd_req_ptr
->header
.dword_0
=
746 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ
,
747 upiu_flags
, 0, TASK_TAG
);
748 ucd_req_ptr
->header
.dword_1
=
749 UPIU_HEADER_DWORD(0, query
->request
.query_func
,
752 /* Data segment length only need for WRITE_DESC */
753 if (query
->request
.upiu_req
.opcode
== UPIU_QUERY_OPCODE_WRITE_DESC
)
754 ucd_req_ptr
->header
.dword_2
=
755 UPIU_HEADER_DWORD(0, 0, (len
>> 8), (u8
)len
);
757 ucd_req_ptr
->header
.dword_2
= 0;
759 /* Copy the Query Request buffer as is */
760 memcpy(&ucd_req_ptr
->qr
, &query
->request
.upiu_req
, QUERY_OSF_SIZE
);
762 /* Copy the Descriptor */
763 if (query
->request
.upiu_req
.opcode
== UPIU_QUERY_OPCODE_WRITE_DESC
)
764 memcpy(ucd_req_ptr
+ 1, query
->descriptor
, len
);
766 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
769 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba
*hba
)
771 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
773 memset(ucd_req_ptr
, 0, sizeof(struct utp_upiu_req
));
775 /* command descriptor fields */
776 ucd_req_ptr
->header
.dword_0
=
777 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT
, 0, 0, 0x1f);
778 /* clear rest of the fields of basic header */
779 ucd_req_ptr
->header
.dword_1
= 0;
780 ucd_req_ptr
->header
.dword_2
= 0;
782 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
786 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
787 * for Device Management Purposes
789 static int ufshcd_comp_devman_upiu(struct ufs_hba
*hba
,
790 enum dev_cmd_type cmd_type
)
794 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
796 hba
->dev_cmd
.type
= cmd_type
;
798 ufshcd_prepare_req_desc_hdr(req_desc
, &upiu_flags
, DMA_NONE
);
800 case DEV_CMD_TYPE_QUERY
:
801 ufshcd_prepare_utp_query_req_upiu(hba
, upiu_flags
);
803 case DEV_CMD_TYPE_NOP
:
804 ufshcd_prepare_utp_nop_upiu(hba
);
813 static int ufshcd_send_command(struct ufs_hba
*hba
, unsigned int task_tag
)
817 u32 enabled_intr_status
;
819 ufshcd_writel(hba
, 1 << task_tag
, REG_UTP_TRANSFER_REQ_DOOR_BELL
);
821 start
= get_timer(0);
823 intr_status
= ufshcd_readl(hba
, REG_INTERRUPT_STATUS
);
824 enabled_intr_status
= intr_status
& hba
->intr_mask
;
825 ufshcd_writel(hba
, intr_status
, REG_INTERRUPT_STATUS
);
827 if (get_timer(start
) > QUERY_REQ_TIMEOUT
) {
829 "Timedout waiting for UTP response\n");
834 if (enabled_intr_status
& UFSHCD_ERROR_MASK
) {
835 dev_err(hba
->dev
, "Error in status:%08x\n",
836 enabled_intr_status
);
840 } while (!(enabled_intr_status
& UTP_TRANSFER_REQ_COMPL
));
846 * ufshcd_get_req_rsp - returns the TR response transaction type
848 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp
*ucd_rsp_ptr
)
850 return be32_to_cpu(ucd_rsp_ptr
->header
.dword_0
) >> 24;
854 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
857 static inline int ufshcd_get_tr_ocs(struct ufs_hba
*hba
)
859 return le32_to_cpu(hba
->utrdl
->header
.dword_2
) & MASK_OCS
;
862 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp
*ucd_rsp_ptr
)
864 return be32_to_cpu(ucd_rsp_ptr
->header
.dword_1
) & MASK_RSP_UPIU_RESULT
;
867 static int ufshcd_check_query_response(struct ufs_hba
*hba
)
869 struct ufs_query_res
*query_res
= &hba
->dev_cmd
.query
.response
;
871 /* Get the UPIU response */
872 query_res
->response
= ufshcd_get_rsp_upiu_result(hba
->ucd_rsp_ptr
) >>
873 UPIU_RSP_CODE_OFFSET
;
874 return query_res
->response
;
878 * ufshcd_copy_query_response() - Copy the Query Response and the data
881 static int ufshcd_copy_query_response(struct ufs_hba
*hba
)
883 struct ufs_query_res
*query_res
= &hba
->dev_cmd
.query
.response
;
885 memcpy(&query_res
->upiu_res
, &hba
->ucd_rsp_ptr
->qr
, QUERY_OSF_SIZE
);
887 /* Get the descriptor */
888 if (hba
->dev_cmd
.query
.descriptor
&&
889 hba
->ucd_rsp_ptr
->qr
.opcode
== UPIU_QUERY_OPCODE_READ_DESC
) {
890 u8
*descp
= (u8
*)hba
->ucd_rsp_ptr
+
891 GENERAL_UPIU_REQUEST_SIZE
;
895 /* data segment length */
896 resp_len
= be32_to_cpu(hba
->ucd_rsp_ptr
->header
.dword_2
) &
897 MASK_QUERY_DATA_SEG_LEN
;
899 be16_to_cpu(hba
->dev_cmd
.query
.request
.upiu_req
.length
);
900 if (likely(buf_len
>= resp_len
)) {
901 memcpy(hba
->dev_cmd
.query
.descriptor
, descp
, resp_len
);
904 "%s: Response size is bigger than buffer",
914 * ufshcd_exec_dev_cmd - API for sending device management requests
916 static int ufshcd_exec_dev_cmd(struct ufs_hba
*hba
, enum dev_cmd_type cmd_type
,
922 err
= ufshcd_comp_devman_upiu(hba
, cmd_type
);
926 err
= ufshcd_send_command(hba
, TASK_TAG
);
930 err
= ufshcd_get_tr_ocs(hba
);
932 dev_err(hba
->dev
, "Error in OCS:%d\n", err
);
936 resp
= ufshcd_get_req_rsp(hba
->ucd_rsp_ptr
);
938 case UPIU_TRANSACTION_NOP_IN
:
940 case UPIU_TRANSACTION_QUERY_RSP
:
941 err
= ufshcd_check_query_response(hba
);
943 err
= ufshcd_copy_query_response(hba
);
945 case UPIU_TRANSACTION_REJECT_UPIU
:
946 /* TODO: handle Reject UPIU Response */
948 dev_err(hba
->dev
, "%s: Reject UPIU not fully implemented\n",
953 dev_err(hba
->dev
, "%s: Invalid device management cmd response: %x\n",
961 * ufshcd_init_query() - init the query response and request parameters
963 static inline void ufshcd_init_query(struct ufs_hba
*hba
,
964 struct ufs_query_req
**request
,
965 struct ufs_query_res
**response
,
966 enum query_opcode opcode
,
967 u8 idn
, u8 index
, u8 selector
)
969 *request
= &hba
->dev_cmd
.query
.request
;
970 *response
= &hba
->dev_cmd
.query
.response
;
971 memset(*request
, 0, sizeof(struct ufs_query_req
));
972 memset(*response
, 0, sizeof(struct ufs_query_res
));
973 (*request
)->upiu_req
.opcode
= opcode
;
974 (*request
)->upiu_req
.idn
= idn
;
975 (*request
)->upiu_req
.index
= index
;
976 (*request
)->upiu_req
.selector
= selector
;
980 * ufshcd_query_flag() - API function for sending flag query requests
982 int ufshcd_query_flag(struct ufs_hba
*hba
, enum query_opcode opcode
,
983 enum flag_idn idn
, bool *flag_res
)
985 struct ufs_query_req
*request
= NULL
;
986 struct ufs_query_res
*response
= NULL
;
987 int err
, index
= 0, selector
= 0;
988 int timeout
= QUERY_REQ_TIMEOUT
;
990 ufshcd_init_query(hba
, &request
, &response
, opcode
, idn
, index
,
994 case UPIU_QUERY_OPCODE_SET_FLAG
:
995 case UPIU_QUERY_OPCODE_CLEAR_FLAG
:
996 case UPIU_QUERY_OPCODE_TOGGLE_FLAG
:
997 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST
;
999 case UPIU_QUERY_OPCODE_READ_FLAG
:
1000 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_READ_REQUEST
;
1002 /* No dummy reads */
1003 dev_err(hba
->dev
, "%s: Invalid argument for read request\n",
1011 "%s: Expected query flag opcode but got = %d\n",
1017 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_QUERY
, timeout
);
1021 "%s: Sending flag query for idn %d failed, err = %d\n",
1022 __func__
, idn
, err
);
1027 *flag_res
= (be32_to_cpu(response
->upiu_res
.value
) &
1028 MASK_QUERY_UPIU_FLAG_LOC
) & 0x1;
1034 static int ufshcd_query_flag_retry(struct ufs_hba
*hba
,
1035 enum query_opcode opcode
,
1036 enum flag_idn idn
, bool *flag_res
)
1041 for (retries
= 0; retries
< QUERY_REQ_RETRIES
; retries
++) {
1042 ret
= ufshcd_query_flag(hba
, opcode
, idn
, flag_res
);
1045 "%s: failed with error %d, retries %d\n",
1046 __func__
, ret
, retries
);
1053 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1054 __func__
, opcode
, idn
, ret
, retries
);
1058 static int __ufshcd_query_descriptor(struct ufs_hba
*hba
,
1059 enum query_opcode opcode
,
1060 enum desc_idn idn
, u8 index
, u8 selector
,
1061 u8
*desc_buf
, int *buf_len
)
1063 struct ufs_query_req
*request
= NULL
;
1064 struct ufs_query_res
*response
= NULL
;
1068 dev_err(hba
->dev
, "%s: descriptor buffer required for opcode 0x%x\n",
1074 if (*buf_len
< QUERY_DESC_MIN_SIZE
|| *buf_len
> QUERY_DESC_MAX_SIZE
) {
1075 dev_err(hba
->dev
, "%s: descriptor buffer size (%d) is out of range\n",
1076 __func__
, *buf_len
);
1081 ufshcd_init_query(hba
, &request
, &response
, opcode
, idn
, index
,
1083 hba
->dev_cmd
.query
.descriptor
= desc_buf
;
1084 request
->upiu_req
.length
= cpu_to_be16(*buf_len
);
1087 case UPIU_QUERY_OPCODE_WRITE_DESC
:
1088 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST
;
1090 case UPIU_QUERY_OPCODE_READ_DESC
:
1091 request
->query_func
= UPIU_QUERY_FUNC_STANDARD_READ_REQUEST
;
1094 dev_err(hba
->dev
, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1100 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_QUERY
, QUERY_REQ_TIMEOUT
);
1103 dev_err(hba
->dev
, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1104 __func__
, opcode
, idn
, index
, err
);
1108 hba
->dev_cmd
.query
.descriptor
= NULL
;
1109 *buf_len
= be16_to_cpu(response
->upiu_res
.length
);
1116 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
1118 int ufshcd_query_descriptor_retry(struct ufs_hba
*hba
, enum query_opcode opcode
,
1119 enum desc_idn idn
, u8 index
, u8 selector
,
1120 u8
*desc_buf
, int *buf_len
)
1125 for (retries
= QUERY_REQ_RETRIES
; retries
> 0; retries
--) {
1126 err
= __ufshcd_query_descriptor(hba
, opcode
, idn
, index
,
1127 selector
, desc_buf
, buf_len
);
1128 if (!err
|| err
== -EINVAL
)
1136 * ufshcd_read_desc_length - read the specified descriptor length from header
1138 static int ufshcd_read_desc_length(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1139 int desc_index
, int *desc_length
)
1142 u8 header
[QUERY_DESC_HDR_SIZE
];
1143 int header_len
= QUERY_DESC_HDR_SIZE
;
1145 if (desc_id
>= QUERY_DESC_IDN_MAX
)
1148 ret
= ufshcd_query_descriptor_retry(hba
, UPIU_QUERY_OPCODE_READ_DESC
,
1149 desc_id
, desc_index
, 0, header
,
1153 dev_err(hba
->dev
, "%s: Failed to get descriptor header id %d",
1156 } else if (desc_id
!= header
[QUERY_DESC_DESC_TYPE_OFFSET
]) {
1157 dev_warn(hba
->dev
, "%s: descriptor header id %d and desc_id %d mismatch",
1158 __func__
, header
[QUERY_DESC_DESC_TYPE_OFFSET
],
1163 *desc_length
= header
[QUERY_DESC_LENGTH_OFFSET
];
1168 static void ufshcd_init_desc_sizes(struct ufs_hba
*hba
)
1172 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_DEVICE
, 0,
1173 &hba
->desc_size
.dev_desc
);
1175 hba
->desc_size
.dev_desc
= QUERY_DESC_DEVICE_DEF_SIZE
;
1177 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_POWER
, 0,
1178 &hba
->desc_size
.pwr_desc
);
1180 hba
->desc_size
.pwr_desc
= QUERY_DESC_POWER_DEF_SIZE
;
1182 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_INTERCONNECT
, 0,
1183 &hba
->desc_size
.interc_desc
);
1185 hba
->desc_size
.interc_desc
= QUERY_DESC_INTERCONNECT_DEF_SIZE
;
1187 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_CONFIGURATION
, 0,
1188 &hba
->desc_size
.conf_desc
);
1190 hba
->desc_size
.conf_desc
= QUERY_DESC_CONFIGURATION_DEF_SIZE
;
1192 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_UNIT
, 0,
1193 &hba
->desc_size
.unit_desc
);
1195 hba
->desc_size
.unit_desc
= QUERY_DESC_UNIT_DEF_SIZE
;
1197 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_GEOMETRY
, 0,
1198 &hba
->desc_size
.geom_desc
);
1200 hba
->desc_size
.geom_desc
= QUERY_DESC_GEOMETRY_DEF_SIZE
;
1202 err
= ufshcd_read_desc_length(hba
, QUERY_DESC_IDN_HEALTH
, 0,
1203 &hba
->desc_size
.hlth_desc
);
1205 hba
->desc_size
.hlth_desc
= QUERY_DESC_HEALTH_DEF_SIZE
;
1209 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
1212 int ufshcd_map_desc_id_to_length(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1216 case QUERY_DESC_IDN_DEVICE
:
1217 *desc_len
= hba
->desc_size
.dev_desc
;
1219 case QUERY_DESC_IDN_POWER
:
1220 *desc_len
= hba
->desc_size
.pwr_desc
;
1222 case QUERY_DESC_IDN_GEOMETRY
:
1223 *desc_len
= hba
->desc_size
.geom_desc
;
1225 case QUERY_DESC_IDN_CONFIGURATION
:
1226 *desc_len
= hba
->desc_size
.conf_desc
;
1228 case QUERY_DESC_IDN_UNIT
:
1229 *desc_len
= hba
->desc_size
.unit_desc
;
1231 case QUERY_DESC_IDN_INTERCONNECT
:
1232 *desc_len
= hba
->desc_size
.interc_desc
;
1234 case QUERY_DESC_IDN_STRING
:
1235 *desc_len
= QUERY_DESC_MAX_SIZE
;
1237 case QUERY_DESC_IDN_HEALTH
:
1238 *desc_len
= hba
->desc_size
.hlth_desc
;
1240 case QUERY_DESC_IDN_RFU_0
:
1241 case QUERY_DESC_IDN_RFU_1
:
1250 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length
);
1253 * ufshcd_read_desc_param - read the specified descriptor parameter
1256 int ufshcd_read_desc_param(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1257 int desc_index
, u8 param_offset
, u8
*param_read_buf
,
1263 bool is_kmalloc
= true;
1266 if (desc_id
>= QUERY_DESC_IDN_MAX
|| !param_size
)
1269 /* Get the max length of descriptor from structure filled up at probe
1272 ret
= ufshcd_map_desc_id_to_length(hba
, desc_id
, &buff_len
);
1275 if (ret
|| !buff_len
) {
1276 dev_err(hba
->dev
, "%s: Failed to get full descriptor length",
1281 /* Check whether we need temp memory */
1282 if (param_offset
!= 0 || param_size
< buff_len
) {
1283 desc_buf
= kmalloc(buff_len
, GFP_KERNEL
);
1287 desc_buf
= param_read_buf
;
1291 /* Request for full descriptor */
1292 ret
= ufshcd_query_descriptor_retry(hba
, UPIU_QUERY_OPCODE_READ_DESC
,
1293 desc_id
, desc_index
, 0, desc_buf
,
1297 dev_err(hba
->dev
, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
1298 __func__
, desc_id
, desc_index
, param_offset
, ret
);
1303 if (desc_buf
[QUERY_DESC_DESC_TYPE_OFFSET
] != desc_id
) {
1304 dev_err(hba
->dev
, "%s: invalid desc_id %d in descriptor header",
1305 __func__
, desc_buf
[QUERY_DESC_DESC_TYPE_OFFSET
]);
1310 /* Check wherher we will not copy more data, than available */
1311 if (is_kmalloc
&& param_size
> buff_len
)
1312 param_size
= buff_len
;
1315 memcpy(param_read_buf
, &desc_buf
[param_offset
], param_size
);
1322 /* replace non-printable or non-ASCII characters with spaces */
1323 static inline void ufshcd_remove_non_printable(uint8_t *val
)
1328 if (*val
< 0x20 || *val
> 0x7e)
1333 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
1334 * state) and waits for it to take effect.
1337 static int ufshcd_uic_pwr_ctrl(struct ufs_hba
*hba
, struct uic_command
*cmd
)
1339 unsigned long start
= 0;
1343 ret
= ufshcd_send_uic_cmd(hba
, cmd
);
1346 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
1347 cmd
->command
, cmd
->argument3
, ret
);
1352 start
= get_timer(0);
1354 status
= ufshcd_get_upmcrs(hba
);
1355 if (get_timer(start
) > UFS_UIC_CMD_TIMEOUT
) {
1357 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
1358 cmd
->command
, status
);
1359 ret
= (status
!= PWR_OK
) ? status
: -1;
1362 } while (status
!= PWR_LOCAL
);
1368 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
1369 * using DME_SET primitives.
1371 static int ufshcd_uic_change_pwr_mode(struct ufs_hba
*hba
, u8 mode
)
1373 struct uic_command uic_cmd
= {0};
1376 uic_cmd
.command
= UIC_CMD_DME_SET
;
1377 uic_cmd
.argument1
= UIC_ARG_MIB(PA_PWRMODE
);
1378 uic_cmd
.argument3
= mode
;
1379 ret
= ufshcd_uic_pwr_ctrl(hba
, &uic_cmd
);
1385 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba
*hba
,
1386 struct scsi_cmd
*pccb
, u32 upiu_flags
)
1388 struct utp_upiu_req
*ucd_req_ptr
= hba
->ucd_req_ptr
;
1389 unsigned int cdb_len
;
1391 /* command descriptor fields */
1392 ucd_req_ptr
->header
.dword_0
=
1393 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND
, upiu_flags
,
1394 pccb
->lun
, TASK_TAG
);
1395 ucd_req_ptr
->header
.dword_1
=
1396 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI
, 0, 0, 0);
1398 /* Total EHS length and Data segment length will be zero */
1399 ucd_req_ptr
->header
.dword_2
= 0;
1401 ucd_req_ptr
->sc
.exp_data_transfer_len
= cpu_to_be32(pccb
->datalen
);
1403 cdb_len
= min_t(unsigned short, pccb
->cmdlen
, UFS_CDB_SIZE
);
1404 memset(ucd_req_ptr
->sc
.cdb
, 0, UFS_CDB_SIZE
);
1405 memcpy(ucd_req_ptr
->sc
.cdb
, pccb
->cmd
, cdb_len
);
1407 memset(hba
->ucd_rsp_ptr
, 0, sizeof(struct utp_upiu_rsp
));
1410 static inline void prepare_prdt_desc(struct ufshcd_sg_entry
*entry
,
1411 unsigned char *buf
, ulong len
)
1413 entry
->size
= cpu_to_le32(len
) | GENMASK(1, 0);
1414 entry
->base_addr
= cpu_to_le32(lower_32_bits((unsigned long)buf
));
1415 entry
->upper_addr
= cpu_to_le32(upper_32_bits((unsigned long)buf
));
1418 static void prepare_prdt_table(struct ufs_hba
*hba
, struct scsi_cmd
*pccb
)
1420 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
1421 struct ufshcd_sg_entry
*prd_table
= hba
->ucd_prdt_ptr
;
1422 ulong datalen
= pccb
->datalen
;
1428 req_desc
->prd_table_length
= 0;
1432 table_length
= DIV_ROUND_UP(pccb
->datalen
, MAX_PRDT_ENTRY
);
1436 prepare_prdt_desc(&prd_table
[table_length
- i
- 1], buf
,
1437 MAX_PRDT_ENTRY
- 1);
1438 buf
+= MAX_PRDT_ENTRY
;
1439 datalen
-= MAX_PRDT_ENTRY
;
1442 prepare_prdt_desc(&prd_table
[table_length
- i
- 1], buf
, datalen
- 1);
1444 req_desc
->prd_table_length
= table_length
;
1447 static int ufs_scsi_exec(struct udevice
*scsi_dev
, struct scsi_cmd
*pccb
)
1449 struct ufs_hba
*hba
= dev_get_uclass_priv(scsi_dev
->parent
);
1450 struct utp_transfer_req_desc
*req_desc
= hba
->utrdl
;
1452 int ocs
, result
= 0;
1455 ufshcd_prepare_req_desc_hdr(req_desc
, &upiu_flags
, pccb
->dma_dir
);
1456 ufshcd_prepare_utp_scsi_cmd_upiu(hba
, pccb
, upiu_flags
);
1457 prepare_prdt_table(hba
, pccb
);
1459 ufshcd_send_command(hba
, TASK_TAG
);
1461 ocs
= ufshcd_get_tr_ocs(hba
);
1464 result
= ufshcd_get_req_rsp(hba
->ucd_rsp_ptr
);
1466 case UPIU_TRANSACTION_RESPONSE
:
1467 result
= ufshcd_get_rsp_upiu_result(hba
->ucd_rsp_ptr
);
1469 scsi_status
= result
& MASK_SCSI_STATUS
;
1474 case UPIU_TRANSACTION_REJECT_UPIU
:
1475 /* TODO: handle Reject UPIU Response */
1477 "Reject UPIU not fully implemented\n");
1481 "Unexpected request response code = %x\n",
1487 dev_err(hba
->dev
, "OCS error from controller = %x\n", ocs
);
1494 static inline int ufshcd_read_desc(struct ufs_hba
*hba
, enum desc_idn desc_id
,
1495 int desc_index
, u8
*buf
, u32 size
)
1497 return ufshcd_read_desc_param(hba
, desc_id
, desc_index
, 0, buf
, size
);
1500 static int ufshcd_read_device_desc(struct ufs_hba
*hba
, u8
*buf
, u32 size
)
1502 return ufshcd_read_desc(hba
, QUERY_DESC_IDN_DEVICE
, 0, buf
, size
);
1506 * ufshcd_read_string_desc - read string descriptor
1509 int ufshcd_read_string_desc(struct ufs_hba
*hba
, int desc_index
,
1510 u8
*buf
, u32 size
, bool ascii
)
1514 err
= ufshcd_read_desc(hba
, QUERY_DESC_IDN_STRING
, desc_index
, buf
,
1518 dev_err(hba
->dev
, "%s: reading String Desc failed after %d retries. err = %d\n",
1519 __func__
, QUERY_REQ_RETRIES
, err
);
1530 /* remove header and divide by 2 to move from UTF16 to UTF8 */
1531 ascii_len
= (desc_len
- QUERY_DESC_HDR_SIZE
) / 2 + 1;
1532 if (size
< ascii_len
+ QUERY_DESC_HDR_SIZE
) {
1533 dev_err(hba
->dev
, "%s: buffer allocated size is too small\n",
1539 buff_ascii
= kmalloc(ascii_len
, GFP_KERNEL
);
1546 * the descriptor contains string in UTF16 format
1547 * we need to convert to utf-8 so it can be displayed
1549 utf16_to_utf8(buff_ascii
,
1550 (uint16_t *)&buf
[QUERY_DESC_HDR_SIZE
], ascii_len
);
1552 /* replace non-printable or non-ASCII characters with spaces */
1553 for (i
= 0; i
< ascii_len
; i
++)
1554 ufshcd_remove_non_printable(&buff_ascii
[i
]);
1556 memset(buf
+ QUERY_DESC_HDR_SIZE
, 0,
1557 size
- QUERY_DESC_HDR_SIZE
);
1558 memcpy(buf
+ QUERY_DESC_HDR_SIZE
, buff_ascii
, ascii_len
);
1559 buf
[QUERY_DESC_LENGTH_OFFSET
] = ascii_len
+ QUERY_DESC_HDR_SIZE
;
1566 static int ufs_get_device_desc(struct ufs_hba
*hba
,
1567 struct ufs_dev_desc
*dev_desc
)
1574 buff_len
= max_t(size_t, hba
->desc_size
.dev_desc
,
1575 QUERY_DESC_MAX_SIZE
+ 1);
1576 desc_buf
= kmalloc(buff_len
, GFP_KERNEL
);
1582 err
= ufshcd_read_device_desc(hba
, desc_buf
, hba
->desc_size
.dev_desc
);
1584 dev_err(hba
->dev
, "%s: Failed reading Device Desc. err = %d\n",
1590 * getting vendor (manufacturerID) and Bank Index in big endian
1593 dev_desc
->wmanufacturerid
= desc_buf
[DEVICE_DESC_PARAM_MANF_ID
] << 8 |
1594 desc_buf
[DEVICE_DESC_PARAM_MANF_ID
+ 1];
1596 model_index
= desc_buf
[DEVICE_DESC_PARAM_PRDCT_NAME
];
1598 /* Zero-pad entire buffer for string termination. */
1599 memset(desc_buf
, 0, buff_len
);
1601 err
= ufshcd_read_string_desc(hba
, model_index
, desc_buf
,
1602 QUERY_DESC_MAX_SIZE
, true/*ASCII*/);
1604 dev_err(hba
->dev
, "%s: Failed reading Product Name. err = %d\n",
1609 desc_buf
[QUERY_DESC_MAX_SIZE
] = '\0';
1610 strlcpy(dev_desc
->model
, (char *)(desc_buf
+ QUERY_DESC_HDR_SIZE
),
1611 min_t(u8
, desc_buf
[QUERY_DESC_LENGTH_OFFSET
],
1614 /* Null terminate the model string */
1615 dev_desc
->model
[MAX_MODEL_LEN
] = '\0';
1623 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
1625 static int ufshcd_get_max_pwr_mode(struct ufs_hba
*hba
)
1627 struct ufs_pa_layer_attr
*pwr_info
= &hba
->max_pwr_info
.info
;
1629 if (hba
->max_pwr_info
.is_valid
)
1632 pwr_info
->pwr_tx
= FAST_MODE
;
1633 pwr_info
->pwr_rx
= FAST_MODE
;
1634 pwr_info
->hs_rate
= PA_HS_MODE_B
;
1636 /* Get the connected lane count */
1637 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES
),
1638 &pwr_info
->lane_rx
);
1639 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES
),
1640 &pwr_info
->lane_tx
);
1642 if (!pwr_info
->lane_rx
|| !pwr_info
->lane_tx
) {
1643 dev_err(hba
->dev
, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
1644 __func__
, pwr_info
->lane_rx
, pwr_info
->lane_tx
);
1649 * First, get the maximum gears of HS speed.
1650 * If a zero value, it means there is no HSGEAR capability.
1651 * Then, get the maximum gears of PWM speed.
1653 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_MAXRXHSGEAR
), &pwr_info
->gear_rx
);
1654 if (!pwr_info
->gear_rx
) {
1655 ufshcd_dme_get(hba
, UIC_ARG_MIB(PA_MAXRXPWMGEAR
),
1656 &pwr_info
->gear_rx
);
1657 if (!pwr_info
->gear_rx
) {
1658 dev_err(hba
->dev
, "%s: invalid max pwm rx gear read = %d\n",
1659 __func__
, pwr_info
->gear_rx
);
1662 pwr_info
->pwr_rx
= SLOW_MODE
;
1665 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_MAXRXHSGEAR
),
1666 &pwr_info
->gear_tx
);
1667 if (!pwr_info
->gear_tx
) {
1668 ufshcd_dme_peer_get(hba
, UIC_ARG_MIB(PA_MAXRXPWMGEAR
),
1669 &pwr_info
->gear_tx
);
1670 if (!pwr_info
->gear_tx
) {
1671 dev_err(hba
->dev
, "%s: invalid max pwm tx gear read = %d\n",
1672 __func__
, pwr_info
->gear_tx
);
1675 pwr_info
->pwr_tx
= SLOW_MODE
;
1678 hba
->max_pwr_info
.is_valid
= true;
1682 static int ufshcd_change_power_mode(struct ufs_hba
*hba
,
1683 struct ufs_pa_layer_attr
*pwr_mode
)
1687 /* if already configured to the requested pwr_mode */
1688 if (pwr_mode
->gear_rx
== hba
->pwr_info
.gear_rx
&&
1689 pwr_mode
->gear_tx
== hba
->pwr_info
.gear_tx
&&
1690 pwr_mode
->lane_rx
== hba
->pwr_info
.lane_rx
&&
1691 pwr_mode
->lane_tx
== hba
->pwr_info
.lane_tx
&&
1692 pwr_mode
->pwr_rx
== hba
->pwr_info
.pwr_rx
&&
1693 pwr_mode
->pwr_tx
== hba
->pwr_info
.pwr_tx
&&
1694 pwr_mode
->hs_rate
== hba
->pwr_info
.hs_rate
) {
1695 dev_dbg(hba
->dev
, "%s: power already configured\n", __func__
);
1700 * Configure attributes for power mode change with below.
1701 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1702 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1705 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXGEAR
), pwr_mode
->gear_rx
);
1706 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_ACTIVERXDATALANES
),
1708 if (pwr_mode
->pwr_rx
== FASTAUTO_MODE
|| pwr_mode
->pwr_rx
== FAST_MODE
)
1709 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXTERMINATION
), TRUE
);
1711 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_RXTERMINATION
), FALSE
);
1713 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXGEAR
), pwr_mode
->gear_tx
);
1714 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_ACTIVETXDATALANES
),
1716 if (pwr_mode
->pwr_tx
== FASTAUTO_MODE
|| pwr_mode
->pwr_tx
== FAST_MODE
)
1717 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXTERMINATION
), TRUE
);
1719 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_TXTERMINATION
), FALSE
);
1721 if (pwr_mode
->pwr_rx
== FASTAUTO_MODE
||
1722 pwr_mode
->pwr_tx
== FASTAUTO_MODE
||
1723 pwr_mode
->pwr_rx
== FAST_MODE
||
1724 pwr_mode
->pwr_tx
== FAST_MODE
)
1725 ufshcd_dme_set(hba
, UIC_ARG_MIB(PA_HSSERIES
),
1728 ret
= ufshcd_uic_change_pwr_mode(hba
, pwr_mode
->pwr_rx
<< 4 |
1733 "%s: power mode change failed %d\n", __func__
, ret
);
1738 /* Copy new Power Mode to power info */
1739 memcpy(&hba
->pwr_info
, pwr_mode
, sizeof(struct ufs_pa_layer_attr
));
1745 * ufshcd_verify_dev_init() - Verify device initialization
1748 static int ufshcd_verify_dev_init(struct ufs_hba
*hba
)
1753 for (retries
= NOP_OUT_RETRIES
; retries
> 0; retries
--) {
1754 err
= ufshcd_exec_dev_cmd(hba
, DEV_CMD_TYPE_NOP
,
1756 if (!err
|| err
== -ETIMEDOUT
)
1759 dev_dbg(hba
->dev
, "%s: error %d retrying\n", __func__
, err
);
1763 dev_err(hba
->dev
, "%s: NOP OUT failed %d\n", __func__
, err
);
1769 * ufshcd_complete_dev_init() - checks device readiness
1771 static int ufshcd_complete_dev_init(struct ufs_hba
*hba
)
1777 err
= ufshcd_query_flag_retry(hba
, UPIU_QUERY_OPCODE_SET_FLAG
,
1778 QUERY_FLAG_IDN_FDEVICEINIT
, NULL
);
1781 "%s setting fDeviceInit flag failed with error %d\n",
1786 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
1787 for (i
= 0; i
< 1000 && !err
&& flag_res
; i
++)
1788 err
= ufshcd_query_flag_retry(hba
, UPIU_QUERY_OPCODE_READ_FLAG
,
1789 QUERY_FLAG_IDN_FDEVICEINIT
,
1794 "%s reading fDeviceInit flag failed with error %d\n",
1798 "%s fDeviceInit was not cleared by the device\n",
1805 static void ufshcd_def_desc_sizes(struct ufs_hba
*hba
)
1807 hba
->desc_size
.dev_desc
= QUERY_DESC_DEVICE_DEF_SIZE
;
1808 hba
->desc_size
.pwr_desc
= QUERY_DESC_POWER_DEF_SIZE
;
1809 hba
->desc_size
.interc_desc
= QUERY_DESC_INTERCONNECT_DEF_SIZE
;
1810 hba
->desc_size
.conf_desc
= QUERY_DESC_CONFIGURATION_DEF_SIZE
;
1811 hba
->desc_size
.unit_desc
= QUERY_DESC_UNIT_DEF_SIZE
;
1812 hba
->desc_size
.geom_desc
= QUERY_DESC_GEOMETRY_DEF_SIZE
;
1813 hba
->desc_size
.hlth_desc
= QUERY_DESC_HEALTH_DEF_SIZE
;
1816 int ufs_start(struct ufs_hba
*hba
)
1818 struct ufs_dev_desc card
= {0};
1821 ret
= ufshcd_link_startup(hba
);
1825 ret
= ufshcd_verify_dev_init(hba
);
1829 ret
= ufshcd_complete_dev_init(hba
);
1833 /* Init check for device descriptor sizes */
1834 ufshcd_init_desc_sizes(hba
);
1836 ret
= ufs_get_device_desc(hba
, &card
);
1838 dev_err(hba
->dev
, "%s: Failed getting device info. err = %d\n",
1844 if (ufshcd_get_max_pwr_mode(hba
)) {
1846 "%s: Failed getting max supported power mode\n",
1849 ret
= ufshcd_change_power_mode(hba
, &hba
->max_pwr_info
.info
);
1851 dev_err(hba
->dev
, "%s: Failed setting power mode, err = %d\n",
1857 printf("Device at %s up at:", hba
->dev
->name
);
1858 ufshcd_print_pwr_info(hba
);
1864 int ufshcd_probe(struct udevice
*ufs_dev
, struct ufs_hba_ops
*hba_ops
)
1866 struct ufs_hba
*hba
= dev_get_uclass_priv(ufs_dev
);
1867 struct scsi_platdata
*scsi_plat
;
1868 struct udevice
*scsi_dev
;
1871 device_find_first_child(ufs_dev
, &scsi_dev
);
1875 scsi_plat
= dev_get_uclass_platdata(scsi_dev
);
1876 scsi_plat
->max_id
= UFSHCD_MAX_ID
;
1877 scsi_plat
->max_lun
= UFS_MAX_LUNS
;
1878 scsi_plat
->max_bytes_per_req
= UFS_MAX_BYTES
;
1882 hba
->mmio_base
= (void *)dev_read_addr(ufs_dev
);
1884 /* Set descriptor lengths to specification defaults */
1885 ufshcd_def_desc_sizes(hba
);
1887 ufshcd_ops_init(hba
);
1889 /* Read capabilties registers */
1890 hba
->capabilities
= ufshcd_readl(hba
, REG_CONTROLLER_CAPABILITIES
);
1892 /* Get UFS version supported by the controller */
1893 hba
->version
= ufshcd_get_ufs_version(hba
);
1894 if (hba
->version
!= UFSHCI_VERSION_10
&&
1895 hba
->version
!= UFSHCI_VERSION_11
&&
1896 hba
->version
!= UFSHCI_VERSION_20
&&
1897 hba
->version
!= UFSHCI_VERSION_21
)
1898 dev_err(hba
->dev
, "invalid UFS version 0x%x\n",
1901 /* Get Interrupt bit mask per version */
1902 hba
->intr_mask
= ufshcd_get_intr_mask(hba
);
1904 /* Allocate memory for host memory space */
1905 err
= ufshcd_memory_alloc(hba
);
1907 dev_err(hba
->dev
, "Memory allocation failed\n");
1911 /* Configure Local data structures */
1912 ufshcd_host_memory_configure(hba
);
1915 * In order to avoid any spurious interrupt immediately after
1916 * registering UFS controller interrupt handler, clear any pending UFS
1917 * interrupt status and disable all the UFS interrupts.
1919 ufshcd_writel(hba
, ufshcd_readl(hba
, REG_INTERRUPT_STATUS
),
1920 REG_INTERRUPT_STATUS
);
1921 ufshcd_writel(hba
, 0, REG_INTERRUPT_ENABLE
);
1923 err
= ufshcd_hba_enable(hba
);
1925 dev_err(hba
->dev
, "Host controller enable failed\n");
1929 err
= ufs_start(hba
);
1936 int ufs_scsi_bind(struct udevice
*ufs_dev
, struct udevice
**scsi_devp
)
1938 int ret
= device_bind_driver(ufs_dev
, "ufs_scsi", "ufs_scsi",
1944 static struct scsi_ops ufs_ops
= {
1945 .exec
= ufs_scsi_exec
,
1948 int ufs_probe_dev(int index
)
1950 struct udevice
*dev
;
1952 return uclass_get_device(UCLASS_UFS
, index
, &dev
);
1957 struct udevice
*dev
;
1961 ret
= uclass_get_device(UCLASS_UFS
, i
, &dev
);
1969 U_BOOT_DRIVER(ufs_scsi
) = {