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ufs: Add UFSHCD_QUIRK_HIBERN_FASTAUTO
[thirdparty/u-boot.git] / drivers / ufs / ufs.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /**
3 * ufs.c - Universal Flash Subsystem (UFS) driver
4 *
5 * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
6 * to u-boot.
7 *
8 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
9 */
10
11 #include <bouncebuf.h>
12 #include <charset.h>
13 #include <common.h>
14 #include <dm.h>
15 #include <log.h>
16 #include <dm/device_compat.h>
17 #include <dm/devres.h>
18 #include <dm/lists.h>
19 #include <dm/device-internal.h>
20 #include <malloc.h>
21 #include <hexdump.h>
22 #include <scsi.h>
23 #include <asm/io.h>
24 #include <asm/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28
29 #include "ufs.h"
30
31 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
32 UTP_TASK_REQ_COMPL |\
33 UFSHCD_ERROR_MASK)
34 /* maximum number of link-startup retries */
35 #define DME_LINKSTARTUP_RETRIES 3
36
37 /* maximum number of retries for a general UIC command */
38 #define UFS_UIC_COMMAND_RETRIES 3
39
40 /* Query request retries */
41 #define QUERY_REQ_RETRIES 3
42 /* Query request timeout */
43 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
44
45 /* maximum timeout in ms for a general UIC command */
46 #define UFS_UIC_CMD_TIMEOUT 1000
47 /* NOP OUT retries waiting for NOP IN response */
48 #define NOP_OUT_RETRIES 10
49 /* Timeout after 30 msecs if NOP OUT hangs without response */
50 #define NOP_OUT_TIMEOUT 30 /* msecs */
51
52 /* Only use one Task Tag for all requests */
53 #define TASK_TAG 0
54
55 /* Expose the flag value from utp_upiu_query.value */
56 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
57
58 #define MAX_PRDT_ENTRY 262144
59
60 /* maximum bytes per request */
61 #define UFS_MAX_BYTES (128 * 256 * 1024)
62
63 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
64 static inline void ufshcd_hba_stop(struct ufs_hba *hba);
65 static int ufshcd_hba_enable(struct ufs_hba *hba);
66
67 /*
68 * ufshcd_wait_for_register - wait for register value to change
69 */
70 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
71 u32 val, unsigned long timeout_ms)
72 {
73 int err = 0;
74 unsigned long start = get_timer(0);
75
76 /* ignore bits that we don't intend to wait on */
77 val = val & mask;
78
79 while ((ufshcd_readl(hba, reg) & mask) != val) {
80 if (get_timer(start) > timeout_ms) {
81 if ((ufshcd_readl(hba, reg) & mask) != val)
82 err = -ETIMEDOUT;
83 break;
84 }
85 }
86
87 return err;
88 }
89
90 /**
91 * ufshcd_init_pwr_info - setting the POR (power on reset)
92 * values in hba power info
93 */
94 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
95 {
96 hba->pwr_info.gear_rx = UFS_PWM_G1;
97 hba->pwr_info.gear_tx = UFS_PWM_G1;
98 hba->pwr_info.lane_rx = 1;
99 hba->pwr_info.lane_tx = 1;
100 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
101 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
102 hba->pwr_info.hs_rate = 0;
103 }
104
105 /**
106 * ufshcd_print_pwr_info - print power params as saved in hba
107 * power info
108 */
109 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
110 {
111 static const char * const names[] = {
112 "INVALID MODE",
113 "FAST MODE",
114 "SLOW_MODE",
115 "INVALID MODE",
116 "FASTAUTO_MODE",
117 "SLOWAUTO_MODE",
118 "INVALID MODE",
119 };
120
121 dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
122 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
123 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
124 names[hba->pwr_info.pwr_rx],
125 names[hba->pwr_info.pwr_tx],
126 hba->pwr_info.hs_rate);
127 }
128
129 /**
130 * ufshcd_ready_for_uic_cmd - Check if controller is ready
131 * to accept UIC commands
132 */
133 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
134 {
135 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
136 return true;
137 else
138 return false;
139 }
140
141 /**
142 * ufshcd_get_uic_cmd_result - Get the UIC command result
143 */
144 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
145 {
146 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
147 MASK_UIC_COMMAND_RESULT;
148 }
149
150 /**
151 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
152 */
153 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
154 {
155 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
156 }
157
158 /**
159 * ufshcd_is_device_present - Check if any device connected to
160 * the host controller
161 */
162 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
163 {
164 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
165 DEVICE_PRESENT) ? true : false;
166 }
167
168 /**
169 * ufshcd_send_uic_cmd - UFS Interconnect layer command API
170 *
171 */
172 static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
173 {
174 unsigned long start = 0;
175 u32 intr_status;
176 u32 enabled_intr_status;
177
178 if (!ufshcd_ready_for_uic_cmd(hba)) {
179 dev_err(hba->dev,
180 "Controller not ready to accept UIC commands\n");
181 return -EIO;
182 }
183
184 debug("sending uic command:%d\n", uic_cmd->command);
185
186 /* Write Args */
187 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
188 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
189 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
190
191 /* Write UIC Cmd */
192 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
193 REG_UIC_COMMAND);
194
195 start = get_timer(0);
196 do {
197 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
198 enabled_intr_status = intr_status & hba->intr_mask;
199 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
200
201 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
202 dev_err(hba->dev,
203 "Timedout waiting for UIC response\n");
204
205 return -ETIMEDOUT;
206 }
207
208 if (enabled_intr_status & UFSHCD_ERROR_MASK) {
209 dev_err(hba->dev, "Error in status:%08x\n",
210 enabled_intr_status);
211
212 return -1;
213 }
214 } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
215
216 uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
217 uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
218
219 debug("Sent successfully\n");
220
221 return 0;
222 }
223
224 /**
225 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
226 *
227 */
228 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
229 u32 mib_val, u8 peer)
230 {
231 struct uic_command uic_cmd = {0};
232 static const char *const action[] = {
233 "dme-set",
234 "dme-peer-set"
235 };
236 const char *set = action[!!peer];
237 int ret;
238 int retries = UFS_UIC_COMMAND_RETRIES;
239
240 uic_cmd.command = peer ?
241 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
242 uic_cmd.argument1 = attr_sel;
243 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
244 uic_cmd.argument3 = mib_val;
245
246 do {
247 /* for peer attributes we retry upon failure */
248 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
249 if (ret)
250 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
251 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
252 } while (ret && peer && --retries);
253
254 if (ret)
255 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
256 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
257 UFS_UIC_COMMAND_RETRIES - retries);
258
259 return ret;
260 }
261
262 /**
263 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
264 *
265 */
266 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
267 u32 *mib_val, u8 peer)
268 {
269 struct uic_command uic_cmd = {0};
270 static const char *const action[] = {
271 "dme-get",
272 "dme-peer-get"
273 };
274 const char *get = action[!!peer];
275 int ret;
276 int retries = UFS_UIC_COMMAND_RETRIES;
277
278 uic_cmd.command = peer ?
279 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
280 uic_cmd.argument1 = attr_sel;
281
282 do {
283 /* for peer attributes we retry upon failure */
284 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
285 if (ret)
286 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
287 get, UIC_GET_ATTR_ID(attr_sel), ret);
288 } while (ret && peer && --retries);
289
290 if (ret)
291 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
292 get, UIC_GET_ATTR_ID(attr_sel),
293 UFS_UIC_COMMAND_RETRIES - retries);
294
295 if (mib_val && !ret)
296 *mib_val = uic_cmd.argument3;
297
298 return ret;
299 }
300
301 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
302 {
303 u32 tx_lanes, i, err = 0;
304
305 if (!peer)
306 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
307 &tx_lanes);
308 else
309 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
310 &tx_lanes);
311 for (i = 0; i < tx_lanes; i++) {
312 if (!peer)
313 err = ufshcd_dme_set(hba,
314 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
315 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
316 0);
317 else
318 err = ufshcd_dme_peer_set(hba,
319 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
320 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
321 0);
322 if (err) {
323 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
324 __func__, peer, i, err);
325 break;
326 }
327 }
328
329 return err;
330 }
331
332 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
333 {
334 return ufshcd_disable_tx_lcc(hba, true);
335 }
336
337 /**
338 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
339 *
340 */
341 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
342 {
343 struct uic_command uic_cmd = {0};
344 int ret;
345
346 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
347
348 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
349 if (ret)
350 dev_dbg(hba->dev,
351 "dme-link-startup: error code %d\n", ret);
352 return ret;
353 }
354
355 /**
356 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
357 *
358 */
359 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
360 {
361 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
362 }
363
364 /**
365 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
366 */
367 static inline int ufshcd_get_lists_status(u32 reg)
368 {
369 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
370 }
371
372 /**
373 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
374 * When run-stop registers are set to 1, it indicates the
375 * host controller that it can process the requests
376 */
377 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
378 {
379 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
380 REG_UTP_TASK_REQ_LIST_RUN_STOP);
381 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
382 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
383 }
384
385 /**
386 * ufshcd_enable_intr - enable interrupts
387 */
388 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
389 {
390 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
391 u32 rw;
392
393 if (hba->version == UFSHCI_VERSION_10) {
394 rw = set & INTERRUPT_MASK_RW_VER_10;
395 set = rw | ((set ^ intrs) & intrs);
396 } else {
397 set |= intrs;
398 }
399
400 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
401
402 hba->intr_mask = set;
403 }
404
405 /**
406 * ufshcd_make_hba_operational - Make UFS controller operational
407 *
408 * To bring UFS host controller to operational state,
409 * 1. Enable required interrupts
410 * 2. Configure interrupt aggregation
411 * 3. Program UTRL and UTMRL base address
412 * 4. Configure run-stop-registers
413 *
414 */
415 static int ufshcd_make_hba_operational(struct ufs_hba *hba)
416 {
417 int err = 0;
418 u32 reg;
419
420 /* Enable required interrupts */
421 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
422
423 /* Disable interrupt aggregation */
424 ufshcd_disable_intr_aggr(hba);
425
426 /* Configure UTRL and UTMRL base address registers */
427 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
428 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
429 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
430 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
431 ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
432 REG_UTP_TASK_REQ_LIST_BASE_L);
433 ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
434 REG_UTP_TASK_REQ_LIST_BASE_H);
435
436 /*
437 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
438 */
439 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
440 if (!(ufshcd_get_lists_status(reg))) {
441 ufshcd_enable_run_stop_reg(hba);
442 } else {
443 dev_err(hba->dev,
444 "Host controller not ready to process requests");
445 err = -EIO;
446 goto out;
447 }
448
449 out:
450 return err;
451 }
452
453 /**
454 * ufshcd_link_startup - Initialize unipro link startup
455 */
456 static int ufshcd_link_startup(struct ufs_hba *hba)
457 {
458 int ret;
459 int retries = DME_LINKSTARTUP_RETRIES;
460 bool link_startup_again = true;
461
462 link_startup:
463 do {
464 ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
465
466 ret = ufshcd_dme_link_startup(hba);
467
468 /* check if device is detected by inter-connect layer */
469 if (!ret && !ufshcd_is_device_present(hba)) {
470 dev_err(hba->dev, "%s: Device not present\n", __func__);
471 ret = -ENXIO;
472 goto out;
473 }
474
475 /*
476 * DME link lost indication is only received when link is up,
477 * but we can't be sure if the link is up until link startup
478 * succeeds. So reset the local Uni-Pro and try again.
479 */
480 if (ret && ufshcd_hba_enable(hba))
481 goto out;
482 } while (ret && retries--);
483
484 if (ret)
485 /* failed to get the link up... retire */
486 goto out;
487
488 if (link_startup_again) {
489 link_startup_again = false;
490 retries = DME_LINKSTARTUP_RETRIES;
491 goto link_startup;
492 }
493
494 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
495 ufshcd_init_pwr_info(hba);
496
497 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
498 ret = ufshcd_disable_device_tx_lcc(hba);
499 if (ret)
500 goto out;
501 }
502
503 /* Include any host controller configuration via UIC commands */
504 ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
505 if (ret)
506 goto out;
507
508 ret = ufshcd_make_hba_operational(hba);
509 out:
510 if (ret)
511 dev_err(hba->dev, "link startup failed %d\n", ret);
512
513 return ret;
514 }
515
516 /**
517 * ufshcd_hba_stop - Send controller to reset state
518 */
519 static inline void ufshcd_hba_stop(struct ufs_hba *hba)
520 {
521 int err;
522
523 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
524 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
525 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
526 10);
527 if (err)
528 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
529 }
530
531 /**
532 * ufshcd_is_hba_active - Get controller state
533 */
534 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
535 {
536 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
537 ? false : true;
538 }
539
540 /**
541 * ufshcd_hba_start - Start controller initialization sequence
542 */
543 static inline void ufshcd_hba_start(struct ufs_hba *hba)
544 {
545 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
546 }
547
548 /**
549 * ufshcd_hba_enable - initialize the controller
550 */
551 static int ufshcd_hba_enable(struct ufs_hba *hba)
552 {
553 int retry;
554
555 if (!ufshcd_is_hba_active(hba))
556 /* change controller state to "reset state" */
557 ufshcd_hba_stop(hba);
558
559 ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
560
561 /* start controller initialization sequence */
562 ufshcd_hba_start(hba);
563
564 /*
565 * To initialize a UFS host controller HCE bit must be set to 1.
566 * During initialization the HCE bit value changes from 1->0->1.
567 * When the host controller completes initialization sequence
568 * it sets the value of HCE bit to 1. The same HCE bit is read back
569 * to check if the controller has completed initialization sequence.
570 * So without this delay the value HCE = 1, set in the previous
571 * instruction might be read back.
572 * This delay can be changed based on the controller.
573 */
574 mdelay(1);
575
576 /* wait for the host controller to complete initialization */
577 retry = 10;
578 while (ufshcd_is_hba_active(hba)) {
579 if (retry) {
580 retry--;
581 } else {
582 dev_err(hba->dev, "Controller enable failed\n");
583 return -EIO;
584 }
585 mdelay(5);
586 }
587
588 /* enable UIC related interrupts */
589 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
590
591 ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
592
593 return 0;
594 }
595
596 /**
597 * ufshcd_host_memory_configure - configure local reference block with
598 * memory offsets
599 */
600 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
601 {
602 struct utp_transfer_req_desc *utrdlp;
603 dma_addr_t cmd_desc_dma_addr;
604 u16 response_offset;
605 u16 prdt_offset;
606
607 utrdlp = hba->utrdl;
608 cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
609
610 utrdlp->command_desc_base_addr_lo =
611 cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
612 utrdlp->command_desc_base_addr_hi =
613 cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
614
615 response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
616 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
617
618 utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
619 utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
620 utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
621
622 hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
623 hba->ucd_rsp_ptr =
624 (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
625 hba->ucd_prdt_ptr =
626 (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
627 }
628
629 /**
630 * ufshcd_memory_alloc - allocate memory for host memory space data structures
631 */
632 static int ufshcd_memory_alloc(struct ufs_hba *hba)
633 {
634 /* Allocate one Transfer Request Descriptor
635 * Should be aligned to 1k boundary.
636 */
637 hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
638 if (!hba->utrdl) {
639 dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
640 return -ENOMEM;
641 }
642
643 /* Allocate one Command Descriptor
644 * Should be aligned to 1k boundary.
645 */
646 hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
647 if (!hba->ucdl) {
648 dev_err(hba->dev, "Command descriptor memory allocation failed\n");
649 return -ENOMEM;
650 }
651
652 return 0;
653 }
654
655 /**
656 * ufshcd_get_intr_mask - Get the interrupt bit mask
657 */
658 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
659 {
660 u32 intr_mask = 0;
661
662 switch (hba->version) {
663 case UFSHCI_VERSION_10:
664 intr_mask = INTERRUPT_MASK_ALL_VER_10;
665 break;
666 case UFSHCI_VERSION_11:
667 case UFSHCI_VERSION_20:
668 intr_mask = INTERRUPT_MASK_ALL_VER_11;
669 break;
670 case UFSHCI_VERSION_21:
671 default:
672 intr_mask = INTERRUPT_MASK_ALL_VER_21;
673 break;
674 }
675
676 return intr_mask;
677 }
678
679 /**
680 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
681 */
682 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
683 {
684 return ufshcd_readl(hba, REG_UFS_VERSION);
685 }
686
687 /**
688 * ufshcd_get_upmcrs - Get the power mode change request status
689 */
690 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
691 {
692 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
693 }
694
695 /**
696 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
697 * descriptor according to request
698 */
699 static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
700 u32 *upiu_flags,
701 enum dma_data_direction cmd_dir)
702 {
703 u32 data_direction;
704 u32 dword_0;
705
706 if (cmd_dir == DMA_FROM_DEVICE) {
707 data_direction = UTP_DEVICE_TO_HOST;
708 *upiu_flags = UPIU_CMD_FLAGS_READ;
709 } else if (cmd_dir == DMA_TO_DEVICE) {
710 data_direction = UTP_HOST_TO_DEVICE;
711 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
712 } else {
713 data_direction = UTP_NO_DATA_TRANSFER;
714 *upiu_flags = UPIU_CMD_FLAGS_NONE;
715 }
716
717 dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
718
719 /* Enable Interrupt for command */
720 dword_0 |= UTP_REQ_DESC_INT_CMD;
721
722 /* Transfer request descriptor header fields */
723 req_desc->header.dword_0 = cpu_to_le32(dword_0);
724 /* dword_1 is reserved, hence it is set to 0 */
725 req_desc->header.dword_1 = 0;
726 /*
727 * assigning invalid value for command status. Controller
728 * updates OCS on command completion, with the command
729 * status
730 */
731 req_desc->header.dword_2 =
732 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
733 /* dword_3 is reserved, hence it is set to 0 */
734 req_desc->header.dword_3 = 0;
735
736 req_desc->prd_table_length = 0;
737 }
738
739 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
740 u32 upiu_flags)
741 {
742 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
743 struct ufs_query *query = &hba->dev_cmd.query;
744 u16 len = be16_to_cpu(query->request.upiu_req.length);
745
746 /* Query request header */
747 ucd_req_ptr->header.dword_0 =
748 UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
749 upiu_flags, 0, TASK_TAG);
750 ucd_req_ptr->header.dword_1 =
751 UPIU_HEADER_DWORD(0, query->request.query_func,
752 0, 0);
753
754 /* Data segment length only need for WRITE_DESC */
755 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
756 ucd_req_ptr->header.dword_2 =
757 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
758 else
759 ucd_req_ptr->header.dword_2 = 0;
760
761 /* Copy the Query Request buffer as is */
762 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
763
764 /* Copy the Descriptor */
765 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
766 memcpy(ucd_req_ptr + 1, query->descriptor, len);
767
768 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
769 }
770
771 static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
772 {
773 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
774
775 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
776
777 /* command descriptor fields */
778 ucd_req_ptr->header.dword_0 =
779 UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG);
780 /* clear rest of the fields of basic header */
781 ucd_req_ptr->header.dword_1 = 0;
782 ucd_req_ptr->header.dword_2 = 0;
783
784 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
785 }
786
787 /**
788 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
789 * for Device Management Purposes
790 */
791 static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
792 enum dev_cmd_type cmd_type)
793 {
794 u32 upiu_flags;
795 int ret = 0;
796 struct utp_transfer_req_desc *req_desc = hba->utrdl;
797
798 hba->dev_cmd.type = cmd_type;
799
800 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
801 switch (cmd_type) {
802 case DEV_CMD_TYPE_QUERY:
803 ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
804 break;
805 case DEV_CMD_TYPE_NOP:
806 ufshcd_prepare_utp_nop_upiu(hba);
807 break;
808 default:
809 ret = -EINVAL;
810 }
811
812 return ret;
813 }
814
815 static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
816 {
817 unsigned long start;
818 u32 intr_status;
819 u32 enabled_intr_status;
820
821 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
822
823 start = get_timer(0);
824 do {
825 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
826 enabled_intr_status = intr_status & hba->intr_mask;
827 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
828
829 if (get_timer(start) > QUERY_REQ_TIMEOUT) {
830 dev_err(hba->dev,
831 "Timedout waiting for UTP response\n");
832
833 return -ETIMEDOUT;
834 }
835
836 if (enabled_intr_status & UFSHCD_ERROR_MASK) {
837 dev_err(hba->dev, "Error in status:%08x\n",
838 enabled_intr_status);
839
840 return -1;
841 }
842 } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
843
844 return 0;
845 }
846
847 /**
848 * ufshcd_get_req_rsp - returns the TR response transaction type
849 */
850 static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
851 {
852 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
853 }
854
855 /**
856 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
857 *
858 */
859 static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
860 {
861 return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
862 }
863
864 static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
865 {
866 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
867 }
868
869 static int ufshcd_check_query_response(struct ufs_hba *hba)
870 {
871 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
872
873 /* Get the UPIU response */
874 query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
875 UPIU_RSP_CODE_OFFSET;
876 return query_res->response;
877 }
878
879 /**
880 * ufshcd_copy_query_response() - Copy the Query Response and the data
881 * descriptor
882 */
883 static int ufshcd_copy_query_response(struct ufs_hba *hba)
884 {
885 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
886
887 memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
888
889 /* Get the descriptor */
890 if (hba->dev_cmd.query.descriptor &&
891 hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
892 u8 *descp = (u8 *)hba->ucd_rsp_ptr +
893 GENERAL_UPIU_REQUEST_SIZE;
894 u16 resp_len;
895 u16 buf_len;
896
897 /* data segment length */
898 resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
899 MASK_QUERY_DATA_SEG_LEN;
900 buf_len =
901 be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
902 if (likely(buf_len >= resp_len)) {
903 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
904 } else {
905 dev_warn(hba->dev,
906 "%s: Response size is bigger than buffer",
907 __func__);
908 return -EINVAL;
909 }
910 }
911
912 return 0;
913 }
914
915 /**
916 * ufshcd_exec_dev_cmd - API for sending device management requests
917 */
918 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
919 int timeout)
920 {
921 int err;
922 int resp;
923
924 err = ufshcd_comp_devman_upiu(hba, cmd_type);
925 if (err)
926 return err;
927
928 err = ufshcd_send_command(hba, TASK_TAG);
929 if (err)
930 return err;
931
932 err = ufshcd_get_tr_ocs(hba);
933 if (err) {
934 dev_err(hba->dev, "Error in OCS:%d\n", err);
935 return -EINVAL;
936 }
937
938 resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
939 switch (resp) {
940 case UPIU_TRANSACTION_NOP_IN:
941 break;
942 case UPIU_TRANSACTION_QUERY_RSP:
943 err = ufshcd_check_query_response(hba);
944 if (!err)
945 err = ufshcd_copy_query_response(hba);
946 break;
947 case UPIU_TRANSACTION_REJECT_UPIU:
948 /* TODO: handle Reject UPIU Response */
949 err = -EPERM;
950 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
951 __func__);
952 break;
953 default:
954 err = -EINVAL;
955 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
956 __func__, resp);
957 }
958
959 return err;
960 }
961
962 /**
963 * ufshcd_init_query() - init the query response and request parameters
964 */
965 static inline void ufshcd_init_query(struct ufs_hba *hba,
966 struct ufs_query_req **request,
967 struct ufs_query_res **response,
968 enum query_opcode opcode,
969 u8 idn, u8 index, u8 selector)
970 {
971 *request = &hba->dev_cmd.query.request;
972 *response = &hba->dev_cmd.query.response;
973 memset(*request, 0, sizeof(struct ufs_query_req));
974 memset(*response, 0, sizeof(struct ufs_query_res));
975 (*request)->upiu_req.opcode = opcode;
976 (*request)->upiu_req.idn = idn;
977 (*request)->upiu_req.index = index;
978 (*request)->upiu_req.selector = selector;
979 }
980
981 /**
982 * ufshcd_query_flag() - API function for sending flag query requests
983 */
984 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
985 enum flag_idn idn, bool *flag_res)
986 {
987 struct ufs_query_req *request = NULL;
988 struct ufs_query_res *response = NULL;
989 int err, index = 0, selector = 0;
990 int timeout = QUERY_REQ_TIMEOUT;
991
992 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
993 selector);
994
995 switch (opcode) {
996 case UPIU_QUERY_OPCODE_SET_FLAG:
997 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
998 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
999 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1000 break;
1001 case UPIU_QUERY_OPCODE_READ_FLAG:
1002 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1003 if (!flag_res) {
1004 /* No dummy reads */
1005 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1006 __func__);
1007 err = -EINVAL;
1008 goto out;
1009 }
1010 break;
1011 default:
1012 dev_err(hba->dev,
1013 "%s: Expected query flag opcode but got = %d\n",
1014 __func__, opcode);
1015 err = -EINVAL;
1016 goto out;
1017 }
1018
1019 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
1020
1021 if (err) {
1022 dev_err(hba->dev,
1023 "%s: Sending flag query for idn %d failed, err = %d\n",
1024 __func__, idn, err);
1025 goto out;
1026 }
1027
1028 if (flag_res)
1029 *flag_res = (be32_to_cpu(response->upiu_res.value) &
1030 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1031
1032 out:
1033 return err;
1034 }
1035
1036 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1037 enum query_opcode opcode,
1038 enum flag_idn idn, bool *flag_res)
1039 {
1040 int ret;
1041 int retries;
1042
1043 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1044 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1045 if (ret)
1046 dev_dbg(hba->dev,
1047 "%s: failed with error %d, retries %d\n",
1048 __func__, ret, retries);
1049 else
1050 break;
1051 }
1052
1053 if (ret)
1054 dev_err(hba->dev,
1055 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1056 __func__, opcode, idn, ret, retries);
1057 return ret;
1058 }
1059
1060 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
1061 enum query_opcode opcode,
1062 enum desc_idn idn, u8 index, u8 selector,
1063 u8 *desc_buf, int *buf_len)
1064 {
1065 struct ufs_query_req *request = NULL;
1066 struct ufs_query_res *response = NULL;
1067 int err;
1068
1069 if (!desc_buf) {
1070 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1071 __func__, opcode);
1072 err = -EINVAL;
1073 goto out;
1074 }
1075
1076 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1077 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1078 __func__, *buf_len);
1079 err = -EINVAL;
1080 goto out;
1081 }
1082
1083 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1084 selector);
1085 hba->dev_cmd.query.descriptor = desc_buf;
1086 request->upiu_req.length = cpu_to_be16(*buf_len);
1087
1088 switch (opcode) {
1089 case UPIU_QUERY_OPCODE_WRITE_DESC:
1090 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1091 break;
1092 case UPIU_QUERY_OPCODE_READ_DESC:
1093 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1094 break;
1095 default:
1096 dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1097 __func__, opcode);
1098 err = -EINVAL;
1099 goto out;
1100 }
1101
1102 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1103
1104 if (err) {
1105 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1106 __func__, opcode, idn, index, err);
1107 goto out;
1108 }
1109
1110 hba->dev_cmd.query.descriptor = NULL;
1111 *buf_len = be16_to_cpu(response->upiu_res.length);
1112
1113 out:
1114 return err;
1115 }
1116
1117 /**
1118 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
1119 */
1120 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
1121 enum desc_idn idn, u8 index, u8 selector,
1122 u8 *desc_buf, int *buf_len)
1123 {
1124 int err;
1125 int retries;
1126
1127 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1128 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
1129 selector, desc_buf, buf_len);
1130 if (!err || err == -EINVAL)
1131 break;
1132 }
1133
1134 return err;
1135 }
1136
1137 /**
1138 * ufshcd_read_desc_length - read the specified descriptor length from header
1139 */
1140 static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
1141 int desc_index, int *desc_length)
1142 {
1143 int ret;
1144 u8 header[QUERY_DESC_HDR_SIZE];
1145 int header_len = QUERY_DESC_HDR_SIZE;
1146
1147 if (desc_id >= QUERY_DESC_IDN_MAX)
1148 return -EINVAL;
1149
1150 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1151 desc_id, desc_index, 0, header,
1152 &header_len);
1153
1154 if (ret) {
1155 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
1156 __func__, desc_id);
1157 return ret;
1158 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
1159 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
1160 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
1161 desc_id);
1162 ret = -EINVAL;
1163 }
1164
1165 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
1166
1167 return ret;
1168 }
1169
1170 static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
1171 {
1172 int err;
1173
1174 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
1175 &hba->desc_size.dev_desc);
1176 if (err)
1177 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1178
1179 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
1180 &hba->desc_size.pwr_desc);
1181 if (err)
1182 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1183
1184 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
1185 &hba->desc_size.interc_desc);
1186 if (err)
1187 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1188
1189 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
1190 &hba->desc_size.conf_desc);
1191 if (err)
1192 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1193
1194 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
1195 &hba->desc_size.unit_desc);
1196 if (err)
1197 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1198
1199 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
1200 &hba->desc_size.geom_desc);
1201 if (err)
1202 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1203
1204 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
1205 &hba->desc_size.hlth_desc);
1206 if (err)
1207 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1208 }
1209
1210 /**
1211 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
1212 *
1213 */
1214 int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1215 int *desc_len)
1216 {
1217 switch (desc_id) {
1218 case QUERY_DESC_IDN_DEVICE:
1219 *desc_len = hba->desc_size.dev_desc;
1220 break;
1221 case QUERY_DESC_IDN_POWER:
1222 *desc_len = hba->desc_size.pwr_desc;
1223 break;
1224 case QUERY_DESC_IDN_GEOMETRY:
1225 *desc_len = hba->desc_size.geom_desc;
1226 break;
1227 case QUERY_DESC_IDN_CONFIGURATION:
1228 *desc_len = hba->desc_size.conf_desc;
1229 break;
1230 case QUERY_DESC_IDN_UNIT:
1231 *desc_len = hba->desc_size.unit_desc;
1232 break;
1233 case QUERY_DESC_IDN_INTERCONNECT:
1234 *desc_len = hba->desc_size.interc_desc;
1235 break;
1236 case QUERY_DESC_IDN_STRING:
1237 *desc_len = QUERY_DESC_MAX_SIZE;
1238 break;
1239 case QUERY_DESC_IDN_HEALTH:
1240 *desc_len = hba->desc_size.hlth_desc;
1241 break;
1242 case QUERY_DESC_IDN_RFU_0:
1243 case QUERY_DESC_IDN_RFU_1:
1244 *desc_len = 0;
1245 break;
1246 default:
1247 *desc_len = 0;
1248 return -EINVAL;
1249 }
1250 return 0;
1251 }
1252 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
1253
1254 /**
1255 * ufshcd_read_desc_param - read the specified descriptor parameter
1256 *
1257 */
1258 int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
1259 int desc_index, u8 param_offset, u8 *param_read_buf,
1260 u8 param_size)
1261 {
1262 int ret;
1263 u8 *desc_buf;
1264 int buff_len;
1265 bool is_kmalloc = true;
1266
1267 /* Safety check */
1268 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
1269 return -EINVAL;
1270
1271 /* Get the max length of descriptor from structure filled up at probe
1272 * time.
1273 */
1274 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
1275
1276 /* Sanity checks */
1277 if (ret || !buff_len) {
1278 dev_err(hba->dev, "%s: Failed to get full descriptor length",
1279 __func__);
1280 return ret;
1281 }
1282
1283 /* Check whether we need temp memory */
1284 if (param_offset != 0 || param_size < buff_len) {
1285 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1286 if (!desc_buf)
1287 return -ENOMEM;
1288 } else {
1289 desc_buf = param_read_buf;
1290 is_kmalloc = false;
1291 }
1292
1293 /* Request for full descriptor */
1294 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1295 desc_id, desc_index, 0, desc_buf,
1296 &buff_len);
1297
1298 if (ret) {
1299 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
1300 __func__, desc_id, desc_index, param_offset, ret);
1301 goto out;
1302 }
1303
1304 /* Sanity check */
1305 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1306 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
1307 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
1308 ret = -EINVAL;
1309 goto out;
1310 }
1311
1312 /* Check wherher we will not copy more data, than available */
1313 if (is_kmalloc && param_size > buff_len)
1314 param_size = buff_len;
1315
1316 if (is_kmalloc)
1317 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1318 out:
1319 if (is_kmalloc)
1320 kfree(desc_buf);
1321 return ret;
1322 }
1323
1324 /* replace non-printable or non-ASCII characters with spaces */
1325 static inline void ufshcd_remove_non_printable(uint8_t *val)
1326 {
1327 if (!val)
1328 return;
1329
1330 if (*val < 0x20 || *val > 0x7e)
1331 *val = ' ';
1332 }
1333
1334 /**
1335 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
1336 * state) and waits for it to take effect.
1337 *
1338 */
1339 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
1340 {
1341 unsigned long start = 0;
1342 u8 status;
1343 int ret;
1344
1345 ret = ufshcd_send_uic_cmd(hba, cmd);
1346 if (ret) {
1347 dev_err(hba->dev,
1348 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
1349 cmd->command, cmd->argument3, ret);
1350
1351 return ret;
1352 }
1353
1354 start = get_timer(0);
1355 do {
1356 status = ufshcd_get_upmcrs(hba);
1357 if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
1358 dev_err(hba->dev,
1359 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
1360 cmd->command, status);
1361 ret = (status != PWR_OK) ? status : -1;
1362 break;
1363 }
1364 } while (status != PWR_LOCAL);
1365
1366 return ret;
1367 }
1368
1369 /**
1370 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
1371 * using DME_SET primitives.
1372 */
1373 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
1374 {
1375 struct uic_command uic_cmd = {0};
1376 int ret;
1377
1378 uic_cmd.command = UIC_CMD_DME_SET;
1379 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
1380 uic_cmd.argument3 = mode;
1381 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
1382
1383 return ret;
1384 }
1385
1386 static
1387 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
1388 struct scsi_cmd *pccb, u32 upiu_flags)
1389 {
1390 struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
1391 unsigned int cdb_len;
1392
1393 /* command descriptor fields */
1394 ucd_req_ptr->header.dword_0 =
1395 UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
1396 pccb->lun, TASK_TAG);
1397 ucd_req_ptr->header.dword_1 =
1398 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1399
1400 /* Total EHS length and Data segment length will be zero */
1401 ucd_req_ptr->header.dword_2 = 0;
1402
1403 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
1404
1405 cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
1406 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1407 memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
1408
1409 memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
1410 }
1411
1412 static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
1413 unsigned char *buf, ulong len)
1414 {
1415 entry->size = cpu_to_le32(len) | GENMASK(1, 0);
1416 entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
1417 entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
1418 }
1419
1420 static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
1421 {
1422 struct utp_transfer_req_desc *req_desc = hba->utrdl;
1423 struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
1424 ulong datalen = pccb->datalen;
1425 int table_length;
1426 u8 *buf;
1427 int i;
1428
1429 if (!datalen) {
1430 req_desc->prd_table_length = 0;
1431 return;
1432 }
1433
1434 table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
1435 buf = pccb->pdata;
1436 i = table_length;
1437 while (--i) {
1438 prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
1439 MAX_PRDT_ENTRY - 1);
1440 buf += MAX_PRDT_ENTRY;
1441 datalen -= MAX_PRDT_ENTRY;
1442 }
1443
1444 prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
1445
1446 req_desc->prd_table_length = table_length;
1447 }
1448
1449 static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
1450 {
1451 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
1452 struct utp_transfer_req_desc *req_desc = hba->utrdl;
1453 u32 upiu_flags;
1454 int ocs, result = 0;
1455 u8 scsi_status;
1456
1457 ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
1458 ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
1459 prepare_prdt_table(hba, pccb);
1460
1461 ufshcd_send_command(hba, TASK_TAG);
1462
1463 ocs = ufshcd_get_tr_ocs(hba);
1464 switch (ocs) {
1465 case OCS_SUCCESS:
1466 result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
1467 switch (result) {
1468 case UPIU_TRANSACTION_RESPONSE:
1469 result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
1470
1471 scsi_status = result & MASK_SCSI_STATUS;
1472 if (scsi_status)
1473 return -EINVAL;
1474
1475 break;
1476 case UPIU_TRANSACTION_REJECT_UPIU:
1477 /* TODO: handle Reject UPIU Response */
1478 dev_err(hba->dev,
1479 "Reject UPIU not fully implemented\n");
1480 return -EINVAL;
1481 default:
1482 dev_err(hba->dev,
1483 "Unexpected request response code = %x\n",
1484 result);
1485 return -EINVAL;
1486 }
1487 break;
1488 default:
1489 dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
1490 return -EINVAL;
1491 }
1492
1493 return 0;
1494 }
1495
1496 static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
1497 int desc_index, u8 *buf, u32 size)
1498 {
1499 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1500 }
1501
1502 static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
1503 {
1504 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
1505 }
1506
1507 /**
1508 * ufshcd_read_string_desc - read string descriptor
1509 *
1510 */
1511 int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
1512 u8 *buf, u32 size, bool ascii)
1513 {
1514 int err = 0;
1515
1516 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
1517 size);
1518
1519 if (err) {
1520 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
1521 __func__, QUERY_REQ_RETRIES, err);
1522 goto out;
1523 }
1524
1525 if (ascii) {
1526 int desc_len;
1527 int ascii_len;
1528 int i;
1529 u8 *buff_ascii;
1530
1531 desc_len = buf[0];
1532 /* remove header and divide by 2 to move from UTF16 to UTF8 */
1533 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
1534 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
1535 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
1536 __func__);
1537 err = -ENOMEM;
1538 goto out;
1539 }
1540
1541 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
1542 if (!buff_ascii) {
1543 err = -ENOMEM;
1544 goto out;
1545 }
1546
1547 /*
1548 * the descriptor contains string in UTF16 format
1549 * we need to convert to utf-8 so it can be displayed
1550 */
1551 utf16_to_utf8(buff_ascii,
1552 (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
1553
1554 /* replace non-printable or non-ASCII characters with spaces */
1555 for (i = 0; i < ascii_len; i++)
1556 ufshcd_remove_non_printable(&buff_ascii[i]);
1557
1558 memset(buf + QUERY_DESC_HDR_SIZE, 0,
1559 size - QUERY_DESC_HDR_SIZE);
1560 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
1561 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
1562 kfree(buff_ascii);
1563 }
1564 out:
1565 return err;
1566 }
1567
1568 static int ufs_get_device_desc(struct ufs_hba *hba,
1569 struct ufs_dev_desc *dev_desc)
1570 {
1571 int err;
1572 size_t buff_len;
1573 u8 model_index;
1574 u8 *desc_buf;
1575
1576 buff_len = max_t(size_t, hba->desc_size.dev_desc,
1577 QUERY_DESC_MAX_SIZE + 1);
1578 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1579 if (!desc_buf) {
1580 err = -ENOMEM;
1581 goto out;
1582 }
1583
1584 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
1585 if (err) {
1586 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
1587 __func__, err);
1588 goto out;
1589 }
1590
1591 /*
1592 * getting vendor (manufacturerID) and Bank Index in big endian
1593 * format
1594 */
1595 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
1596 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
1597
1598 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
1599
1600 /* Zero-pad entire buffer for string termination. */
1601 memset(desc_buf, 0, buff_len);
1602
1603 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
1604 QUERY_DESC_MAX_SIZE, true/*ASCII*/);
1605 if (err) {
1606 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
1607 __func__, err);
1608 goto out;
1609 }
1610
1611 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
1612 strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
1613 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
1614 MAX_MODEL_LEN));
1615
1616 /* Null terminate the model string */
1617 dev_desc->model[MAX_MODEL_LEN] = '\0';
1618
1619 out:
1620 kfree(desc_buf);
1621 return err;
1622 }
1623
1624 /**
1625 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
1626 */
1627 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
1628 {
1629 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
1630
1631 if (hba->max_pwr_info.is_valid)
1632 return 0;
1633
1634 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
1635 pwr_info->pwr_tx = FASTAUTO_MODE;
1636 pwr_info->pwr_rx = FASTAUTO_MODE;
1637 } else {
1638 pwr_info->pwr_tx = FAST_MODE;
1639 pwr_info->pwr_rx = FAST_MODE;
1640 }
1641 pwr_info->hs_rate = PA_HS_MODE_B;
1642
1643 /* Get the connected lane count */
1644 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
1645 &pwr_info->lane_rx);
1646 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
1647 &pwr_info->lane_tx);
1648
1649 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
1650 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
1651 __func__, pwr_info->lane_rx, pwr_info->lane_tx);
1652 return -EINVAL;
1653 }
1654
1655 /*
1656 * First, get the maximum gears of HS speed.
1657 * If a zero value, it means there is no HSGEAR capability.
1658 * Then, get the maximum gears of PWM speed.
1659 */
1660 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
1661 if (!pwr_info->gear_rx) {
1662 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1663 &pwr_info->gear_rx);
1664 if (!pwr_info->gear_rx) {
1665 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
1666 __func__, pwr_info->gear_rx);
1667 return -EINVAL;
1668 }
1669 pwr_info->pwr_rx = SLOW_MODE;
1670 }
1671
1672 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
1673 &pwr_info->gear_tx);
1674 if (!pwr_info->gear_tx) {
1675 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1676 &pwr_info->gear_tx);
1677 if (!pwr_info->gear_tx) {
1678 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
1679 __func__, pwr_info->gear_tx);
1680 return -EINVAL;
1681 }
1682 pwr_info->pwr_tx = SLOW_MODE;
1683 }
1684
1685 hba->max_pwr_info.is_valid = true;
1686 return 0;
1687 }
1688
1689 static int ufshcd_change_power_mode(struct ufs_hba *hba,
1690 struct ufs_pa_layer_attr *pwr_mode)
1691 {
1692 int ret;
1693
1694 /* if already configured to the requested pwr_mode */
1695 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
1696 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
1697 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
1698 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
1699 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
1700 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
1701 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
1702 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
1703 return 0;
1704 }
1705
1706 /*
1707 * Configure attributes for power mode change with below.
1708 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1709 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1710 * - PA_HSSERIES
1711 */
1712 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
1713 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
1714 pwr_mode->lane_rx);
1715 if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
1716 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
1717 else
1718 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
1719
1720 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
1721 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
1722 pwr_mode->lane_tx);
1723 if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
1724 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
1725 else
1726 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
1727
1728 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
1729 pwr_mode->pwr_tx == FASTAUTO_MODE ||
1730 pwr_mode->pwr_rx == FAST_MODE ||
1731 pwr_mode->pwr_tx == FAST_MODE)
1732 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
1733 pwr_mode->hs_rate);
1734
1735 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
1736 pwr_mode->pwr_tx);
1737
1738 if (ret) {
1739 dev_err(hba->dev,
1740 "%s: power mode change failed %d\n", __func__, ret);
1741
1742 return ret;
1743 }
1744
1745 /* Copy new Power Mode to power info */
1746 memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
1747
1748 return ret;
1749 }
1750
1751 /**
1752 * ufshcd_verify_dev_init() - Verify device initialization
1753 *
1754 */
1755 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
1756 {
1757 int retries;
1758 int err;
1759
1760 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
1761 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1762 NOP_OUT_TIMEOUT);
1763 if (!err || err == -ETIMEDOUT)
1764 break;
1765
1766 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1767 }
1768
1769 if (err)
1770 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
1771
1772 return err;
1773 }
1774
1775 /**
1776 * ufshcd_complete_dev_init() - checks device readiness
1777 */
1778 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
1779 {
1780 int i;
1781 int err;
1782 bool flag_res = 1;
1783
1784 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1785 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
1786 if (err) {
1787 dev_err(hba->dev,
1788 "%s setting fDeviceInit flag failed with error %d\n",
1789 __func__, err);
1790 goto out;
1791 }
1792
1793 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
1794 for (i = 0; i < 1000 && !err && flag_res; i++)
1795 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1796 QUERY_FLAG_IDN_FDEVICEINIT,
1797 &flag_res);
1798
1799 if (err)
1800 dev_err(hba->dev,
1801 "%s reading fDeviceInit flag failed with error %d\n",
1802 __func__, err);
1803 else if (flag_res)
1804 dev_err(hba->dev,
1805 "%s fDeviceInit was not cleared by the device\n",
1806 __func__);
1807
1808 out:
1809 return err;
1810 }
1811
1812 static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
1813 {
1814 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1815 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1816 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1817 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1818 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1819 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1820 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1821 }
1822
1823 int ufs_start(struct ufs_hba *hba)
1824 {
1825 struct ufs_dev_desc card = {0};
1826 int ret;
1827
1828 ret = ufshcd_link_startup(hba);
1829 if (ret)
1830 return ret;
1831
1832 ret = ufshcd_verify_dev_init(hba);
1833 if (ret)
1834 return ret;
1835
1836 ret = ufshcd_complete_dev_init(hba);
1837 if (ret)
1838 return ret;
1839
1840 /* Init check for device descriptor sizes */
1841 ufshcd_init_desc_sizes(hba);
1842
1843 ret = ufs_get_device_desc(hba, &card);
1844 if (ret) {
1845 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
1846 __func__, ret);
1847
1848 return ret;
1849 }
1850
1851 if (ufshcd_get_max_pwr_mode(hba)) {
1852 dev_err(hba->dev,
1853 "%s: Failed getting max supported power mode\n",
1854 __func__);
1855 } else {
1856 ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
1857 if (ret) {
1858 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
1859 __func__, ret);
1860
1861 return ret;
1862 }
1863
1864 printf("Device at %s up at:", hba->dev->name);
1865 ufshcd_print_pwr_info(hba);
1866 }
1867
1868 return 0;
1869 }
1870
1871 int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
1872 {
1873 struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
1874 struct scsi_plat *scsi_plat;
1875 struct udevice *scsi_dev;
1876 int err;
1877
1878 device_find_first_child(ufs_dev, &scsi_dev);
1879 if (!scsi_dev)
1880 return -ENODEV;
1881
1882 scsi_plat = dev_get_uclass_plat(scsi_dev);
1883 scsi_plat->max_id = UFSHCD_MAX_ID;
1884 scsi_plat->max_lun = UFS_MAX_LUNS;
1885 scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
1886
1887 hba->dev = ufs_dev;
1888 hba->ops = hba_ops;
1889 hba->mmio_base = dev_read_addr_ptr(ufs_dev);
1890
1891 /* Set descriptor lengths to specification defaults */
1892 ufshcd_def_desc_sizes(hba);
1893
1894 ufshcd_ops_init(hba);
1895
1896 /* Read capabilties registers */
1897 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1898 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
1899 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
1900
1901 /* Get UFS version supported by the controller */
1902 hba->version = ufshcd_get_ufs_version(hba);
1903 if (hba->version != UFSHCI_VERSION_10 &&
1904 hba->version != UFSHCI_VERSION_11 &&
1905 hba->version != UFSHCI_VERSION_20 &&
1906 hba->version != UFSHCI_VERSION_21)
1907 dev_err(hba->dev, "invalid UFS version 0x%x\n",
1908 hba->version);
1909
1910 /* Get Interrupt bit mask per version */
1911 hba->intr_mask = ufshcd_get_intr_mask(hba);
1912
1913 /* Allocate memory for host memory space */
1914 err = ufshcd_memory_alloc(hba);
1915 if (err) {
1916 dev_err(hba->dev, "Memory allocation failed\n");
1917 return err;
1918 }
1919
1920 /* Configure Local data structures */
1921 ufshcd_host_memory_configure(hba);
1922
1923 /*
1924 * In order to avoid any spurious interrupt immediately after
1925 * registering UFS controller interrupt handler, clear any pending UFS
1926 * interrupt status and disable all the UFS interrupts.
1927 */
1928 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
1929 REG_INTERRUPT_STATUS);
1930 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
1931
1932 err = ufshcd_hba_enable(hba);
1933 if (err) {
1934 dev_err(hba->dev, "Host controller enable failed\n");
1935 return err;
1936 }
1937
1938 err = ufs_start(hba);
1939 if (err)
1940 return err;
1941
1942 return 0;
1943 }
1944
1945 int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
1946 {
1947 int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
1948 scsi_devp);
1949
1950 return ret;
1951 }
1952
1953 #if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
1954 static int ufs_scsi_buffer_aligned(struct udevice *scsi_dev, struct bounce_buffer *state)
1955 {
1956 #ifdef CONFIG_PHYS_64BIT
1957 struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
1958 uintptr_t ubuf = (uintptr_t)state->user_buffer;
1959 size_t len = state->len_aligned;
1960
1961 /* Check if below 32bit boundary */
1962 if ((hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) &&
1963 ((ubuf >> 32) || (ubuf + len) >> 32)) {
1964 dev_dbg(scsi_dev, "Buffer above 32bit boundary %lx-%lx\n",
1965 ubuf, ubuf + len);
1966 return 0;
1967 }
1968 #endif
1969 return 1;
1970 }
1971 #endif /* CONFIG_BOUNCE_BUFFER */
1972
1973 static struct scsi_ops ufs_ops = {
1974 .exec = ufs_scsi_exec,
1975 #if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
1976 .buffer_aligned = ufs_scsi_buffer_aligned,
1977 #endif /* CONFIG_BOUNCE_BUFFER */
1978 };
1979
1980 int ufs_probe_dev(int index)
1981 {
1982 struct udevice *dev;
1983
1984 return uclass_get_device(UCLASS_UFS, index, &dev);
1985 }
1986
1987 int ufs_probe(void)
1988 {
1989 struct udevice *dev;
1990 int ret, i;
1991
1992 for (i = 0;; i++) {
1993 ret = uclass_get_device(UCLASS_UFS, i, &dev);
1994 if (ret == -ENODEV)
1995 break;
1996 }
1997
1998 return 0;
1999 }
2000
2001 U_BOOT_DRIVER(ufs_scsi) = {
2002 .id = UCLASS_SCSI,
2003 .name = "ufs_scsi",
2004 .ops = &ufs_ops,
2005 };
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