2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
12 * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
14 * SPDX-License-Identifier: GPL-2.0
19 #include <asm/dma-mapping.h>
20 #include <usb/lin_gadget_compat.h>
21 #include <linux/bug.h>
22 #include <linux/list.h>
24 #include <linux/usb/ch9.h>
25 #include <linux/usb/gadget.h>
26 #include <asm/arch/sys_proto.h>
32 #include "linux-compat.h"
35 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
36 * @dwc: pointer to our context structure
37 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
39 * Caller should take care of locking. This function will
40 * return 0 on success or -EINVAL if wrong Test Selector
43 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
47 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
48 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
62 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
68 * dwc3_gadget_get_link_state - Gets current state of USB Link
69 * @dwc: pointer to our context structure
71 * Caller should take care of locking. This function will
72 * return the link state on success (>= 0) or -ETIMEDOUT.
74 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
78 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
80 return DWC3_DSTS_USBLNKST(reg
);
84 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
85 * @dwc: pointer to our context structure
86 * @state: the state to put link into
88 * Caller should take care of locking. This function will
89 * return 0 on success or -ETIMEDOUT.
91 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
97 * Wait until device controller is ready. Only applies to 1.94a and
100 if (dwc
->revision
>= DWC3_REVISION_194A
) {
102 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
103 if (reg
& DWC3_DSTS_DCNRD
)
113 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
114 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
116 /* set requested state */
117 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
118 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
121 * The following code is racy when called from dwc3_gadget_wakeup,
122 * and is not needed, at least on newer versions
124 if (dwc
->revision
>= DWC3_REVISION_194A
)
127 /* wait for a change in DSTS */
130 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
132 if (DWC3_DSTS_USBLNKST(reg
) == state
)
138 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
144 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
145 * @dwc: pointer to our context structure
147 * This function will a best effort FIFO allocation in order
148 * to improve FIFO usage and throughput, while still allowing
149 * us to enable as many endpoints as possible.
151 * Keep in mind that this operation will be highly dependent
152 * on the configured size for RAM1 - which contains TxFifo -,
153 * the amount of endpoints enabled on coreConsultant tool, and
154 * the width of the Master Bus.
156 * In the ideal world, we would always be able to satisfy the
157 * following equation:
159 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
160 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
162 * Unfortunately, due to many variables that's not always the case.
164 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
166 int last_fifo_depth
= 0;
171 if (!dwc
->needs_fifo_resize
)
174 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
176 /* MDWIDTH is represented in bits, we need it in bytes */
180 * FIXME For now we will only allocate 1 wMaxPacketSize space
181 * for each enabled endpoint, later patches will come to
182 * improve this algorithm so that we better use the internal
185 for (num
= 0; num
< dwc
->num_in_eps
; num
++) {
186 /* bit0 indicates direction; 1 means IN ep */
187 struct dwc3_ep
*dep
= dwc
->eps
[(num
<< 1) | 1];
191 if (!(dep
->flags
& DWC3_EP_ENABLED
))
194 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
195 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
199 * REVISIT: the following assumes we will always have enough
200 * space available on the FIFO RAM for all possible use cases.
201 * Make sure that's true somehow and change FIFO allocation
204 * If we have Bulk or Isochronous endpoints, we want
205 * them to be able to be very, very fast. So we're giving
206 * those endpoints a fifo_size which is enough for 3 full
209 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
212 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
214 fifo_size
|= (last_fifo_depth
<< 16);
216 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
217 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
219 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(num
), fifo_size
);
221 last_fifo_depth
+= (fifo_size
& 0xffff);
227 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
230 struct dwc3
*dwc
= dep
->dwc
;
235 * Skip LINK TRB. We can't use req->trb and check for
236 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
237 * just completed (not the LINK TRB).
239 if (((dep
->busy_slot
& DWC3_TRB_MASK
) ==
241 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
246 list_del(&req
->list
);
248 dwc3_flush_cache((long)req
->request
.dma
, req
->request
.length
);
250 if (req
->request
.status
== -EINPROGRESS
)
251 req
->request
.status
= status
;
253 if (dwc
->ep0_bounced
&& dep
->number
== 0)
254 dwc
->ep0_bounced
= false;
256 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
259 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
260 req
, dep
->name
, req
->request
.actual
,
261 req
->request
.length
, status
);
263 spin_unlock(&dwc
->lock
);
264 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
265 spin_lock(&dwc
->lock
);
268 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
273 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
274 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
277 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
278 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
279 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
280 DWC3_DGCMD_STATUS(reg
));
285 * We can't sleep here, because it's also called from
295 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
296 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
301 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
302 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
303 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
305 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
307 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
308 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
309 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
310 DWC3_DEPCMD_STATUS(reg
));
315 * We can't sleep here, because it is also called from
326 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
327 struct dwc3_trb
*trb
)
329 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
331 return dep
->trb_pool_dma
+ offset
;
334 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
339 if (dep
->number
== 0 || dep
->number
== 1)
342 dep
->trb_pool
= dma_alloc_coherent(sizeof(struct dwc3_trb
) *
344 (unsigned long *)&dep
->trb_pool_dma
);
345 if (!dep
->trb_pool
) {
346 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
354 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
356 dma_free_coherent(dep
->trb_pool
);
358 dep
->trb_pool
= NULL
;
359 dep
->trb_pool_dma
= 0;
362 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
364 struct dwc3_gadget_ep_cmd_params params
;
367 memset(¶ms
, 0x00, sizeof(params
));
369 if (dep
->number
!= 1) {
370 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
371 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
372 if (dep
->number
> 1) {
373 if (dwc
->start_config_issued
)
375 dwc
->start_config_issued
= true;
376 cmd
|= DWC3_DEPCMD_PARAM(2);
379 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
385 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
386 const struct usb_endpoint_descriptor
*desc
,
387 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
388 bool ignore
, bool restore
)
390 struct dwc3_gadget_ep_cmd_params params
;
392 memset(¶ms
, 0x00, sizeof(params
));
394 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
395 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
397 /* Burst size is only needed in SuperSpeed mode */
398 if (dwc
->gadget
.speed
== USB_SPEED_SUPER
) {
399 u32 burst
= dep
->endpoint
.maxburst
- 1;
401 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
);
405 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
408 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
409 params
.param2
|= dep
->saved_state
;
412 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
413 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
415 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
416 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
417 | DWC3_DEPCFG_STREAM_EVENT_EN
;
418 dep
->stream_capable
= true;
421 if (!usb_endpoint_xfer_control(desc
))
422 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
425 * We are doing 1:1 mapping for endpoints, meaning
426 * Physical Endpoints 2 maps to Logical Endpoint 2 and
427 * so on. We consider the direction bit as part of the physical
428 * endpoint number. So USB endpoint 0x81 is 0x03.
430 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
433 * We must use the lower 16 TX FIFOs even though
437 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
439 if (desc
->bInterval
) {
440 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
441 dep
->interval
= 1 << (desc
->bInterval
- 1);
444 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
445 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
448 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
450 struct dwc3_gadget_ep_cmd_params params
;
452 memset(¶ms
, 0x00, sizeof(params
));
454 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
456 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
457 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
461 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
462 * @dep: endpoint to be initialized
463 * @desc: USB Endpoint Descriptor
465 * Caller should take care of locking
467 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
468 const struct usb_endpoint_descriptor
*desc
,
469 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
470 bool ignore
, bool restore
)
472 struct dwc3
*dwc
= dep
->dwc
;
476 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
478 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
479 ret
= dwc3_gadget_start_config(dwc
, dep
);
484 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
489 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
490 struct dwc3_trb
*trb_st_hw
;
491 struct dwc3_trb
*trb_link
;
493 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
497 dep
->endpoint
.desc
= desc
;
498 dep
->comp_desc
= comp_desc
;
499 dep
->type
= usb_endpoint_type(desc
);
500 dep
->flags
|= DWC3_EP_ENABLED
;
502 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
503 reg
|= DWC3_DALEPENA_EP(dep
->number
);
504 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
506 if (!usb_endpoint_xfer_isoc(desc
))
509 /* Link TRB for ISOC. The HWO bit is never reset */
510 trb_st_hw
= &dep
->trb_pool
[0];
512 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
513 memset(trb_link
, 0, sizeof(*trb_link
));
515 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
516 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
517 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
518 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
524 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
525 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
527 struct dwc3_request
*req
;
529 if (!list_empty(&dep
->req_queued
)) {
530 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
532 /* - giveback all requests to gadget driver */
533 while (!list_empty(&dep
->req_queued
)) {
534 req
= next_request(&dep
->req_queued
);
536 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
540 while (!list_empty(&dep
->request_list
)) {
541 req
= next_request(&dep
->request_list
);
543 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
548 * __dwc3_gadget_ep_disable - Disables a HW endpoint
549 * @dep: the endpoint to disable
551 * This function also removes requests which are currently processed ny the
552 * hardware and those which are not yet scheduled.
553 * Caller should take care of locking.
555 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
557 struct dwc3
*dwc
= dep
->dwc
;
560 dwc3_remove_requests(dwc
, dep
);
562 /* make sure HW endpoint isn't stalled */
563 if (dep
->flags
& DWC3_EP_STALL
)
564 __dwc3_gadget_ep_set_halt(dep
, 0, false);
566 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
567 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
568 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
570 dep
->stream_capable
= false;
571 dep
->endpoint
.desc
= NULL
;
572 dep
->comp_desc
= NULL
;
579 /* -------------------------------------------------------------------------- */
581 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
582 const struct usb_endpoint_descriptor
*desc
)
587 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
592 /* -------------------------------------------------------------------------- */
594 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
595 const struct usb_endpoint_descriptor
*desc
)
601 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
602 pr_debug("dwc3: invalid parameters\n");
606 if (!desc
->wMaxPacketSize
) {
607 pr_debug("dwc3: missing wMaxPacketSize\n");
611 dep
= to_dwc3_ep(ep
);
613 if (dep
->flags
& DWC3_EP_ENABLED
) {
614 WARN(true, "%s is already enabled\n",
619 switch (usb_endpoint_type(desc
)) {
620 case USB_ENDPOINT_XFER_CONTROL
:
621 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
623 case USB_ENDPOINT_XFER_ISOC
:
624 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
626 case USB_ENDPOINT_XFER_BULK
:
627 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
629 case USB_ENDPOINT_XFER_INT
:
630 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
633 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
636 spin_lock_irqsave(&dwc
->lock
, flags
);
637 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
638 spin_unlock_irqrestore(&dwc
->lock
, flags
);
643 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
650 pr_debug("dwc3: invalid parameters\n");
654 dep
= to_dwc3_ep(ep
);
656 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
657 WARN(true, "%s is already disabled\n",
662 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
664 (dep
->number
& 1) ? "in" : "out");
666 spin_lock_irqsave(&dwc
->lock
, flags
);
667 ret
= __dwc3_gadget_ep_disable(dep
);
668 spin_unlock_irqrestore(&dwc
->lock
, flags
);
673 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
676 struct dwc3_request
*req
;
677 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
679 req
= kzalloc(sizeof(*req
), gfp_flags
);
683 req
->epnum
= dep
->number
;
686 return &req
->request
;
689 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
690 struct usb_request
*request
)
692 struct dwc3_request
*req
= to_dwc3_request(request
);
698 * dwc3_prepare_one_trb - setup one TRB from one request
699 * @dep: endpoint for which this request is prepared
700 * @req: dwc3_request pointer
702 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
703 struct dwc3_request
*req
, dma_addr_t dma
,
704 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
706 struct dwc3_trb
*trb
;
708 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
709 dep
->name
, req
, (unsigned long long) dma
,
710 length
, last
? " last" : "",
711 chain
? " chain" : "");
714 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
717 dwc3_gadget_move_request_queued(req
);
719 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
720 req
->start_slot
= dep
->free_slot
& DWC3_TRB_MASK
;
724 /* Skip the LINK-TRB on ISOC */
725 if (((dep
->free_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
726 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
729 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
730 trb
->bpl
= lower_32_bits(dma
);
731 trb
->bph
= upper_32_bits(dma
);
733 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
734 case USB_ENDPOINT_XFER_CONTROL
:
735 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
738 case USB_ENDPOINT_XFER_ISOC
:
740 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
742 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
745 case USB_ENDPOINT_XFER_BULK
:
746 case USB_ENDPOINT_XFER_INT
:
747 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
751 * This is only possible with faulty memory because we
752 * checked it already :)
757 if (!req
->request
.no_interrupt
&& !chain
)
758 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
760 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
761 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
762 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
764 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
768 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
770 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
771 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
773 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
775 dwc3_flush_cache((long)dma
, length
);
776 dwc3_flush_cache((long)trb
, sizeof(*trb
));
780 * dwc3_prepare_trbs - setup TRBs from requests
781 * @dep: endpoint for which requests are being prepared
782 * @starting: true if the endpoint is idle and no requests are queued.
784 * The function goes through the requests list and sets up TRBs for the
785 * transfers. The function returns once there are no more TRBs available or
786 * it runs out of requests.
788 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
790 struct dwc3_request
*req
, *n
;
794 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
796 /* the first request must not be queued */
797 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
799 /* Can't wrap around on a non-isoc EP since there's no link TRB */
800 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
801 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
807 * If busy & slot are equal than it is either full or empty. If we are
808 * starting to process requests then we are empty. Otherwise we are
809 * full and don't do anything
814 trbs_left
= DWC3_TRB_NUM
;
816 * In case we start from scratch, we queue the ISOC requests
817 * starting from slot 1. This is done because we use ring
818 * buffer and have no LST bit to stop us. Instead, we place
819 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
820 * after the first request so we start at slot 1 and have
821 * 7 requests proceed before we hit the first IOC.
822 * Other transfer types don't use the ring buffer and are
823 * processed from the first TRB until the last one. Since we
824 * don't wrap around we have to start at the beginning.
826 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
835 /* The last TRB is a link TRB, not used for xfer */
836 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
839 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
843 dma
= req
->request
.dma
;
844 length
= req
->request
.length
;
846 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
853 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
856 struct dwc3_gadget_ep_cmd_params params
;
857 struct dwc3_request
*req
;
858 struct dwc3
*dwc
= dep
->dwc
;
862 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
863 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
866 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
869 * If we are getting here after a short-out-packet we don't enqueue any
870 * new requests as we try to set the IOC bit only on the last request.
873 if (list_empty(&dep
->req_queued
))
874 dwc3_prepare_trbs(dep
, start_new
);
876 /* req points to the first request which will be sent */
877 req
= next_request(&dep
->req_queued
);
879 dwc3_prepare_trbs(dep
, start_new
);
882 * req points to the first request where HWO changed from 0 to 1
884 req
= next_request(&dep
->req_queued
);
887 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
891 memset(¶ms
, 0, sizeof(params
));
894 params
.param0
= upper_32_bits(req
->trb_dma
);
895 params
.param1
= lower_32_bits(req
->trb_dma
);
896 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
898 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
901 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
902 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
904 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
907 * FIXME we need to iterate over the list of requests
908 * here and stop, unmap, free and del each of the linked
909 * requests instead of what we do now.
911 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
913 list_del(&req
->list
);
917 dep
->flags
|= DWC3_EP_BUSY
;
920 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
922 WARN_ON_ONCE(!dep
->resource_index
);
928 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
929 struct dwc3_ep
*dep
, u32 cur_uf
)
933 if (list_empty(&dep
->request_list
)) {
934 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
936 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
940 /* 4 micro frames in the future */
941 uf
= cur_uf
+ dep
->interval
* 4;
943 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
946 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
947 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
951 mask
= ~(dep
->interval
- 1);
952 cur_uf
= event
->parameters
& mask
;
954 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
957 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
959 struct dwc3
*dwc
= dep
->dwc
;
962 req
->request
.actual
= 0;
963 req
->request
.status
= -EINPROGRESS
;
964 req
->direction
= dep
->direction
;
965 req
->epnum
= dep
->number
;
968 * DWC3 hangs on OUT requests smaller than maxpacket size,
969 * so HACK the request length
971 if (dep
->direction
== 0 &&
972 req
->request
.length
< dep
->endpoint
.maxpacket
)
973 req
->request
.length
= dep
->endpoint
.maxpacket
;
976 * We only add to our list of requests now and
977 * start consuming the list once we get XferNotReady
980 * That way, we avoid doing anything that we don't need
981 * to do now and defer it until the point we receive a
982 * particular token from the Host side.
984 * This will also avoid Host cancelling URBs due to too
987 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
992 list_add_tail(&req
->list
, &dep
->request_list
);
995 * There are a few special cases:
997 * 1. XferNotReady with empty list of requests. We need to kick the
998 * transfer here in that situation, otherwise we will be NAKing
999 * forever. If we get XferNotReady before gadget driver has a
1000 * chance to queue a request, we will ACK the IRQ but won't be
1001 * able to receive the data until the next request is queued.
1002 * The following code is handling exactly that.
1005 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1007 * If xfernotready is already elapsed and it is a case
1008 * of isoc transfer, then issue END TRANSFER, so that
1009 * you can receive xfernotready again and can have
1010 * notion of current microframe.
1012 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1013 if (list_empty(&dep
->req_queued
)) {
1014 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1015 dep
->flags
= DWC3_EP_ENABLED
;
1020 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1021 if (ret
&& ret
!= -EBUSY
)
1022 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1028 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1029 * kick the transfer here after queuing a request, otherwise the
1030 * core may not see the modified TRB(s).
1032 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1033 (dep
->flags
& DWC3_EP_BUSY
) &&
1034 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1035 WARN_ON_ONCE(!dep
->resource_index
);
1036 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1038 if (ret
&& ret
!= -EBUSY
)
1039 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1045 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1046 * right away, otherwise host will not know we have streams to be
1049 if (dep
->stream_capable
) {
1052 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1053 if (ret
&& ret
!= -EBUSY
) {
1054 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1062 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1065 struct dwc3_request
*req
= to_dwc3_request(request
);
1066 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1068 unsigned long flags
;
1072 spin_lock_irqsave(&dwc
->lock
, flags
);
1073 if (!dep
->endpoint
.desc
) {
1074 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1080 if (req
->dep
!= dep
) {
1081 WARN(true, "request %p belongs to '%s'\n",
1082 request
, req
->dep
->name
);
1087 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1088 request
, ep
->name
, request
->length
);
1090 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1093 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1098 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1099 struct usb_request
*request
)
1101 struct dwc3_request
*req
= to_dwc3_request(request
);
1102 struct dwc3_request
*r
= NULL
;
1104 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1105 struct dwc3
*dwc
= dep
->dwc
;
1107 unsigned long flags
;
1110 spin_lock_irqsave(&dwc
->lock
, flags
);
1112 list_for_each_entry(r
, &dep
->request_list
, list
) {
1118 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1123 /* wait until it is processed */
1124 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1127 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1134 /* giveback the request */
1135 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1138 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1143 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1145 struct dwc3_gadget_ep_cmd_params params
;
1146 struct dwc3
*dwc
= dep
->dwc
;
1149 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1150 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1154 memset(¶ms
, 0x00, sizeof(params
));
1157 if (!protocol
&& ((dep
->direction
&& dep
->flags
& DWC3_EP_BUSY
) ||
1158 (!list_empty(&dep
->req_queued
) ||
1159 !list_empty(&dep
->request_list
)))) {
1160 dev_dbg(dwc
->dev
, "%s: pending request, cannot halt\n",
1165 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1166 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1168 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1171 dep
->flags
|= DWC3_EP_STALL
;
1173 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1174 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1176 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1179 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1185 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1187 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1189 unsigned long flags
;
1193 spin_lock_irqsave(&dwc
->lock
, flags
);
1194 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1195 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1200 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1202 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1203 unsigned long flags
;
1206 spin_lock_irqsave(&dwc
->lock
, flags
);
1207 dep
->flags
|= DWC3_EP_WEDGE
;
1209 if (dep
->number
== 0 || dep
->number
== 1)
1210 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1212 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1213 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1218 /* -------------------------------------------------------------------------- */
1220 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1221 .bLength
= USB_DT_ENDPOINT_SIZE
,
1222 .bDescriptorType
= USB_DT_ENDPOINT
,
1223 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1226 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1227 .enable
= dwc3_gadget_ep0_enable
,
1228 .disable
= dwc3_gadget_ep0_disable
,
1229 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1230 .free_request
= dwc3_gadget_ep_free_request
,
1231 .queue
= dwc3_gadget_ep0_queue
,
1232 .dequeue
= dwc3_gadget_ep_dequeue
,
1233 .set_halt
= dwc3_gadget_ep0_set_halt
,
1234 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1237 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1238 .enable
= dwc3_gadget_ep_enable
,
1239 .disable
= dwc3_gadget_ep_disable
,
1240 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1241 .free_request
= dwc3_gadget_ep_free_request
,
1242 .queue
= dwc3_gadget_ep_queue
,
1243 .dequeue
= dwc3_gadget_ep_dequeue
,
1244 .set_halt
= dwc3_gadget_ep_set_halt
,
1245 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1248 /* -------------------------------------------------------------------------- */
1250 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1252 struct dwc3
*dwc
= gadget_to_dwc(g
);
1255 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1256 return DWC3_DSTS_SOFFN(reg
);
1259 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1261 struct dwc3
*dwc
= gadget_to_dwc(g
);
1263 unsigned long timeout
;
1264 unsigned long flags
;
1273 spin_lock_irqsave(&dwc
->lock
, flags
);
1276 * According to the Databook Remote wakeup request should
1277 * be issued only when the device is in early suspend state.
1279 * We can check that via USB Link State bits in DSTS register.
1281 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1283 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1284 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1285 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1290 link_state
= DWC3_DSTS_USBLNKST(reg
);
1292 switch (link_state
) {
1293 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1294 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1297 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1303 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1305 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1309 /* Recent versions do this automatically */
1310 if (dwc
->revision
< DWC3_REVISION_194A
) {
1311 /* write zeroes to Link Change Request */
1312 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1313 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1314 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1317 /* poll until Link State changes to ON */
1321 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1323 /* in HS, means ON */
1324 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1328 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1329 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1334 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1339 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1342 struct dwc3
*dwc
= gadget_to_dwc(g
);
1343 unsigned long flags
;
1345 spin_lock_irqsave(&dwc
->lock
, flags
);
1346 dwc
->is_selfpowered
= !!is_selfpowered
;
1347 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1352 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1357 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1359 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1360 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1361 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1364 if (dwc
->revision
>= DWC3_REVISION_194A
)
1365 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1366 reg
|= DWC3_DCTL_RUN_STOP
;
1368 if (dwc
->has_hibernation
)
1369 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1371 dwc
->pullups_connected
= true;
1373 reg
&= ~DWC3_DCTL_RUN_STOP
;
1375 if (dwc
->has_hibernation
&& !suspend
)
1376 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1378 dwc
->pullups_connected
= false;
1381 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1384 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1386 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1389 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1398 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1400 ? dwc
->gadget_driver
->function
: "no-function",
1401 is_on
? "connect" : "disconnect");
1406 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1408 struct dwc3
*dwc
= gadget_to_dwc(g
);
1409 unsigned long flags
;
1414 spin_lock_irqsave(&dwc
->lock
, flags
);
1415 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1416 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1421 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1425 /* Enable all but Start and End of Frame IRQs */
1426 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1427 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1428 DWC3_DEVTEN_CMDCMPLTEN
|
1429 DWC3_DEVTEN_ERRTICERREN
|
1430 DWC3_DEVTEN_WKUPEVTEN
|
1431 DWC3_DEVTEN_ULSTCNGEN
|
1432 DWC3_DEVTEN_CONNECTDONEEN
|
1433 DWC3_DEVTEN_USBRSTEN
|
1434 DWC3_DEVTEN_DISCONNEVTEN
);
1436 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1439 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1441 /* mask all interrupts */
1442 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1445 static int dwc3_gadget_start(struct usb_gadget
*g
,
1446 struct usb_gadget_driver
*driver
)
1448 struct dwc3
*dwc
= gadget_to_dwc(g
);
1449 struct dwc3_ep
*dep
;
1450 unsigned long flags
;
1454 spin_lock_irqsave(&dwc
->lock
, flags
);
1456 if (dwc
->gadget_driver
) {
1457 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1459 dwc
->gadget_driver
->function
);
1464 dwc
->gadget_driver
= driver
;
1466 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1467 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1470 * WORKAROUND: DWC3 revision < 2.20a have an issue
1471 * which would cause metastability state on Run/Stop
1472 * bit if we try to force the IP to USB2-only mode.
1474 * Because of that, we cannot configure the IP to any
1475 * speed other than the SuperSpeed
1479 * STAR#9000525659: Clock Domain Crossing on DCTL in
1482 if (dwc
->revision
< DWC3_REVISION_220A
) {
1483 reg
|= DWC3_DCFG_SUPERSPEED
;
1485 switch (dwc
->maximum_speed
) {
1487 reg
|= DWC3_DSTS_LOWSPEED
;
1489 case USB_SPEED_FULL
:
1490 reg
|= DWC3_DSTS_FULLSPEED1
;
1492 case USB_SPEED_HIGH
:
1493 reg
|= DWC3_DSTS_HIGHSPEED
;
1495 case USB_SPEED_SUPER
: /* FALLTHROUGH */
1496 case USB_SPEED_UNKNOWN
: /* FALTHROUGH */
1498 reg
|= DWC3_DSTS_SUPERSPEED
;
1501 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1503 dwc
->start_config_issued
= false;
1505 /* Start with SuperSpeed Default */
1506 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1509 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1512 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1517 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1520 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1524 /* begin to receive SETUP packets */
1525 dwc
->ep0state
= EP0_SETUP_PHASE
;
1526 dwc3_ep0_out_start(dwc
);
1528 dwc3_gadget_enable_irq(dwc
);
1530 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1535 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1538 dwc
->gadget_driver
= NULL
;
1541 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1546 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1548 struct dwc3
*dwc
= gadget_to_dwc(g
);
1549 unsigned long flags
;
1551 spin_lock_irqsave(&dwc
->lock
, flags
);
1553 dwc3_gadget_disable_irq(dwc
);
1554 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1555 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1557 dwc
->gadget_driver
= NULL
;
1559 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1564 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1565 .get_frame
= dwc3_gadget_get_frame
,
1566 .wakeup
= dwc3_gadget_wakeup
,
1567 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1568 .pullup
= dwc3_gadget_pullup
,
1569 .udc_start
= dwc3_gadget_start
,
1570 .udc_stop
= dwc3_gadget_stop
,
1573 /* -------------------------------------------------------------------------- */
1575 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1576 u8 num
, u32 direction
)
1578 struct dwc3_ep
*dep
;
1581 for (i
= 0; i
< num
; i
++) {
1582 u8 epnum
= (i
<< 1) | (!!direction
);
1584 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1589 dep
->number
= epnum
;
1590 dep
->direction
= !!direction
;
1591 dwc
->eps
[epnum
] = dep
;
1593 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1594 (epnum
& 1) ? "in" : "out");
1596 dep
->endpoint
.name
= dep
->name
;
1598 dev_vdbg(dwc
->dev
, "initializing %s\n", dep
->name
);
1600 if (epnum
== 0 || epnum
== 1) {
1601 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1602 dep
->endpoint
.maxburst
= 1;
1603 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1605 dwc
->gadget
.ep0
= &dep
->endpoint
;
1609 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1610 dep
->endpoint
.max_streams
= 15;
1611 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1612 list_add_tail(&dep
->endpoint
.ep_list
,
1613 &dwc
->gadget
.ep_list
);
1615 ret
= dwc3_alloc_trb_pool(dep
);
1620 INIT_LIST_HEAD(&dep
->request_list
);
1621 INIT_LIST_HEAD(&dep
->req_queued
);
1627 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1631 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1633 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1635 dev_vdbg(dwc
->dev
, "failed to allocate OUT endpoints\n");
1639 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1641 dev_vdbg(dwc
->dev
, "failed to allocate IN endpoints\n");
1648 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1650 struct dwc3_ep
*dep
;
1653 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1654 dep
= dwc
->eps
[epnum
];
1658 * Physical endpoints 0 and 1 are special; they form the
1659 * bi-directional USB endpoint 0.
1661 * For those two physical endpoints, we don't allocate a TRB
1662 * pool nor do we add them the endpoints list. Due to that, we
1663 * shouldn't do these two operations otherwise we would end up
1664 * with all sorts of bugs when removing dwc3.ko.
1666 if (epnum
!= 0 && epnum
!= 1) {
1667 dwc3_free_trb_pool(dep
);
1668 list_del(&dep
->endpoint
.ep_list
);
1675 /* -------------------------------------------------------------------------- */
1677 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1678 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1679 const struct dwc3_event_depevt
*event
, int status
)
1682 unsigned int s_pkt
= 0;
1683 unsigned int trb_status
;
1685 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1687 * We continue despite the error. There is not much we
1688 * can do. If we don't clean it up we loop forever. If
1689 * we skip the TRB then it gets overwritten after a
1690 * while since we use them in a ring buffer. A BUG()
1691 * would help. Lets hope that if this occurs, someone
1692 * fixes the root cause instead of looking away :)
1694 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1696 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1698 if (dep
->direction
) {
1700 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1701 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1702 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1705 * If missed isoc occurred and there is
1706 * no request queued then issue END
1707 * TRANSFER, so that core generates
1708 * next xfernotready and we will issue
1709 * a fresh START TRANSFER.
1710 * If there are still queued request
1711 * then wait, do not issue either END
1712 * or UPDATE TRANSFER, just attach next
1713 * request in request_list during
1714 * giveback.If any future queued request
1715 * is successfully transferred then we
1716 * will issue UPDATE TRANSFER for all
1717 * request in the request_list.
1719 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1721 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1723 status
= -ECONNRESET
;
1726 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1729 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1734 * We assume here we will always receive the entire data block
1735 * which we should receive. Meaning, if we program RX to
1736 * receive 4K but we receive only 2K, we assume that's all we
1737 * should receive and we simply bounce the request back to the
1738 * gadget driver for further processing.
1740 req
->request
.actual
+= req
->request
.length
- count
;
1743 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1744 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1745 DWC3_TRB_CTRL_HWO
)))
1747 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1748 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1753 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1754 const struct dwc3_event_depevt
*event
, int status
)
1756 struct dwc3_request
*req
;
1757 struct dwc3_trb
*trb
;
1760 req
= next_request(&dep
->req_queued
);
1766 slot
= req
->start_slot
;
1767 if ((slot
== DWC3_TRB_NUM
- 1) &&
1768 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1770 slot
%= DWC3_TRB_NUM
;
1771 trb
= &dep
->trb_pool
[slot
];
1773 dwc3_flush_cache((long)trb
, sizeof(*trb
));
1774 __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
, event
, status
);
1775 dwc3_gadget_giveback(dep
, req
, status
);
1777 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1778 list_empty(&dep
->req_queued
)) {
1779 if (list_empty(&dep
->request_list
)) {
1781 * If there is no entry in request list then do
1782 * not issue END TRANSFER now. Just set PENDING
1783 * flag, so that END TRANSFER is issued when an
1784 * entry is added into request list.
1786 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
1788 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1789 dep
->flags
= DWC3_EP_ENABLED
;
1797 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1798 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1800 unsigned status
= 0;
1803 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1804 status
= -ECONNRESET
;
1806 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1808 dep
->flags
&= ~DWC3_EP_BUSY
;
1811 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1812 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1814 if (dwc
->revision
< DWC3_REVISION_183A
) {
1818 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1821 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1824 if (!list_empty(&dep
->req_queued
))
1828 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1830 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1836 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1837 const struct dwc3_event_depevt
*event
)
1839 struct dwc3_ep
*dep
;
1840 u8 epnum
= event
->endpoint_number
;
1842 dep
= dwc
->eps
[epnum
];
1844 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1847 if (epnum
== 0 || epnum
== 1) {
1848 dwc3_ep0_interrupt(dwc
, event
);
1852 switch (event
->endpoint_event
) {
1853 case DWC3_DEPEVT_XFERCOMPLETE
:
1854 dep
->resource_index
= 0;
1856 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1857 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1862 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1864 case DWC3_DEPEVT_XFERINPROGRESS
:
1865 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1867 case DWC3_DEPEVT_XFERNOTREADY
:
1868 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1869 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1873 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1874 dep
->name
, event
->status
&
1875 DEPEVT_STATUS_TRANSFER_ACTIVE
1877 : "Transfer Not Active");
1879 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1880 if (!ret
|| ret
== -EBUSY
)
1883 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1888 case DWC3_DEPEVT_STREAMEVT
:
1889 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1890 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1895 switch (event
->status
) {
1896 case DEPEVT_STREAMEVT_FOUND
:
1897 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1901 case DEPEVT_STREAMEVT_NOTFOUND
:
1904 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
1907 case DWC3_DEPEVT_RXTXFIFOEVT
:
1908 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
1910 case DWC3_DEPEVT_EPCMDCMPLT
:
1911 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
1916 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
1918 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
1919 spin_unlock(&dwc
->lock
);
1920 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
1921 spin_lock(&dwc
->lock
);
1925 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
1927 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
1928 spin_unlock(&dwc
->lock
);
1929 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
1930 spin_lock(&dwc
->lock
);
1934 static void dwc3_resume_gadget(struct dwc3
*dwc
)
1936 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
1937 spin_unlock(&dwc
->lock
);
1938 dwc
->gadget_driver
->resume(&dwc
->gadget
);
1942 static void dwc3_reset_gadget(struct dwc3
*dwc
)
1944 if (!dwc
->gadget_driver
)
1947 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1948 spin_unlock(&dwc
->lock
);
1949 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
1950 spin_lock(&dwc
->lock
);
1954 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
1956 struct dwc3_ep
*dep
;
1957 struct dwc3_gadget_ep_cmd_params params
;
1961 dep
= dwc
->eps
[epnum
];
1963 if (!dep
->resource_index
)
1967 * NOTICE: We are violating what the Databook says about the
1968 * EndTransfer command. Ideally we would _always_ wait for the
1969 * EndTransfer Command Completion IRQ, but that's causing too
1970 * much trouble synchronizing between us and gadget driver.
1972 * We have discussed this with the IP Provider and it was
1973 * suggested to giveback all requests here, but give HW some
1974 * extra time to synchronize with the interconnect. We're using
1975 * an arbitraty 100us delay for that.
1977 * Note also that a similar handling was tested by Synopsys
1978 * (thanks a lot Paul) and nothing bad has come out of it.
1979 * In short, what we're doing is:
1981 * - Issue EndTransfer WITH CMDIOC bit set
1985 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1986 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
1987 cmd
|= DWC3_DEPCMD_CMDIOC
;
1988 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1989 memset(¶ms
, 0, sizeof(params
));
1990 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1992 dep
->resource_index
= 0;
1993 dep
->flags
&= ~DWC3_EP_BUSY
;
1997 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2001 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2002 struct dwc3_ep
*dep
;
2004 dep
= dwc
->eps
[epnum
];
2008 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2011 dwc3_remove_requests(dwc
, dep
);
2015 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2019 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2020 struct dwc3_ep
*dep
;
2021 struct dwc3_gadget_ep_cmd_params params
;
2024 dep
= dwc
->eps
[epnum
];
2028 if (!(dep
->flags
& DWC3_EP_STALL
))
2031 dep
->flags
&= ~DWC3_EP_STALL
;
2033 memset(¶ms
, 0, sizeof(params
));
2034 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
2035 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
2040 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2044 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2045 reg
&= ~DWC3_DCTL_INITU1ENA
;
2046 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2048 reg
&= ~DWC3_DCTL_INITU2ENA
;
2049 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2051 dwc3_disconnect_gadget(dwc
);
2052 dwc
->start_config_issued
= false;
2054 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2055 dwc
->setup_packet_pending
= false;
2056 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2059 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2064 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2065 * would cause a missing Disconnect Event if there's a
2066 * pending Setup Packet in the FIFO.
2068 * There's no suggested workaround on the official Bug
2069 * report, which states that "unless the driver/application
2070 * is doing any special handling of a disconnect event,
2071 * there is no functional issue".
2073 * Unfortunately, it turns out that we _do_ some special
2074 * handling of a disconnect event, namely complete all
2075 * pending transfers, notify gadget driver of the
2076 * disconnection, and so on.
2078 * Our suggested workaround is to follow the Disconnect
2079 * Event steps here, instead, based on a setup_packet_pending
2080 * flag. Such flag gets set whenever we have a XferNotReady
2081 * event on EP0 and gets cleared on XferComplete for the
2086 * STAR#9000466709: RTL: Device : Disconnect event not
2087 * generated if setup packet pending in FIFO
2089 if (dwc
->revision
< DWC3_REVISION_188A
) {
2090 if (dwc
->setup_packet_pending
)
2091 dwc3_gadget_disconnect_interrupt(dwc
);
2094 dwc3_reset_gadget(dwc
);
2096 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2097 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2098 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2099 dwc
->test_mode
= false;
2101 dwc3_stop_active_transfers(dwc
);
2102 dwc3_clear_stall_all_ep(dwc
);
2103 dwc
->start_config_issued
= false;
2105 /* Reset device address to zero */
2106 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2107 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2108 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2111 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2114 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2117 * We change the clock only at SS but I dunno why I would want to do
2118 * this. Maybe it becomes part of the power saving plan.
2121 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2125 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2126 * each time on Connect Done.
2131 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2132 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2133 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2136 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2138 struct dwc3_ep
*dep
;
2143 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2144 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2147 dwc3_update_ram_clk_sel(dwc
, speed
);
2150 case DWC3_DCFG_SUPERSPEED
:
2152 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2153 * would cause a missing USB3 Reset event.
2155 * In such situations, we should force a USB3 Reset
2156 * event by calling our dwc3_gadget_reset_interrupt()
2161 * STAR#9000483510: RTL: SS : USB3 reset event may
2162 * not be generated always when the link enters poll
2164 if (dwc
->revision
< DWC3_REVISION_190A
)
2165 dwc3_gadget_reset_interrupt(dwc
);
2167 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2168 dwc
->gadget
.ep0
->maxpacket
= 512;
2169 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2171 case DWC3_DCFG_HIGHSPEED
:
2172 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2173 dwc
->gadget
.ep0
->maxpacket
= 64;
2174 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2176 case DWC3_DCFG_FULLSPEED2
:
2177 case DWC3_DCFG_FULLSPEED1
:
2178 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2179 dwc
->gadget
.ep0
->maxpacket
= 64;
2180 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2182 case DWC3_DCFG_LOWSPEED
:
2183 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2184 dwc
->gadget
.ep0
->maxpacket
= 8;
2185 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2189 /* Enable USB2 LPM Capability */
2191 if ((dwc
->revision
> DWC3_REVISION_194A
)
2192 && (speed
!= DWC3_DCFG_SUPERSPEED
)) {
2193 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2194 reg
|= DWC3_DCFG_LPM_CAP
;
2195 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2197 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2198 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2200 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2203 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2204 * DCFG.LPMCap is set, core responses with an ACK and the
2205 * BESL value in the LPM token is less than or equal to LPM
2208 if (dwc
->revision
< DWC3_REVISION_240A
&& dwc
->has_lpm_erratum
)
2209 WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2211 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2212 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2214 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2216 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2217 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2218 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2222 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2225 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2230 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2233 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2238 * Configure PHY via GUSB3PIPECTLn if required.
2240 * Update GTXFIFOSIZn
2242 * In both cases reset values should be sufficient.
2246 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2249 * TODO take core out of low power mode when that's
2253 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2256 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2257 unsigned int evtinfo
)
2259 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2260 unsigned int pwropt
;
2263 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2264 * Hibernation mode enabled which would show up when device detects
2265 * host-initiated U3 exit.
2267 * In that case, device will generate a Link State Change Interrupt
2268 * from U3 to RESUME which is only necessary if Hibernation is
2271 * There are no functional changes due to such spurious event and we
2272 * just need to ignore it.
2276 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2279 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2280 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2281 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2282 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2283 (next
== DWC3_LINK_STATE_RESUME
)) {
2284 dev_vdbg(dwc
->dev
, "ignoring transition U3 -> Resume\n");
2290 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2291 * on the link partner, the USB session might do multiple entry/exit
2292 * of low power states before a transfer takes place.
2294 * Due to this problem, we might experience lower throughput. The
2295 * suggested workaround is to disable DCTL[12:9] bits if we're
2296 * transitioning from U1/U2 to U0 and enable those bits again
2297 * after a transfer completes and there are no pending transfers
2298 * on any of the enabled endpoints.
2300 * This is the first half of that workaround.
2304 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2305 * core send LGO_Ux entering U0
2307 if (dwc
->revision
< DWC3_REVISION_183A
) {
2308 if (next
== DWC3_LINK_STATE_U0
) {
2312 switch (dwc
->link_state
) {
2313 case DWC3_LINK_STATE_U1
:
2314 case DWC3_LINK_STATE_U2
:
2315 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2316 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2317 | DWC3_DCTL_ACCEPTU2ENA
2318 | DWC3_DCTL_INITU1ENA
2319 | DWC3_DCTL_ACCEPTU1ENA
);
2322 dwc
->u1u2
= reg
& u1u2
;
2326 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2336 case DWC3_LINK_STATE_U1
:
2337 if (dwc
->speed
== USB_SPEED_SUPER
)
2338 dwc3_suspend_gadget(dwc
);
2340 case DWC3_LINK_STATE_U2
:
2341 case DWC3_LINK_STATE_U3
:
2342 dwc3_suspend_gadget(dwc
);
2344 case DWC3_LINK_STATE_RESUME
:
2345 dwc3_resume_gadget(dwc
);
2352 dwc
->link_state
= next
;
2355 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2356 unsigned int evtinfo
)
2358 unsigned int is_ss
= evtinfo
& (1UL << 4);
2361 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2362 * have a known issue which can cause USB CV TD.9.23 to fail
2365 * Because of this issue, core could generate bogus hibernation
2366 * events which SW needs to ignore.
2370 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2371 * Device Fallback from SuperSpeed
2373 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2376 /* enter hibernation here */
2379 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2380 const struct dwc3_event_devt
*event
)
2382 switch (event
->type
) {
2383 case DWC3_DEVICE_EVENT_DISCONNECT
:
2384 dwc3_gadget_disconnect_interrupt(dwc
);
2386 case DWC3_DEVICE_EVENT_RESET
:
2387 dwc3_gadget_reset_interrupt(dwc
);
2389 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2390 dwc3_gadget_conndone_interrupt(dwc
);
2392 case DWC3_DEVICE_EVENT_WAKEUP
:
2393 dwc3_gadget_wakeup_interrupt(dwc
);
2395 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2396 if (!dwc
->has_hibernation
) {
2397 WARN(1 ,"unexpected hibernation event\n");
2400 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2402 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2403 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2405 case DWC3_DEVICE_EVENT_EOPF
:
2406 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2408 case DWC3_DEVICE_EVENT_SOF
:
2409 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2411 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2412 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2414 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2415 dev_vdbg(dwc
->dev
, "Command Complete\n");
2417 case DWC3_DEVICE_EVENT_OVERFLOW
:
2418 dev_vdbg(dwc
->dev
, "Overflow\n");
2421 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2425 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2426 const union dwc3_event
*event
)
2428 /* Endpoint IRQ, handle it and return early */
2429 if (event
->type
.is_devspec
== 0) {
2431 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2434 switch (event
->type
.type
) {
2435 case DWC3_EVENT_TYPE_DEV
:
2436 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2438 /* REVISIT what to do with Carkit and I2C events ? */
2440 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2444 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2446 struct dwc3_event_buffer
*evt
;
2447 irqreturn_t ret
= IRQ_NONE
;
2451 evt
= dwc
->ev_buffs
[buf
];
2454 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2458 union dwc3_event event
;
2460 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2462 dwc3_process_event_entry(dwc
, &event
);
2465 * FIXME we wrap around correctly to the next entry as
2466 * almost all entries are 4 bytes in size. There is one
2467 * entry which has 12 bytes which is a regular entry
2468 * followed by 8 bytes data. ATM I don't know how
2469 * things are organized if we get next to the a
2470 * boundary so I worry about that once we try to handle
2473 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2476 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2480 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2483 /* Unmask interrupt */
2484 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2485 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2486 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2491 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
)
2493 struct dwc3
*dwc
= _dwc
;
2494 unsigned long flags
;
2495 irqreturn_t ret
= IRQ_NONE
;
2498 spin_lock_irqsave(&dwc
->lock
, flags
);
2500 for (i
= 0; i
< dwc
->num_event_buffers
; i
++)
2501 ret
|= dwc3_process_event_buf(dwc
, i
);
2503 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2508 static irqreturn_t
dwc3_check_event_buf(struct dwc3
*dwc
, u32 buf
)
2510 struct dwc3_event_buffer
*evt
;
2514 evt
= dwc
->ev_buffs
[buf
];
2516 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2517 count
&= DWC3_GEVNTCOUNT_MASK
;
2522 evt
->flags
|= DWC3_EVENT_PENDING
;
2524 /* Mask interrupt */
2525 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2526 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2527 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2529 return IRQ_WAKE_THREAD
;
2532 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2534 struct dwc3
*dwc
= _dwc
;
2536 irqreturn_t ret
= IRQ_NONE
;
2538 spin_lock(&dwc
->lock
);
2540 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2543 status
= dwc3_check_event_buf(dwc
, i
);
2544 if (status
== IRQ_WAKE_THREAD
)
2548 spin_unlock(&dwc
->lock
);
2554 * dwc3_gadget_init - Initializes gadget related registers
2555 * @dwc: pointer to our controller context structure
2557 * Returns 0 on success otherwise negative errno.
2559 int dwc3_gadget_init(struct dwc3
*dwc
)
2563 dwc
->ctrl_req
= dma_alloc_coherent(sizeof(*dwc
->ctrl_req
),
2564 (unsigned long *)&dwc
->ctrl_req_addr
);
2565 if (!dwc
->ctrl_req
) {
2566 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2571 dwc
->ep0_trb
= dma_alloc_coherent(sizeof(*dwc
->ep0_trb
) * 2,
2572 (unsigned long *)&dwc
->ep0_trb_addr
);
2573 if (!dwc
->ep0_trb
) {
2574 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2579 dwc
->setup_buf
= memalign(CONFIG_SYS_CACHELINE_SIZE
,
2580 DWC3_EP0_BOUNCE_SIZE
);
2581 if (!dwc
->setup_buf
) {
2586 dwc
->ep0_bounce
= dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE
,
2587 (unsigned long *)&dwc
->ep0_bounce_addr
);
2588 if (!dwc
->ep0_bounce
) {
2589 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2594 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2595 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2596 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2597 dwc
->gadget
.name
= "dwc3-gadget";
2600 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2603 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2606 * REVISIT: Here we should clear all pending IRQs to be
2607 * sure we're starting from a well known location.
2610 ret
= dwc3_gadget_init_endpoints(dwc
);
2614 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2616 dev_err(dwc
->dev
, "failed to register udc\n");
2623 dwc3_gadget_free_endpoints(dwc
);
2624 dma_free_coherent(dwc
->ep0_bounce
);
2627 kfree(dwc
->setup_buf
);
2630 dma_free_coherent(dwc
->ep0_trb
);
2633 dma_free_coherent(dwc
->ctrl_req
);
2639 /* -------------------------------------------------------------------------- */
2641 void dwc3_gadget_exit(struct dwc3
*dwc
)
2643 usb_del_gadget_udc(&dwc
->gadget
);
2645 dwc3_gadget_free_endpoints(dwc
);
2647 dma_free_coherent(dwc
->ep0_bounce
);
2649 kfree(dwc
->setup_buf
);
2651 dma_free_coherent(dwc
->ep0_trb
);
2653 dma_free_coherent(dwc
->ctrl_req
);
2657 * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2658 * @dwc: struct dwce *
2660 * Handles ep0 and gadget interrupt
2662 * Should be called from dwc3 core.
2664 void dwc3_gadget_uboot_handle_interrupt(struct dwc3
*dwc
)
2666 int ret
= dwc3_interrupt(0, dwc
);
2668 if (ret
== IRQ_WAKE_THREAD
) {
2670 struct dwc3_event_buffer
*evt
;
2672 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2673 evt
= dwc
->ev_buffs
[i
];
2674 dwc3_flush_cache((long)evt
->buf
, evt
->length
);
2677 dwc3_thread_interrupt(0, dwc
);