1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
45 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
46 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
60 dwc3_gadget_dctl_write_safe(dwc
, reg
);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
76 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
78 return DWC3_DSTS_USBLNKST(reg
);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc
->revision
>= DWC3_REVISION_194A
) {
100 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
101 if (reg
& DWC3_DSTS_DCNRD
)
111 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
112 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
117 /* set requested state */
118 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
119 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (dwc
->revision
>= DWC3_REVISION_194A
)
128 /* wait for a change in DSTS */
131 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
133 if (DWC3_DSTS_USBLNKST(reg
) == state
)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8
*index
)
153 if (*index
== (DWC3_TRB_NUM
- 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
163 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
172 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep
*dep
,
176 struct dwc3_request
*req
, int status
)
178 struct dwc3
*dwc
= dep
->dwc
;
180 list_del(&req
->list
);
182 req
->needs_extra_trb
= false;
184 if (req
->request
.status
== -EINPROGRESS
)
185 req
->request
.status
= status
;
188 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
189 &req
->request
, req
->direction
);
192 trace_dwc3_gadget_giveback(req
);
195 pm_runtime_put(dwc
->dev
);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
211 struct dwc3
*dwc
= dep
->dwc
;
213 dwc3_gadget_del_and_unmap_request(dep
, req
, status
);
214 req
->status
= DWC3_REQUEST_STATUS_COMPLETED
;
216 spin_unlock(&dwc
->lock
);
217 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
218 spin_lock(&dwc
->lock
);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
237 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
238 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
241 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
242 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
243 status
= DWC3_DGCMD_STATUS(reg
);
255 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
260 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
263 * dwc3_send_gadget_ep_cmd - issue an endpoint command
264 * @dep: the endpoint to which the command is going to be issued
265 * @cmd: the command to be issued
266 * @params: parameters to the command
268 * Caller should handle locking. This function will issue @cmd with given
269 * @params to @dep and wait for its completion.
271 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
272 struct dwc3_gadget_ep_cmd_params
*params
)
274 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
275 struct dwc3
*dwc
= dep
->dwc
;
277 u32 saved_config
= 0;
284 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
285 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
288 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
289 * settings. Restore them after the command is completed.
291 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
293 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
294 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
295 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
296 saved_config
|= DWC3_GUSB2PHYCFG_SUSPHY
;
297 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
300 if (reg
& DWC3_GUSB2PHYCFG_ENBLSLPM
) {
301 saved_config
|= DWC3_GUSB2PHYCFG_ENBLSLPM
;
302 reg
&= ~DWC3_GUSB2PHYCFG_ENBLSLPM
;
306 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
309 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
312 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
313 dwc
->link_state
== DWC3_LINK_STATE_U2
||
314 dwc
->link_state
== DWC3_LINK_STATE_U3
);
316 if (unlikely(needs_wakeup
)) {
317 ret
= __dwc3_gadget_wakeup(dwc
);
318 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
323 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
324 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
325 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
328 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329 * not relying on XferNotReady, we can make use of a special "No
330 * Response Update Transfer" command where we should clear both CmdAct
333 * With this, we don't need to wait for command completion and can
334 * straight away issue further commands to the endpoint.
336 * NOTICE: We're making an assumption that control endpoints will never
337 * make use of Update Transfer command. This is a safe assumption
338 * because we can never have more than one request at a time with
339 * Control Endpoints. If anybody changes that assumption, this chunk
340 * needs to be updated accordingly.
342 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
343 !usb_endpoint_xfer_isoc(desc
))
344 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
346 cmd
|= DWC3_DEPCMD_CMDACT
;
348 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
350 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
351 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
352 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
354 switch (cmd_status
) {
358 case DEPEVT_TRANSFER_NO_RESOURCE
:
361 case DEPEVT_TRANSFER_BUS_EXPIRY
:
363 * SW issues START TRANSFER command to
364 * isochronous ep with future frame interval. If
365 * future interval time has already passed when
366 * core receives the command, it will respond
367 * with an error status of 'Bus Expiry'.
369 * Instead of always returning -EINVAL, let's
370 * give a hint to the gadget driver that this is
371 * the case by returning -EAGAIN.
376 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
385 cmd_status
= -ETIMEDOUT
;
388 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
390 if (ret
== 0 && DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
391 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
392 dwc3_gadget_ep_get_transfer_index(dep
);
396 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
398 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
404 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
406 struct dwc3
*dwc
= dep
->dwc
;
407 struct dwc3_gadget_ep_cmd_params params
;
408 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
411 * As of core revision 2.60a the recommended programming model
412 * is to set the ClearPendIN bit when issuing a Clear Stall EP
413 * command for IN endpoints. This is to prevent an issue where
414 * some (non-compliant) hosts may not send ACK TPs for pending
415 * IN transfers due to a mishandled error condition. Synopsys
418 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
419 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
420 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
422 memset(¶ms
, 0, sizeof(params
));
424 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
427 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
428 struct dwc3_trb
*trb
)
430 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
432 return dep
->trb_pool_dma
+ offset
;
435 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
437 struct dwc3
*dwc
= dep
->dwc
;
442 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
443 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
444 &dep
->trb_pool_dma
, GFP_KERNEL
);
445 if (!dep
->trb_pool
) {
446 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
454 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
456 struct dwc3
*dwc
= dep
->dwc
;
458 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
459 dep
->trb_pool
, dep
->trb_pool_dma
);
461 dep
->trb_pool
= NULL
;
462 dep
->trb_pool_dma
= 0;
465 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep
*dep
)
467 struct dwc3_gadget_ep_cmd_params params
;
469 memset(¶ms
, 0x00, sizeof(params
));
471 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
473 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
478 * dwc3_gadget_start_config - configure ep resources
479 * @dep: endpoint that is being enabled
481 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
482 * completion, it will set Transfer Resource for all available endpoints.
484 * The assignment of transfer resources cannot perfectly follow the data book
485 * due to the fact that the controller driver does not have all knowledge of the
486 * configuration in advance. It is given this information piecemeal by the
487 * composite gadget framework after every SET_CONFIGURATION and
488 * SET_INTERFACE. Trying to follow the databook programming model in this
489 * scenario can cause errors. For two reasons:
491 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
492 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
493 * incorrect in the scenario of multiple interfaces.
495 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
496 * endpoint on alt setting (8.1.6).
498 * The following simplified method is used instead:
500 * All hardware endpoints can be assigned a transfer resource and this setting
501 * will stay persistent until either a core reset or hibernation. So whenever we
502 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
503 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
504 * guaranteed that there are as many transfer resources as endpoints.
506 * This function is called for each endpoint when it is being enabled but is
507 * triggered only when called for EP0-out, which always happens first, and which
508 * should only happen in one of the above conditions.
510 static int dwc3_gadget_start_config(struct dwc3_ep
*dep
)
512 struct dwc3_gadget_ep_cmd_params params
;
521 memset(¶ms
, 0x00, sizeof(params
));
522 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
525 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
529 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
530 struct dwc3_ep
*dep
= dwc
->eps
[i
];
535 ret
= dwc3_gadget_set_xfer_resource(dep
);
543 static int dwc3_gadget_set_ep_config(struct dwc3_ep
*dep
, unsigned int action
)
545 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
546 const struct usb_endpoint_descriptor
*desc
;
547 struct dwc3_gadget_ep_cmd_params params
;
548 struct dwc3
*dwc
= dep
->dwc
;
550 comp_desc
= dep
->endpoint
.comp_desc
;
551 desc
= dep
->endpoint
.desc
;
553 memset(¶ms
, 0x00, sizeof(params
));
555 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
556 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
558 /* Burst size is only needed in SuperSpeed mode */
559 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
560 u32 burst
= dep
->endpoint
.maxburst
;
561 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
564 params
.param0
|= action
;
565 if (action
== DWC3_DEPCFG_ACTION_RESTORE
)
566 params
.param2
|= dep
->saved_state
;
568 if (usb_endpoint_xfer_control(desc
))
569 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
571 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
572 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
574 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
575 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
576 | DWC3_DEPCFG_STREAM_EVENT_EN
;
577 dep
->stream_capable
= true;
580 if (!usb_endpoint_xfer_control(desc
))
581 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
584 * We are doing 1:1 mapping for endpoints, meaning
585 * Physical Endpoints 2 maps to Logical Endpoint 2 and
586 * so on. We consider the direction bit as part of the physical
587 * endpoint number. So USB endpoint 0x81 is 0x03.
589 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
592 * We must use the lower 16 TX FIFOs even though
596 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
598 if (desc
->bInterval
) {
599 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
600 dep
->interval
= 1 << (desc
->bInterval
- 1);
603 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
607 * __dwc3_gadget_ep_enable - initializes a hw endpoint
608 * @dep: endpoint to be initialized
609 * @action: one of INIT, MODIFY or RESTORE
611 * Caller should take care of locking. Execute all necessary commands to
612 * initialize a HW endpoint so it can be used by a gadget driver.
614 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
, unsigned int action
)
616 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
617 struct dwc3
*dwc
= dep
->dwc
;
622 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
623 ret
= dwc3_gadget_start_config(dep
);
628 ret
= dwc3_gadget_set_ep_config(dep
, action
);
632 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
633 struct dwc3_trb
*trb_st_hw
;
634 struct dwc3_trb
*trb_link
;
636 dep
->type
= usb_endpoint_type(desc
);
637 dep
->flags
|= DWC3_EP_ENABLED
;
639 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
640 reg
|= DWC3_DALEPENA_EP(dep
->number
);
641 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
643 if (usb_endpoint_xfer_control(desc
))
646 /* Initialize the TRB ring */
647 dep
->trb_dequeue
= 0;
648 dep
->trb_enqueue
= 0;
649 memset(dep
->trb_pool
, 0,
650 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
652 /* Link TRB. The HWO bit is never reset */
653 trb_st_hw
= &dep
->trb_pool
[0];
655 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
656 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
657 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
658 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
659 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
663 * Issue StartTransfer here with no-op TRB so we can always rely on No
664 * Response Update Transfer command.
666 if ((usb_endpoint_xfer_bulk(desc
) && !dep
->stream_capable
) ||
667 usb_endpoint_xfer_int(desc
)) {
668 struct dwc3_gadget_ep_cmd_params params
;
669 struct dwc3_trb
*trb
;
673 memset(¶ms
, 0, sizeof(params
));
674 trb
= &dep
->trb_pool
[0];
675 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
677 params
.param0
= upper_32_bits(trb_dma
);
678 params
.param1
= lower_32_bits(trb_dma
);
680 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
682 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
688 trace_dwc3_gadget_ep_enable(dep
);
693 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
,
695 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
697 struct dwc3_request
*req
;
699 dwc3_stop_active_transfer(dep
, true, false);
701 /* - giveback all requests to gadget driver */
702 while (!list_empty(&dep
->started_list
)) {
703 req
= next_request(&dep
->started_list
);
705 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
708 while (!list_empty(&dep
->pending_list
)) {
709 req
= next_request(&dep
->pending_list
);
711 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
714 while (!list_empty(&dep
->cancelled_list
)) {
715 req
= next_request(&dep
->cancelled_list
);
717 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
722 * __dwc3_gadget_ep_disable - disables a hw endpoint
723 * @dep: the endpoint to disable
725 * This function undoes what __dwc3_gadget_ep_enable did and also removes
726 * requests which are currently being processed by the hardware and those which
727 * are not yet scheduled.
729 * Caller should take care of locking.
731 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
733 struct dwc3
*dwc
= dep
->dwc
;
736 trace_dwc3_gadget_ep_disable(dep
);
738 dwc3_remove_requests(dwc
, dep
);
740 /* make sure HW endpoint isn't stalled */
741 if (dep
->flags
& DWC3_EP_STALL
)
742 __dwc3_gadget_ep_set_halt(dep
, 0, false);
744 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
745 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
746 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
748 dep
->stream_capable
= false;
752 /* Clear out the ep descriptors for non-ep0 */
753 if (dep
->number
> 1) {
754 dep
->endpoint
.comp_desc
= NULL
;
755 dep
->endpoint
.desc
= NULL
;
761 /* -------------------------------------------------------------------------- */
763 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
764 const struct usb_endpoint_descriptor
*desc
)
769 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
774 /* -------------------------------------------------------------------------- */
776 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
777 const struct usb_endpoint_descriptor
*desc
)
784 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
785 pr_debug("dwc3: invalid parameters\n");
789 if (!desc
->wMaxPacketSize
) {
790 pr_debug("dwc3: missing wMaxPacketSize\n");
794 dep
= to_dwc3_ep(ep
);
797 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
798 "%s is already enabled\n",
802 spin_lock_irqsave(&dwc
->lock
, flags
);
803 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
804 spin_unlock_irqrestore(&dwc
->lock
, flags
);
809 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
817 pr_debug("dwc3: invalid parameters\n");
821 dep
= to_dwc3_ep(ep
);
824 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
825 "%s is already disabled\n",
829 spin_lock_irqsave(&dwc
->lock
, flags
);
830 ret
= __dwc3_gadget_ep_disable(dep
);
831 spin_unlock_irqrestore(&dwc
->lock
, flags
);
836 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
839 struct dwc3_request
*req
;
840 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
842 req
= kzalloc(sizeof(*req
), gfp_flags
);
846 req
->direction
= dep
->direction
;
847 req
->epnum
= dep
->number
;
849 req
->status
= DWC3_REQUEST_STATUS_UNKNOWN
;
851 trace_dwc3_alloc_request(req
);
853 return &req
->request
;
856 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
857 struct usb_request
*request
)
859 struct dwc3_request
*req
= to_dwc3_request(request
);
861 trace_dwc3_free_request(req
);
866 * dwc3_ep_prev_trb - returns the previous TRB in the ring
867 * @dep: The endpoint with the TRB ring
868 * @index: The index of the current TRB in the ring
870 * Returns the TRB prior to the one pointed to by the index. If the
871 * index is 0, we will wrap backwards, skip the link TRB, and return
872 * the one just before that.
874 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
879 tmp
= DWC3_TRB_NUM
- 1;
881 return &dep
->trb_pool
[tmp
- 1];
884 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
886 struct dwc3_trb
*tmp
;
890 * If enqueue & dequeue are equal than it is either full or empty.
892 * One way to know for sure is if the TRB right before us has HWO bit
893 * set or not. If it has, then we're definitely full and can't fit any
894 * more transfers in our ring.
896 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
897 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
898 if (tmp
->ctrl
& DWC3_TRB_CTRL_HWO
)
901 return DWC3_TRB_NUM
- 1;
904 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
905 trbs_left
&= (DWC3_TRB_NUM
- 1);
907 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
913 static void __dwc3_prepare_one_trb(struct dwc3_ep
*dep
, struct dwc3_trb
*trb
,
914 dma_addr_t dma
, unsigned length
, unsigned chain
, unsigned node
,
915 unsigned stream_id
, unsigned short_not_ok
, unsigned no_interrupt
)
917 struct dwc3
*dwc
= dep
->dwc
;
918 struct usb_gadget
*gadget
= &dwc
->gadget
;
919 enum usb_device_speed speed
= gadget
->speed
;
921 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
922 trb
->bpl
= lower_32_bits(dma
);
923 trb
->bph
= upper_32_bits(dma
);
925 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
926 case USB_ENDPOINT_XFER_CONTROL
:
927 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
930 case USB_ENDPOINT_XFER_ISOC
:
932 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
935 * USB Specification 2.0 Section 5.9.2 states that: "If
936 * there is only a single transaction in the microframe,
937 * only a DATA0 data packet PID is used. If there are
938 * two transactions per microframe, DATA1 is used for
939 * the first transaction data packet and DATA0 is used
940 * for the second transaction data packet. If there are
941 * three transactions per microframe, DATA2 is used for
942 * the first transaction data packet, DATA1 is used for
943 * the second, and DATA0 is used for the third."
945 * IOW, we should satisfy the following cases:
947 * 1) length <= maxpacket
950 * 2) maxpacket < length <= (2 * maxpacket)
953 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
954 * - DATA2, DATA1, DATA0
956 if (speed
== USB_SPEED_HIGH
) {
957 struct usb_ep
*ep
= &dep
->endpoint
;
958 unsigned int mult
= 2;
959 unsigned int maxp
= usb_endpoint_maxp(ep
->desc
);
961 if (length
<= (2 * maxp
))
967 trb
->size
|= DWC3_TRB_SIZE_PCM1(mult
);
970 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
973 /* always enable Interrupt on Missed ISOC */
974 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
977 case USB_ENDPOINT_XFER_BULK
:
978 case USB_ENDPOINT_XFER_INT
:
979 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
983 * This is only possible with faulty memory because we
984 * checked it already :)
986 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
987 usb_endpoint_type(dep
->endpoint
.desc
));
991 * Enable Continue on Short Packet
992 * when endpoint is not a stream capable
994 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
995 if (!dep
->stream_capable
)
996 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
999 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
1002 if ((!no_interrupt
&& !chain
) ||
1003 (dwc3_calc_trbs_left(dep
) == 1))
1004 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
1007 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
1009 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
1010 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(stream_id
);
1012 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
1014 dwc3_ep_inc_enq(dep
);
1016 trace_dwc3_prepare_trb(dep
, trb
);
1020 * dwc3_prepare_one_trb - setup one TRB from one request
1021 * @dep: endpoint for which this request is prepared
1022 * @req: dwc3_request pointer
1023 * @chain: should this TRB be chained to the next?
1024 * @node: only for isochronous endpoints. First TRB needs different type.
1026 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
1027 struct dwc3_request
*req
, unsigned chain
, unsigned node
)
1029 struct dwc3_trb
*trb
;
1030 unsigned int length
;
1032 unsigned stream_id
= req
->request
.stream_id
;
1033 unsigned short_not_ok
= req
->request
.short_not_ok
;
1034 unsigned no_interrupt
= req
->request
.no_interrupt
;
1036 if (req
->request
.num_sgs
> 0) {
1037 length
= sg_dma_len(req
->start_sg
);
1038 dma
= sg_dma_address(req
->start_sg
);
1040 length
= req
->request
.length
;
1041 dma
= req
->request
.dma
;
1044 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1047 dwc3_gadget_move_started_request(req
);
1049 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
1054 __dwc3_prepare_one_trb(dep
, trb
, dma
, length
, chain
, node
,
1055 stream_id
, short_not_ok
, no_interrupt
);
1058 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
1059 struct dwc3_request
*req
)
1061 struct scatterlist
*sg
= req
->start_sg
;
1062 struct scatterlist
*s
;
1065 unsigned int remaining
= req
->request
.num_mapped_sgs
1066 - req
->num_queued_sgs
;
1068 for_each_sg(sg
, s
, remaining
, i
) {
1069 unsigned int length
= req
->request
.length
;
1070 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1071 unsigned int rem
= length
% maxp
;
1072 unsigned chain
= true;
1075 * IOMMU driver is coalescing the list of sgs which shares a
1076 * page boundary into one and giving it to USB driver. With
1077 * this the number of sgs mapped is not equal to the number of
1078 * sgs passed. So mark the chain bit to false if it isthe last
1081 if (i
== remaining
- 1)
1084 if (rem
&& usb_endpoint_dir_out(dep
->endpoint
.desc
) && !chain
) {
1085 struct dwc3
*dwc
= dep
->dwc
;
1086 struct dwc3_trb
*trb
;
1088 req
->needs_extra_trb
= true;
1090 /* prepare normal TRB */
1091 dwc3_prepare_one_trb(dep
, req
, true, i
);
1093 /* Now prepare one extra TRB to align transfer size */
1094 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1096 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
,
1097 maxp
- rem
, false, 1,
1098 req
->request
.stream_id
,
1099 req
->request
.short_not_ok
,
1100 req
->request
.no_interrupt
);
1102 dwc3_prepare_one_trb(dep
, req
, chain
, i
);
1106 * There can be a situation where all sgs in sglist are not
1107 * queued because of insufficient trb number. To handle this
1108 * case, update start_sg to next sg to be queued, so that
1109 * we have free trbs we can continue queuing from where we
1110 * previously stopped
1113 req
->start_sg
= sg_next(s
);
1115 req
->num_queued_sgs
++;
1117 if (!dwc3_calc_trbs_left(dep
))
1122 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
1123 struct dwc3_request
*req
)
1125 unsigned int length
= req
->request
.length
;
1126 unsigned int maxp
= usb_endpoint_maxp(dep
->endpoint
.desc
);
1127 unsigned int rem
= length
% maxp
;
1129 if ((!length
|| rem
) && usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
1130 struct dwc3
*dwc
= dep
->dwc
;
1131 struct dwc3_trb
*trb
;
1133 req
->needs_extra_trb
= true;
1135 /* prepare normal TRB */
1136 dwc3_prepare_one_trb(dep
, req
, true, 0);
1138 /* Now prepare one extra TRB to align transfer size */
1139 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1141 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, maxp
- rem
,
1142 false, 1, req
->request
.stream_id
,
1143 req
->request
.short_not_ok
,
1144 req
->request
.no_interrupt
);
1145 } else if (req
->request
.zero
&& req
->request
.length
&&
1146 (IS_ALIGNED(req
->request
.length
, maxp
))) {
1147 struct dwc3
*dwc
= dep
->dwc
;
1148 struct dwc3_trb
*trb
;
1150 req
->needs_extra_trb
= true;
1152 /* prepare normal TRB */
1153 dwc3_prepare_one_trb(dep
, req
, true, 0);
1155 /* Now prepare one extra TRB to handle ZLP */
1156 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
1158 __dwc3_prepare_one_trb(dep
, trb
, dwc
->bounce_addr
, 0,
1159 false, 1, req
->request
.stream_id
,
1160 req
->request
.short_not_ok
,
1161 req
->request
.no_interrupt
);
1163 dwc3_prepare_one_trb(dep
, req
, false, 0);
1168 * dwc3_prepare_trbs - setup TRBs from requests
1169 * @dep: endpoint for which requests are being prepared
1171 * The function goes through the requests list and sets up TRBs for the
1172 * transfers. The function returns once there are no more TRBs available or
1173 * it runs out of requests.
1175 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1177 struct dwc3_request
*req
, *n
;
1179 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1182 * We can get in a situation where there's a request in the started list
1183 * but there weren't enough TRBs to fully kick it in the first time
1184 * around, so it has been waiting for more TRBs to be freed up.
1186 * In that case, we should check if we have a request with pending_sgs
1187 * in the started list and prepare TRBs for that request first,
1188 * otherwise we will prepare TRBs completely out of order and that will
1191 list_for_each_entry(req
, &dep
->started_list
, list
) {
1192 if (req
->num_pending_sgs
> 0)
1193 dwc3_prepare_one_trb_sg(dep
, req
);
1195 if (!dwc3_calc_trbs_left(dep
))
1199 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1200 struct dwc3
*dwc
= dep
->dwc
;
1203 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1208 req
->sg
= req
->request
.sg
;
1209 req
->start_sg
= req
->sg
;
1210 req
->num_queued_sgs
= 0;
1211 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1213 if (req
->num_pending_sgs
> 0)
1214 dwc3_prepare_one_trb_sg(dep
, req
);
1216 dwc3_prepare_one_trb_linear(dep
, req
);
1218 if (!dwc3_calc_trbs_left(dep
))
1223 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
)
1225 struct dwc3_gadget_ep_cmd_params params
;
1226 struct dwc3_request
*req
;
1231 if (!dwc3_calc_trbs_left(dep
))
1234 starting
= !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
);
1236 dwc3_prepare_trbs(dep
);
1237 req
= next_request(&dep
->started_list
);
1239 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1243 memset(¶ms
, 0, sizeof(params
));
1246 params
.param0
= upper_32_bits(req
->trb_dma
);
1247 params
.param1
= lower_32_bits(req
->trb_dma
);
1248 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1250 if (dep
->stream_capable
)
1251 cmd
|= DWC3_DEPCMD_PARAM(req
->request
.stream_id
);
1253 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1254 cmd
|= DWC3_DEPCMD_PARAM(dep
->frame_number
);
1256 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1257 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1260 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1263 * FIXME we need to iterate over the list of requests
1264 * here and stop, unmap, free and del each of the linked
1265 * requests instead of what we do now.
1268 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1269 dwc3_gadget_del_and_unmap_request(dep
, req
, ret
);
1276 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1280 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1281 return DWC3_DSTS_SOFFN(reg
);
1285 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1286 * @dep: isoc endpoint
1288 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1289 * microframe number reported by the XferNotReady event for the future frame
1290 * number to start the isoc transfer.
1292 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1293 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1294 * XferNotReady event are invalid. The driver uses this number to schedule the
1295 * isochronous transfer and passes it to the START TRANSFER command. Because
1296 * this number is invalid, the command may fail. If BIT[15:14] matches the
1297 * internal 16-bit microframe, the START TRANSFER command will pass and the
1298 * transfer will start at the scheduled time, if it is off by 1, the command
1299 * will still pass, but the transfer will start 2 seconds in the future. For all
1300 * other conditions, the START TRANSFER command will fail with bus-expiry.
1302 * In order to workaround this issue, we can test for the correct combination of
1303 * BIT[15:14] by sending START TRANSFER commands with different values of
1304 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1305 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1306 * As the result, within the 4 possible combinations for BIT[15:14], there will
1307 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1308 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1309 * value is the correct combination.
1311 * Since there are only 4 outcomes and the results are ordered, we can simply
1312 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1313 * deduce the smaller successful combination.
1315 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1316 * of BIT[15:14]. The correct combination is as follow:
1318 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1319 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1320 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1321 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1323 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1326 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep
*dep
)
1332 while (dep
->combo_num
< 2) {
1333 struct dwc3_gadget_ep_cmd_params params
;
1334 u32 test_frame_number
;
1338 * Check if we can start isoc transfer on the next interval or
1339 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1341 test_frame_number
= dep
->frame_number
& 0x3fff;
1342 test_frame_number
|= dep
->combo_num
<< 14;
1343 test_frame_number
+= max_t(u32
, 4, dep
->interval
);
1345 params
.param0
= upper_32_bits(dep
->dwc
->bounce_addr
);
1346 params
.param1
= lower_32_bits(dep
->dwc
->bounce_addr
);
1348 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
1349 cmd
|= DWC3_DEPCMD_PARAM(test_frame_number
);
1350 cmd_status
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1352 /* Redo if some other failure beside bus-expiry is received */
1353 if (cmd_status
&& cmd_status
!= -EAGAIN
) {
1354 dep
->start_cmd_status
= 0;
1359 /* Store the first test status */
1360 if (dep
->combo_num
== 0)
1361 dep
->start_cmd_status
= cmd_status
;
1366 * End the transfer if the START_TRANSFER command is successful
1367 * to wait for the next XferNotReady to test the command again
1369 if (cmd_status
== 0) {
1370 dwc3_stop_active_transfer(dep
, true, true);
1375 /* test0 and test1 are both completed at this point */
1376 test0
= (dep
->start_cmd_status
== 0);
1377 test1
= (cmd_status
== 0);
1379 if (!test0
&& test1
)
1381 else if (!test0
&& !test1
)
1383 else if (test0
&& !test1
)
1385 else if (test0
&& test1
)
1388 dep
->frame_number
&= 0x3fff;
1389 dep
->frame_number
|= dep
->combo_num
<< 14;
1390 dep
->frame_number
+= max_t(u32
, 4, dep
->interval
);
1392 /* Reinitialize test variables */
1393 dep
->start_cmd_status
= 0;
1396 return __dwc3_gadget_kick_transfer(dep
);
1399 static int __dwc3_gadget_start_isoc(struct dwc3_ep
*dep
)
1401 struct dwc3
*dwc
= dep
->dwc
;
1405 if (list_empty(&dep
->pending_list
)) {
1406 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1410 if (!dwc
->dis_start_transfer_quirk
&& dwc3_is_usb31(dwc
) &&
1411 (dwc
->revision
<= DWC3_USB31_REVISION_160A
||
1412 (dwc
->revision
== DWC3_USB31_REVISION_170A
&&
1413 dwc
->version_type
>= DWC31_VERSIONTYPE_EA01
&&
1414 dwc
->version_type
<= DWC31_VERSIONTYPE_EA06
))) {
1416 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
&& dep
->direction
)
1417 return dwc3_gadget_start_isoc_quirk(dep
);
1420 for (i
= 0; i
< DWC3_ISOC_MAX_RETRIES
; i
++) {
1421 dep
->frame_number
= DWC3_ALIGN_FRAME(dep
, i
+ 1);
1423 ret
= __dwc3_gadget_kick_transfer(dep
);
1431 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1433 struct dwc3
*dwc
= dep
->dwc
;
1435 if (!dep
->endpoint
.desc
) {
1436 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1441 if (WARN(req
->dep
!= dep
, "request %pK belongs to '%s'\n",
1442 &req
->request
, req
->dep
->name
))
1445 if (WARN(req
->status
< DWC3_REQUEST_STATUS_COMPLETED
,
1446 "%s: request %pK already in flight\n",
1447 dep
->name
, &req
->request
))
1450 pm_runtime_get(dwc
->dev
);
1452 req
->request
.actual
= 0;
1453 req
->request
.status
= -EINPROGRESS
;
1455 trace_dwc3_ep_queue(req
);
1457 list_add_tail(&req
->list
, &dep
->pending_list
);
1458 req
->status
= DWC3_REQUEST_STATUS_QUEUED
;
1460 /* Start the transfer only after the END_TRANSFER is completed */
1461 if (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) {
1462 dep
->flags
|= DWC3_EP_DELAY_START
;
1467 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1468 * wait for a XferNotReady event so we will know what's the current
1469 * (micro-)frame number.
1471 * Without this trick, we are very, very likely gonna get Bus Expiry
1472 * errors which will force us issue EndTransfer command.
1474 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1475 if (!(dep
->flags
& DWC3_EP_PENDING_REQUEST
) &&
1476 !(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
1479 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1480 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
)) {
1481 return __dwc3_gadget_start_isoc(dep
);
1486 return __dwc3_gadget_kick_transfer(dep
);
1489 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1492 struct dwc3_request
*req
= to_dwc3_request(request
);
1493 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1494 struct dwc3
*dwc
= dep
->dwc
;
1496 unsigned long flags
;
1500 spin_lock_irqsave(&dwc
->lock
, flags
);
1501 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1502 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1507 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1512 * If request was already started, this means we had to
1513 * stop the transfer. With that we also need to ignore
1514 * all TRBs used by the request, however TRBs can only
1515 * be modified after completion of END_TRANSFER
1516 * command. So what we do here is that we wait for
1517 * END_TRANSFER completion and only after that, we jump
1518 * over TRBs by clearing HWO and incrementing dequeue
1521 for (i
= 0; i
< req
->num_trbs
; i
++) {
1522 struct dwc3_trb
*trb
;
1524 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
1525 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
1526 dwc3_ep_inc_deq(dep
);
1532 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep
*dep
)
1534 struct dwc3_request
*req
;
1535 struct dwc3_request
*tmp
;
1537 list_for_each_entry_safe(req
, tmp
, &dep
->cancelled_list
, list
) {
1538 dwc3_gadget_ep_skip_trbs(dep
, req
);
1539 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1543 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1544 struct usb_request
*request
)
1546 struct dwc3_request
*req
= to_dwc3_request(request
);
1547 struct dwc3_request
*r
= NULL
;
1549 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1550 struct dwc3
*dwc
= dep
->dwc
;
1552 unsigned long flags
;
1555 trace_dwc3_ep_dequeue(req
);
1557 spin_lock_irqsave(&dwc
->lock
, flags
);
1559 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1565 list_for_each_entry(r
, &dep
->started_list
, list
) {
1570 /* wait until it is processed */
1571 dwc3_stop_active_transfer(dep
, true, true);
1576 dwc3_gadget_move_cancelled_request(req
);
1577 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
)
1582 dev_err(dwc
->dev
, "request %pK was not queued to %s\n",
1589 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1592 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1597 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1599 struct dwc3_gadget_ep_cmd_params params
;
1600 struct dwc3
*dwc
= dep
->dwc
;
1603 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1604 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1608 memset(¶ms
, 0x00, sizeof(params
));
1611 struct dwc3_trb
*trb
;
1613 unsigned transfer_in_flight
;
1616 if (dep
->number
> 1)
1617 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1619 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1621 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1622 started
= !list_empty(&dep
->started_list
);
1624 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1625 (!dep
->direction
&& started
))) {
1629 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1632 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1635 dep
->flags
|= DWC3_EP_STALL
;
1638 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1640 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1643 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1649 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1651 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1652 struct dwc3
*dwc
= dep
->dwc
;
1654 unsigned long flags
;
1658 spin_lock_irqsave(&dwc
->lock
, flags
);
1659 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1660 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1665 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1667 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1668 struct dwc3
*dwc
= dep
->dwc
;
1669 unsigned long flags
;
1672 spin_lock_irqsave(&dwc
->lock
, flags
);
1673 dep
->flags
|= DWC3_EP_WEDGE
;
1675 if (dep
->number
== 0 || dep
->number
== 1)
1676 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1678 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1679 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1684 /* -------------------------------------------------------------------------- */
1686 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1687 .bLength
= USB_DT_ENDPOINT_SIZE
,
1688 .bDescriptorType
= USB_DT_ENDPOINT
,
1689 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1692 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1693 .enable
= dwc3_gadget_ep0_enable
,
1694 .disable
= dwc3_gadget_ep0_disable
,
1695 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1696 .free_request
= dwc3_gadget_ep_free_request
,
1697 .queue
= dwc3_gadget_ep0_queue
,
1698 .dequeue
= dwc3_gadget_ep_dequeue
,
1699 .set_halt
= dwc3_gadget_ep0_set_halt
,
1700 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1703 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1704 .enable
= dwc3_gadget_ep_enable
,
1705 .disable
= dwc3_gadget_ep_disable
,
1706 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1707 .free_request
= dwc3_gadget_ep_free_request
,
1708 .queue
= dwc3_gadget_ep_queue
,
1709 .dequeue
= dwc3_gadget_ep_dequeue
,
1710 .set_halt
= dwc3_gadget_ep_set_halt
,
1711 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1714 /* -------------------------------------------------------------------------- */
1716 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1718 struct dwc3
*dwc
= gadget_to_dwc(g
);
1720 return __dwc3_gadget_get_frame(dwc
);
1723 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1733 * According to the Databook Remote wakeup request should
1734 * be issued only when the device is in early suspend state.
1736 * We can check that via USB Link State bits in DSTS register.
1738 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1740 link_state
= DWC3_DSTS_USBLNKST(reg
);
1742 switch (link_state
) {
1743 case DWC3_LINK_STATE_RESET
:
1744 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1745 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1746 case DWC3_LINK_STATE_RESUME
:
1752 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1754 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1758 /* Recent versions do this automatically */
1759 if (dwc
->revision
< DWC3_REVISION_194A
) {
1760 /* write zeroes to Link Change Request */
1761 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1762 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1763 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1766 /* poll until Link State changes to ON */
1770 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1772 /* in HS, means ON */
1773 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1777 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1778 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1785 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1787 struct dwc3
*dwc
= gadget_to_dwc(g
);
1788 unsigned long flags
;
1791 spin_lock_irqsave(&dwc
->lock
, flags
);
1792 ret
= __dwc3_gadget_wakeup(dwc
);
1793 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1798 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1801 struct dwc3
*dwc
= gadget_to_dwc(g
);
1802 unsigned long flags
;
1804 spin_lock_irqsave(&dwc
->lock
, flags
);
1805 g
->is_selfpowered
= !!is_selfpowered
;
1806 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1811 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1816 if (pm_runtime_suspended(dwc
->dev
))
1819 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1821 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1822 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1823 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1826 if (dwc
->revision
>= DWC3_REVISION_194A
)
1827 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1828 reg
|= DWC3_DCTL_RUN_STOP
;
1830 if (dwc
->has_hibernation
)
1831 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1833 dwc
->pullups_connected
= true;
1835 reg
&= ~DWC3_DCTL_RUN_STOP
;
1837 if (dwc
->has_hibernation
&& !suspend
)
1838 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1840 dwc
->pullups_connected
= false;
1843 dwc3_gadget_dctl_write_safe(dwc
, reg
);
1846 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1847 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1848 } while (--timeout
&& !(!is_on
^ !reg
));
1856 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1858 struct dwc3
*dwc
= gadget_to_dwc(g
);
1859 unsigned long flags
;
1865 * Per databook, when we want to stop the gadget, if a control transfer
1866 * is still in process, complete it and get the core into setup phase.
1868 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1869 reinit_completion(&dwc
->ep0_in_setup
);
1871 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1872 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1874 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1879 spin_lock_irqsave(&dwc
->lock
, flags
);
1880 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1881 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1886 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1890 /* Enable all but Start and End of Frame IRQs */
1891 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1892 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1893 DWC3_DEVTEN_CMDCMPLTEN
|
1894 DWC3_DEVTEN_ERRTICERREN
|
1895 DWC3_DEVTEN_WKUPEVTEN
|
1896 DWC3_DEVTEN_CONNECTDONEEN
|
1897 DWC3_DEVTEN_USBRSTEN
|
1898 DWC3_DEVTEN_DISCONNEVTEN
);
1900 if (dwc
->revision
< DWC3_REVISION_250A
)
1901 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1903 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1906 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1908 /* mask all interrupts */
1909 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1912 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1913 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1916 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1917 * @dwc: pointer to our context structure
1919 * The following looks like complex but it's actually very simple. In order to
1920 * calculate the number of packets we can burst at once on OUT transfers, we're
1921 * gonna use RxFIFO size.
1923 * To calculate RxFIFO size we need two numbers:
1924 * MDWIDTH = size, in bits, of the internal memory bus
1925 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1927 * Given these two numbers, the formula is simple:
1929 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1931 * 24 bytes is for 3x SETUP packets
1932 * 16 bytes is a clock domain crossing tolerance
1934 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1936 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1943 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1944 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1946 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1947 nump
= min_t(u32
, nump
, 16);
1950 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1951 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1952 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1953 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1956 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1958 struct dwc3_ep
*dep
;
1963 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1964 * the core supports IMOD, disable it.
1966 if (dwc
->imod_interval
) {
1967 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
1968 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
1969 } else if (dwc3_has_imod(dwc
)) {
1970 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
1974 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1975 * field instead of letting dwc3 itself calculate that automatically.
1977 * This way, we maximize the chances that we'll be able to get several
1978 * bursts of data without going through any sort of endpoint throttling.
1980 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1981 if (dwc3_is_usb31(dwc
))
1982 reg
&= ~DWC31_GRXTHRCFG_PKTCNTSEL
;
1984 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1986 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1988 dwc3_gadget_setup_nump(dwc
);
1990 /* Start with SuperSpeed Default */
1991 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1994 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
1996 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2001 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_INIT
);
2003 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2007 /* begin to receive SETUP packets */
2008 dwc
->ep0state
= EP0_SETUP_PHASE
;
2009 dwc
->link_state
= DWC3_LINK_STATE_SS_DIS
;
2010 dwc3_ep0_out_start(dwc
);
2012 dwc3_gadget_enable_irq(dwc
);
2017 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2023 static int dwc3_gadget_start(struct usb_gadget
*g
,
2024 struct usb_gadget_driver
*driver
)
2026 struct dwc3
*dwc
= gadget_to_dwc(g
);
2027 unsigned long flags
;
2031 irq
= dwc
->irq_gadget
;
2032 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
2033 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
2035 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
2040 spin_lock_irqsave(&dwc
->lock
, flags
);
2041 if (dwc
->gadget_driver
) {
2042 dev_err(dwc
->dev
, "%s is already bound to %s\n",
2044 dwc
->gadget_driver
->driver
.name
);
2049 dwc
->gadget_driver
= driver
;
2051 if (pm_runtime_active(dwc
->dev
))
2052 __dwc3_gadget_start(dwc
);
2054 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2059 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2066 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
2068 dwc3_gadget_disable_irq(dwc
);
2069 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2070 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2073 static int dwc3_gadget_stop(struct usb_gadget
*g
)
2075 struct dwc3
*dwc
= gadget_to_dwc(g
);
2076 unsigned long flags
;
2078 spin_lock_irqsave(&dwc
->lock
, flags
);
2080 if (pm_runtime_suspended(dwc
->dev
))
2083 __dwc3_gadget_stop(dwc
);
2086 dwc
->gadget_driver
= NULL
;
2087 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2089 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
2094 static void dwc3_gadget_config_params(struct usb_gadget
*g
,
2095 struct usb_dcd_config_params
*params
)
2097 struct dwc3
*dwc
= gadget_to_dwc(g
);
2099 params
->besl_baseline
= USB_DEFAULT_BESL_UNSPECIFIED
;
2100 params
->besl_deep
= USB_DEFAULT_BESL_UNSPECIFIED
;
2102 /* Recommended BESL */
2103 if (!dwc
->dis_enblslpm_quirk
) {
2105 * If the recommended BESL baseline is 0 or if the BESL deep is
2106 * less than 2, Microsoft's Windows 10 host usb stack will issue
2107 * a usb reset immediately after it receives the extended BOS
2108 * descriptor and the enumeration will fail. To maintain
2109 * compatibility with the Windows' usb stack, let's set the
2110 * recommended BESL baseline to 1 and clamp the BESL deep to be
2113 params
->besl_baseline
= 1;
2114 if (dwc
->is_utmi_l1_suspend
)
2116 clamp_t(u8
, dwc
->hird_threshold
, 2, 15);
2119 /* U1 Device exit Latency */
2120 if (dwc
->dis_u1_entry_quirk
)
2121 params
->bU1devExitLat
= 0;
2123 params
->bU1devExitLat
= DWC3_DEFAULT_U1_DEV_EXIT_LAT
;
2125 /* U2 Device exit Latency */
2126 if (dwc
->dis_u2_entry_quirk
)
2127 params
->bU2DevExitLat
= 0;
2129 params
->bU2DevExitLat
=
2130 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT
);
2133 static void dwc3_gadget_set_speed(struct usb_gadget
*g
,
2134 enum usb_device_speed speed
)
2136 struct dwc3
*dwc
= gadget_to_dwc(g
);
2137 unsigned long flags
;
2140 spin_lock_irqsave(&dwc
->lock
, flags
);
2141 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2142 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
2145 * WORKAROUND: DWC3 revision < 2.20a have an issue
2146 * which would cause metastability state on Run/Stop
2147 * bit if we try to force the IP to USB2-only mode.
2149 * Because of that, we cannot configure the IP to any
2150 * speed other than the SuperSpeed
2154 * STAR#9000525659: Clock Domain Crossing on DCTL in
2157 if (dwc
->revision
< DWC3_REVISION_220A
&&
2158 !dwc
->dis_metastability_quirk
) {
2159 reg
|= DWC3_DCFG_SUPERSPEED
;
2163 reg
|= DWC3_DCFG_LOWSPEED
;
2165 case USB_SPEED_FULL
:
2166 reg
|= DWC3_DCFG_FULLSPEED
;
2168 case USB_SPEED_HIGH
:
2169 reg
|= DWC3_DCFG_HIGHSPEED
;
2171 case USB_SPEED_SUPER
:
2172 reg
|= DWC3_DCFG_SUPERSPEED
;
2174 case USB_SPEED_SUPER_PLUS
:
2175 if (dwc3_is_usb31(dwc
))
2176 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2178 reg
|= DWC3_DCFG_SUPERSPEED
;
2181 dev_err(dwc
->dev
, "invalid speed (%d)\n", speed
);
2183 if (dwc
->revision
& DWC3_REVISION_IS_DWC31
)
2184 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
2186 reg
|= DWC3_DCFG_SUPERSPEED
;
2189 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2191 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2194 static const struct usb_gadget_ops dwc3_gadget_ops
= {
2195 .get_frame
= dwc3_gadget_get_frame
,
2196 .wakeup
= dwc3_gadget_wakeup
,
2197 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
2198 .pullup
= dwc3_gadget_pullup
,
2199 .udc_start
= dwc3_gadget_start
,
2200 .udc_stop
= dwc3_gadget_stop
,
2201 .udc_set_speed
= dwc3_gadget_set_speed
,
2202 .get_config_params
= dwc3_gadget_config_params
,
2205 /* -------------------------------------------------------------------------- */
2207 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep
*dep
)
2209 struct dwc3
*dwc
= dep
->dwc
;
2211 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
2212 dep
->endpoint
.maxburst
= 1;
2213 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
2214 if (!dep
->direction
)
2215 dwc
->gadget
.ep0
= &dep
->endpoint
;
2217 dep
->endpoint
.caps
.type_control
= true;
2222 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep
*dep
)
2224 struct dwc3
*dwc
= dep
->dwc
;
2228 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2229 /* MDWIDTH is represented in bits, we need it in bytes */
2232 size
= dwc3_readl(dwc
->regs
, DWC3_GTXFIFOSIZ(dep
->number
>> 1));
2233 if (dwc3_is_usb31(dwc
))
2234 size
= DWC31_GTXFIFOSIZ_TXFDEP(size
);
2236 size
= DWC3_GTXFIFOSIZ_TXFDEP(size
);
2238 /* FIFO Depth is in MDWDITH bytes. Multiply */
2242 * To meet performance requirement, a minimum TxFIFO size of 3x
2243 * MaxPacketSize is recommended for endpoints that support burst and a
2244 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2245 * support burst. Use those numbers and we can calculate the max packet
2248 if (dwc
->maximum_speed
>= USB_SPEED_SUPER
)
2253 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2255 dep
->endpoint
.max_streams
= 15;
2256 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2257 list_add_tail(&dep
->endpoint
.ep_list
,
2258 &dwc
->gadget
.ep_list
);
2259 dep
->endpoint
.caps
.type_iso
= true;
2260 dep
->endpoint
.caps
.type_bulk
= true;
2261 dep
->endpoint
.caps
.type_int
= true;
2263 return dwc3_alloc_trb_pool(dep
);
2266 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep
*dep
)
2268 struct dwc3
*dwc
= dep
->dwc
;
2272 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
2274 /* MDWIDTH is represented in bits, convert to bytes */
2277 /* All OUT endpoints share a single RxFIFO space */
2278 size
= dwc3_readl(dwc
->regs
, DWC3_GRXFIFOSIZ(0));
2279 if (dwc3_is_usb31(dwc
))
2280 size
= DWC31_GRXFIFOSIZ_RXFDEP(size
);
2282 size
= DWC3_GRXFIFOSIZ_RXFDEP(size
);
2284 /* FIFO depth is in MDWDITH bytes */
2288 * To meet performance requirement, a minimum recommended RxFIFO size
2289 * is defined as follow:
2290 * RxFIFO size >= (3 x MaxPacketSize) +
2291 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2293 * Then calculate the max packet limit as below.
2295 size
-= (3 * 8) + 16;
2301 usb_ep_set_maxpacket_limit(&dep
->endpoint
, size
);
2302 dep
->endpoint
.max_streams
= 15;
2303 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
2304 list_add_tail(&dep
->endpoint
.ep_list
,
2305 &dwc
->gadget
.ep_list
);
2306 dep
->endpoint
.caps
.type_iso
= true;
2307 dep
->endpoint
.caps
.type_bulk
= true;
2308 dep
->endpoint
.caps
.type_int
= true;
2310 return dwc3_alloc_trb_pool(dep
);
2313 static int dwc3_gadget_init_endpoint(struct dwc3
*dwc
, u8 epnum
)
2315 struct dwc3_ep
*dep
;
2316 bool direction
= epnum
& 1;
2318 u8 num
= epnum
>> 1;
2320 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
2325 dep
->number
= epnum
;
2326 dep
->direction
= direction
;
2327 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
2328 dwc
->eps
[epnum
] = dep
;
2330 dep
->start_cmd_status
= 0;
2332 snprintf(dep
->name
, sizeof(dep
->name
), "ep%u%s", num
,
2333 direction
? "in" : "out");
2335 dep
->endpoint
.name
= dep
->name
;
2337 if (!(dep
->number
> 1)) {
2338 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
2339 dep
->endpoint
.comp_desc
= NULL
;
2343 ret
= dwc3_gadget_init_control_endpoint(dep
);
2345 ret
= dwc3_gadget_init_in_endpoint(dep
);
2347 ret
= dwc3_gadget_init_out_endpoint(dep
);
2352 dep
->endpoint
.caps
.dir_in
= direction
;
2353 dep
->endpoint
.caps
.dir_out
= !direction
;
2355 INIT_LIST_HEAD(&dep
->pending_list
);
2356 INIT_LIST_HEAD(&dep
->started_list
);
2357 INIT_LIST_HEAD(&dep
->cancelled_list
);
2362 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
, u8 total
)
2366 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
2368 for (epnum
= 0; epnum
< total
; epnum
++) {
2371 ret
= dwc3_gadget_init_endpoint(dwc
, epnum
);
2379 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
2381 struct dwc3_ep
*dep
;
2384 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2385 dep
= dwc
->eps
[epnum
];
2389 * Physical endpoints 0 and 1 are special; they form the
2390 * bi-directional USB endpoint 0.
2392 * For those two physical endpoints, we don't allocate a TRB
2393 * pool nor do we add them the endpoints list. Due to that, we
2394 * shouldn't do these two operations otherwise we would end up
2395 * with all sorts of bugs when removing dwc3.ko.
2397 if (epnum
!= 0 && epnum
!= 1) {
2398 dwc3_free_trb_pool(dep
);
2399 list_del(&dep
->endpoint
.ep_list
);
2406 /* -------------------------------------------------------------------------- */
2408 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep
*dep
,
2409 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2410 const struct dwc3_event_depevt
*event
, int status
, int chain
)
2414 dwc3_ep_inc_deq(dep
);
2416 trace_dwc3_complete_trb(dep
, trb
);
2420 * If we're in the middle of series of chained TRBs and we
2421 * receive a short transfer along the way, DWC3 will skip
2422 * through all TRBs including the last TRB in the chain (the
2423 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2424 * bit and SW has to do it manually.
2426 * We're going to do that here to avoid problems of HW trying
2427 * to use bogus TRBs for transfers.
2429 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2430 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2433 * For isochronous transfers, the first TRB in a service interval must
2434 * have the Isoc-First type. Track and report its interval frame number.
2436 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2437 (trb
->ctrl
& DWC3_TRBCTL_ISOCHRONOUS_FIRST
)) {
2438 unsigned int frame_number
;
2440 frame_number
= DWC3_TRB_CTRL_GET_SID_SOFN(trb
->ctrl
);
2441 frame_number
&= ~(dep
->interval
- 1);
2442 req
->request
.frame_number
= frame_number
;
2446 * If we're dealing with unaligned size OUT transfer, we will be left
2447 * with one TRB pending in the ring. We need to manually clear HWO bit
2451 if (req
->needs_extra_trb
&& !(trb
->ctrl
& DWC3_TRB_CTRL_CHN
)) {
2452 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2456 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2457 req
->remaining
+= count
;
2459 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2462 if (event
->status
& DEPEVT_STATUS_SHORT
&& !chain
)
2465 if ((trb
->ctrl
& DWC3_TRB_CTRL_IOC
) ||
2466 (trb
->ctrl
& DWC3_TRB_CTRL_LST
))
2472 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep
*dep
,
2473 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2476 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2477 struct scatterlist
*sg
= req
->sg
;
2478 struct scatterlist
*s
;
2479 unsigned int pending
= req
->num_pending_sgs
;
2483 for_each_sg(sg
, s
, pending
, i
) {
2484 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2486 req
->sg
= sg_next(s
);
2487 req
->num_pending_sgs
--;
2489 ret
= dwc3_gadget_ep_reclaim_completed_trb(dep
, req
,
2490 trb
, event
, status
, true);
2498 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep
*dep
,
2499 struct dwc3_request
*req
, const struct dwc3_event_depevt
*event
,
2502 struct dwc3_trb
*trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2504 return dwc3_gadget_ep_reclaim_completed_trb(dep
, req
, trb
,
2505 event
, status
, false);
2508 static bool dwc3_gadget_ep_request_completed(struct dwc3_request
*req
)
2510 return req
->num_pending_sgs
== 0;
2513 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep
*dep
,
2514 const struct dwc3_event_depevt
*event
,
2515 struct dwc3_request
*req
, int status
)
2519 if (req
->num_pending_sgs
)
2520 ret
= dwc3_gadget_ep_reclaim_trb_sg(dep
, req
, event
,
2523 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2526 if (req
->needs_extra_trb
) {
2527 ret
= dwc3_gadget_ep_reclaim_trb_linear(dep
, req
, event
,
2529 req
->needs_extra_trb
= false;
2532 req
->request
.actual
= req
->request
.length
- req
->remaining
;
2534 if (!dwc3_gadget_ep_request_completed(req
)) {
2535 __dwc3_gadget_kick_transfer(dep
);
2539 dwc3_gadget_giveback(dep
, req
, status
);
2545 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep
*dep
,
2546 const struct dwc3_event_depevt
*event
, int status
)
2548 struct dwc3_request
*req
;
2549 struct dwc3_request
*tmp
;
2551 list_for_each_entry_safe(req
, tmp
, &dep
->started_list
, list
) {
2554 ret
= dwc3_gadget_ep_cleanup_completed_request(dep
, event
,
2561 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep
*dep
,
2562 const struct dwc3_event_depevt
*event
)
2564 dep
->frame_number
= event
->parameters
;
2567 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep
*dep
,
2568 const struct dwc3_event_depevt
*event
)
2570 struct dwc3
*dwc
= dep
->dwc
;
2571 unsigned status
= 0;
2574 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2576 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2577 status
= -ECONNRESET
;
2579 if (event
->status
& DEPEVT_STATUS_MISSED_ISOC
) {
2582 if (list_empty(&dep
->started_list
))
2586 dwc3_gadget_ep_cleanup_completed_requests(dep
, event
, status
);
2589 dwc3_stop_active_transfer(dep
, true, true);
2592 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2593 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2595 if (dwc
->revision
< DWC3_REVISION_183A
) {
2599 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2602 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2605 if (!list_empty(&dep
->started_list
))
2609 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2611 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2617 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep
*dep
,
2618 const struct dwc3_event_depevt
*event
)
2620 dwc3_gadget_endpoint_frame_from_event(dep
, event
);
2621 (void) __dwc3_gadget_start_isoc(dep
);
2624 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2625 const struct dwc3_event_depevt
*event
)
2627 struct dwc3_ep
*dep
;
2628 u8 epnum
= event
->endpoint_number
;
2631 dep
= dwc
->eps
[epnum
];
2633 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
2634 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
))
2637 /* Handle only EPCMDCMPLT when EP disabled */
2638 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
2642 if (epnum
== 0 || epnum
== 1) {
2643 dwc3_ep0_interrupt(dwc
, event
);
2647 switch (event
->endpoint_event
) {
2648 case DWC3_DEPEVT_XFERINPROGRESS
:
2649 dwc3_gadget_endpoint_transfer_in_progress(dep
, event
);
2651 case DWC3_DEPEVT_XFERNOTREADY
:
2652 dwc3_gadget_endpoint_transfer_not_ready(dep
, event
);
2654 case DWC3_DEPEVT_EPCMDCMPLT
:
2655 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2657 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2658 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2659 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
2660 dwc3_gadget_ep_cleanup_cancelled_requests(dep
);
2661 if ((dep
->flags
& DWC3_EP_DELAY_START
) &&
2662 !usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
2663 __dwc3_gadget_kick_transfer(dep
);
2665 dep
->flags
&= ~DWC3_EP_DELAY_START
;
2668 case DWC3_DEPEVT_STREAMEVT
:
2669 case DWC3_DEPEVT_XFERCOMPLETE
:
2670 case DWC3_DEPEVT_RXTXFIFOEVT
:
2675 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2677 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2678 spin_unlock(&dwc
->lock
);
2679 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2680 spin_lock(&dwc
->lock
);
2684 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2686 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2687 spin_unlock(&dwc
->lock
);
2688 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2689 spin_lock(&dwc
->lock
);
2693 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2695 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2696 spin_unlock(&dwc
->lock
);
2697 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2698 spin_lock(&dwc
->lock
);
2702 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2704 if (!dwc
->gadget_driver
)
2707 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2708 spin_unlock(&dwc
->lock
);
2709 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2710 spin_lock(&dwc
->lock
);
2714 static void dwc3_stop_active_transfer(struct dwc3_ep
*dep
, bool force
,
2717 struct dwc3_gadget_ep_cmd_params params
;
2721 if (!(dep
->flags
& DWC3_EP_TRANSFER_STARTED
) ||
2722 (dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2726 * NOTICE: We are violating what the Databook says about the
2727 * EndTransfer command. Ideally we would _always_ wait for the
2728 * EndTransfer Command Completion IRQ, but that's causing too
2729 * much trouble synchronizing between us and gadget driver.
2731 * We have discussed this with the IP Provider and it was
2732 * suggested to giveback all requests here.
2734 * Note also that a similar handling was tested by Synopsys
2735 * (thanks a lot Paul) and nothing bad has come out of it.
2736 * In short, what we're doing is issuing EndTransfer with
2737 * CMDIOC bit set and delay kicking transfer until the
2738 * EndTransfer command had completed.
2740 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2741 * supports a mode to work around the above limitation. The
2742 * software can poll the CMDACT bit in the DEPCMD register
2743 * after issuing a EndTransfer command. This mode is enabled
2744 * by writing GUCTL2[14]. This polling is already done in the
2745 * dwc3_send_gadget_ep_cmd() function so if the mode is
2746 * enabled, the EndTransfer command will have completed upon
2747 * returning from this function.
2749 * This mode is NOT available on the DWC_usb31 IP.
2752 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2753 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2754 cmd
|= interrupt
? DWC3_DEPCMD_CMDIOC
: 0;
2755 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2756 memset(¶ms
, 0, sizeof(params
));
2757 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2759 dep
->resource_index
= 0;
2762 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
2764 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2767 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2771 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2772 struct dwc3_ep
*dep
;
2775 dep
= dwc
->eps
[epnum
];
2779 if (!(dep
->flags
& DWC3_EP_STALL
))
2782 dep
->flags
&= ~DWC3_EP_STALL
;
2784 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2789 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2793 dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RX_DET
);
2795 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2796 reg
&= ~DWC3_DCTL_INITU1ENA
;
2797 reg
&= ~DWC3_DCTL_INITU2ENA
;
2798 dwc3_gadget_dctl_write_safe(dwc
, reg
);
2800 dwc3_disconnect_gadget(dwc
);
2802 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2803 dwc
->setup_packet_pending
= false;
2804 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2806 dwc
->connected
= false;
2809 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2813 dwc
->connected
= true;
2816 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2817 * would cause a missing Disconnect Event if there's a
2818 * pending Setup Packet in the FIFO.
2820 * There's no suggested workaround on the official Bug
2821 * report, which states that "unless the driver/application
2822 * is doing any special handling of a disconnect event,
2823 * there is no functional issue".
2825 * Unfortunately, it turns out that we _do_ some special
2826 * handling of a disconnect event, namely complete all
2827 * pending transfers, notify gadget driver of the
2828 * disconnection, and so on.
2830 * Our suggested workaround is to follow the Disconnect
2831 * Event steps here, instead, based on a setup_packet_pending
2832 * flag. Such flag gets set whenever we have a SETUP_PENDING
2833 * status for EP0 TRBs and gets cleared on XferComplete for the
2838 * STAR#9000466709: RTL: Device : Disconnect event not
2839 * generated if setup packet pending in FIFO
2841 if (dwc
->revision
< DWC3_REVISION_188A
) {
2842 if (dwc
->setup_packet_pending
)
2843 dwc3_gadget_disconnect_interrupt(dwc
);
2846 dwc3_reset_gadget(dwc
);
2848 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2849 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2850 dwc3_gadget_dctl_write_safe(dwc
, reg
);
2851 dwc
->test_mode
= false;
2852 dwc3_clear_stall_all_ep(dwc
);
2854 /* Reset device address to zero */
2855 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2856 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2857 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2860 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2862 struct dwc3_ep
*dep
;
2867 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2868 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2872 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2873 * each time on Connect Done.
2875 * Currently we always use the reset value. If any platform
2876 * wants to set this to a different value, we need to add a
2877 * setting and update GCTL.RAMCLKSEL here.
2881 case DWC3_DSTS_SUPERSPEED_PLUS
:
2882 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2883 dwc
->gadget
.ep0
->maxpacket
= 512;
2884 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2886 case DWC3_DSTS_SUPERSPEED
:
2888 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2889 * would cause a missing USB3 Reset event.
2891 * In such situations, we should force a USB3 Reset
2892 * event by calling our dwc3_gadget_reset_interrupt()
2897 * STAR#9000483510: RTL: SS : USB3 reset event may
2898 * not be generated always when the link enters poll
2900 if (dwc
->revision
< DWC3_REVISION_190A
)
2901 dwc3_gadget_reset_interrupt(dwc
);
2903 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2904 dwc
->gadget
.ep0
->maxpacket
= 512;
2905 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2907 case DWC3_DSTS_HIGHSPEED
:
2908 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2909 dwc
->gadget
.ep0
->maxpacket
= 64;
2910 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2912 case DWC3_DSTS_FULLSPEED
:
2913 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2914 dwc
->gadget
.ep0
->maxpacket
= 64;
2915 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2917 case DWC3_DSTS_LOWSPEED
:
2918 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2919 dwc
->gadget
.ep0
->maxpacket
= 8;
2920 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2924 dwc
->eps
[1]->endpoint
.maxpacket
= dwc
->gadget
.ep0
->maxpacket
;
2926 /* Enable USB2 LPM Capability */
2928 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2929 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2930 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2931 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2932 reg
|= DWC3_DCFG_LPM_CAP
;
2933 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2935 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2936 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2938 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
|
2939 (dwc
->is_utmi_l1_suspend
<< 4));
2942 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2943 * DCFG.LPMCap is set, core responses with an ACK and the
2944 * BESL value in the LPM token is less than or equal to LPM
2947 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2948 && dwc
->has_lpm_erratum
,
2949 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2951 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2952 reg
|= DWC3_DCTL_NYET_THRES(dwc
->lpm_nyet_threshold
);
2954 dwc3_gadget_dctl_write_safe(dwc
, reg
);
2956 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2957 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2958 dwc3_gadget_dctl_write_safe(dwc
, reg
);
2962 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
2964 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2969 ret
= __dwc3_gadget_ep_enable(dep
, DWC3_DEPCFG_ACTION_MODIFY
);
2971 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2976 * Configure PHY via GUSB3PIPECTLn if required.
2978 * Update GTXFIFOSIZn
2980 * In both cases reset values should be sufficient.
2984 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2987 * TODO take core out of low power mode when that's
2991 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2992 spin_unlock(&dwc
->lock
);
2993 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2994 spin_lock(&dwc
->lock
);
2998 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2999 unsigned int evtinfo
)
3001 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
3002 unsigned int pwropt
;
3005 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3006 * Hibernation mode enabled which would show up when device detects
3007 * host-initiated U3 exit.
3009 * In that case, device will generate a Link State Change Interrupt
3010 * from U3 to RESUME which is only necessary if Hibernation is
3013 * There are no functional changes due to such spurious event and we
3014 * just need to ignore it.
3018 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3021 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
3022 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
3023 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
3024 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
3025 (next
== DWC3_LINK_STATE_RESUME
)) {
3031 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3032 * on the link partner, the USB session might do multiple entry/exit
3033 * of low power states before a transfer takes place.
3035 * Due to this problem, we might experience lower throughput. The
3036 * suggested workaround is to disable DCTL[12:9] bits if we're
3037 * transitioning from U1/U2 to U0 and enable those bits again
3038 * after a transfer completes and there are no pending transfers
3039 * on any of the enabled endpoints.
3041 * This is the first half of that workaround.
3045 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3046 * core send LGO_Ux entering U0
3048 if (dwc
->revision
< DWC3_REVISION_183A
) {
3049 if (next
== DWC3_LINK_STATE_U0
) {
3053 switch (dwc
->link_state
) {
3054 case DWC3_LINK_STATE_U1
:
3055 case DWC3_LINK_STATE_U2
:
3056 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
3057 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
3058 | DWC3_DCTL_ACCEPTU2ENA
3059 | DWC3_DCTL_INITU1ENA
3060 | DWC3_DCTL_ACCEPTU1ENA
);
3063 dwc
->u1u2
= reg
& u1u2
;
3067 dwc3_gadget_dctl_write_safe(dwc
, reg
);
3077 case DWC3_LINK_STATE_U1
:
3078 if (dwc
->speed
== USB_SPEED_SUPER
)
3079 dwc3_suspend_gadget(dwc
);
3081 case DWC3_LINK_STATE_U2
:
3082 case DWC3_LINK_STATE_U3
:
3083 dwc3_suspend_gadget(dwc
);
3085 case DWC3_LINK_STATE_RESUME
:
3086 dwc3_resume_gadget(dwc
);
3093 dwc
->link_state
= next
;
3096 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
3097 unsigned int evtinfo
)
3099 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
3101 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
3102 dwc3_suspend_gadget(dwc
);
3104 dwc
->link_state
= next
;
3107 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
3108 unsigned int evtinfo
)
3110 unsigned int is_ss
= evtinfo
& BIT(4);
3113 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3114 * have a known issue which can cause USB CV TD.9.23 to fail
3117 * Because of this issue, core could generate bogus hibernation
3118 * events which SW needs to ignore.
3122 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3123 * Device Fallback from SuperSpeed
3125 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
3128 /* enter hibernation here */
3131 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
3132 const struct dwc3_event_devt
*event
)
3134 switch (event
->type
) {
3135 case DWC3_DEVICE_EVENT_DISCONNECT
:
3136 dwc3_gadget_disconnect_interrupt(dwc
);
3138 case DWC3_DEVICE_EVENT_RESET
:
3139 dwc3_gadget_reset_interrupt(dwc
);
3141 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
3142 dwc3_gadget_conndone_interrupt(dwc
);
3144 case DWC3_DEVICE_EVENT_WAKEUP
:
3145 dwc3_gadget_wakeup_interrupt(dwc
);
3147 case DWC3_DEVICE_EVENT_HIBER_REQ
:
3148 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
3149 "unexpected hibernation event\n"))
3152 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
3154 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
3155 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
3157 case DWC3_DEVICE_EVENT_EOPF
:
3158 /* It changed to be suspend event for version 2.30a and above */
3159 if (dwc
->revision
>= DWC3_REVISION_230A
) {
3161 * Ignore suspend event until the gadget enters into
3162 * USB_STATE_CONFIGURED state.
3164 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
3165 dwc3_gadget_suspend_interrupt(dwc
,
3169 case DWC3_DEVICE_EVENT_SOF
:
3170 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
3171 case DWC3_DEVICE_EVENT_CMD_CMPL
:
3172 case DWC3_DEVICE_EVENT_OVERFLOW
:
3175 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
3179 static void dwc3_process_event_entry(struct dwc3
*dwc
,
3180 const union dwc3_event
*event
)
3182 trace_dwc3_event(event
->raw
, dwc
);
3184 if (!event
->type
.is_devspec
)
3185 dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
3186 else if (event
->type
.type
== DWC3_EVENT_TYPE_DEV
)
3187 dwc3_gadget_interrupt(dwc
, &event
->devt
);
3189 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
3192 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
3194 struct dwc3
*dwc
= evt
->dwc
;
3195 irqreturn_t ret
= IRQ_NONE
;
3201 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
3205 union dwc3_event event
;
3207 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
3209 dwc3_process_event_entry(dwc
, &event
);
3212 * FIXME we wrap around correctly to the next entry as
3213 * almost all entries are 4 bytes in size. There is one
3214 * entry which has 12 bytes which is a regular entry
3215 * followed by 8 bytes data. ATM I don't know how
3216 * things are organized if we get next to the a
3217 * boundary so I worry about that once we try to handle
3220 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
3225 evt
->flags
&= ~DWC3_EVENT_PENDING
;
3228 /* Unmask interrupt */
3229 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3230 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
3231 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3233 if (dwc
->imod_interval
) {
3234 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
3235 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
3241 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
3243 struct dwc3_event_buffer
*evt
= _evt
;
3244 struct dwc3
*dwc
= evt
->dwc
;
3245 unsigned long flags
;
3246 irqreturn_t ret
= IRQ_NONE
;
3248 spin_lock_irqsave(&dwc
->lock
, flags
);
3249 ret
= dwc3_process_event_buf(evt
);
3250 spin_unlock_irqrestore(&dwc
->lock
, flags
);
3255 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
3257 struct dwc3
*dwc
= evt
->dwc
;
3262 if (pm_runtime_suspended(dwc
->dev
)) {
3263 pm_runtime_get(dwc
->dev
);
3264 disable_irq_nosync(dwc
->irq_gadget
);
3265 dwc
->pending_events
= true;
3270 * With PCIe legacy interrupt, test shows that top-half irq handler can
3271 * be called again after HW interrupt deassertion. Check if bottom-half
3272 * irq event handler completes before caching new event to prevent
3275 if (evt
->flags
& DWC3_EVENT_PENDING
)
3278 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
3279 count
&= DWC3_GEVNTCOUNT_MASK
;
3284 evt
->flags
|= DWC3_EVENT_PENDING
;
3286 /* Mask interrupt */
3287 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
3288 reg
|= DWC3_GEVNTSIZ_INTMASK
;
3289 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
3291 amount
= min(count
, evt
->length
- evt
->lpos
);
3292 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
3295 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
3297 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
3299 return IRQ_WAKE_THREAD
;
3302 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
3304 struct dwc3_event_buffer
*evt
= _evt
;
3306 return dwc3_check_event_buf(evt
);
3309 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
3311 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
3314 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "peripheral");
3318 if (irq
== -EPROBE_DEFER
)
3321 irq
= platform_get_irq_byname_optional(dwc3_pdev
, "dwc_usb3");
3325 if (irq
== -EPROBE_DEFER
)
3328 irq
= platform_get_irq(dwc3_pdev
, 0);
3340 * dwc3_gadget_init - initializes gadget related registers
3341 * @dwc: pointer to our controller context structure
3343 * Returns 0 on success otherwise negative errno.
3345 int dwc3_gadget_init(struct dwc3
*dwc
)
3350 irq
= dwc3_gadget_get_irq(dwc
);
3356 dwc
->irq_gadget
= irq
;
3358 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
3359 sizeof(*dwc
->ep0_trb
) * 2,
3360 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
3361 if (!dwc
->ep0_trb
) {
3362 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3367 dwc
->setup_buf
= kzalloc(DWC3_EP0_SETUP_SIZE
, GFP_KERNEL
);
3368 if (!dwc
->setup_buf
) {
3373 dwc
->bounce
= dma_alloc_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
,
3374 &dwc
->bounce_addr
, GFP_KERNEL
);
3380 init_completion(&dwc
->ep0_in_setup
);
3382 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3383 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3384 dwc
->gadget
.sg_supported
= true;
3385 dwc
->gadget
.name
= "dwc3-gadget";
3386 dwc
->gadget
.lpm_capable
= true;
3389 * FIXME We might be setting max_speed to <SUPER, however versions
3390 * <2.20a of dwc3 have an issue with metastability (documented
3391 * elsewhere in this driver) which tells us we can't set max speed to
3392 * anything lower than SUPER.
3394 * Because gadget.max_speed is only used by composite.c and function
3395 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3396 * to happen so we avoid sending SuperSpeed Capability descriptor
3397 * together with our BOS descriptor as that could confuse host into
3398 * thinking we can handle super speed.
3400 * Note that, in fact, we won't even support GetBOS requests when speed
3401 * is less than super speed because we don't have means, yet, to tell
3402 * composite.c that we are USB 2.0 + LPM ECN.
3404 if (dwc
->revision
< DWC3_REVISION_220A
&&
3405 !dwc
->dis_metastability_quirk
)
3406 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3409 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3412 * REVISIT: Here we should clear all pending IRQs to be
3413 * sure we're starting from a well known location.
3416 ret
= dwc3_gadget_init_endpoints(dwc
, dwc
->num_eps
);
3420 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3422 dev_err(dwc
->dev
, "failed to register udc\n");
3426 dwc3_gadget_set_speed(&dwc
->gadget
, dwc
->maximum_speed
);
3431 dwc3_gadget_free_endpoints(dwc
);
3434 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3438 kfree(dwc
->setup_buf
);
3441 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3442 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3448 /* -------------------------------------------------------------------------- */
3450 void dwc3_gadget_exit(struct dwc3
*dwc
)
3452 usb_del_gadget_udc(&dwc
->gadget
);
3453 dwc3_gadget_free_endpoints(dwc
);
3454 dma_free_coherent(dwc
->sysdev
, DWC3_BOUNCE_SIZE
, dwc
->bounce
,
3456 kfree(dwc
->setup_buf
);
3457 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3458 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3461 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3463 if (!dwc
->gadget_driver
)
3466 dwc3_gadget_run_stop(dwc
, false, false);
3467 dwc3_disconnect_gadget(dwc
);
3468 __dwc3_gadget_stop(dwc
);
3473 int dwc3_gadget_resume(struct dwc3
*dwc
)
3477 if (!dwc
->gadget_driver
)
3480 ret
= __dwc3_gadget_start(dwc
);
3484 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3491 __dwc3_gadget_stop(dwc
);
3497 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3499 if (dwc
->pending_events
) {
3500 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3501 dwc
->pending_events
= false;
3502 enable_irq(dwc
->irq_gadget
);