1 // SPDX-License-Identifier: GPL-2.0
3 * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
5 * Copyright (C) 2015 Samsung Electronics
7 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
11 #include <asm/arch/power.h>
12 #include <asm/arch/xhci-exynos.h>
14 void exynos5_usb3_phy_init(struct exynos_usb3_phy
*phy
)
18 /* Reset USB 3.0 PHY */
19 writel(0x0, &phy
->phy_reg0
);
21 clrbits_le32(&phy
->phy_param0
,
22 /* Select PHY CLK source */
23 PHYPARAM0_REF_USE_PAD
|
24 /* Set Loss-of-Signal Detector sensitivity */
25 PHYPARAM0_REF_LOSLEVEL_MASK
);
26 setbits_le32(&phy
->phy_param0
, PHYPARAM0_REF_LOSLEVEL
);
29 writel(0x0, &phy
->phy_resume
);
32 * Setting the Frame length Adj value[6:1] to default 0x20
33 * See xHCI 1.0 spec, 5.2.4
35 setbits_le32(&phy
->link_system
,
36 LINKSYSTEM_XHCI_VERSION_CONTROL
|
37 LINKSYSTEM_FLADJ(0x20));
39 /* Set Tx De-Emphasis level */
40 clrbits_le32(&phy
->phy_param1
, PHYPARAM1_PCS_TXDEEMPH_MASK
);
41 setbits_le32(&phy
->phy_param1
, PHYPARAM1_PCS_TXDEEMPH
);
43 setbits_le32(&phy
->phy_batchg
, PHYBATCHG_UTMI_CLKSEL
);
45 /* PHYTEST POWERDOWN Control */
46 clrbits_le32(&phy
->phy_test
,
47 PHYTEST_POWERDOWN_SSP
|
48 PHYTEST_POWERDOWN_HSP
);
50 /* UTMI Power Control */
51 writel(PHYUTMI_OTGDISABLE
, &phy
->phy_utmi
);
53 /* Use core clock from main PLL */
54 reg
= PHYCLKRST_REFCLKSEL_EXT_REFCLK
|
55 /* Default 24Mhz crystal clock */
56 PHYCLKRST_FSEL(FSEL_CLKSEL_24M
) |
57 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF
|
58 PHYCLKRST_SSC_REFCLKSEL(0) |
59 /* Force PortReset of PHY */
61 /* Digital power supply in normal operating mode */
62 PHYCLKRST_RETENABLEN
|
63 /* Enable ref clock for SS function */
64 PHYCLKRST_REF_SSP_EN
|
65 /* Enable spread spectrum */
67 /* Power down HS Bias and PLL blocks in suspend mode */
70 writel(reg
, &phy
->phy_clk_rst
);
72 /* giving time to Phy clock to settle before resetting */
75 reg
&= ~PHYCLKRST_PORTRESET
;
76 writel(reg
, &phy
->phy_clk_rst
);