2 * Copyright (c) 2011 The Chromium OS Authors.
4 * Patched for AX88772B by Antmicro Ltd <www.antmicro.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mii.h>
15 #include "usb_ether.h"
17 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
19 #define AX_CMD_SET_SW_MII 0x06
20 #define AX_CMD_READ_MII_REG 0x07
21 #define AX_CMD_WRITE_MII_REG 0x08
22 #define AX_CMD_SET_HW_MII 0x0a
23 #define AX_CMD_READ_EEPROM 0x0b
24 #define AX_CMD_READ_RX_CTL 0x0f
25 #define AX_CMD_WRITE_RX_CTL 0x10
26 #define AX_CMD_WRITE_IPG0 0x12
27 #define AX_CMD_READ_NODE_ID 0x13
28 #define AX_CMD_WRITE_NODE_ID 0x14
29 #define AX_CMD_READ_PHY_ID 0x19
30 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
31 #define AX_CMD_WRITE_GPIOS 0x1f
32 #define AX_CMD_SW_RESET 0x20
33 #define AX_CMD_SW_PHY_SELECT 0x22
35 #define AX_SWRESET_CLEAR 0x00
36 #define AX_SWRESET_PRTE 0x04
37 #define AX_SWRESET_PRL 0x08
38 #define AX_SWRESET_IPRL 0x20
39 #define AX_SWRESET_IPPD 0x40
41 #define AX88772_IPG0_DEFAULT 0x15
42 #define AX88772_IPG1_DEFAULT 0x0c
43 #define AX88772_IPG2_DEFAULT 0x12
45 /* AX88772 & AX88178 Medium Mode Register */
46 #define AX_MEDIUM_PF 0x0080
47 #define AX_MEDIUM_JFE 0x0040
48 #define AX_MEDIUM_TFC 0x0020
49 #define AX_MEDIUM_RFC 0x0010
50 #define AX_MEDIUM_ENCK 0x0008
51 #define AX_MEDIUM_AC 0x0004
52 #define AX_MEDIUM_FD 0x0002
53 #define AX_MEDIUM_GM 0x0001
54 #define AX_MEDIUM_SM 0x1000
55 #define AX_MEDIUM_SBP 0x0800
56 #define AX_MEDIUM_PS 0x0200
57 #define AX_MEDIUM_RE 0x0100
59 #define AX88178_MEDIUM_DEFAULT \
60 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
61 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
64 #define AX88772_MEDIUM_DEFAULT \
65 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
66 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
67 AX_MEDIUM_AC | AX_MEDIUM_RE)
69 /* AX88772 & AX88178 RX_CTL values */
70 #define AX_RX_CTL_RH2M 0x0200 /* 32-bit aligned RX IP header */
71 #define AX_RX_CTL_RH1M 0x0100 /* Enable RX header format type 1 */
72 #define AX_RX_CTL_SO 0x0080
73 #define AX_RX_CTL_AB 0x0008
74 #define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
76 #define AX_DEFAULT_RX_CTL \
77 (AX_RX_CTL_SO | AX_RX_CTL_AB)
80 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
81 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
82 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
85 #define ASIX_BASE_NAME "asx"
86 #define USB_CTRL_SET_TIMEOUT 5000
87 #define USB_CTRL_GET_TIMEOUT 5000
88 #define USB_BULK_SEND_TIMEOUT 5000
89 #define USB_BULK_RECV_TIMEOUT 5000
91 #define AX_RX_URB_SIZE 2048
92 #define PHY_CONNECT_TIMEOUT 5000
94 /* asix_flags defines */
96 #define FLAG_TYPE_AX88172 (1U << 0)
97 #define FLAG_TYPE_AX88772 (1U << 1)
98 #define FLAG_TYPE_AX88772B (1U << 2)
99 #define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
101 #define ASIX_USB_VENDOR_ID 0x0b95
102 #define AX88772B_USB_PRODUCT_ID 0x772b
105 struct asix_private
{
108 struct ueth_data ueth
;
112 #ifndef CONFIG_DM_ETH
114 static int curr_eth_dev
; /* index for name of next device detected */
118 * Asix infrastructure commands
120 static int asix_write_cmd(struct ueth_data
*dev
, u8 cmd
, u16 value
, u16 index
,
121 u16 size
, void *data
)
125 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
126 "size=%d\n", cmd
, value
, index
, size
);
128 len
= usb_control_msg(
130 usb_sndctrlpipe(dev
->pusb_dev
, 0),
132 USB_DIR_OUT
| USB_TYPE_VENDOR
| USB_RECIP_DEVICE
,
137 USB_CTRL_SET_TIMEOUT
);
139 return len
== size
? 0 : -1;
142 static int asix_read_cmd(struct ueth_data
*dev
, u8 cmd
, u16 value
, u16 index
,
143 u16 size
, void *data
)
147 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
148 cmd
, value
, index
, size
);
150 len
= usb_control_msg(
152 usb_rcvctrlpipe(dev
->pusb_dev
, 0),
154 USB_DIR_IN
| USB_TYPE_VENDOR
| USB_RECIP_DEVICE
,
159 USB_CTRL_GET_TIMEOUT
);
160 return len
== size
? 0 : -1;
163 static inline int asix_set_sw_mii(struct ueth_data
*dev
)
167 ret
= asix_write_cmd(dev
, AX_CMD_SET_SW_MII
, 0x0000, 0, 0, NULL
);
169 debug("Failed to enable software MII access\n");
173 static inline int asix_set_hw_mii(struct ueth_data
*dev
)
177 ret
= asix_write_cmd(dev
, AX_CMD_SET_HW_MII
, 0x0000, 0, 0, NULL
);
179 debug("Failed to enable hardware MII access\n");
183 static int asix_mdio_read(struct ueth_data
*dev
, int phy_id
, int loc
)
185 ALLOC_CACHE_ALIGN_BUFFER(__le16
, res
, 1);
187 asix_set_sw_mii(dev
);
188 asix_read_cmd(dev
, AX_CMD_READ_MII_REG
, phy_id
, (__u16
)loc
, 2, res
);
189 asix_set_hw_mii(dev
);
191 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
192 phy_id
, loc
, le16_to_cpu(*res
));
194 return le16_to_cpu(*res
);
198 asix_mdio_write(struct ueth_data
*dev
, int phy_id
, int loc
, int val
)
200 ALLOC_CACHE_ALIGN_BUFFER(__le16
, res
, 1);
201 *res
= cpu_to_le16(val
);
203 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
205 asix_set_sw_mii(dev
);
206 asix_write_cmd(dev
, AX_CMD_WRITE_MII_REG
, phy_id
, (__u16
)loc
, 2, res
);
207 asix_set_hw_mii(dev
);
211 * Asix "high level" commands
213 static int asix_sw_reset(struct ueth_data
*dev
, u8 flags
)
217 ret
= asix_write_cmd(dev
, AX_CMD_SW_RESET
, flags
, 0, 0, NULL
);
219 debug("Failed to send software reset: %02x\n", ret
);
226 static inline int asix_get_phy_addr(struct ueth_data
*dev
)
228 ALLOC_CACHE_ALIGN_BUFFER(u8
, buf
, 2);
230 int ret
= asix_read_cmd(dev
, AX_CMD_READ_PHY_ID
, 0, 0, 2, buf
);
232 debug("asix_get_phy_addr()\n");
235 debug("Error reading PHYID register: %02x\n", ret
);
238 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf
[0], buf
[1]);
245 static int asix_write_medium_mode(struct ueth_data
*dev
, u16 mode
)
249 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode
);
250 ret
= asix_write_cmd(dev
, AX_CMD_WRITE_MEDIUM_MODE
, mode
,
253 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
259 static u16
asix_read_rx_ctl(struct ueth_data
*dev
)
261 ALLOC_CACHE_ALIGN_BUFFER(__le16
, v
, 1);
263 int ret
= asix_read_cmd(dev
, AX_CMD_READ_RX_CTL
, 0, 0, 2, v
);
266 debug("Error reading RX_CTL register: %02x\n", ret
);
268 ret
= le16_to_cpu(*v
);
272 static int asix_write_rx_ctl(struct ueth_data
*dev
, u16 mode
)
276 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode
);
277 ret
= asix_write_cmd(dev
, AX_CMD_WRITE_RX_CTL
, mode
, 0, 0, NULL
);
279 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
285 static int asix_write_gpio(struct ueth_data
*dev
, u16 value
, int sleep
)
289 debug("asix_write_gpio() - value = 0x%04x\n", value
);
290 ret
= asix_write_cmd(dev
, AX_CMD_WRITE_GPIOS
, value
, 0, 0, NULL
);
292 debug("Failed to write GPIO value 0x%04x: %02x\n",
296 udelay(sleep
* 1000);
301 static int asix_write_hwaddr_common(struct ueth_data
*dev
, uint8_t *enetaddr
)
304 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf
, ETH_ALEN
);
306 memcpy(buf
, enetaddr
, ETH_ALEN
);
308 ret
= asix_write_cmd(dev
, AX_CMD_WRITE_NODE_ID
, 0, 0, ETH_ALEN
, buf
);
310 debug("Failed to set MAC address: %02x\n", ret
);
320 * mii_nway_restart - restart NWay (autonegotiation) for this interface
322 * Returns 0 on success, negative on error.
324 static int mii_nway_restart(struct ueth_data
*dev
)
329 /* if autoneg is off, it's an error */
330 bmcr
= asix_mdio_read(dev
, dev
->phy_id
, MII_BMCR
);
332 if (bmcr
& BMCR_ANENABLE
) {
333 bmcr
|= BMCR_ANRESTART
;
334 asix_mdio_write(dev
, dev
->phy_id
, MII_BMCR
, bmcr
);
341 static int asix_read_mac_common(struct ueth_data
*dev
,
342 struct asix_private
*priv
, uint8_t *enetaddr
)
344 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf
, ETH_ALEN
);
347 if (priv
->flags
& FLAG_EEPROM_MAC
) {
348 for (i
= 0; i
< (ETH_ALEN
>> 1); i
++) {
349 if (asix_read_cmd(dev
, AX_CMD_READ_EEPROM
,
350 0x04 + i
, 0, 2, buf
) < 0) {
351 debug("Failed to read SROM address 04h.\n");
354 memcpy(enetaddr
+ i
* 2, buf
, 2);
357 if (asix_read_cmd(dev
, AX_CMD_READ_NODE_ID
, 0, 0, ETH_ALEN
, buf
)
359 debug("Failed to read MAC address.\n");
362 memcpy(enetaddr
, buf
, ETH_ALEN
);
368 static int asix_basic_reset(struct ueth_data
*dev
)
373 if (asix_write_gpio(dev
,
374 AX_GPIO_RSE
| AX_GPIO_GPO_2
| AX_GPIO_GPO2EN
, 5) < 0)
377 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
378 embd_phy
= ((asix_get_phy_addr(dev
) & 0x1f) == 0x10 ? 1 : 0);
379 if (asix_write_cmd(dev
, AX_CMD_SW_PHY_SELECT
,
380 embd_phy
, 0, 0, NULL
) < 0) {
381 debug("Select PHY #1 failed\n");
385 if (asix_sw_reset(dev
, AX_SWRESET_IPPD
| AX_SWRESET_PRL
) < 0)
388 if (asix_sw_reset(dev
, AX_SWRESET_CLEAR
) < 0)
392 if (asix_sw_reset(dev
, AX_SWRESET_IPRL
) < 0)
395 if (asix_sw_reset(dev
, AX_SWRESET_PRTE
) < 0)
399 rx_ctl
= asix_read_rx_ctl(dev
);
400 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl
);
401 if (asix_write_rx_ctl(dev
, 0x0000) < 0)
404 rx_ctl
= asix_read_rx_ctl(dev
);
405 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl
);
407 dev
->phy_id
= asix_get_phy_addr(dev
);
409 debug("Failed to read phy id\n");
411 asix_mdio_write(dev
, dev
->phy_id
, MII_BMCR
, BMCR_RESET
);
412 asix_mdio_write(dev
, dev
->phy_id
, MII_ADVERTISE
,
413 ADVERTISE_ALL
| ADVERTISE_CSMA
);
414 mii_nway_restart(dev
);
416 if (asix_write_medium_mode(dev
, AX88772_MEDIUM_DEFAULT
) < 0)
419 if (asix_write_cmd(dev
, AX_CMD_WRITE_IPG0
,
420 AX88772_IPG0_DEFAULT
| AX88772_IPG1_DEFAULT
,
421 AX88772_IPG2_DEFAULT
, 0, NULL
) < 0) {
422 debug("Write IPG,IPG1,IPG2 failed\n");
429 static int asix_init_common(struct ueth_data
*dev
, uint8_t *enetaddr
)
432 #define TIMEOUT_RESOLUTION 50 /* ms */
434 u32 ctl
= AX_DEFAULT_RX_CTL
;
436 debug("** %s()\n", __func__
);
438 if ((dev
->pusb_dev
->descriptor
.idVendor
== ASIX_USB_VENDOR_ID
) &&
439 (dev
->pusb_dev
->descriptor
.idProduct
== AX88772B_USB_PRODUCT_ID
))
440 ctl
|= AX_RX_HEADER_DEFAULT
;
442 if (asix_write_rx_ctl(dev
, ctl
) < 0)
445 if (asix_write_hwaddr_common(dev
, enetaddr
) < 0)
449 link_detected
= asix_mdio_read(dev
, dev
->phy_id
, MII_BMSR
) &
451 if (!link_detected
) {
453 printf("Waiting for Ethernet connection... ");
454 udelay(TIMEOUT_RESOLUTION
* 1000);
455 timeout
+= TIMEOUT_RESOLUTION
;
457 } while (!link_detected
&& timeout
< PHY_CONNECT_TIMEOUT
);
462 printf("unable to connect.\n");
467 * Wait some more to avoid timeout on first transfer
468 * (e.g. EHCI timed out on TD - token=0x8008d80)
477 static int asix_send_common(struct ueth_data
*dev
, void *packet
, int length
)
482 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg
,
483 PKTSIZE
+ sizeof(packet_len
));
485 debug("** %s(), len %d\n", __func__
, length
);
487 packet_len
= (((length
) ^ 0x0000ffff) << 16) + (length
);
488 cpu_to_le32s(&packet_len
);
490 memcpy(msg
, &packet_len
, sizeof(packet_len
));
491 memcpy(msg
+ sizeof(packet_len
), (void *)packet
, length
);
493 err
= usb_bulk_msg(dev
->pusb_dev
,
494 usb_sndbulkpipe(dev
->pusb_dev
, dev
->ep_out
),
496 length
+ sizeof(packet_len
),
498 USB_BULK_SEND_TIMEOUT
);
499 debug("Tx: len = %zu, actual = %u, err = %d\n",
500 length
+ sizeof(packet_len
), actual_len
, err
);
505 #ifndef CONFIG_DM_ETH
509 static int asix_init(struct eth_device
*eth
, bd_t
*bd
)
511 struct ueth_data
*dev
= (struct ueth_data
*)eth
->priv
;
513 return asix_init_common(dev
, eth
->enetaddr
);
516 static int asix_send(struct eth_device
*eth
, void *packet
, int length
)
518 struct ueth_data
*dev
= (struct ueth_data
*)eth
->priv
;
520 return asix_send_common(dev
, packet
, length
);
523 static int asix_recv(struct eth_device
*eth
)
525 struct ueth_data
*dev
= (struct ueth_data
*)eth
->priv
;
526 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf
, AX_RX_URB_SIZE
);
527 unsigned char *buf_ptr
;
532 debug("** %s()\n", __func__
);
534 err
= usb_bulk_msg(dev
->pusb_dev
,
535 usb_rcvbulkpipe(dev
->pusb_dev
, dev
->ep_in
),
539 USB_BULK_RECV_TIMEOUT
);
540 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE
,
543 debug("Rx: failed to receive\n");
546 if (actual_len
> AX_RX_URB_SIZE
) {
547 debug("Rx: received too many bytes %d\n", actual_len
);
552 while (actual_len
> 0) {
554 * 1st 4 bytes contain the length of the actual data as two
555 * complementary 16-bit words. Extract the length of the data.
557 if (actual_len
< sizeof(packet_len
)) {
558 debug("Rx: incomplete packet length\n");
561 memcpy(&packet_len
, buf_ptr
, sizeof(packet_len
));
562 le32_to_cpus(&packet_len
);
563 if (((~packet_len
>> 16) & 0x7ff) != (packet_len
& 0x7ff)) {
564 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
565 packet_len
, (~packet_len
>> 16) & 0x7ff,
569 packet_len
= packet_len
& 0x7ff;
570 if (packet_len
> actual_len
- sizeof(packet_len
)) {
571 debug("Rx: too large packet: %d\n", packet_len
);
575 if ((dev
->pusb_dev
->descriptor
.idVendor
==
576 ASIX_USB_VENDOR_ID
) &&
577 (dev
->pusb_dev
->descriptor
.idProduct
==
578 AX88772B_USB_PRODUCT_ID
))
581 /* Notify net stack */
582 net_process_received_packet(buf_ptr
+ sizeof(packet_len
),
585 /* Adjust for next iteration. Packets are padded to 16-bits */
588 actual_len
-= sizeof(packet_len
) + packet_len
;
589 buf_ptr
+= sizeof(packet_len
) + packet_len
;
595 static void asix_halt(struct eth_device
*eth
)
597 debug("** %s()\n", __func__
);
600 static int asix_write_hwaddr(struct eth_device
*eth
)
602 struct ueth_data
*dev
= (struct ueth_data
*)eth
->priv
;
604 return asix_write_hwaddr_common(dev
, eth
->enetaddr
);
608 * Asix probing functions
610 void asix_eth_before_probe(void)
616 unsigned short vendor
;
617 unsigned short product
;
621 static const struct asix_dongle asix_dongles
[] = {
622 { 0x05ac, 0x1402, FLAG_TYPE_AX88772
}, /* Apple USB Ethernet Adapter */
623 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772
}, /* D-Link DUB-E100 H/W Ver B1 */
624 { 0x2001, 0x1a02, FLAG_TYPE_AX88772
}, /* D-Link DUB-E100 H/W Ver C1 */
625 /* Cables-to-Go USB Ethernet Adapter */
626 { 0x0b95, 0x772a, FLAG_TYPE_AX88772
},
627 { 0x0b95, 0x7720, FLAG_TYPE_AX88772
}, /* Trendnet TU2-ET100 V3.0R */
628 { 0x0b95, 0x1720, FLAG_TYPE_AX88172
}, /* SMC */
629 { 0x0db0, 0xa877, FLAG_TYPE_AX88772
}, /* MSI - ASIX 88772a */
630 { 0x13b1, 0x0018, FLAG_TYPE_AX88172
}, /* Linksys 200M v2.1 */
631 { 0x1557, 0x7720, FLAG_TYPE_AX88772
}, /* 0Q0 cable ethernet */
632 /* DLink DUB-E100 H/W Ver B1 Alternate */
633 { 0x2001, 0x3c05, FLAG_TYPE_AX88772
},
635 { 0x0b95, 0x772b, FLAG_TYPE_AX88772B
| FLAG_EEPROM_MAC
},
636 { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B
},
637 { 0x0000, 0x0000, FLAG_NONE
} /* END - Do not remove */
640 /* Probe to see if a new device is actually an asix device */
641 int asix_eth_probe(struct usb_device
*dev
, unsigned int ifnum
,
642 struct ueth_data
*ss
)
644 struct usb_interface
*iface
;
645 struct usb_interface_descriptor
*iface_desc
;
646 int ep_in_found
= 0, ep_out_found
= 0;
649 /* let's examine the device now */
650 iface
= &dev
->config
.if_desc
[ifnum
];
651 iface_desc
= &dev
->config
.if_desc
[ifnum
].desc
;
653 for (i
= 0; asix_dongles
[i
].vendor
!= 0; i
++) {
654 if (dev
->descriptor
.idVendor
== asix_dongles
[i
].vendor
&&
655 dev
->descriptor
.idProduct
== asix_dongles
[i
].product
)
656 /* Found a supported dongle */
660 if (asix_dongles
[i
].vendor
== 0)
663 memset(ss
, 0, sizeof(struct ueth_data
));
665 /* At this point, we know we've got a live one */
666 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
667 dev
->descriptor
.idVendor
, dev
->descriptor
.idProduct
);
669 /* Initialize the ueth_data structure with some useful info */
672 ss
->subclass
= iface_desc
->bInterfaceSubClass
;
673 ss
->protocol
= iface_desc
->bInterfaceProtocol
;
675 /* alloc driver private */
676 ss
->dev_priv
= calloc(1, sizeof(struct asix_private
));
680 ((struct asix_private
*)ss
->dev_priv
)->flags
= asix_dongles
[i
].flags
;
683 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
684 * int. We will ignore any others.
686 for (i
= 0; i
< iface_desc
->bNumEndpoints
; i
++) {
687 /* is it an BULK endpoint? */
688 if ((iface
->ep_desc
[i
].bmAttributes
&
689 USB_ENDPOINT_XFERTYPE_MASK
) == USB_ENDPOINT_XFER_BULK
) {
690 u8 ep_addr
= iface
->ep_desc
[i
].bEndpointAddress
;
691 if (ep_addr
& USB_DIR_IN
) {
693 ss
->ep_in
= ep_addr
&
694 USB_ENDPOINT_NUMBER_MASK
;
699 ss
->ep_out
= ep_addr
&
700 USB_ENDPOINT_NUMBER_MASK
;
706 /* is it an interrupt endpoint? */
707 if ((iface
->ep_desc
[i
].bmAttributes
&
708 USB_ENDPOINT_XFERTYPE_MASK
) == USB_ENDPOINT_XFER_INT
) {
709 ss
->ep_int
= iface
->ep_desc
[i
].bEndpointAddress
&
710 USB_ENDPOINT_NUMBER_MASK
;
711 ss
->irqinterval
= iface
->ep_desc
[i
].bInterval
;
714 debug("Endpoints In %d Out %d Int %d\n",
715 ss
->ep_in
, ss
->ep_out
, ss
->ep_int
);
717 /* Do some basic sanity checks, and bail if we find a problem */
718 if (usb_set_interface(dev
, iface_desc
->bInterfaceNumber
, 0) ||
719 !ss
->ep_in
|| !ss
->ep_out
|| !ss
->ep_int
) {
720 debug("Problems with device\n");
723 dev
->privptr
= (void *)ss
;
727 int asix_eth_get_info(struct usb_device
*dev
, struct ueth_data
*ss
,
728 struct eth_device
*eth
)
730 struct asix_private
*priv
= (struct asix_private
*)ss
->dev_priv
;
733 debug("%s: missing parameter.\n", __func__
);
736 sprintf(eth
->name
, "%s%d", ASIX_BASE_NAME
, curr_eth_dev
++);
737 eth
->init
= asix_init
;
738 eth
->send
= asix_send
;
739 eth
->recv
= asix_recv
;
740 eth
->halt
= asix_halt
;
741 if (!(priv
->flags
& FLAG_TYPE_AX88172
))
742 eth
->write_hwaddr
= asix_write_hwaddr
;
745 if (asix_basic_reset(ss
))
748 /* Get the MAC address */
749 if (asix_read_mac_common(ss
, priv
, eth
->enetaddr
))
751 debug("MAC %pM\n", eth
->enetaddr
);
758 static int asix_eth_start(struct udevice
*dev
)
760 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
761 struct asix_private
*priv
= dev_get_priv(dev
);
763 return asix_init_common(&priv
->ueth
, pdata
->enetaddr
);
766 void asix_eth_stop(struct udevice
*dev
)
768 debug("** %s()\n", __func__
);
771 int asix_eth_send(struct udevice
*dev
, void *packet
, int length
)
773 struct asix_private
*priv
= dev_get_priv(dev
);
775 return asix_send_common(&priv
->ueth
, packet
, length
);
778 int asix_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
780 struct asix_private
*priv
= dev_get_priv(dev
);
781 struct ueth_data
*ueth
= &priv
->ueth
;
786 len
= usb_ether_get_rx_bytes(ueth
, &ptr
);
787 debug("%s: first try, len=%d\n", __func__
, len
);
789 if (!(flags
& ETH_RECV_CHECK_DEVICE
))
791 ret
= usb_ether_receive(ueth
, AX_RX_URB_SIZE
);
795 len
= usb_ether_get_rx_bytes(ueth
, &ptr
);
796 debug("%s: second try, len=%d\n", __func__
, len
);
800 * 1st 4 bytes contain the length of the actual data as two
801 * complementary 16-bit words. Extract the length of the data.
803 if (len
< sizeof(packet_len
)) {
804 debug("Rx: incomplete packet length\n");
807 memcpy(&packet_len
, ptr
, sizeof(packet_len
));
808 le32_to_cpus(&packet_len
);
809 if (((~packet_len
>> 16) & 0x7ff) != (packet_len
& 0x7ff)) {
810 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
811 packet_len
, (~packet_len
>> 16) & 0x7ff,
815 packet_len
= packet_len
& 0x7ff;
816 if (packet_len
> len
- sizeof(packet_len
)) {
817 debug("Rx: too large packet: %d\n", packet_len
);
821 *packetp
= ptr
+ sizeof(packet_len
);
825 usb_ether_advance_rxbuf(ueth
, -1);
829 static int asix_free_pkt(struct udevice
*dev
, uchar
*packet
, int packet_len
)
831 struct asix_private
*priv
= dev_get_priv(dev
);
835 usb_ether_advance_rxbuf(&priv
->ueth
, sizeof(u32
) + packet_len
);
840 int asix_write_hwaddr(struct udevice
*dev
)
842 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
843 struct asix_private
*priv
= dev_get_priv(dev
);
845 if (priv
->flags
& FLAG_TYPE_AX88172
)
848 return asix_write_hwaddr_common(&priv
->ueth
, pdata
->enetaddr
);
851 static int asix_eth_probe(struct udevice
*dev
)
853 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
854 struct asix_private
*priv
= dev_get_priv(dev
);
855 struct ueth_data
*ss
= &priv
->ueth
;
858 priv
->flags
= dev
->driver_data
;
859 ret
= usb_ether_register(dev
, ss
, AX_RX_URB_SIZE
);
863 ret
= asix_basic_reset(ss
);
867 /* Get the MAC address */
868 ret
= asix_read_mac_common(ss
, priv
, pdata
->enetaddr
);
871 debug("MAC %pM\n", pdata
->enetaddr
);
876 return usb_ether_deregister(ss
);
879 static const struct eth_ops asix_eth_ops
= {
880 .start
= asix_eth_start
,
881 .send
= asix_eth_send
,
882 .recv
= asix_eth_recv
,
883 .free_pkt
= asix_free_pkt
,
884 .stop
= asix_eth_stop
,
885 .write_hwaddr
= asix_write_hwaddr
,
888 U_BOOT_DRIVER(asix_eth
) = {
891 .probe
= asix_eth_probe
,
892 .ops
= &asix_eth_ops
,
893 .priv_auto_alloc_size
= sizeof(struct asix_private
),
894 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
897 static const struct usb_device_id asix_eth_id_table
[] = {
898 /* Apple USB Ethernet Adapter */
899 { USB_DEVICE(0x05ac, 0x1402), .driver_info
= FLAG_TYPE_AX88772
},
900 /* D-Link DUB-E100 H/W Ver B1 */
901 { USB_DEVICE(0x07d1, 0x3c05), .driver_info
= FLAG_TYPE_AX88772
},
902 /* D-Link DUB-E100 H/W Ver C1 */
903 { USB_DEVICE(0x2001, 0x1a02), .driver_info
= FLAG_TYPE_AX88772
},
904 /* Cables-to-Go USB Ethernet Adapter */
905 { USB_DEVICE(0x0b95, 0x772a), .driver_info
= FLAG_TYPE_AX88772
},
906 /* Trendnet TU2-ET100 V3.0R */
907 { USB_DEVICE(0x0b95, 0x7720), .driver_info
= FLAG_TYPE_AX88772
},
909 { USB_DEVICE(0x0b95, 0x1720), .driver_info
= FLAG_TYPE_AX88172
},
910 /* MSI - ASIX 88772a */
911 { USB_DEVICE(0x0db0, 0xa877), .driver_info
= FLAG_TYPE_AX88772
},
912 /* Linksys 200M v2.1 */
913 { USB_DEVICE(0x13b1, 0x0018), .driver_info
= FLAG_TYPE_AX88172
},
914 /* 0Q0 cable ethernet */
915 { USB_DEVICE(0x1557, 0x7720), .driver_info
= FLAG_TYPE_AX88772
},
916 /* DLink DUB-E100 H/W Ver B1 Alternate */
917 { USB_DEVICE(0x2001, 0x3c05), .driver_info
= FLAG_TYPE_AX88772
},
919 { USB_DEVICE(0x0b95, 0x772b),
920 .driver_info
= FLAG_TYPE_AX88772B
| FLAG_EEPROM_MAC
},
921 { USB_DEVICE(0x0b95, 0x7e2b), .driver_info
= FLAG_TYPE_AX88772B
},
922 { } /* Terminating entry */
925 U_BOOT_USB_DEVICE(asix_eth
, asix_eth_id_table
);