2 * Based on drivers/usb/gadget/omap1510_udc.c
3 * TI OMAP1510 USB bus interface driver
6 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <usbdevice.h>
16 #include <usb/designware_udc.h>
17 #include <asm/arch/hardware.h>
19 #define UDC_INIT_MDELAY 80 /* Device settle delay */
21 /* Some kind of debugging output... */
22 #ifndef DEBUG_DWUSBTTY
24 #define UDCDBGA(fmt, args...)
26 #define UDCDBG(str) serial_printf(str "\n")
27 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
30 static struct urb
*ep0_urb
;
31 static struct usb_device_instance
*udc_device
;
33 static struct plug_regs
*const plug_regs_p
=
34 (struct plug_regs
* const)CONFIG_SYS_PLUG_BASE
;
35 static struct udc_regs
*const udc_regs_p
=
36 (struct udc_regs
* const)CONFIG_SYS_USBD_BASE
;
37 static struct udc_endp_regs
*const outep_regs_p
=
38 &((struct udc_regs
* const)CONFIG_SYS_USBD_BASE
)->out_regs
[0];
39 static struct udc_endp_regs
*const inep_regs_p
=
40 &((struct udc_regs
* const)CONFIG_SYS_USBD_BASE
)->in_regs
[0];
43 * udc_state_transition - Write the next packet to TxFIFO.
44 * @initial: Initial state.
45 * @final: Final state.
47 * Helper function to implement device state changes. The device states and
48 * the events that transition between them are:
53 * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
59 * DEVICE_RESET DEVICE_POWER_INTERRUPTION
65 * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
71 * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
76 * udc_state_transition transitions up (in the direction from STATE_ATTACHED
77 * to STATE_CONFIGURED) from the specified initial state to the specified final
78 * state, passing through each intermediate state on the way. If the initial
79 * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
80 * no state transitions will take place.
82 * udc_state_transition also transitions down (in the direction from
83 * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
84 * specified final state, passing through each intermediate state on the way.
85 * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
86 * state, then no state transitions will take place.
88 * This function must only be called with interrupts disabled.
90 static void udc_state_transition(usb_device_state_t initial
,
91 usb_device_state_t final
)
93 if (initial
< final
) {
96 usbd_device_event_irq(udc_device
,
97 DEVICE_HUB_CONFIGURED
, 0);
98 if (final
== STATE_POWERED
)
101 usbd_device_event_irq(udc_device
, DEVICE_RESET
, 0);
102 if (final
== STATE_DEFAULT
)
105 usbd_device_event_irq(udc_device
,
106 DEVICE_ADDRESS_ASSIGNED
, 0);
107 if (final
== STATE_ADDRESSED
)
109 case STATE_ADDRESSED
:
110 usbd_device_event_irq(udc_device
, DEVICE_CONFIGURED
, 0);
111 case STATE_CONFIGURED
:
116 } else if (initial
> final
) {
118 case STATE_CONFIGURED
:
119 usbd_device_event_irq(udc_device
,
120 DEVICE_DE_CONFIGURED
, 0);
121 if (final
== STATE_ADDRESSED
)
123 case STATE_ADDRESSED
:
124 usbd_device_event_irq(udc_device
, DEVICE_RESET
, 0);
125 if (final
== STATE_DEFAULT
)
128 usbd_device_event_irq(udc_device
,
129 DEVICE_POWER_INTERRUPTION
, 0);
130 if (final
== STATE_POWERED
)
133 usbd_device_event_irq(udc_device
, DEVICE_HUB_RESET
, 0);
143 static void udc_stall_ep(u32 ep_num
)
145 writel(readl(&inep_regs_p
[ep_num
].endp_cntl
) | ENDP_CNTL_STALL
,
146 &inep_regs_p
[ep_num
].endp_cntl
);
148 writel(readl(&outep_regs_p
[ep_num
].endp_cntl
) | ENDP_CNTL_STALL
,
149 &outep_regs_p
[ep_num
].endp_cntl
);
152 static void *get_fifo(int ep_num
, int in
)
154 u32
*fifo_ptr
= (u32
*)CONFIG_SYS_FIFO_BASE
;
158 fifo_ptr
+= readl(&inep_regs_p
[1].endp_bsorfn
);
159 /* break intentionally left out */
162 fifo_ptr
+= readl(&inep_regs_p
[0].endp_bsorfn
);
163 /* break intentionally left out */
169 readl(&outep_regs_p
[2].endp_maxpacksize
) >> 16;
170 /* break intentionally left out */
176 fifo_ptr
+= readl(&outep_regs_p
[0].endp_maxpacksize
) >> 16;
177 /* break intentionally left out */
180 return (void *)fifo_ptr
;
183 static int usbgetpckfromfifo(int epNum
, u8
*bufp
, u32 len
)
185 u8
*fifo_ptr
= (u8
*)get_fifo(epNum
, 0);
191 if (readl(&udc_regs_p
->dev_stat
) & DEV_STAT_RXFIFO_EMPTY
)
194 nw
= len
/ sizeof(u32
);
195 nb
= len
% sizeof(u32
);
197 /* use tmp buf if bufp is not word aligned */
199 wrdp
= (u32
*)&tmp
[0];
203 for (i
= 0; i
< nw
; i
++) {
204 writel(readl(fifo_ptr
), wrdp
);
209 for (i
= 0; i
< nb
; i
++) {
210 writeb(readb(fifo_ptr
), bytp
);
214 readl(&outep_regs_p
[epNum
].write_done
);
216 /* copy back tmp buffer to bufp if bufp is not word aligned */
218 memcpy(bufp
, tmp
, len
);
223 static void usbputpcktofifo(int epNum
, u8
*bufp
, u32 len
)
228 u8
*fifo_ptr
= get_fifo(epNum
, 1);
230 nw
= len
/ sizeof(int);
231 nb
= len
% sizeof(int);
233 for (i
= 0; i
< nw
; i
++) {
234 writel(*wrdp
, fifo_ptr
);
239 for (i
= 0; i
< nb
; i
++) {
240 writeb(*bytp
, fifo_ptr
);
247 * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
248 * @endpoint: Endpoint pointer.
250 * If the endpoint has an active tx_urb, then the next packet of data from the
251 * URB is written to the tx FIFO. The total amount of data in the urb is given
252 * by urb->actual_length. The maximum amount of data that can be sent in any
253 * one packet is given by endpoint->tx_packetSize. The number of data bytes
254 * from this URB that have already been transmitted is given by endpoint->sent.
255 * endpoint->last is updated by this routine with the number of data bytes
256 * transmitted in this packet.
259 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
262 struct urb
*urb
= endpoint
->tx_urb
;
268 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
269 urb
->buffer
, urb
->buffer_length
, urb
->actual_length
);
271 last
= MIN(urb
->actual_length
- endpoint
->sent
,
272 endpoint
->tx_packetSize
);
275 u8
*cp
= urb
->buffer
+ endpoint
->sent
;
278 * This ensures that USBD packet fifo is accessed
279 * - through word aligned pointer or
280 * - through non word aligned pointer but only
281 * with a max length to make the next packet
285 align
= ((ulong
)cp
% sizeof(int));
287 last
= MIN(last
, sizeof(int) - align
);
289 UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
290 endpoint
->sent
, endpoint
->tx_packetSize
, last
);
292 usbputpcktofifo(endpoint
->endpoint_address
&
293 USB_ENDPOINT_NUMBER_MASK
, cp
, last
);
295 endpoint
->last
= last
;
300 * Handle SETUP USB interrupt.
301 * This function implements TRM Figure 14-14.
303 static void dw_udc_setup(struct usb_endpoint_instance
*endpoint
)
305 u8
*datap
= (u8
*)&ep0_urb
->device_request
;
306 int ep_addr
= endpoint
->endpoint_address
;
308 UDCDBG("-> Entering device setup");
309 usbgetpckfromfifo(ep_addr
, datap
, 8);
311 /* Try to process setup packet */
312 if (ep0_recv_setup(ep0_urb
)) {
313 /* Not a setup packet, stall next EP0 transaction */
315 UDCDBG("can't parse setup packet, still waiting for setup");
319 /* Check direction */
320 if ((ep0_urb
->device_request
.bmRequestType
& USB_REQ_DIRECTION_MASK
)
321 == USB_REQ_HOST2DEVICE
) {
322 UDCDBG("control write on EP0");
323 if (le16_to_cpu(ep0_urb
->device_request
.wLength
)) {
324 /* Stall this request */
325 UDCDBG("Stalling unsupported EP0 control write data "
331 UDCDBG("control read on EP0");
333 * The ep0_recv_setup function has already placed our response
334 * packet data in ep0_urb->buffer and the packet length in
335 * ep0_urb->actual_length.
337 endpoint
->tx_urb
= ep0_urb
;
340 * Write packet data to the FIFO. dw_write_noniso_tx_fifo
341 * will update endpoint->last with the number of bytes written
344 dw_write_noniso_tx_fifo(endpoint
);
346 writel(0x0, &inep_regs_p
[ep_addr
].write_done
);
349 udc_unset_nak(endpoint
->endpoint_address
);
351 UDCDBG("<- Leaving device setup");
355 * Handle endpoint 0 RX interrupt
357 static void dw_udc_ep0_rx(struct usb_endpoint_instance
*endpoint
)
363 /* Check direction */
364 if ((ep0_urb
->device_request
.bmRequestType
365 & USB_REQ_DIRECTION_MASK
) == USB_REQ_HOST2DEVICE
) {
367 * This rx interrupt must be for a control write data
370 * We don't support control write data stages.
371 * We should never end up here.
374 UDCDBG("Stalling unexpected EP0 control write "
375 "data stage packet");
379 * This rx interrupt must be for a control read status
382 UDCDBG("ACK on EP0 control read status stage packet");
383 u32 len
= (readl(&outep_regs_p
[0].endp_status
) >> 11) & 0xfff;
384 usbgetpckfromfifo(0, dummy
, len
);
389 * Handle endpoint 0 TX interrupt
391 static void dw_udc_ep0_tx(struct usb_endpoint_instance
*endpoint
)
393 struct usb_device_request
*request
= &ep0_urb
->device_request
;
398 /* Check direction */
399 if ((request
->bmRequestType
& USB_REQ_DIRECTION_MASK
) ==
400 USB_REQ_HOST2DEVICE
) {
402 * This tx interrupt must be for a control write status
405 UDCDBG("ACK on EP0 control write status stage packet");
408 * This tx interrupt must be for a control read data
411 int wLength
= le16_to_cpu(request
->wLength
);
414 * Update our count of bytes sent so far in this
417 endpoint
->sent
+= endpoint
->last
;
420 * We are finished with this transfer if we have sent
421 * all of the bytes in our tx urb (urb->actual_length)
422 * unless we need a zero-length terminating packet. We
423 * need a zero-length terminating packet if we returned
424 * fewer bytes than were requested (wLength) by the host,
425 * and the number of bytes we returned is an exact
426 * multiple of the packet size endpoint->tx_packetSize.
428 if ((endpoint
->sent
== ep0_urb
->actual_length
) &&
429 ((ep0_urb
->actual_length
== wLength
) ||
430 (endpoint
->last
!= endpoint
->tx_packetSize
))) {
431 /* Done with control read data stage. */
432 UDCDBG("control read data stage complete");
435 * We still have another packet of data to send
436 * in this control read data stage or else we
437 * need a zero-length terminating packet.
439 UDCDBG("ACK control read data stage packet");
440 dw_write_noniso_tx_fifo(endpoint
);
442 ep_addr
= endpoint
->endpoint_address
;
443 writel(0x0, &inep_regs_p
[ep_addr
].write_done
);
448 static struct usb_endpoint_instance
*dw_find_ep(int ep
)
452 for (i
= 0; i
< udc_device
->bus
->max_endpoints
; i
++) {
453 if ((udc_device
->bus
->endpoint_array
[i
].endpoint_address
&
454 USB_ENDPOINT_NUMBER_MASK
) == ep
)
455 return &udc_device
->bus
->endpoint_array
[i
];
461 * Handle RX transaction on non-ISO endpoint.
462 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
463 * in the range 1 to 15.
465 static void dw_udc_epn_rx(int ep
)
469 struct usb_endpoint_instance
*endpoint
= dw_find_ep(ep
);
472 urb
= endpoint
->rcv_urb
;
475 u8
*cp
= urb
->buffer
+ urb
->actual_length
;
477 nbytes
= (readl(&outep_regs_p
[ep
].endp_status
) >> 11) &
479 usbgetpckfromfifo(ep
, cp
, nbytes
);
480 usbd_rcv_complete(endpoint
, nbytes
, 0);
486 * Handle TX transaction on non-ISO endpoint.
487 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
488 * in the range 16 to 30.
490 static void dw_udc_epn_tx(int ep
)
492 struct usb_endpoint_instance
*endpoint
= dw_find_ep(ep
);
498 * We need to transmit a terminating zero-length packet now if
499 * we have sent all of the data in this URB and the transfer
500 * size was an exact multiple of the packet size.
502 if (endpoint
->tx_urb
&&
503 (endpoint
->last
== endpoint
->tx_packetSize
) &&
504 (endpoint
->tx_urb
->actual_length
- endpoint
->sent
-
505 endpoint
->last
== 0)) {
506 /* handle zero length packet here */
507 writel(0x0, &inep_regs_p
[ep
].write_done
);
511 if (endpoint
->tx_urb
&& endpoint
->tx_urb
->actual_length
) {
512 /* retire the data that was just sent */
513 usbd_tx_complete(endpoint
);
515 * Check to see if we have more data ready to transmit
518 if (endpoint
->tx_urb
&& endpoint
->tx_urb
->actual_length
) {
519 /* write data to FIFO */
520 dw_write_noniso_tx_fifo(endpoint
);
521 writel(0x0, &inep_regs_p
[ep
].write_done
);
523 } else if (endpoint
->tx_urb
524 && (endpoint
->tx_urb
->actual_length
== 0)) {
525 /* udc_set_nak(ep); */
531 * Start of public functions.
534 /* Called to start packet transmission. */
535 int udc_endpoint_write(struct usb_endpoint_instance
*endpoint
)
537 udc_unset_nak(endpoint
->endpoint_address
& USB_ENDPOINT_NUMBER_MASK
);
541 /* Start to initialize h/w stuff */
551 readl(&plug_regs_p
->plug_pending
);
553 for (i
= 0; i
< UDC_INIT_MDELAY
; i
++)
556 plug_st
= readl(&plug_regs_p
->plug_state
);
557 writel(plug_st
| PLUG_STATUS_EN
, &plug_regs_p
->plug_state
);
559 writel(~0x0, &udc_regs_p
->endp_int
);
560 writel(~0x0, &udc_regs_p
->dev_int_mask
);
561 writel(~0x0, &udc_regs_p
->endp_int_mask
);
563 #ifndef CONFIG_USBD_HS
564 writel(DEV_CONF_FS_SPEED
| DEV_CONF_REMWAKEUP
| DEV_CONF_SELFPOW
|
565 DEV_CONF_PHYINT_16
, &udc_regs_p
->dev_conf
);
567 writel(DEV_CONF_HS_SPEED
| DEV_CONF_REMWAKEUP
| DEV_CONF_SELFPOW
|
568 DEV_CONF_PHYINT_16
, &udc_regs_p
->dev_conf
);
571 writel(DEV_CNTL_SOFTDISCONNECT
, &udc_regs_p
->dev_cntl
);
573 /* Clear all interrupts pending */
574 writel(DEV_INT_MSK
, &udc_regs_p
->dev_int
);
579 int is_usbd_high_speed(void)
581 return (readl(&udc_regs_p
->dev_stat
) & DEV_STAT_ENUM
) ? 0 : 1;
585 * udc_setup_ep - setup endpoint
586 * Associate a physical endpoint with endpoint_instance
588 void udc_setup_ep(struct usb_device_instance
*device
,
589 u32 ep
, struct usb_endpoint_instance
*endpoint
)
591 UDCDBGA("setting up endpoint addr %x", endpoint
->endpoint_address
);
600 if ((ep
!= 0) && (udc_device
->device_state
< STATE_ADDRESSED
))
603 tt
= getenv("usbtty");
607 ep_addr
= endpoint
->endpoint_address
;
608 ep_num
= ep_addr
& USB_ENDPOINT_NUMBER_MASK
;
610 if ((ep_addr
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
) {
612 packet_size
= endpoint
->tx_packetSize
;
613 buffer_size
= packet_size
* 2;
614 attributes
= endpoint
->tx_attributes
;
617 packet_size
= endpoint
->rcv_packetSize
;
618 buffer_size
= packet_size
* 2;
619 attributes
= endpoint
->rcv_attributes
;
622 switch (attributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
623 case USB_ENDPOINT_XFER_CONTROL
:
624 ep_type
= ENDP_EPTYPE_CNTL
;
626 case USB_ENDPOINT_XFER_BULK
:
628 ep_type
= ENDP_EPTYPE_BULK
;
630 case USB_ENDPOINT_XFER_INT
:
631 ep_type
= ENDP_EPTYPE_INT
;
633 case USB_ENDPOINT_XFER_ISOC
:
634 ep_type
= ENDP_EPTYPE_ISO
;
638 struct udc_endp_regs
*out_p
= &outep_regs_p
[ep_num
];
639 struct udc_endp_regs
*in_p
= &inep_regs_p
[ep_num
];
642 /* Setup endpoint 0 */
643 buffer_size
= packet_size
;
645 writel(readl(&in_p
->endp_cntl
) | ENDP_CNTL_CNAK
,
648 writel(readl(&out_p
->endp_cntl
) | ENDP_CNTL_CNAK
,
651 writel(ENDP_CNTL_CONTROL
| ENDP_CNTL_FLUSH
, &in_p
->endp_cntl
);
653 writel(buffer_size
/ sizeof(int), &in_p
->endp_bsorfn
);
655 writel(packet_size
, &in_p
->endp_maxpacksize
);
657 writel(ENDP_CNTL_CONTROL
| ENDP_CNTL_RRDY
, &out_p
->endp_cntl
);
659 writel(packet_size
| ((buffer_size
/ sizeof(int)) << 16),
660 &out_p
->endp_maxpacksize
);
662 } else if ((ep_addr
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
) {
663 /* Setup the IN endpoint */
664 writel(0x0, &in_p
->endp_status
);
665 writel((ep_type
<< 4) | ENDP_CNTL_RRDY
, &in_p
->endp_cntl
);
666 writel(buffer_size
/ sizeof(int), &in_p
->endp_bsorfn
);
667 writel(packet_size
, &in_p
->endp_maxpacksize
);
669 if (!strcmp(tt
, "cdc_acm")) {
670 if (ep_type
== ENDP_EPTYPE_INT
) {
671 /* Conf no. 1 Interface no. 0 */
672 writel((packet_size
<< 19) |
673 ENDP_EPDIR_IN
| (1 << 7) |
674 (0 << 11) | (ep_type
<< 5) | ep_num
,
675 &udc_regs_p
->udc_endp_reg
[ep_num
]);
677 /* Conf no. 1 Interface no. 1 */
678 writel((packet_size
<< 19) |
679 ENDP_EPDIR_IN
| (1 << 7) |
680 (1 << 11) | (ep_type
<< 5) | ep_num
,
681 &udc_regs_p
->udc_endp_reg
[ep_num
]);
684 /* Conf no. 1 Interface no. 0 */
685 writel((packet_size
<< 19) |
686 ENDP_EPDIR_IN
| (1 << 7) |
687 (0 << 11) | (ep_type
<< 5) | ep_num
,
688 &udc_regs_p
->udc_endp_reg
[ep_num
]);
692 /* Setup the OUT endpoint */
693 writel(0x0, &out_p
->endp_status
);
694 writel((ep_type
<< 4) | ENDP_CNTL_RRDY
, &out_p
->endp_cntl
);
695 writel(packet_size
| ((buffer_size
/ sizeof(int)) << 16),
696 &out_p
->endp_maxpacksize
);
698 if (!strcmp(tt
, "cdc_acm")) {
699 writel((packet_size
<< 19) |
700 ENDP_EPDIR_OUT
| (1 << 7) |
701 (1 << 11) | (ep_type
<< 5) | ep_num
,
702 &udc_regs_p
->udc_endp_reg
[ep_num
]);
704 writel((packet_size
<< 19) |
705 ENDP_EPDIR_OUT
| (1 << 7) |
706 (0 << 11) | (ep_type
<< 5) | ep_num
,
707 &udc_regs_p
->udc_endp_reg
[ep_num
]);
712 endp_intmask
= readl(&udc_regs_p
->endp_int_mask
);
713 endp_intmask
&= ~((1 << ep_num
) | 0x10000 << ep_num
);
714 writel(endp_intmask
, &udc_regs_p
->endp_int_mask
);
717 /* Turn on the USB connection by enabling the pullup resistor */
718 void udc_connect(void)
720 u32 plug_st
, dev_cntl
;
722 dev_cntl
= readl(&udc_regs_p
->dev_cntl
);
723 dev_cntl
|= DEV_CNTL_SOFTDISCONNECT
;
724 writel(dev_cntl
, &udc_regs_p
->dev_cntl
);
728 dev_cntl
= readl(&udc_regs_p
->dev_cntl
);
729 dev_cntl
&= ~DEV_CNTL_SOFTDISCONNECT
;
730 writel(dev_cntl
, &udc_regs_p
->dev_cntl
);
732 plug_st
= readl(&plug_regs_p
->plug_state
);
733 plug_st
&= ~(PLUG_STATUS_PHY_RESET
| PLUG_STATUS_PHY_MODE
);
734 writel(plug_st
, &plug_regs_p
->plug_state
);
737 /* Turn off the USB connection by disabling the pullup resistor */
738 void udc_disconnect(void)
742 writel(DEV_CNTL_SOFTDISCONNECT
, &udc_regs_p
->dev_cntl
);
744 plug_st
= readl(&plug_regs_p
->plug_state
);
745 plug_st
|= (PLUG_STATUS_PHY_RESET
| PLUG_STATUS_PHY_MODE
);
746 writel(plug_st
, &plug_regs_p
->plug_state
);
749 /* Switch on the UDC */
750 void udc_enable(struct usb_device_instance
*device
)
752 UDCDBGA("enable device %p, status %d", device
, device
->status
);
754 /* Save the device structure pointer */
760 usbd_alloc_urb(udc_device
, udc_device
->bus
->endpoint_array
);
762 serial_printf("udc_enable: ep0_urb already allocated %p\n",
766 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int_mask
);
770 * udc_startup - allow udc code to do any additional startup
772 void udc_startup_events(struct usb_device_instance
*device
)
774 /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
775 usbd_device_event_irq(device
, DEVICE_INIT
, 0);
778 * The DEVICE_CREATE event puts the USB device in the state
781 usbd_device_event_irq(device
, DEVICE_CREATE
, 0);
784 * Some USB controller driver implementations signal
785 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
786 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
787 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
788 * The DW USB client controller has the capability to detect when the
789 * USB cable is connected to a powered USB bus, so we will defer the
790 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
797 * Plug detection interrupt handling
799 static void dw_udc_plug_irq(void)
801 if (readl(&plug_regs_p
->plug_state
) & PLUG_STATUS_ATTACHED
) {
804 * Turn off PHY reset bit (PLUG detect).
805 * Switch PHY opmode to normal operation (PLUG detect).
808 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int_mask
);
810 UDCDBG("device attached and powered");
811 udc_state_transition(udc_device
->device_state
, STATE_POWERED
);
813 writel(~0x0, &udc_regs_p
->dev_int_mask
);
815 UDCDBG("device detached or unpowered");
816 udc_state_transition(udc_device
->device_state
, STATE_ATTACHED
);
821 * Device interrupt handling
823 static void dw_udc_dev_irq(void)
825 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_USBRESET
) {
826 writel(~0x0, &udc_regs_p
->endp_int_mask
);
828 writel(readl(&inep_regs_p
[0].endp_cntl
) | ENDP_CNTL_FLUSH
,
829 &inep_regs_p
[0].endp_cntl
);
831 writel(DEV_INT_USBRESET
, &udc_regs_p
->dev_int
);
834 * This endpoint0 specific register can be programmed only
835 * after the phy clock is initialized
837 writel((EP0_MAX_PACKET_SIZE
<< 19) | ENDP_EPTYPE_CNTL
,
838 &udc_regs_p
->udc_endp_reg
[0]);
840 UDCDBG("device reset in progess");
841 udc_state_transition(udc_device
->device_state
, STATE_DEFAULT
);
844 /* Device Enumeration completed */
845 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_ENUM
) {
846 writel(DEV_INT_ENUM
, &udc_regs_p
->dev_int
);
848 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
849 writel(readl(&udc_regs_p
->endp_int_mask
) & ~0x10001,
850 &udc_regs_p
->endp_int_mask
);
852 UDCDBG("default -> addressed");
853 udc_state_transition(udc_device
->device_state
, STATE_ADDRESSED
);
856 /* The USB will be in SUSPEND in 3 ms */
857 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_INACTIVE
) {
858 writel(DEV_INT_INACTIVE
, &udc_regs_p
->dev_int
);
860 UDCDBG("entering inactive state");
861 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
864 /* SetConfiguration command received */
865 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SETCFG
) {
866 writel(DEV_INT_SETCFG
, &udc_regs_p
->dev_int
);
868 UDCDBG("entering configured state");
869 udc_state_transition(udc_device
->device_state
,
873 /* SetInterface command received */
874 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SETINTF
)
875 writel(DEV_INT_SETINTF
, &udc_regs_p
->dev_int
);
877 /* USB Suspend detected on cable */
878 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SUSPUSB
) {
879 writel(DEV_INT_SUSPUSB
, &udc_regs_p
->dev_int
);
881 UDCDBG("entering suspended state");
882 usbd_device_event_irq(udc_device
, DEVICE_BUS_INACTIVE
, 0);
885 /* USB Start-Of-Frame detected on cable */
886 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SOF
)
887 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int
);
891 * Endpoint interrupt handling
893 static void dw_udc_endpoint_irq(void)
895 while (readl(&udc_regs_p
->endp_int
) & ENDP0_INT_CTRLOUT
) {
897 writel(ENDP0_INT_CTRLOUT
, &udc_regs_p
->endp_int
);
899 if ((readl(&outep_regs_p
[0].endp_status
) & ENDP_STATUS_OUTMSK
)
900 == ENDP_STATUS_OUT_SETUP
) {
901 dw_udc_setup(udc_device
->bus
->endpoint_array
+ 0);
902 writel(ENDP_STATUS_OUT_SETUP
,
903 &outep_regs_p
[0].endp_status
);
905 } else if ((readl(&outep_regs_p
[0].endp_status
) &
906 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_DATA
) {
907 dw_udc_ep0_rx(udc_device
->bus
->endpoint_array
+ 0);
908 writel(ENDP_STATUS_OUT_DATA
,
909 &outep_regs_p
[0].endp_status
);
911 } else if ((readl(&outep_regs_p
[0].endp_status
) &
912 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_NONE
) {
916 writel(0x0, &outep_regs_p
[0].endp_status
);
919 if (readl(&udc_regs_p
->endp_int
) & ENDP0_INT_CTRLIN
) {
920 dw_udc_ep0_tx(udc_device
->bus
->endpoint_array
+ 0);
922 writel(ENDP_STATUS_IN
, &inep_regs_p
[0].endp_status
);
923 writel(ENDP0_INT_CTRLIN
, &udc_regs_p
->endp_int
);
926 if (readl(&udc_regs_p
->endp_int
) & ENDP_INT_NONISOOUT_MSK
) {
928 u32 ep_int
= readl(&udc_regs_p
->endp_int
) &
929 ENDP_INT_NONISOOUT_MSK
;
932 while (0x0 == (ep_int
& 0x1)) {
937 writel((1 << 16) << epnum
, &udc_regs_p
->endp_int
);
939 if ((readl(&outep_regs_p
[epnum
].endp_status
) &
940 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_DATA
) {
942 dw_udc_epn_rx(epnum
);
943 writel(ENDP_STATUS_OUT_DATA
,
944 &outep_regs_p
[epnum
].endp_status
);
945 } else if ((readl(&outep_regs_p
[epnum
].endp_status
) &
946 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_NONE
) {
947 writel(0x0, &outep_regs_p
[epnum
].endp_status
);
951 if (readl(&udc_regs_p
->endp_int
) & ENDP_INT_NONISOIN_MSK
) {
953 u32 ep_int
= readl(&udc_regs_p
->endp_int
) &
954 ENDP_INT_NONISOIN_MSK
;
956 while (0x0 == (ep_int
& 0x1)) {
961 if (readl(&inep_regs_p
[epnum
].endp_status
) & ENDP_STATUS_IN
) {
962 writel(ENDP_STATUS_IN
,
963 &outep_regs_p
[epnum
].endp_status
);
964 dw_udc_epn_tx(epnum
);
966 writel(ENDP_STATUS_IN
,
967 &outep_regs_p
[epnum
].endp_status
);
970 writel((1 << epnum
), &udc_regs_p
->endp_int
);
980 * Loop while we have interrupts.
981 * If we don't do this, the input chain
982 * polling delay is likely to miss
985 while (readl(&plug_regs_p
->plug_pending
))
988 while (readl(&udc_regs_p
->dev_int
))
991 if (readl(&udc_regs_p
->endp_int
))
992 dw_udc_endpoint_irq();
996 void udc_set_nak(int epid
)
998 writel(readl(&inep_regs_p
[epid
].endp_cntl
) | ENDP_CNTL_SNAK
,
999 &inep_regs_p
[epid
].endp_cntl
);
1001 writel(readl(&outep_regs_p
[epid
].endp_cntl
) | ENDP_CNTL_SNAK
,
1002 &outep_regs_p
[epid
].endp_cntl
);
1005 void udc_unset_nak(int epid
)
1009 val
= readl(&inep_regs_p
[epid
].endp_cntl
);
1010 val
&= ~ENDP_CNTL_SNAK
;
1011 val
|= ENDP_CNTL_CNAK
;
1012 writel(val
, &inep_regs_p
[epid
].endp_cntl
);
1014 val
= readl(&outep_regs_p
[epid
].endp_cntl
);
1015 val
&= ~ENDP_CNTL_SNAK
;
1016 val
|= ENDP_CNTL_CNAK
;
1017 writel(val
, &outep_regs_p
[epid
].endp_cntl
);