]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/usb/gadget/dwc2_udc_otg_phy.c
2 * drivers/usb/gadget/dwc2_udc_otg.c
3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2008 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * SPDX-License-Identifier: GPL-2.0+
22 #include <linux/errno.h>
23 #include <linux/list.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
29 #include <asm/byteorder.h>
30 #include <asm/unaligned.h>
33 #include <asm/mach-types.h>
35 #include "dwc2_udc_otg_regs.h"
36 #include "dwc2_udc_otg_priv.h"
37 #include <usb/lin_gadget_compat.h>
39 #include <usb/dwc2_udc.h>
41 void otg_phy_init(struct dwc2_udc
*dev
)
43 unsigned int usb_phy_ctrl
= dev
->pdata
->usb_phy_ctrl
;
44 struct dwc2_usbotg_phy
*phy
=
45 (struct dwc2_usbotg_phy
*)dev
->pdata
->regs_phy
;
47 dev
->pdata
->phy_control(1);
50 printf("USB PHY0 Enable\n");
53 writel(readl(usb_phy_ctrl
) | USB_PHY_CTRL_EN0
, usb_phy_ctrl
);
55 if (dev
->pdata
->usb_flags
== PHY0_SLEEP
) /* C210 Universal */
56 writel((readl(&phy
->phypwr
)
57 &~(PHY_0_SLEEP
| OTG_DISABLE_0
| ANALOG_PWRDOWN
)
58 &~FORCE_SUSPEND_0
), &phy
->phypwr
);
60 writel((readl(&phy
->phypwr
) &~(OTG_DISABLE_0
| ANALOG_PWRDOWN
)
61 &~FORCE_SUSPEND_0
), &phy
->phypwr
);
63 if (s5p_cpu_id
== 0x4412)
64 writel((readl(&phy
->phyclk
) & ~(EXYNOS4X12_ID_PULLUP0
|
65 EXYNOS4X12_COMMON_ON_N0
)) | EXYNOS4X12_CLK_SEL_24MHZ
,
66 &phy
->phyclk
); /* PLL 24Mhz */
68 writel((readl(&phy
->phyclk
) & ~(ID_PULLUP0
| COMMON_ON_N0
)) |
69 CLK_SEL_24MHZ
, &phy
->phyclk
); /* PLL 24Mhz */
71 writel((readl(&phy
->rstcon
) &~(LINK_SW_RST
| PHYLNK_SW_RST
))
72 | PHY_SW_RST0
, &phy
->rstcon
);
74 writel(readl(&phy
->rstcon
)
75 &~(PHY_SW_RST0
| LINK_SW_RST
| PHYLNK_SW_RST
), &phy
->rstcon
);
79 void otg_phy_off(struct dwc2_udc
*dev
)
81 unsigned int usb_phy_ctrl
= dev
->pdata
->usb_phy_ctrl
;
82 struct dwc2_usbotg_phy
*phy
=
83 (struct dwc2_usbotg_phy
*)dev
->pdata
->regs_phy
;
85 /* reset controller just in case */
86 writel(PHY_SW_RST0
, &phy
->rstcon
);
88 writel(readl(&phy
->phypwr
) &~PHY_SW_RST0
, &phy
->rstcon
);
91 writel(readl(&phy
->phypwr
) | OTG_DISABLE_0
| ANALOG_PWRDOWN
92 | FORCE_SUSPEND_0
, &phy
->phypwr
);
94 writel(readl(usb_phy_ctrl
) &~USB_PHY_CTRL_EN0
, usb_phy_ctrl
);
96 writel((readl(&phy
->phyclk
) & ~(ID_PULLUP0
| COMMON_ON_N0
)),
101 dev
->pdata
->phy_control(0);