drivers/usb/gadget/dwc2_udc_otg_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* linux/arch/arm/plat-s3c/include/plat/regs-otg.h
   3  *
   4  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
   5  *
   6  * Registers remapping:
   7  * Lukasz Majewski <l.majewski@samsumg.com>
   8  */
   9
  10 #ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
  11 #define __ASM_ARCH_REGS_USB_OTG_HS_H
  12
  13 /* USB2.0 OTG Controller register */
  14 struct dwc2_usbotg_phy {
  15         u32 phypwr;
  16         u32 phyclk;
  17         u32 rstcon;
  18 };
  19
  20 /* Device Logical IN Endpoint-Specific Registers */
  21 struct dwc2_dev_in_endp {
  22         u32 diepctl;
  23         u8  res1[4];
  24         u32 diepint;
  25         u8  res2[4];
  26         u32 dieptsiz;
  27         u32 diepdma;
  28         u8  res3[4];
  29         u32 diepdmab;
  30 };
  31
  32 /* Device Logical OUT Endpoint-Specific Registers */
  33 struct dwc2_dev_out_endp {
  34         u32 doepctl;
  35         u8  res1[4];
  36         u32 doepint;
  37         u8  res2[4];
  38         u32 doeptsiz;
  39         u32 doepdma;
  40         u8  res3[4];
  41         u32 doepdmab;
  42 };
  43
  44 struct ep_fifo {
  45         u32 fifo;
  46         u8  res[4092];
  47 };
  48
  49 /* USB2.0 OTG Controller register */
  50 struct dwc2_usbotg_reg {
  51         /* Core Global Registers */
  52         u32 gotgctl; /* OTG Control & Status */
  53         u32 gotgint; /* OTG Interrupt */
  54         u32 gahbcfg; /* Core AHB Configuration */
  55         u32 gusbcfg; /* Core USB Configuration */
  56         u32 grstctl; /* Core Reset */
  57         u32 gintsts; /* Core Interrupt */
  58         u32 gintmsk; /* Core Interrupt Mask */
  59         u32 grxstsr; /* Receive Status Debug Read/Status Read */
  60         u32 grxstsp; /* Receive Status Debug Pop/Status Pop */
  61         u32 grxfsiz; /* Receive FIFO Size */
  62         u32 gnptxfsiz; /* Non-Periodic Transmit FIFO Size */
  63
  64         u8  res1[36];
  65         u32 ghwcfg4; /* User HW Config4 */
  66         u8  res2[176];
  67         u32 dieptxf[15]; /* Device Periodic Transmit FIFO size register */
  68         u8  res3[1728];
  69         /* Device Configuration */
  70         u32 dcfg; /* Device Configuration Register */
  71         u32 dctl; /* Device Control */
  72         u32 dsts; /* Device Status */
  73         u8  res4[4];
  74         u32 diepmsk; /* Device IN Endpoint Common Interrupt Mask */
  75         u32 doepmsk; /* Device OUT Endpoint Common Interrupt Mask */
  76         u32 daint; /* Device All Endpoints Interrupt */
  77         u32 daintmsk; /* Device All Endpoints Interrupt Mask */
  78         u8  res5[224];
  79         struct dwc2_dev_in_endp in_endp[16];
  80         struct dwc2_dev_out_endp out_endp[16];
  81         u8  res6[768];
  82         struct ep_fifo ep[16];
  83 };
  84
  85 /*===================================================================== */
  86 /*definitions related to CSR setting */
  87
  88 /* DWC2_UDC_OTG_GOTGCTL */
  89 #define B_SESSION_VALID                 BIT(19)
  90 #define A_SESSION_VALID                 BIT(18)
  91 #define B_VALOVAL                       BIT(7)
  92 #define B_VALOEN                        BIT(6)
  93 #define A_VALOVAL                       BIT(5)
  94 #define A_VALOEN                        BIT(4)
  95
  96 /* DWC2_UDC_OTG_GAHBCFG */
  97 #define PTXFE_HALF                      (0<<8)
  98 #define PTXFE_ZERO                      (1<<8)
  99 #define NPTXFE_HALF                     (0<<7)
 100 #define NPTXFE_ZERO                     (1<<7)
 101 #define MODE_SLAVE                      (0<<5)
 102 #define MODE_DMA                        (1<<5)
 103 #define BURST_SINGLE                    (0<<1)
 104 #define BURST_INCR                      (1<<1)
 105 #define BURST_INCR4                     (3<<1)
 106 #define BURST_INCR8                     (5<<1)
 107 #define BURST_INCR16                    (7<<1)
 108 #define GBL_INT_UNMASK                  (1<<0)
 109 #define GBL_INT_MASK                    (0<<0)
 110
 111 /* DWC2_UDC_OTG_GRSTCTL */
 112 #define AHB_MASTER_IDLE         (1u<<31)
 113 #define CORE_SOFT_RESET         (0x1<<0)
 114
 115 /* DWC2_UDC_OTG_GINTSTS/DWC2_UDC_OTG_GINTMSK core interrupt register */
 116 #define INT_RESUME                      (1u<<31)
 117 #define INT_DISCONN                     (0x1<<29)
 118 #define INT_CONN_ID_STS_CNG             (0x1<<28)
 119 #define INT_OUT_EP                      (0x1<<19)
 120 #define INT_IN_EP                       (0x1<<18)
 121 #define INT_ENUMDONE                    (0x1<<13)
 122 #define INT_RESET                       (0x1<<12)
 123 #define INT_SUSPEND                     (0x1<<11)
 124 #define INT_EARLY_SUSPEND               (0x1<<10)
 125 #define INT_NP_TX_FIFO_EMPTY            (0x1<<5)
 126 #define INT_RX_FIFO_NOT_EMPTY           (0x1<<4)
 127 #define INT_SOF                 (0x1<<3)
 128 #define INT_DEV_MODE                    (0x0<<0)
 129 #define INT_HOST_MODE                   (0x1<<1)
 130 #define INT_GOUTNakEff                  (0x01<<7)
 131 #define INT_GINNakEff                   (0x01<<6)
 132
 133 #define FULL_SPEED_CONTROL_PKT_SIZE     8
 134 #define FULL_SPEED_BULK_PKT_SIZE        64
 135
 136 #define HIGH_SPEED_CONTROL_PKT_SIZE     64
 137 #define HIGH_SPEED_BULK_PKT_SIZE        512
 138
 139 #define RX_FIFO_SIZE                    (1024)
 140 #define NPTX_FIFO_SIZE                  (1024)
 141 #define PTX_FIFO_SIZE                   (384)
 142
 143 #define DEPCTL_TXFNUM_0         (0x0<<22)
 144 #define DEPCTL_TXFNUM_1         (0x1<<22)
 145 #define DEPCTL_TXFNUM_2         (0x2<<22)
 146 #define DEPCTL_TXFNUM_3         (0x3<<22)
 147 #define DEPCTL_TXFNUM_4         (0x4<<22)
 148
 149 /* Enumeration speed */
 150 #define USB_HIGH_30_60MHZ               (0x0<<1)
 151 #define USB_FULL_30_60MHZ               (0x1<<1)
 152 #define USB_LOW_6MHZ                    (0x2<<1)
 153 #define USB_FULL_48MHZ                  (0x3<<1)
 154
 155 /* DWC2_UDC_OTG_GRXSTSP STATUS */
 156 #define OUT_PKT_RECEIVED                (0x2<<17)
 157 #define OUT_TRANSFER_COMPLELTED (0x3<<17)
 158 #define SETUP_TRANSACTION_COMPLETED     (0x4<<17)
 159 #define SETUP_PKT_RECEIVED              (0x6<<17)
 160 #define GLOBAL_OUT_NAK                  (0x1<<17)
 161
 162 /* DWC2_UDC_OTG_DCTL device control register */
 163 #define NORMAL_OPERATION                (0x1<<0)
 164 #define SOFT_DISCONNECT         (0x1<<1)
 165
 166 /* DWC2_UDC_OTG_DAINT device all endpoint interrupt register */
 167 #define DAINT_OUT_BIT                   (16)
 168 #define DAINT_MASK                      (0xFFFF)
 169
 170 /* DWC2_UDC_OTG_DIEPCTL0/DOEPCTL0 device
 171    control IN/OUT endpoint 0 control register */
 172 #define DEPCTL_EPENA                    (0x1<<31)
 173 #define DEPCTL_EPDIS                    (0x1<<30)
 174 #define DEPCTL_SETD1PID         (0x1<<29)
 175 #define DEPCTL_SETD0PID         (0x1<<28)
 176 #define DEPCTL_SNAK                     (0x1<<27)
 177 #define DEPCTL_CNAK                     (0x1<<26)
 178 #define DEPCTL_STALL                    (0x1<<21)
 179 #define DEPCTL_TYPE_BIT         (18)
 180 #define DEPCTL_TYPE_MASK                (0x3<<18)
 181 #define DEPCTL_CTRL_TYPE                (0x0<<18)
 182 #define DEPCTL_ISO_TYPE         (0x1<<18)
 183 #define DEPCTL_BULK_TYPE                (0x2<<18)
 184 #define DEPCTL_INTR_TYPE                (0x3<<18)
 185 #define DEPCTL_USBACTEP         (0x1<<15)
 186 #define DEPCTL_NEXT_EP_BIT              (11)
 187 #define DEPCTL_MPS_BIT                  (0)
 188 #define DEPCTL_MPS_MASK         (0x7FF)
 189
 190 #define DEPCTL0_MPS_64                  (0x0<<0)
 191 #define DEPCTL0_MPS_32                  (0x1<<0)
 192 #define DEPCTL0_MPS_16                  (0x2<<0)
 193 #define DEPCTL0_MPS_8                   (0x3<<0)
 194 #define DEPCTL_MPS_BULK_512             (512<<0)
 195 #define DEPCTL_MPS_INT_MPS_16           (16<<0)
 196
 197 #define DIEPCTL0_NEXT_EP_BIT            (11)
 198
 199
 200 /* DWC2_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint
 201    common interrupt mask register */
 202 /* DWC2_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
 203 #define BACK2BACK_SETUP_RECEIVED        (0x1<<6)
 204 #define INTKNEPMIS                      (0x1<<5)
 205 #define INTKN_TXFEMP                    (0x1<<4)
 206 #define NON_ISO_IN_EP_TIMEOUT           (0x1<<3)
 207 #define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
 208 #define AHB_ERROR                       (0x1<<2)
 209 #define EPDISBLD                        (0x1<<1)
 210 #define TRANSFER_DONE                   (0x1<<0)
 211
 212 #define USB_PHY_CTRL_EN0                (0x1 << 0)
 213
 214 /* OPHYPWR */
 215 #define PHY_0_SLEEP                     (0x1 << 5)
 216 #define OTG_DISABLE_0                   (0x1 << 4)
 217 #define ANALOG_PWRDOWN                  (0x1 << 3)
 218 #define FORCE_SUSPEND_0                 (0x1 << 0)
 219
 220 /* URSTCON */
 221 #define HOST_SW_RST                     (0x1 << 4)
 222 #define PHY_SW_RST1                     (0x1 << 3)
 223 #define PHYLNK_SW_RST                   (0x1 << 2)
 224 #define LINK_SW_RST                     (0x1 << 1)
 225 #define PHY_SW_RST0                     (0x1 << 0)
 226
 227 /* OPHYCLK */
 228 #define COMMON_ON_N1                    (0x1 << 7)
 229 #define COMMON_ON_N0                    (0x1 << 4)
 230 #define ID_PULLUP0                      (0x1 << 2)
 231 #define CLK_SEL_24MHZ                   (0x3 << 0)
 232 #define CLK_SEL_12MHZ                   (0x2 << 0)
 233 #define CLK_SEL_48MHZ                   (0x0 << 0)
 234
 235 #define EXYNOS4X12_ID_PULLUP0           (0x01 << 3)
 236 #define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4)
 237 #define EXYNOS4X12_CLK_SEL_12MHZ        (0x02 << 0)
 238 #define EXYNOS4X12_CLK_SEL_24MHZ        (0x05 << 0)
 239
 240 /* Device Configuration Register DCFG */
 241 #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
 242 #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
 243 #define DEV_SPEED_LOW_SPEED_11          (0x2 << 0)
 244 #define DEV_SPEED_FULL_SPEED_11         (0x3 << 0)
 245 #define EP_MISS_CNT(x)                  (x << 18)
 246 #define DEVICE_ADDRESS(x)               (x << 4)
 247
 248 /* Core Reset Register (GRSTCTL) */
 249 #define TX_FIFO_FLUSH                   (0x1 << 5)
 250 #define RX_FIFO_FLUSH                   (0x1 << 4)
 251 #define TX_FIFO_NUMBER(x)               (x << 6)
 252 #define TX_FIFO_FLUSH_ALL               TX_FIFO_NUMBER(0x10)
 253
 254 /* Masks definitions */
 255 #define GINTMSK_INIT    (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
 256                         | INT_RESET | INT_SUSPEND)
 257 #define DOEPMSK_INIT    (CTRL_OUT_EP_SETUP_PHASE_DONE | AHB_ERROR|TRANSFER_DONE)
 258 #define DIEPMSK_INIT    (NON_ISO_IN_EP_TIMEOUT|AHB_ERROR|TRANSFER_DONE)
 259 #define GAHBCFG_INIT    (PTXFE_HALF | NPTXFE_HALF | MODE_DMA | BURST_INCR4\
 260                         | GBL_INT_UNMASK)
 261
 262 /* Device Endpoint X Transfer Size Register (DIEPTSIZX) */
 263 #define DIEPT_SIZ_PKT_CNT(x)                      (x << 19)
 264 #define DIEPT_SIZ_XFER_SIZE(x)                    (x << 0)
 265
 266 /* Device OUT Endpoint X Transfer Size Register (DOEPTSIZX) */
 267 #define DOEPT_SIZ_PKT_CNT(x)                      (x << 19)
 268 #define DOEPT_SIZ_XFER_SIZE(x)                    (x << 0)
 269 #define DOEPT_SIZ_XFER_SIZE_MAX_EP0               (0x7F << 0)
 270 #define DOEPT_SIZ_XFER_SIZE_MAX_EP                (0x7FFF << 0)
 271
 272 /* Device Endpoint-N Control Register (DIEPCTLn/DOEPCTLn) */
 273 #define DIEPCTL_TX_FIFO_NUM(x)                    (x << 22)
 274 #define DIEPCTL_TX_FIFO_NUM_MASK                  (~DIEPCTL_TX_FIFO_NUM(0xF))
 275
 276 /* Device ALL Endpoints Interrupt Register (DAINT) */
 277 #define DAINT_IN_EP_INT(x)                        (x << 0)
 278 #define DAINT_OUT_EP_INT(x)                       (x << 16)
 279
 280 /* User HW Config4 */
 281 #define GHWCFG4_NUM_IN_EPS_MASK         (0xf << 26)
 282 #define GHWCFG4_NUM_IN_EPS_SHIFT        26
 283 #endif