2 * Based on drivers/usb/gadget/omap1510_udc.c
3 * TI OMAP1510 USB bus interface driver
6 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <usbdevice.h>
32 #include <usb/spr_udc.h>
33 #include <asm/arch/hardware.h>
34 #include <asm/arch/spr_misc.h>
36 #define UDC_INIT_MDELAY 80 /* Device settle delay */
38 /* Some kind of debugging output... */
39 #ifndef DEBUG_SPRUSBTTY
41 #define UDCDBGA(fmt, args...)
43 #define UDCDBG(str) serial_printf(str "\n")
44 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
47 static struct urb
*ep0_urb
;
48 static struct usb_device_instance
*udc_device
;
50 static struct plug_regs
*const plug_regs_p
=
51 (struct plug_regs
* const)CONFIG_SYS_PLUG_BASE
;
52 static struct udc_regs
*const udc_regs_p
=
53 (struct udc_regs
* const)CONFIG_SYS_USBD_BASE
;
54 static struct udc_endp_regs
*const outep_regs_p
=
55 &((struct udc_regs
* const)CONFIG_SYS_USBD_BASE
)->out_regs
[0];
56 static struct udc_endp_regs
*const inep_regs_p
=
57 &((struct udc_regs
* const)CONFIG_SYS_USBD_BASE
)->in_regs
[0];
60 * udc_state_transition - Write the next packet to TxFIFO.
61 * @initial: Initial state.
62 * @final: Final state.
64 * Helper function to implement device state changes. The device states and
65 * the events that transition between them are:
70 * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET
76 * DEVICE_RESET DEVICE_POWER_INTERRUPTION
82 * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET
88 * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED
93 * udc_state_transition transitions up (in the direction from STATE_ATTACHED
94 * to STATE_CONFIGURED) from the specified initial state to the specified final
95 * state, passing through each intermediate state on the way. If the initial
96 * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
97 * no state transitions will take place.
99 * udc_state_transition also transitions down (in the direction from
100 * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
101 * specified final state, passing through each intermediate state on the way.
102 * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
103 * state, then no state transitions will take place.
105 * This function must only be called with interrupts disabled.
107 static void udc_state_transition(usb_device_state_t initial
,
108 usb_device_state_t final
)
110 if (initial
< final
) {
113 usbd_device_event_irq(udc_device
,
114 DEVICE_HUB_CONFIGURED
, 0);
115 if (final
== STATE_POWERED
)
118 usbd_device_event_irq(udc_device
, DEVICE_RESET
, 0);
119 if (final
== STATE_DEFAULT
)
122 usbd_device_event_irq(udc_device
,
123 DEVICE_ADDRESS_ASSIGNED
, 0);
124 if (final
== STATE_ADDRESSED
)
126 case STATE_ADDRESSED
:
127 usbd_device_event_irq(udc_device
, DEVICE_CONFIGURED
, 0);
128 case STATE_CONFIGURED
:
133 } else if (initial
> final
) {
135 case STATE_CONFIGURED
:
136 usbd_device_event_irq(udc_device
,
137 DEVICE_DE_CONFIGURED
, 0);
138 if (final
== STATE_ADDRESSED
)
140 case STATE_ADDRESSED
:
141 usbd_device_event_irq(udc_device
, DEVICE_RESET
, 0);
142 if (final
== STATE_DEFAULT
)
145 usbd_device_event_irq(udc_device
,
146 DEVICE_POWER_INTERRUPTION
, 0);
147 if (final
== STATE_POWERED
)
150 usbd_device_event_irq(udc_device
, DEVICE_HUB_RESET
, 0);
160 static void udc_stall_ep(u32 ep_num
)
162 writel(readl(&inep_regs_p
[ep_num
].endp_cntl
) | ENDP_CNTL_STALL
,
163 &inep_regs_p
[ep_num
].endp_cntl
);
165 writel(readl(&outep_regs_p
[ep_num
].endp_cntl
) | ENDP_CNTL_STALL
,
166 &outep_regs_p
[ep_num
].endp_cntl
);
169 static void *get_fifo(int ep_num
, int in
)
171 u32
*fifo_ptr
= (u32
*)CONFIG_SYS_FIFO_BASE
;
175 fifo_ptr
+= readl(&inep_regs_p
[1].endp_bsorfn
);
176 /* break intentionally left out */
179 fifo_ptr
+= readl(&inep_regs_p
[0].endp_bsorfn
);
180 /* break intentionally left out */
186 readl(&outep_regs_p
[2].endp_maxpacksize
) >> 16;
187 /* break intentionally left out */
193 fifo_ptr
+= readl(&outep_regs_p
[0].endp_maxpacksize
) >> 16;
194 /* break intentionally left out */
197 return (void *)fifo_ptr
;
200 static int usbgetpckfromfifo(int epNum
, u8
*bufp
, u32 len
)
202 u8
*fifo_ptr
= (u8
*)get_fifo(epNum
, 0);
207 if (readl(&udc_regs_p
->dev_stat
) & DEV_STAT_RXFIFO_EMPTY
)
210 nw
= len
/ sizeof(u32
);
211 nb
= len
% sizeof(u32
);
214 for (i
= 0; i
< nw
; i
++) {
215 writel(readl(fifo_ptr
), wrdp
);
220 for (i
= 0; i
< nb
; i
++) {
221 writeb(readb(fifo_ptr
), bytp
);
225 readl(&outep_regs_p
[epNum
].write_done
);
230 static void usbputpcktofifo(int epNum
, u8
*bufp
, u32 len
)
235 u8
*fifo_ptr
= get_fifo(epNum
, 1);
237 nw
= len
/ sizeof(int);
238 nb
= len
% sizeof(int);
240 for (i
= 0; i
< nw
; i
++) {
241 writel(*wrdp
, fifo_ptr
);
246 for (i
= 0; i
< nb
; i
++) {
247 writeb(*bytp
, fifo_ptr
);
254 * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO.
255 * @endpoint: Endpoint pointer.
257 * If the endpoint has an active tx_urb, then the next packet of data from the
258 * URB is written to the tx FIFO. The total amount of data in the urb is given
259 * by urb->actual_length. The maximum amount of data that can be sent in any
260 * one packet is given by endpoint->tx_packetSize. The number of data bytes
261 * from this URB that have already been transmitted is given by endpoint->sent.
262 * endpoint->last is updated by this routine with the number of data bytes
263 * transmitted in this packet.
266 static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance
269 struct urb
*urb
= endpoint
->tx_urb
;
275 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
276 urb
->buffer
, urb
->buffer_length
, urb
->actual_length
);
278 last
= MIN(urb
->actual_length
- endpoint
->sent
,
279 endpoint
->tx_packetSize
);
282 u8
*cp
= urb
->buffer
+ endpoint
->sent
;
285 * This ensures that USBD packet fifo is accessed
286 * - through word aligned pointer or
287 * - through non word aligned pointer but only
288 * with a max length to make the next packet
292 align
= ((ulong
)cp
% sizeof(int));
294 last
= MIN(last
, sizeof(int) - align
);
296 UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
297 endpoint
->sent
, endpoint
->tx_packetSize
, last
);
299 usbputpcktofifo(endpoint
->endpoint_address
&
300 USB_ENDPOINT_NUMBER_MASK
, cp
, last
);
302 endpoint
->last
= last
;
307 * Handle SETUP USB interrupt.
308 * This function implements TRM Figure 14-14.
310 static void spear_udc_setup(struct usb_endpoint_instance
*endpoint
)
312 u8
*datap
= (u8
*)&ep0_urb
->device_request
;
313 int ep_addr
= endpoint
->endpoint_address
;
315 UDCDBG("-> Entering device setup");
316 usbgetpckfromfifo(ep_addr
, datap
, 8);
318 /* Try to process setup packet */
319 if (ep0_recv_setup(ep0_urb
)) {
320 /* Not a setup packet, stall next EP0 transaction */
322 UDCDBG("can't parse setup packet, still waiting for setup");
326 /* Check direction */
327 if ((ep0_urb
->device_request
.bmRequestType
& USB_REQ_DIRECTION_MASK
)
328 == USB_REQ_HOST2DEVICE
) {
329 UDCDBG("control write on EP0");
330 if (le16_to_cpu(ep0_urb
->device_request
.wLength
)) {
331 /* Stall this request */
332 UDCDBG("Stalling unsupported EP0 control write data "
338 UDCDBG("control read on EP0");
340 * The ep0_recv_setup function has already placed our response
341 * packet data in ep0_urb->buffer and the packet length in
342 * ep0_urb->actual_length.
344 endpoint
->tx_urb
= ep0_urb
;
347 * Write packet data to the FIFO. spear_write_noniso_tx_fifo
348 * will update endpoint->last with the number of bytes written
351 spear_write_noniso_tx_fifo(endpoint
);
353 writel(0x0, &inep_regs_p
[ep_addr
].write_done
);
356 udc_unset_nak(endpoint
->endpoint_address
);
358 UDCDBG("<- Leaving device setup");
362 * Handle endpoint 0 RX interrupt
364 static void spear_udc_ep0_rx(struct usb_endpoint_instance
*endpoint
)
370 /* Check direction */
371 if ((ep0_urb
->device_request
.bmRequestType
372 & USB_REQ_DIRECTION_MASK
) == USB_REQ_HOST2DEVICE
) {
374 * This rx interrupt must be for a control write data
377 * We don't support control write data stages.
378 * We should never end up here.
381 UDCDBG("Stalling unexpected EP0 control write "
382 "data stage packet");
386 * This rx interrupt must be for a control read status
389 UDCDBG("ACK on EP0 control read status stage packet");
390 u32 len
= (readl(&outep_regs_p
[0].endp_status
) >> 11) & 0xfff;
391 usbgetpckfromfifo(0, dummy
, len
);
396 * Handle endpoint 0 TX interrupt
398 static void spear_udc_ep0_tx(struct usb_endpoint_instance
*endpoint
)
400 struct usb_device_request
*request
= &ep0_urb
->device_request
;
405 /* Check direction */
406 if ((request
->bmRequestType
& USB_REQ_DIRECTION_MASK
) ==
407 USB_REQ_HOST2DEVICE
) {
409 * This tx interrupt must be for a control write status
412 UDCDBG("ACK on EP0 control write status stage packet");
415 * This tx interrupt must be for a control read data
418 int wLength
= le16_to_cpu(request
->wLength
);
421 * Update our count of bytes sent so far in this
424 endpoint
->sent
+= endpoint
->last
;
427 * We are finished with this transfer if we have sent
428 * all of the bytes in our tx urb (urb->actual_length)
429 * unless we need a zero-length terminating packet. We
430 * need a zero-length terminating packet if we returned
431 * fewer bytes than were requested (wLength) by the host,
432 * and the number of bytes we returned is an exact
433 * multiple of the packet size endpoint->tx_packetSize.
435 if ((endpoint
->sent
== ep0_urb
->actual_length
) &&
436 ((ep0_urb
->actual_length
== wLength
) ||
437 (endpoint
->last
!= endpoint
->tx_packetSize
))) {
438 /* Done with control read data stage. */
439 UDCDBG("control read data stage complete");
442 * We still have another packet of data to send
443 * in this control read data stage or else we
444 * need a zero-length terminating packet.
446 UDCDBG("ACK control read data stage packet");
447 spear_write_noniso_tx_fifo(endpoint
);
449 ep_addr
= endpoint
->endpoint_address
;
450 writel(0x0, &inep_regs_p
[ep_addr
].write_done
);
455 static struct usb_endpoint_instance
*spear_find_ep(int ep
)
459 for (i
= 0; i
< udc_device
->bus
->max_endpoints
; i
++) {
460 if ((udc_device
->bus
->endpoint_array
[i
].endpoint_address
&
461 USB_ENDPOINT_NUMBER_MASK
) == ep
)
462 return &udc_device
->bus
->endpoint_array
[i
];
468 * Handle RX transaction on non-ISO endpoint.
469 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
470 * in the range 1 to 15.
472 static void spear_udc_epn_rx(int ep
)
476 struct usb_endpoint_instance
*endpoint
= spear_find_ep(ep
);
479 urb
= endpoint
->rcv_urb
;
482 u8
*cp
= urb
->buffer
+ urb
->actual_length
;
484 nbytes
= (readl(&outep_regs_p
[ep
].endp_status
) >> 11) &
486 usbgetpckfromfifo(ep
, cp
, nbytes
);
487 usbd_rcv_complete(endpoint
, nbytes
, 0);
493 * Handle TX transaction on non-ISO endpoint.
494 * The ep argument is a physical endpoint number for a non-ISO IN endpoint
495 * in the range 16 to 30.
497 static void spear_udc_epn_tx(int ep
)
499 struct usb_endpoint_instance
*endpoint
= spear_find_ep(ep
);
502 * We need to transmit a terminating zero-length packet now if
503 * we have sent all of the data in this URB and the transfer
504 * size was an exact multiple of the packet size.
506 if (endpoint
&& endpoint
->tx_urb
&& endpoint
->tx_urb
->actual_length
) {
507 if (endpoint
->last
== endpoint
->tx_packetSize
) {
508 /* handle zero length packet here */
509 writel(0x0, &inep_regs_p
[ep
].write_done
);
511 /* retire the data that was just sent */
512 usbd_tx_complete(endpoint
);
514 * Check to see if we have more data ready to transmit
517 if (endpoint
->tx_urb
&& endpoint
->tx_urb
->actual_length
) {
518 /* write data to FIFO */
519 spear_write_noniso_tx_fifo(endpoint
);
520 writel(0x0, &inep_regs_p
[ep
].write_done
);
522 } else if (endpoint
->tx_urb
523 && (endpoint
->tx_urb
->actual_length
== 0)) {
524 /* udc_set_nak(ep); */
530 * Start of public functions.
533 /* Called to start packet transmission. */
534 int udc_endpoint_write(struct usb_endpoint_instance
*endpoint
)
536 udc_unset_nak(endpoint
->endpoint_address
& USB_ENDPOINT_NUMBER_MASK
);
540 /* Start to initialize h/w stuff */
550 readl(&plug_regs_p
->plug_pending
);
554 for (i
= 0; i
< UDC_INIT_MDELAY
; i
++)
557 plug_st
= readl(&plug_regs_p
->plug_state
);
558 writel(plug_st
| PLUG_STATUS_EN
, &plug_regs_p
->plug_state
);
560 writel(~0x0, &udc_regs_p
->endp_int
);
561 writel(~0x0, &udc_regs_p
->dev_int_mask
);
562 writel(~0x0, &udc_regs_p
->endp_int_mask
);
564 writel(DEV_CONF_FS_SPEED
| DEV_CONF_REMWAKEUP
| DEV_CONF_SELFPOW
|
565 /* Dev_Conf_SYNCFRAME | */
566 DEV_CONF_PHYINT_16
, &udc_regs_p
->dev_conf
);
568 writel(0x0, &udc_regs_p
->dev_cntl
);
570 /* Clear all interrupts pending */
571 writel(DEV_INT_MSK
, &udc_regs_p
->dev_int
);
577 * udc_setup_ep - setup endpoint
578 * Associate a physical endpoint with endpoint_instance
580 void udc_setup_ep(struct usb_device_instance
*device
,
581 u32 ep
, struct usb_endpoint_instance
*endpoint
)
583 UDCDBGA("setting up endpoint addr %x", endpoint
->endpoint_address
);
592 tt
= getenv("usbtty");
596 ep_addr
= endpoint
->endpoint_address
;
597 ep_num
= ep_addr
& USB_ENDPOINT_NUMBER_MASK
;
599 if ((ep_addr
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
) {
601 packet_size
= endpoint
->tx_packetSize
;
602 buffer_size
= packet_size
* 2;
603 attributes
= endpoint
->tx_attributes
;
606 packet_size
= endpoint
->rcv_packetSize
;
607 buffer_size
= packet_size
* 2;
608 attributes
= endpoint
->rcv_attributes
;
611 switch (attributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
612 case USB_ENDPOINT_XFER_CONTROL
:
613 ep_type
= ENDP_EPTYPE_CNTL
;
615 case USB_ENDPOINT_XFER_BULK
:
617 ep_type
= ENDP_EPTYPE_BULK
;
619 case USB_ENDPOINT_XFER_INT
:
620 ep_type
= ENDP_EPTYPE_INT
;
622 case USB_ENDPOINT_XFER_ISOC
:
623 ep_type
= ENDP_EPTYPE_ISO
;
627 struct udc_endp_regs
*out_p
= &outep_regs_p
[ep_num
];
628 struct udc_endp_regs
*in_p
= &inep_regs_p
[ep_num
];
631 /* Setup endpoint 0 */
632 buffer_size
= packet_size
;
634 writel(readl(&in_p
->endp_cntl
) | ENDP_CNTL_CNAK
,
637 writel(readl(&out_p
->endp_cntl
) | ENDP_CNTL_CNAK
,
640 writel(ENDP_CNTL_CONTROL
| ENDP_CNTL_FLUSH
, &in_p
->endp_cntl
);
642 writel(buffer_size
/ sizeof(int), &in_p
->endp_bsorfn
);
644 writel(packet_size
, &in_p
->endp_maxpacksize
);
646 writel(ENDP_CNTL_CONTROL
| ENDP_CNTL_RRDY
, &out_p
->endp_cntl
);
648 writel(packet_size
| ((buffer_size
/ sizeof(int)) << 16),
649 &out_p
->endp_maxpacksize
);
651 writel((packet_size
<< 19) | ENDP_EPTYPE_CNTL
,
652 &udc_regs_p
->udc_endp_reg
[ep_num
]);
654 } else if ((ep_addr
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
) {
655 /* Setup the IN endpoint */
656 writel(0x0, &in_p
->endp_status
);
657 writel((ep_type
<< 4) | ENDP_CNTL_RRDY
, &in_p
->endp_cntl
);
658 writel(buffer_size
/ sizeof(int), &in_p
->endp_bsorfn
);
659 writel(packet_size
, &in_p
->endp_maxpacksize
);
661 if (!strcmp(tt
, "cdc_acm")) {
662 if (ep_type
== ENDP_EPTYPE_INT
) {
663 /* Conf no. 1 Interface no. 0 */
664 writel((packet_size
<< 19) |
665 ENDP_EPDIR_IN
| (1 << 7) |
666 (0 << 11) | (ep_type
<< 5) | ep_num
,
667 &udc_regs_p
->udc_endp_reg
[ep_num
]);
669 /* Conf no. 1 Interface no. 1 */
670 writel((packet_size
<< 19) |
671 ENDP_EPDIR_IN
| (1 << 7) |
672 (1 << 11) | (ep_type
<< 5) | ep_num
,
673 &udc_regs_p
->udc_endp_reg
[ep_num
]);
676 /* Conf no. 1 Interface no. 0 */
677 writel((packet_size
<< 19) |
678 ENDP_EPDIR_IN
| (1 << 7) |
679 (0 << 11) | (ep_type
<< 5) | ep_num
,
680 &udc_regs_p
->udc_endp_reg
[ep_num
]);
684 /* Setup the OUT endpoint */
685 writel(0x0, &out_p
->endp_status
);
686 writel((ep_type
<< 4) | ENDP_CNTL_RRDY
, &out_p
->endp_cntl
);
687 writel(packet_size
| ((buffer_size
/ sizeof(int)) << 16),
688 &out_p
->endp_maxpacksize
);
690 if (!strcmp(tt
, "cdc_acm")) {
691 writel((packet_size
<< 19) |
692 ENDP_EPDIR_OUT
| (1 << 7) |
693 (1 << 11) | (ep_type
<< 5) | ep_num
,
694 &udc_regs_p
->udc_endp_reg
[ep_num
]);
696 writel((packet_size
<< 19) |
697 ENDP_EPDIR_OUT
| (1 << 7) |
698 (0 << 11) | (ep_type
<< 5) | ep_num
,
699 &udc_regs_p
->udc_endp_reg
[ep_num
]);
704 endp_intmask
= readl(&udc_regs_p
->endp_int_mask
);
705 endp_intmask
&= ~((1 << ep_num
) | 0x10000 << ep_num
);
706 writel(endp_intmask
, &udc_regs_p
->endp_int_mask
);
709 /* Turn on the USB connection by enabling the pullup resistor */
710 void udc_connect(void)
714 plug_st
= readl(&plug_regs_p
->plug_state
);
715 plug_st
&= ~(PLUG_STATUS_PHY_RESET
| PLUG_STATUS_PHY_MODE
);
716 writel(plug_st
, &plug_regs_p
->plug_state
);
719 /* Turn off the USB connection by disabling the pullup resistor */
720 void udc_disconnect(void)
724 plug_st
= readl(&plug_regs_p
->plug_state
);
725 plug_st
|= (PLUG_STATUS_PHY_RESET
| PLUG_STATUS_PHY_MODE
);
726 writel(plug_st
, &plug_regs_p
->plug_state
);
729 /* Switch on the UDC */
730 void udc_enable(struct usb_device_instance
*device
)
732 UDCDBGA("enable device %p, status %d", device
, device
->status
);
734 /* Save the device structure pointer */
740 usbd_alloc_urb(udc_device
, udc_device
->bus
->endpoint_array
);
742 serial_printf("udc_enable: ep0_urb already allocated %p\n",
746 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int_mask
);
750 * udc_startup - allow udc code to do any additional startup
752 void udc_startup_events(struct usb_device_instance
*device
)
754 /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
755 usbd_device_event_irq(device
, DEVICE_INIT
, 0);
758 * The DEVICE_CREATE event puts the USB device in the state
761 usbd_device_event_irq(device
, DEVICE_CREATE
, 0);
764 * Some USB controller driver implementations signal
765 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
766 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
767 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
768 * The SPEAr USB client controller has the capability to detect when the
769 * USB cable is connected to a powered USB bus, so we will defer the
770 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
777 * Plug detection interrupt handling
779 void spear_udc_plug_irq(void)
781 if (readl(&plug_regs_p
->plug_state
) & PLUG_STATUS_ATTACHED
) {
784 * Turn off PHY reset bit (PLUG detect).
785 * Switch PHY opmode to normal operation (PLUG detect).
788 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int_mask
);
790 UDCDBG("device attached and powered");
791 udc_state_transition(udc_device
->device_state
, STATE_POWERED
);
795 * Reset the PHY and switch the mode.
798 writel(~0x0, &udc_regs_p
->dev_int_mask
);
800 UDCDBG("device detached or unpowered");
801 udc_state_transition(udc_device
->device_state
, STATE_ATTACHED
);
806 * Device interrupt handling
808 void spear_udc_dev_irq(void)
810 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_USBRESET
) {
811 writel(~0x0, &udc_regs_p
->endp_int_mask
);
815 writel(readl(&inep_regs_p
[0].endp_cntl
) | ENDP_CNTL_FLUSH
,
816 &inep_regs_p
[0].endp_cntl
);
818 writel(DEV_INT_USBRESET
, &udc_regs_p
->dev_int
);
820 UDCDBG("device reset in progess");
821 udc_state_transition(udc_device
->device_state
, STATE_DEFAULT
);
824 /* Device Enumeration completed */
825 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_ENUM
) {
826 writel(DEV_INT_ENUM
, &udc_regs_p
->dev_int
);
828 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
829 writel(readl(&udc_regs_p
->endp_int_mask
) & ~0x10001,
830 &udc_regs_p
->endp_int_mask
);
832 UDCDBG("default -> addressed");
833 udc_state_transition(udc_device
->device_state
, STATE_ADDRESSED
);
836 /* The USB will be in SUSPEND in 3 ms */
837 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_INACTIVE
) {
838 writel(DEV_INT_INACTIVE
, &udc_regs_p
->dev_int
);
840 UDCDBG("entering inactive state");
841 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
844 /* SetConfiguration command received */
845 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SETCFG
) {
846 writel(DEV_INT_SETCFG
, &udc_regs_p
->dev_int
);
848 UDCDBG("entering configured state");
849 udc_state_transition(udc_device
->device_state
,
853 /* SetInterface command received */
854 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SETINTF
)
855 writel(DEV_INT_SETINTF
, &udc_regs_p
->dev_int
);
857 /* USB Suspend detected on cable */
858 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SUSPUSB
) {
859 writel(DEV_INT_SUSPUSB
, &udc_regs_p
->dev_int
);
861 UDCDBG("entering suspended state");
862 usbd_device_event_irq(udc_device
, DEVICE_BUS_INACTIVE
, 0);
865 /* USB Start-Of-Frame detected on cable */
866 if (readl(&udc_regs_p
->dev_int
) & DEV_INT_SOF
)
867 writel(DEV_INT_SOF
, &udc_regs_p
->dev_int
);
871 * Endpoint interrupt handling
873 void spear_udc_endpoint_irq(void)
875 while (readl(&udc_regs_p
->endp_int
) & ENDP0_INT_CTRLOUT
) {
877 writel(ENDP0_INT_CTRLOUT
, &udc_regs_p
->endp_int
);
879 if ((readl(&outep_regs_p
[0].endp_status
) & ENDP_STATUS_OUTMSK
)
880 == ENDP_STATUS_OUT_SETUP
) {
881 spear_udc_setup(udc_device
->bus
->endpoint_array
+ 0);
882 writel(ENDP_STATUS_OUT_SETUP
,
883 &outep_regs_p
[0].endp_status
);
885 } else if ((readl(&outep_regs_p
[0].endp_status
) &
886 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_DATA
) {
887 spear_udc_ep0_rx(udc_device
->bus
->endpoint_array
+ 0);
888 writel(ENDP_STATUS_OUT_DATA
,
889 &outep_regs_p
[0].endp_status
);
891 } else if ((readl(&outep_regs_p
[0].endp_status
) &
892 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_NONE
) {
896 writel(0x0, &outep_regs_p
[0].endp_status
);
899 if (readl(&udc_regs_p
->endp_int
) & ENDP0_INT_CTRLIN
) {
900 spear_udc_ep0_tx(udc_device
->bus
->endpoint_array
+ 0);
902 writel(ENDP_STATUS_IN
, &inep_regs_p
[0].endp_status
);
903 writel(ENDP0_INT_CTRLIN
, &udc_regs_p
->endp_int
);
906 while (readl(&udc_regs_p
->endp_int
) & ENDP_INT_NONISOOUT_MSK
) {
908 u32 ep_int
= readl(&udc_regs_p
->endp_int
) &
909 ENDP_INT_NONISOOUT_MSK
;
912 while (0x0 == (ep_int
& 0x1)) {
917 writel((1 << 16) << epnum
, &udc_regs_p
->endp_int
);
919 if ((readl(&outep_regs_p
[epnum
].endp_status
) &
920 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_DATA
) {
922 spear_udc_epn_rx(epnum
);
923 writel(ENDP_STATUS_OUT_DATA
,
924 &outep_regs_p
[epnum
].endp_status
);
925 } else if ((readl(&outep_regs_p
[epnum
].endp_status
) &
926 ENDP_STATUS_OUTMSK
) == ENDP_STATUS_OUT_NONE
) {
927 writel(0x0, &outep_regs_p
[epnum
].endp_status
);
931 if (readl(&udc_regs_p
->endp_int
) & ENDP_INT_NONISOIN_MSK
) {
933 u32 ep_int
= readl(&udc_regs_p
->endp_int
) &
934 ENDP_INT_NONISOIN_MSK
;
936 while (0x0 == (ep_int
& 0x1)) {
941 if (readl(&inep_regs_p
[epnum
].endp_status
) & ENDP_STATUS_IN
) {
942 writel(ENDP_STATUS_IN
,
943 &outep_regs_p
[epnum
].endp_status
);
944 spear_udc_epn_tx(epnum
);
946 writel(ENDP_STATUS_IN
,
947 &outep_regs_p
[epnum
].endp_status
);
950 writel((1 << epnum
), &udc_regs_p
->endp_int
);
960 * Loop while we have interrupts.
961 * If we don't do this, the input chain
962 * polling delay is likely to miss
965 while (readl(&plug_regs_p
->plug_pending
))
966 spear_udc_plug_irq();
968 while (readl(&udc_regs_p
->dev_int
))
971 if (readl(&udc_regs_p
->endp_int
))
972 spear_udc_endpoint_irq();
976 void udc_set_nak(int epid
)
978 writel(readl(&inep_regs_p
[epid
].endp_cntl
) | ENDP_CNTL_SNAK
,
979 &inep_regs_p
[epid
].endp_cntl
);
981 writel(readl(&outep_regs_p
[epid
].endp_cntl
) | ENDP_CNTL_SNAK
,
982 &outep_regs_p
[epid
].endp_cntl
);
985 void udc_unset_nak(int epid
)
989 val
= readl(&inep_regs_p
[epid
].endp_cntl
);
990 val
&= ~ENDP_CNTL_SNAK
;
991 val
|= ENDP_CNTL_CNAK
;
992 writel(val
, &inep_regs_p
[epid
].endp_cntl
);
994 val
= readl(&outep_regs_p
[epid
].endp_cntl
);
995 val
&= ~ENDP_CNTL_SNAK
;
996 val
|= ENDP_CNTL_CNAK
;
997 writel(val
, &outep_regs_p
[epid
].endp_cntl
);