2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (64 * 1024)
28 #define MAX_ENDPOINT 16
32 uint8_t aligned_buffer
[DWC2_DATA_BUF_SIZE
] __aligned(ARCH_DMA_MINALIGN
);
33 uint8_t status_buffer
[DWC2_STATUS_BUF_SIZE
] __aligned(ARCH_DMA_MINALIGN
);
35 uint8_t *aligned_buffer
;
36 uint8_t *status_buffer
;
38 int bulk_data_toggle
[MAX_DEVICE
][MAX_ENDPOINT
];
39 struct dwc2_core_regs
*regs
;
44 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
45 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr
, DWC2_DATA_BUF_SIZE
,
47 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr
, DWC2_STATUS_BUF_SIZE
,
50 static struct dwc2_priv local
;
58 * Initializes the FSLSPClkSel field of the HCFG register
59 * depending on the PHY type.
61 static void init_fslspclksel(struct dwc2_core_regs
*regs
)
65 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
66 phyclk
= DWC2_HCFG_FSLSPCLKSEL_48_MHZ
; /* Full speed PHY */
68 /* High speed PHY running at full speed or high speed */
69 phyclk
= DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ
;
72 #ifdef CONFIG_DWC2_ULPI_FS_LS
73 uint32_t hwcfg2
= readl(®s
->ghwcfg2
);
74 uint32_t hval
= (ghwcfg2
& DWC2_HWCFG2_HS_PHY_TYPE_MASK
) >>
75 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET
;
76 uint32_t fval
= (ghwcfg2
& DWC2_HWCFG2_FS_PHY_TYPE_MASK
) >>
77 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET
;
79 if (hval
== 2 && fval
== 1)
80 phyclk
= DWC2_HCFG_FSLSPCLKSEL_48_MHZ
; /* Full speed PHY */
83 clrsetbits_le32(®s
->host_regs
.hcfg
,
84 DWC2_HCFG_FSLSPCLKSEL_MASK
,
85 phyclk
<< DWC2_HCFG_FSLSPCLKSEL_OFFSET
);
91 * @param regs Programming view of DWC_otg controller.
92 * @param num Tx FIFO to flush.
94 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs
*regs
, const int num
)
98 writel(DWC2_GRSTCTL_TXFFLSH
| (num
<< DWC2_GRSTCTL_TXFNUM_OFFSET
),
100 ret
= wait_for_bit(__func__
, ®s
->grstctl
, DWC2_GRSTCTL_TXFFLSH
,
103 printf("%s: Timeout!\n", __func__
);
105 /* Wait for 3 PHY Clocks */
112 * @param regs Programming view of DWC_otg controller.
114 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs
*regs
)
118 writel(DWC2_GRSTCTL_RXFFLSH
, ®s
->grstctl
);
119 ret
= wait_for_bit(__func__
, ®s
->grstctl
, DWC2_GRSTCTL_RXFFLSH
,
122 printf("%s: Timeout!\n", __func__
);
124 /* Wait for 3 PHY Clocks */
129 * Do core a soft reset of the core. Be careful with this because it
130 * resets all the internal state machines of the core.
132 static void dwc_otg_core_reset(struct dwc2_core_regs
*regs
)
136 /* Wait for AHB master IDLE state. */
137 ret
= wait_for_bit(__func__
, ®s
->grstctl
, DWC2_GRSTCTL_AHBIDLE
,
140 printf("%s: Timeout!\n", __func__
);
142 /* Core Soft Reset */
143 writel(DWC2_GRSTCTL_CSFTRST
, ®s
->grstctl
);
144 ret
= wait_for_bit(__func__
, ®s
->grstctl
, DWC2_GRSTCTL_CSFTRST
,
147 printf("%s: Timeout!\n", __func__
);
150 * Wait for core to come out of reset.
151 * NOTE: This long sleep is _very_ important, otherwise the core will
152 * not stay in host mode after a connector ID change!
158 * This function initializes the DWC_otg controller registers for
161 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
162 * request queues. Host channels are reset to ensure that they are ready for
163 * performing transfers.
165 * @param regs Programming view of DWC_otg controller
168 static void dwc_otg_core_host_init(struct dwc2_core_regs
*regs
)
170 uint32_t nptxfifosize
= 0;
171 uint32_t ptxfifosize
= 0;
173 int i
, ret
, num_channels
;
175 /* Restart the Phy Clock */
176 writel(0, ®s
->pcgcctl
);
178 /* Initialize Host Configuration Register */
179 init_fslspclksel(regs
);
180 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
181 setbits_le32(®s
->host_regs
.hcfg
, DWC2_HCFG_FSLSSUPP
);
184 /* Configure data FIFO sizes */
185 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
186 if (readl(®s
->ghwcfg2
) & DWC2_HWCFG2_DYNAMIC_FIFO
) {
188 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE
, ®s
->grxfsiz
);
190 /* Non-periodic Tx FIFO */
191 nptxfifosize
|= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
<<
192 DWC2_FIFOSIZE_DEPTH_OFFSET
;
193 nptxfifosize
|= CONFIG_DWC2_HOST_RX_FIFO_SIZE
<<
194 DWC2_FIFOSIZE_STARTADDR_OFFSET
;
195 writel(nptxfifosize
, ®s
->gnptxfsiz
);
197 /* Periodic Tx FIFO */
198 ptxfifosize
|= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
<<
199 DWC2_FIFOSIZE_DEPTH_OFFSET
;
200 ptxfifosize
|= (CONFIG_DWC2_HOST_RX_FIFO_SIZE
+
201 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
) <<
202 DWC2_FIFOSIZE_STARTADDR_OFFSET
;
203 writel(ptxfifosize
, ®s
->hptxfsiz
);
207 /* Clear Host Set HNP Enable in the OTG Control Register */
208 clrbits_le32(®s
->gotgctl
, DWC2_GOTGCTL_HSTSETHNPEN
);
210 /* Make sure the FIFOs are flushed. */
211 dwc_otg_flush_tx_fifo(regs
, 0x10); /* All Tx FIFOs */
212 dwc_otg_flush_rx_fifo(regs
);
214 /* Flush out any leftover queued requests. */
215 num_channels
= readl(®s
->ghwcfg2
);
216 num_channels
&= DWC2_HWCFG2_NUM_HOST_CHAN_MASK
;
217 num_channels
>>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET
;
220 for (i
= 0; i
< num_channels
; i
++)
221 clrsetbits_le32(®s
->hc_regs
[i
].hcchar
,
222 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_EPDIR
,
225 /* Halt all channels to put them into a known state. */
226 for (i
= 0; i
< num_channels
; i
++) {
227 clrsetbits_le32(®s
->hc_regs
[i
].hcchar
,
229 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_CHDIS
);
230 ret
= wait_for_bit(__func__
, ®s
->hc_regs
[i
].hcchar
,
231 DWC2_HCCHAR_CHEN
, false, 1000, false);
233 printf("%s: Timeout!\n", __func__
);
236 /* Turn on the vbus power. */
237 if (readl(®s
->gintsts
) & DWC2_GINTSTS_CURMODE_HOST
) {
238 hprt0
= readl(®s
->hprt0
);
239 hprt0
&= ~(DWC2_HPRT0_PRTENA
| DWC2_HPRT0_PRTCONNDET
);
240 hprt0
&= ~(DWC2_HPRT0_PRTENCHNG
| DWC2_HPRT0_PRTOVRCURRCHNG
);
241 if (!(hprt0
& DWC2_HPRT0_PRTPWR
)) {
242 hprt0
|= DWC2_HPRT0_PRTPWR
;
243 writel(hprt0
, ®s
->hprt0
);
249 * This function initializes the DWC_otg controller registers and
250 * prepares the core for device mode or host mode operation.
252 * @param regs Programming view of the DWC_otg controller
254 static void dwc_otg_core_init(struct dwc2_core_regs
*regs
)
258 uint8_t brst_sz
= CONFIG_DWC2_DMA_BURST_SIZE
;
260 /* Common Initialization */
261 usbcfg
= readl(®s
->gusbcfg
);
263 /* Program the ULPI External VBUS bit if needed */
264 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
265 usbcfg
|= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV
;
267 usbcfg
&= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV
;
270 /* Set external TS Dline pulsing */
271 #ifdef CONFIG_DWC2_TS_DLINE
272 usbcfg
|= DWC2_GUSBCFG_TERM_SEL_DL_PULSE
;
274 usbcfg
&= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE
;
276 writel(usbcfg
, ®s
->gusbcfg
);
278 /* Reset the Controller */
279 dwc_otg_core_reset(regs
);
282 * This programming sequence needs to happen in FS mode before
283 * any other programming occurs
285 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
286 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
287 /* If FS mode with FS PHY */
288 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_PHYSEL
);
290 /* Reset after a PHY select */
291 dwc_otg_core_reset(regs
);
294 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
295 * Also do this on HNP Dev/Host mode switches (done in dev_init
298 if (readl(®s
->gintsts
) & DWC2_GINTSTS_CURMODE_HOST
)
299 init_fslspclksel(regs
);
301 #ifdef CONFIG_DWC2_I2C_ENABLE
302 /* Program GUSBCFG.OtgUtmifsSel to I2C */
303 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_OTGUTMIFSSEL
);
305 /* Program GI2CCTL.I2CEn */
306 clrsetbits_le32(®s
->gi2cctl
, DWC2_GI2CCTL_I2CEN
|
307 DWC2_GI2CCTL_I2CDEVADDR_MASK
,
308 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET
);
309 setbits_le32(®s
->gi2cctl
, DWC2_GI2CCTL_I2CEN
);
313 /* High speed PHY. */
316 * HS PHY parameters. These parameters are preserved during
317 * soft reset so only program the first time. Do a soft reset
318 * immediately after setting phyif.
320 usbcfg
&= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL
| DWC2_GUSBCFG_PHYIF
);
321 usbcfg
|= CONFIG_DWC2_PHY_TYPE
<< DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET
;
323 if (usbcfg
& DWC2_GUSBCFG_ULPI_UTMI_SEL
) { /* ULPI interface */
324 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
325 usbcfg
|= DWC2_GUSBCFG_DDRSEL
;
327 usbcfg
&= ~DWC2_GUSBCFG_DDRSEL
;
329 } else { /* UTMI+ interface */
330 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
331 usbcfg
|= DWC2_GUSBCFG_PHYIF
;
335 writel(usbcfg
, ®s
->gusbcfg
);
337 /* Reset after setting the PHY parameters */
338 dwc_otg_core_reset(regs
);
341 usbcfg
= readl(®s
->gusbcfg
);
342 usbcfg
&= ~(DWC2_GUSBCFG_ULPI_FSLS
| DWC2_GUSBCFG_ULPI_CLK_SUS_M
);
343 #ifdef CONFIG_DWC2_ULPI_FS_LS
344 uint32_t hwcfg2
= readl(®s
->ghwcfg2
);
345 uint32_t hval
= (ghwcfg2
& DWC2_HWCFG2_HS_PHY_TYPE_MASK
) >>
346 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET
;
347 uint32_t fval
= (ghwcfg2
& DWC2_HWCFG2_FS_PHY_TYPE_MASK
) >>
348 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET
;
349 if (hval
== 2 && fval
== 1) {
350 usbcfg
|= DWC2_GUSBCFG_ULPI_FSLS
;
351 usbcfg
|= DWC2_GUSBCFG_ULPI_CLK_SUS_M
;
354 writel(usbcfg
, ®s
->gusbcfg
);
356 /* Program the GAHBCFG Register. */
357 switch (readl(®s
->ghwcfg2
) & DWC2_HWCFG2_ARCHITECTURE_MASK
) {
358 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY
:
360 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA
:
361 while (brst_sz
> 1) {
362 ahbcfg
|= ahbcfg
+ (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET
);
363 ahbcfg
&= DWC2_GAHBCFG_HBURSTLEN_MASK
;
367 #ifdef CONFIG_DWC2_DMA_ENABLE
368 ahbcfg
|= DWC2_GAHBCFG_DMAENABLE
;
372 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA
:
373 ahbcfg
|= DWC2_GAHBCFG_HBURSTLEN_INCR4
;
374 #ifdef CONFIG_DWC2_DMA_ENABLE
375 ahbcfg
|= DWC2_GAHBCFG_DMAENABLE
;
380 writel(ahbcfg
, ®s
->gahbcfg
);
382 /* Program the GUSBCFG register for HNP/SRP. */
383 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_HNPCAP
| DWC2_GUSBCFG_SRPCAP
);
385 #ifdef CONFIG_DWC2_IC_USB_CAP
386 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_IC_USB_CAP
);
391 * Prepares a host channel for transferring packets to/from a specific
392 * endpoint. The HCCHARn register is set up with the characteristics specified
393 * in _hc. Host channel interrupts that may need to be serviced while this
394 * transfer is in progress are enabled.
396 * @param regs Programming view of DWC_otg controller
397 * @param hc Information needed to initialize the host channel
399 static void dwc_otg_hc_init(struct dwc2_core_regs
*regs
, uint8_t hc_num
,
400 struct usb_device
*dev
, uint8_t dev_addr
, uint8_t ep_num
,
401 uint8_t ep_is_in
, uint8_t ep_type
, uint16_t max_packet
)
403 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[hc_num
];
404 uint32_t hcchar
= (dev_addr
<< DWC2_HCCHAR_DEVADDR_OFFSET
) |
405 (ep_num
<< DWC2_HCCHAR_EPNUM_OFFSET
) |
406 (ep_is_in
<< DWC2_HCCHAR_EPDIR_OFFSET
) |
407 (ep_type
<< DWC2_HCCHAR_EPTYPE_OFFSET
) |
408 (max_packet
<< DWC2_HCCHAR_MPS_OFFSET
);
410 if (dev
->speed
== USB_SPEED_LOW
)
411 hcchar
|= DWC2_HCCHAR_LSPDDEV
;
413 /* Clear old interrupt conditions for this host channel. */
414 writel(0x3fff, &hc_regs
->hcint
);
417 * Program the HCCHARn register with the endpoint characteristics
418 * for the current transfer.
420 writel(hcchar
, &hc_regs
->hcchar
);
422 /* Program the HCSPLIT register for SPLITs */
423 writel(0, &hc_regs
->hcsplt
);
427 * DWC2 to USB API interface
429 /* Direction: In ; Request: Status */
430 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs
*regs
,
431 struct usb_device
*dev
, void *buffer
,
432 int txlen
, struct devrequest
*cmd
)
435 uint32_t port_status
= 0;
436 uint32_t port_change
= 0;
440 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
442 *(uint16_t *)buffer
= cpu_to_le16(1);
445 case USB_RECIP_INTERFACE
:
446 case USB_RECIP_ENDPOINT
:
447 *(uint16_t *)buffer
= cpu_to_le16(0);
451 *(uint32_t *)buffer
= cpu_to_le32(0);
454 case USB_RECIP_OTHER
| USB_TYPE_CLASS
:
455 hprt0
= readl(®s
->hprt0
);
456 if (hprt0
& DWC2_HPRT0_PRTCONNSTS
)
457 port_status
|= USB_PORT_STAT_CONNECTION
;
458 if (hprt0
& DWC2_HPRT0_PRTENA
)
459 port_status
|= USB_PORT_STAT_ENABLE
;
460 if (hprt0
& DWC2_HPRT0_PRTSUSP
)
461 port_status
|= USB_PORT_STAT_SUSPEND
;
462 if (hprt0
& DWC2_HPRT0_PRTOVRCURRACT
)
463 port_status
|= USB_PORT_STAT_OVERCURRENT
;
464 if (hprt0
& DWC2_HPRT0_PRTRST
)
465 port_status
|= USB_PORT_STAT_RESET
;
466 if (hprt0
& DWC2_HPRT0_PRTPWR
)
467 port_status
|= USB_PORT_STAT_POWER
;
469 if ((hprt0
& DWC2_HPRT0_PRTSPD_MASK
) == DWC2_HPRT0_PRTSPD_LOW
)
470 port_status
|= USB_PORT_STAT_LOW_SPEED
;
471 else if ((hprt0
& DWC2_HPRT0_PRTSPD_MASK
) ==
472 DWC2_HPRT0_PRTSPD_HIGH
)
473 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
475 if (hprt0
& DWC2_HPRT0_PRTENCHNG
)
476 port_change
|= USB_PORT_STAT_C_ENABLE
;
477 if (hprt0
& DWC2_HPRT0_PRTCONNDET
)
478 port_change
|= USB_PORT_STAT_C_CONNECTION
;
479 if (hprt0
& DWC2_HPRT0_PRTOVRCURRCHNG
)
480 port_change
|= USB_PORT_STAT_C_OVERCURRENT
;
482 *(uint32_t *)buffer
= cpu_to_le32(port_status
|
483 (port_change
<< 16));
487 puts("unsupported root hub command\n");
488 stat
= USB_ST_STALLED
;
491 dev
->act_len
= min(len
, txlen
);
497 /* Direction: In ; Request: Descriptor */
498 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device
*dev
,
499 void *buffer
, int txlen
,
500 struct devrequest
*cmd
)
502 unsigned char data
[32];
506 uint16_t wValue
= cpu_to_le16(cmd
->value
);
507 uint16_t wLength
= cpu_to_le16(cmd
->length
);
509 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
511 switch (wValue
& 0xff00) {
512 case 0x0100: /* device descriptor */
513 len
= min3(txlen
, (int)sizeof(root_hub_dev_des
), (int)wLength
);
514 memcpy(buffer
, root_hub_dev_des
, len
);
516 case 0x0200: /* configuration descriptor */
517 len
= min3(txlen
, (int)sizeof(root_hub_config_des
), (int)wLength
);
518 memcpy(buffer
, root_hub_config_des
, len
);
520 case 0x0300: /* string descriptors */
521 switch (wValue
& 0xff) {
523 len
= min3(txlen
, (int)sizeof(root_hub_str_index0
),
525 memcpy(buffer
, root_hub_str_index0
, len
);
528 len
= min3(txlen
, (int)sizeof(root_hub_str_index1
),
530 memcpy(buffer
, root_hub_str_index1
, len
);
535 stat
= USB_ST_STALLED
;
540 /* Root port config, set 1 port and nothing else. */
543 data
[0] = 9; /* min length; */
545 data
[2] = dsc
& RH_A_NDP
;
551 else if (dsc
& RH_A_OCPM
)
554 /* corresponds to data[4-7] */
555 data
[5] = (dsc
& RH_A_POTPGT
) >> 24;
556 data
[7] = dsc
& RH_B_DR
;
561 data
[8] = (dsc
& RH_B_DR
) >> 8;
566 len
= min3(txlen
, (int)data
[0], (int)wLength
);
567 memcpy(buffer
, data
, len
);
570 puts("unsupported root hub command\n");
571 stat
= USB_ST_STALLED
;
574 dev
->act_len
= min(len
, txlen
);
580 /* Direction: In ; Request: Configuration */
581 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device
*dev
,
582 void *buffer
, int txlen
,
583 struct devrequest
*cmd
)
588 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
590 *(uint8_t *)buffer
= 0x01;
594 puts("unsupported root hub command\n");
595 stat
= USB_ST_STALLED
;
598 dev
->act_len
= min(len
, txlen
);
605 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv
*priv
,
606 struct usb_device
*dev
, void *buffer
,
607 int txlen
, struct devrequest
*cmd
)
609 switch (cmd
->request
) {
610 case USB_REQ_GET_STATUS
:
611 return dwc_otg_submit_rh_msg_in_status(priv
->regs
, dev
, buffer
,
613 case USB_REQ_GET_DESCRIPTOR
:
614 return dwc_otg_submit_rh_msg_in_descriptor(dev
, buffer
,
616 case USB_REQ_GET_CONFIGURATION
:
617 return dwc_otg_submit_rh_msg_in_configuration(dev
, buffer
,
620 puts("unsupported root hub command\n");
621 return USB_ST_STALLED
;
626 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv
*priv
,
627 struct usb_device
*dev
,
628 void *buffer
, int txlen
,
629 struct devrequest
*cmd
)
631 struct dwc2_core_regs
*regs
= priv
->regs
;
634 uint16_t bmrtype_breq
= cmd
->requesttype
| (cmd
->request
<< 8);
635 uint16_t wValue
= cpu_to_le16(cmd
->value
);
637 switch (bmrtype_breq
& ~USB_DIR_IN
) {
638 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_RECIP_ENDPOINT
:
639 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_TYPE_CLASS
:
642 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_RECIP_OTHER
| USB_TYPE_CLASS
:
644 case USB_PORT_FEAT_C_CONNECTION
:
645 setbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTCONNDET
);
650 case (USB_REQ_SET_FEATURE
<< 8) | USB_RECIP_OTHER
| USB_TYPE_CLASS
:
652 case USB_PORT_FEAT_SUSPEND
:
655 case USB_PORT_FEAT_RESET
:
656 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
657 DWC2_HPRT0_PRTCONNDET
|
658 DWC2_HPRT0_PRTENCHNG
|
659 DWC2_HPRT0_PRTOVRCURRCHNG
,
662 clrbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTRST
);
665 case USB_PORT_FEAT_POWER
:
666 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
667 DWC2_HPRT0_PRTCONNDET
|
668 DWC2_HPRT0_PRTENCHNG
|
669 DWC2_HPRT0_PRTOVRCURRCHNG
,
673 case USB_PORT_FEAT_ENABLE
:
677 case (USB_REQ_SET_ADDRESS
<< 8):
678 priv
->root_hub_devnum
= wValue
;
680 case (USB_REQ_SET_CONFIGURATION
<< 8):
683 puts("unsupported root hub command\n");
684 stat
= USB_ST_STALLED
;
687 len
= min(len
, txlen
);
695 static int dwc_otg_submit_rh_msg(struct dwc2_priv
*priv
, struct usb_device
*dev
,
696 unsigned long pipe
, void *buffer
, int txlen
,
697 struct devrequest
*cmd
)
701 if (usb_pipeint(pipe
)) {
702 puts("Root-Hub submit IRQ: NOT implemented\n");
706 if (cmd
->requesttype
& USB_DIR_IN
)
707 stat
= dwc_otg_submit_rh_msg_in(priv
, dev
, buffer
, txlen
, cmd
);
709 stat
= dwc_otg_submit_rh_msg_out(priv
, dev
, buffer
, txlen
, cmd
);
716 int wait_for_chhltd(struct dwc2_core_regs
*regs
, uint32_t *sub
, int *toggle
,
719 uint32_t hcint_comp_hlt_ack
= DWC2_HCINT_XFERCOMP
| DWC2_HCINT_CHHLTD
;
720 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[DWC2_HC_CHANNEL
];
722 uint32_t hcint
, hctsiz
;
724 ret
= wait_for_bit(__func__
, &hc_regs
->hcint
, DWC2_HCINT_CHHLTD
, true,
729 hcint
= readl(&hc_regs
->hcint
);
730 if (hcint
& (DWC2_HCINT_NAK
| DWC2_HCINT_FRMOVRUN
))
733 hcint
&= ~DWC2_HCINT_ACK
;
735 hcint_comp_hlt_ack
|= DWC2_HCINT_ACK
;
736 if (hcint
!= hcint_comp_hlt_ack
) {
737 debug("%s: Error (HCINT=%08x)\n", __func__
, hcint
);
741 hctsiz
= readl(&hc_regs
->hctsiz
);
742 *sub
= (hctsiz
& DWC2_HCTSIZ_XFERSIZE_MASK
) >>
743 DWC2_HCTSIZ_XFERSIZE_OFFSET
;
744 *toggle
= (hctsiz
& DWC2_HCTSIZ_PID_MASK
) >> DWC2_HCTSIZ_PID_OFFSET
;
746 debug("%s: sub=%u toggle=%d\n", __func__
, *sub
, *toggle
);
751 static int dwc2_eptype
[] = {
752 DWC2_HCCHAR_EPTYPE_ISOC
,
753 DWC2_HCCHAR_EPTYPE_INTR
,
754 DWC2_HCCHAR_EPTYPE_CONTROL
,
755 DWC2_HCCHAR_EPTYPE_BULK
,
758 int chunk_msg(struct dwc2_priv
*priv
, struct usb_device
*dev
,
759 unsigned long pipe
, int *pid
, int in
, void *buffer
, int len
,
762 struct dwc2_core_regs
*regs
= priv
->regs
;
763 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[DWC2_HC_CHANNEL
];
764 int devnum
= usb_pipedevice(pipe
);
765 int ep
= usb_pipeendpoint(pipe
);
766 int max
= usb_maxpacket(dev
, pipe
);
767 int eptype
= dwc2_eptype
[usb_pipetype(pipe
)];
772 uint32_t num_packets
;
773 int stop_transfer
= 0;
775 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__
, pipe
, *pid
,
779 /* Initialize channel */
780 dwc_otg_hc_init(regs
, DWC2_HC_CHANNEL
, dev
, devnum
, ep
, in
,
783 xfer_len
= len
- done
;
784 if (xfer_len
> CONFIG_DWC2_MAX_TRANSFER_SIZE
)
785 xfer_len
= CONFIG_DWC2_MAX_TRANSFER_SIZE
- max
+ 1;
786 if (xfer_len
> DWC2_DATA_BUF_SIZE
)
787 xfer_len
= DWC2_DATA_BUF_SIZE
- max
+ 1;
789 /* Make sure that xfer_len is a multiple of max packet size. */
791 num_packets
= (xfer_len
+ max
- 1) / max
;
792 if (num_packets
> CONFIG_DWC2_MAX_PACKET_COUNT
) {
793 num_packets
= CONFIG_DWC2_MAX_PACKET_COUNT
;
794 xfer_len
= num_packets
* max
;
801 xfer_len
= num_packets
* max
;
803 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__
,
804 *pid
, xfer_len
, num_packets
);
806 writel((xfer_len
<< DWC2_HCTSIZ_XFERSIZE_OFFSET
) |
807 (num_packets
<< DWC2_HCTSIZ_PKTCNT_OFFSET
) |
808 (*pid
<< DWC2_HCTSIZ_PID_OFFSET
),
811 if (!in
&& xfer_len
) {
812 memcpy(priv
->aligned_buffer
, (char *)buffer
+ done
,
815 flush_dcache_range((unsigned long)priv
->aligned_buffer
,
816 (unsigned long)((void *)priv
->aligned_buffer
+
817 roundup(xfer_len
, ARCH_DMA_MINALIGN
)));
820 writel(phys_to_bus((unsigned long)priv
->aligned_buffer
),
823 /* Set host channel enable after all other setup is complete. */
824 clrsetbits_le32(&hc_regs
->hcchar
, DWC2_HCCHAR_MULTICNT_MASK
|
825 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_CHDIS
,
826 (1 << DWC2_HCCHAR_MULTICNT_OFFSET
) |
829 ret
= wait_for_chhltd(regs
, &sub
, pid
, ignore_ack
);
836 invalidate_dcache_range((unsigned long)priv
->aligned_buffer
,
837 (unsigned long)((void *)priv
->aligned_buffer
+
838 roundup(xfer_len
, ARCH_DMA_MINALIGN
)));
840 memcpy(buffer
+ done
, priv
->aligned_buffer
, xfer_len
);
847 } while ((done
< len
) && !stop_transfer
);
849 writel(0, &hc_regs
->hcintmsk
);
850 writel(0xFFFFFFFF, &hc_regs
->hcint
);
858 /* U-Boot USB transmission interface */
859 int _submit_bulk_msg(struct dwc2_priv
*priv
, struct usb_device
*dev
,
860 unsigned long pipe
, void *buffer
, int len
)
862 int devnum
= usb_pipedevice(pipe
);
863 int ep
= usb_pipeendpoint(pipe
);
865 if (devnum
== priv
->root_hub_devnum
) {
870 return chunk_msg(priv
, dev
, pipe
, &priv
->bulk_data_toggle
[devnum
][ep
],
871 usb_pipein(pipe
), buffer
, len
, true);
874 static int _submit_control_msg(struct dwc2_priv
*priv
, struct usb_device
*dev
,
875 unsigned long pipe
, void *buffer
, int len
,
876 struct devrequest
*setup
)
878 int devnum
= usb_pipedevice(pipe
);
879 int pid
, ret
, act_len
;
880 /* For CONTROL endpoint pid should start with DATA1 */
881 int status_direction
;
883 if (devnum
== priv
->root_hub_devnum
) {
885 dev
->speed
= USB_SPEED_HIGH
;
886 return dwc_otg_submit_rh_msg(priv
, dev
, pipe
, buffer
, len
,
890 pid
= DWC2_HC_PID_SETUP
;
891 ret
= chunk_msg(priv
, dev
, pipe
, &pid
, 0, setup
, 8, true);
896 pid
= DWC2_HC_PID_DATA1
;
897 ret
= chunk_msg(priv
, dev
, pipe
, &pid
, usb_pipein(pipe
), buffer
,
901 act_len
= dev
->act_len
;
902 } /* End of DATA stage */
907 if ((len
== 0) || usb_pipeout(pipe
))
908 status_direction
= 1;
910 status_direction
= 0;
912 pid
= DWC2_HC_PID_DATA1
;
913 ret
= chunk_msg(priv
, dev
, pipe
, &pid
, status_direction
,
914 priv
->status_buffer
, 0, false);
918 dev
->act_len
= act_len
;
923 int _submit_int_msg(struct dwc2_priv
*priv
, struct usb_device
*dev
,
924 unsigned long pipe
, void *buffer
, int len
, int interval
)
926 unsigned long timeout
;
929 /* FIXME: what is interval? */
931 timeout
= get_timer(0) + USB_TIMEOUT_MS(pipe
);
933 if (get_timer(0) > timeout
) {
934 printf("Timeout poll on interrupt endpoint\n");
937 ret
= _submit_bulk_msg(priv
, dev
, pipe
, buffer
, len
);
943 static int dwc2_init_common(struct dwc2_priv
*priv
)
945 struct dwc2_core_regs
*regs
= priv
->regs
;
949 snpsid
= readl(®s
->gsnpsid
);
950 printf("Core Release: %x.%03x\n", snpsid
>> 12 & 0xf, snpsid
& 0xfff);
952 if ((snpsid
& DWC2_SNPSID_DEVID_MASK
) != DWC2_SNPSID_DEVID_VER_2xx
&&
953 (snpsid
& DWC2_SNPSID_DEVID_MASK
) != DWC2_SNPSID_DEVID_VER_3xx
) {
954 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid
);
958 dwc_otg_core_init(regs
);
959 dwc_otg_core_host_init(regs
);
961 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
962 DWC2_HPRT0_PRTCONNDET
| DWC2_HPRT0_PRTENCHNG
|
963 DWC2_HPRT0_PRTOVRCURRCHNG
,
966 clrbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
| DWC2_HPRT0_PRTCONNDET
|
967 DWC2_HPRT0_PRTENCHNG
| DWC2_HPRT0_PRTOVRCURRCHNG
|
970 for (i
= 0; i
< MAX_DEVICE
; i
++) {
971 for (j
= 0; j
< MAX_ENDPOINT
; j
++)
972 priv
->bulk_data_toggle
[i
][j
] = DWC2_HC_PID_DATA0
;
978 static void dwc2_uninit_common(struct dwc2_core_regs
*regs
)
980 /* Put everything in reset. */
981 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
982 DWC2_HPRT0_PRTCONNDET
| DWC2_HPRT0_PRTENCHNG
|
983 DWC2_HPRT0_PRTOVRCURRCHNG
,
987 #ifndef CONFIG_DM_USB
988 int submit_control_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
989 int len
, struct devrequest
*setup
)
991 return _submit_control_msg(&local
, dev
, pipe
, buffer
, len
, setup
);
994 int submit_bulk_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
997 return _submit_bulk_msg(&local
, dev
, pipe
, buffer
, len
);
1000 int submit_int_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1001 int len
, int interval
)
1003 return _submit_int_msg(&local
, dev
, pipe
, buffer
, len
, interval
);
1006 /* U-Boot USB control interface */
1007 int usb_lowlevel_init(int index
, enum usb_init_type init
, void **controller
)
1009 struct dwc2_priv
*priv
= &local
;
1011 memset(priv
, '\0', sizeof(*priv
));
1012 priv
->root_hub_devnum
= 0;
1013 priv
->regs
= (struct dwc2_core_regs
*)CONFIG_USB_DWC2_REG_ADDR
;
1014 priv
->aligned_buffer
= aligned_buffer_addr
;
1015 priv
->status_buffer
= status_buffer_addr
;
1017 /* board-dependant init */
1018 if (board_usb_init(index
, USB_INIT_HOST
))
1021 return dwc2_init_common(priv
);
1024 int usb_lowlevel_stop(int index
)
1026 dwc2_uninit_common(local
.regs
);
1032 #ifdef CONFIG_DM_USB
1033 static int dwc2_submit_control_msg(struct udevice
*dev
, struct usb_device
*udev
,
1034 unsigned long pipe
, void *buffer
, int length
,
1035 struct devrequest
*setup
)
1037 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1039 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__
,
1040 dev
->name
, udev
, udev
->dev
->name
, udev
->portnr
);
1042 return _submit_control_msg(priv
, udev
, pipe
, buffer
, length
, setup
);
1045 static int dwc2_submit_bulk_msg(struct udevice
*dev
, struct usb_device
*udev
,
1046 unsigned long pipe
, void *buffer
, int length
)
1048 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1050 debug("%s: dev='%s', udev=%p\n", __func__
, dev
->name
, udev
);
1052 return _submit_bulk_msg(priv
, udev
, pipe
, buffer
, length
);
1055 static int dwc2_submit_int_msg(struct udevice
*dev
, struct usb_device
*udev
,
1056 unsigned long pipe
, void *buffer
, int length
,
1059 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1061 debug("%s: dev='%s', udev=%p\n", __func__
, dev
->name
, udev
);
1063 return _submit_int_msg(priv
, udev
, pipe
, buffer
, length
, interval
);
1066 static int dwc2_usb_ofdata_to_platdata(struct udevice
*dev
)
1068 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1071 addr
= dev_get_addr(dev
);
1072 if (addr
== FDT_ADDR_T_NONE
)
1074 priv
->regs
= (struct dwc2_core_regs
*)addr
;
1079 static int dwc2_usb_probe(struct udevice
*dev
)
1081 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1083 return dwc2_init_common(priv
);
1086 static int dwc2_usb_remove(struct udevice
*dev
)
1088 struct dwc2_priv
*priv
= dev_get_priv(dev
);
1090 dwc2_uninit_common(priv
->regs
);
1095 struct dm_usb_ops dwc2_usb_ops
= {
1096 .control
= dwc2_submit_control_msg
,
1097 .bulk
= dwc2_submit_bulk_msg
,
1098 .interrupt
= dwc2_submit_int_msg
,
1101 static const struct udevice_id dwc2_usb_ids
[] = {
1102 { .compatible
= "brcm,bcm2835-usb" },
1103 { .compatible
= "snps,dwc2" },
1107 U_BOOT_DRIVER(usb_dwc2
) = {
1110 .of_match
= dwc2_usb_ids
,
1111 .ofdata_to_platdata
= dwc2_usb_ofdata_to_platdata
,
1112 .probe
= dwc2_usb_probe
,
1113 .remove
= dwc2_usb_remove
,
1114 .ops
= &dwc2_usb_ops
,
1115 .priv_auto_alloc_size
= sizeof(struct dwc2_priv
),
1116 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,