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usb: dwc2: disable erroneous overcurrent condition
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18
19 #include "dwc2.h"
20
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
23
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (64 * 1024)
26
27 #define MAX_DEVICE 16
28 #define MAX_ENDPOINT 16
29
30 struct dwc2_priv {
31 #ifdef CONFIG_DM_USB
32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 #else
35 uint8_t *aligned_buffer;
36 uint8_t *status_buffer;
37 #endif
38 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
39 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
40 struct dwc2_core_regs *regs;
41 int root_hub_devnum;
42 };
43
44 #ifndef CONFIG_DM_USB
45 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
46 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
47 ARCH_DMA_MINALIGN);
48 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
49 ARCH_DMA_MINALIGN);
50
51 static struct dwc2_priv local;
52 #endif
53
54 /*
55 * DWC2 IP interface
56 */
57
58 /*
59 * Initializes the FSLSPClkSel field of the HCFG register
60 * depending on the PHY type.
61 */
62 static void init_fslspclksel(struct dwc2_core_regs *regs)
63 {
64 uint32_t phyclk;
65
66 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
67 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
68 #else
69 /* High speed PHY running at full speed or high speed */
70 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
71 #endif
72
73 #ifdef CONFIG_DWC2_ULPI_FS_LS
74 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
75 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
76 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
77 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
78 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
79
80 if (hval == 2 && fval == 1)
81 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
82 #endif
83
84 clrsetbits_le32(&regs->host_regs.hcfg,
85 DWC2_HCFG_FSLSPCLKSEL_MASK,
86 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
87 }
88
89 /*
90 * Flush a Tx FIFO.
91 *
92 * @param regs Programming view of DWC_otg controller.
93 * @param num Tx FIFO to flush.
94 */
95 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
96 {
97 int ret;
98
99 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
100 &regs->grstctl);
101 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
102 false, 1000, false);
103 if (ret)
104 printf("%s: Timeout!\n", __func__);
105
106 /* Wait for 3 PHY Clocks */
107 udelay(1);
108 }
109
110 /*
111 * Flush Rx FIFO.
112 *
113 * @param regs Programming view of DWC_otg controller.
114 */
115 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
116 {
117 int ret;
118
119 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
120 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
121 false, 1000, false);
122 if (ret)
123 printf("%s: Timeout!\n", __func__);
124
125 /* Wait for 3 PHY Clocks */
126 udelay(1);
127 }
128
129 /*
130 * Do core a soft reset of the core. Be careful with this because it
131 * resets all the internal state machines of the core.
132 */
133 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
134 {
135 int ret;
136
137 /* Wait for AHB master IDLE state. */
138 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
139 true, 1000, false);
140 if (ret)
141 printf("%s: Timeout!\n", __func__);
142
143 /* Core Soft Reset */
144 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
145 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
146 false, 1000, false);
147 if (ret)
148 printf("%s: Timeout!\n", __func__);
149
150 /*
151 * Wait for core to come out of reset.
152 * NOTE: This long sleep is _very_ important, otherwise the core will
153 * not stay in host mode after a connector ID change!
154 */
155 mdelay(100);
156 }
157
158 /*
159 * This function initializes the DWC_otg controller registers for
160 * host mode.
161 *
162 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
163 * request queues. Host channels are reset to ensure that they are ready for
164 * performing transfers.
165 *
166 * @param regs Programming view of DWC_otg controller
167 *
168 */
169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
170 {
171 uint32_t nptxfifosize = 0;
172 uint32_t ptxfifosize = 0;
173 uint32_t hprt0 = 0;
174 int i, ret, num_channels;
175
176 /* Restart the Phy Clock */
177 writel(0, &regs->pcgcctl);
178
179 /* Initialize Host Configuration Register */
180 init_fslspclksel(regs);
181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
182 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
183 #endif
184
185 /* Configure data FIFO sizes */
186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
187 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
188 /* Rx FIFO */
189 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
190
191 /* Non-periodic Tx FIFO */
192 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
193 DWC2_FIFOSIZE_DEPTH_OFFSET;
194 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
195 DWC2_FIFOSIZE_STARTADDR_OFFSET;
196 writel(nptxfifosize, &regs->gnptxfsiz);
197
198 /* Periodic Tx FIFO */
199 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
200 DWC2_FIFOSIZE_DEPTH_OFFSET;
201 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
202 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
203 DWC2_FIFOSIZE_STARTADDR_OFFSET;
204 writel(ptxfifosize, &regs->hptxfsiz);
205 }
206 #endif
207
208 /* Clear Host Set HNP Enable in the OTG Control Register */
209 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
210
211 /* Make sure the FIFOs are flushed. */
212 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
213 dwc_otg_flush_rx_fifo(regs);
214
215 /* Flush out any leftover queued requests. */
216 num_channels = readl(&regs->ghwcfg2);
217 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
218 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
219 num_channels += 1;
220
221 for (i = 0; i < num_channels; i++)
222 clrsetbits_le32(&regs->hc_regs[i].hcchar,
223 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
224 DWC2_HCCHAR_CHDIS);
225
226 /* Halt all channels to put them into a known state. */
227 for (i = 0; i < num_channels; i++) {
228 clrsetbits_le32(&regs->hc_regs[i].hcchar,
229 DWC2_HCCHAR_EPDIR,
230 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
231 ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
232 DWC2_HCCHAR_CHEN, false, 1000, false);
233 if (ret)
234 printf("%s: Timeout!\n", __func__);
235 }
236
237 /* Turn on the vbus power. */
238 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
239 hprt0 = readl(&regs->hprt0);
240 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
241 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
242 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
243 hprt0 |= DWC2_HPRT0_PRTPWR;
244 writel(hprt0, &regs->hprt0);
245 }
246 }
247 }
248
249 /*
250 * This function initializes the DWC_otg controller registers and
251 * prepares the core for device mode or host mode operation.
252 *
253 * @param regs Programming view of the DWC_otg controller
254 */
255 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
256 {
257 uint32_t ahbcfg = 0;
258 uint32_t usbcfg = 0;
259 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
260
261 /* Common Initialization */
262 usbcfg = readl(&regs->gusbcfg);
263
264 /* Program the ULPI External VBUS bit if needed */
265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
266 usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
267 DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
268 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
269 #else
270 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
271 #endif
272
273 /* Set external TS Dline pulsing */
274 #ifdef CONFIG_DWC2_TS_DLINE
275 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
276 #else
277 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
278 #endif
279 writel(usbcfg, &regs->gusbcfg);
280
281 /* Reset the Controller */
282 dwc_otg_core_reset(regs);
283
284 /*
285 * This programming sequence needs to happen in FS mode before
286 * any other programming occurs
287 */
288 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
289 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
290 /* If FS mode with FS PHY */
291 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
292
293 /* Reset after a PHY select */
294 dwc_otg_core_reset(regs);
295
296 /*
297 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
298 * Also do this on HNP Dev/Host mode switches (done in dev_init
299 * and host_init).
300 */
301 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
302 init_fslspclksel(regs);
303
304 #ifdef CONFIG_DWC2_I2C_ENABLE
305 /* Program GUSBCFG.OtgUtmifsSel to I2C */
306 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
307
308 /* Program GI2CCTL.I2CEn */
309 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
310 DWC2_GI2CCTL_I2CDEVADDR_MASK,
311 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
312 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
313 #endif
314
315 #else
316 /* High speed PHY. */
317
318 /*
319 * HS PHY parameters. These parameters are preserved during
320 * soft reset so only program the first time. Do a soft reset
321 * immediately after setting phyif.
322 */
323 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
324 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
325
326 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
327 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
328 usbcfg |= DWC2_GUSBCFG_DDRSEL;
329 #else
330 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
331 #endif
332 } else { /* UTMI+ interface */
333 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
334 usbcfg |= DWC2_GUSBCFG_PHYIF;
335 #endif
336 }
337
338 writel(usbcfg, &regs->gusbcfg);
339
340 /* Reset after setting the PHY parameters */
341 dwc_otg_core_reset(regs);
342 #endif
343
344 usbcfg = readl(&regs->gusbcfg);
345 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
346 #ifdef CONFIG_DWC2_ULPI_FS_LS
347 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
348 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
349 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
350 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
351 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
352 if (hval == 2 && fval == 1) {
353 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
354 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
355 }
356 #endif
357 writel(usbcfg, &regs->gusbcfg);
358
359 /* Program the GAHBCFG Register. */
360 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
361 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
362 break;
363 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
364 while (brst_sz > 1) {
365 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
366 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
367 brst_sz >>= 1;
368 }
369
370 #ifdef CONFIG_DWC2_DMA_ENABLE
371 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
372 #endif
373 break;
374
375 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
376 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
377 #ifdef CONFIG_DWC2_DMA_ENABLE
378 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
379 #endif
380 break;
381 }
382
383 writel(ahbcfg, &regs->gahbcfg);
384
385 /* Program the GUSBCFG register for HNP/SRP. */
386 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
387
388 #ifdef CONFIG_DWC2_IC_USB_CAP
389 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
390 #endif
391 }
392
393 /*
394 * Prepares a host channel for transferring packets to/from a specific
395 * endpoint. The HCCHARn register is set up with the characteristics specified
396 * in _hc. Host channel interrupts that may need to be serviced while this
397 * transfer is in progress are enabled.
398 *
399 * @param regs Programming view of DWC_otg controller
400 * @param hc Information needed to initialize the host channel
401 */
402 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
403 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
404 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
405 {
406 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
407 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
408 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
409 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
410 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
411 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
412
413 if (dev->speed == USB_SPEED_LOW)
414 hcchar |= DWC2_HCCHAR_LSPDDEV;
415
416 /*
417 * Program the HCCHARn register with the endpoint characteristics
418 * for the current transfer.
419 */
420 writel(hcchar, &hc_regs->hcchar);
421
422 /* Program the HCSPLIT register, default to no SPLIT */
423 writel(0, &hc_regs->hcsplt);
424 }
425
426 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
427 uint8_t hub_devnum, uint8_t hub_port)
428 {
429 uint32_t hcsplt = 0;
430
431 hcsplt = DWC2_HCSPLT_SPLTENA;
432 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
433 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
434
435 /* Program the HCSPLIT register for SPLITs */
436 writel(hcsplt, &hc_regs->hcsplt);
437 }
438
439 /*
440 * DWC2 to USB API interface
441 */
442 /* Direction: In ; Request: Status */
443 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
444 struct usb_device *dev, void *buffer,
445 int txlen, struct devrequest *cmd)
446 {
447 uint32_t hprt0 = 0;
448 uint32_t port_status = 0;
449 uint32_t port_change = 0;
450 int len = 0;
451 int stat = 0;
452
453 switch (cmd->requesttype & ~USB_DIR_IN) {
454 case 0:
455 *(uint16_t *)buffer = cpu_to_le16(1);
456 len = 2;
457 break;
458 case USB_RECIP_INTERFACE:
459 case USB_RECIP_ENDPOINT:
460 *(uint16_t *)buffer = cpu_to_le16(0);
461 len = 2;
462 break;
463 case USB_TYPE_CLASS:
464 *(uint32_t *)buffer = cpu_to_le32(0);
465 len = 4;
466 break;
467 case USB_RECIP_OTHER | USB_TYPE_CLASS:
468 hprt0 = readl(&regs->hprt0);
469 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
470 port_status |= USB_PORT_STAT_CONNECTION;
471 if (hprt0 & DWC2_HPRT0_PRTENA)
472 port_status |= USB_PORT_STAT_ENABLE;
473 if (hprt0 & DWC2_HPRT0_PRTSUSP)
474 port_status |= USB_PORT_STAT_SUSPEND;
475 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
476 port_status |= USB_PORT_STAT_OVERCURRENT;
477 if (hprt0 & DWC2_HPRT0_PRTRST)
478 port_status |= USB_PORT_STAT_RESET;
479 if (hprt0 & DWC2_HPRT0_PRTPWR)
480 port_status |= USB_PORT_STAT_POWER;
481
482 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
483 port_status |= USB_PORT_STAT_LOW_SPEED;
484 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
485 DWC2_HPRT0_PRTSPD_HIGH)
486 port_status |= USB_PORT_STAT_HIGH_SPEED;
487
488 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
489 port_change |= USB_PORT_STAT_C_ENABLE;
490 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
491 port_change |= USB_PORT_STAT_C_CONNECTION;
492 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
493 port_change |= USB_PORT_STAT_C_OVERCURRENT;
494
495 *(uint32_t *)buffer = cpu_to_le32(port_status |
496 (port_change << 16));
497 len = 4;
498 break;
499 default:
500 puts("unsupported root hub command\n");
501 stat = USB_ST_STALLED;
502 }
503
504 dev->act_len = min(len, txlen);
505 dev->status = stat;
506
507 return stat;
508 }
509
510 /* Direction: In ; Request: Descriptor */
511 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
512 void *buffer, int txlen,
513 struct devrequest *cmd)
514 {
515 unsigned char data[32];
516 uint32_t dsc;
517 int len = 0;
518 int stat = 0;
519 uint16_t wValue = cpu_to_le16(cmd->value);
520 uint16_t wLength = cpu_to_le16(cmd->length);
521
522 switch (cmd->requesttype & ~USB_DIR_IN) {
523 case 0:
524 switch (wValue & 0xff00) {
525 case 0x0100: /* device descriptor */
526 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
527 memcpy(buffer, root_hub_dev_des, len);
528 break;
529 case 0x0200: /* configuration descriptor */
530 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
531 memcpy(buffer, root_hub_config_des, len);
532 break;
533 case 0x0300: /* string descriptors */
534 switch (wValue & 0xff) {
535 case 0x00:
536 len = min3(txlen, (int)sizeof(root_hub_str_index0),
537 (int)wLength);
538 memcpy(buffer, root_hub_str_index0, len);
539 break;
540 case 0x01:
541 len = min3(txlen, (int)sizeof(root_hub_str_index1),
542 (int)wLength);
543 memcpy(buffer, root_hub_str_index1, len);
544 break;
545 }
546 break;
547 default:
548 stat = USB_ST_STALLED;
549 }
550 break;
551
552 case USB_TYPE_CLASS:
553 /* Root port config, set 1 port and nothing else. */
554 dsc = 0x00000001;
555
556 data[0] = 9; /* min length; */
557 data[1] = 0x29;
558 data[2] = dsc & RH_A_NDP;
559 data[3] = 0;
560 if (dsc & RH_A_PSM)
561 data[3] |= 0x1;
562 if (dsc & RH_A_NOCP)
563 data[3] |= 0x10;
564 else if (dsc & RH_A_OCPM)
565 data[3] |= 0x8;
566
567 /* corresponds to data[4-7] */
568 data[5] = (dsc & RH_A_POTPGT) >> 24;
569 data[7] = dsc & RH_B_DR;
570 if (data[2] < 7) {
571 data[8] = 0xff;
572 } else {
573 data[0] += 2;
574 data[8] = (dsc & RH_B_DR) >> 8;
575 data[9] = 0xff;
576 data[10] = data[9];
577 }
578
579 len = min3(txlen, (int)data[0], (int)wLength);
580 memcpy(buffer, data, len);
581 break;
582 default:
583 puts("unsupported root hub command\n");
584 stat = USB_ST_STALLED;
585 }
586
587 dev->act_len = min(len, txlen);
588 dev->status = stat;
589
590 return stat;
591 }
592
593 /* Direction: In ; Request: Configuration */
594 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
595 void *buffer, int txlen,
596 struct devrequest *cmd)
597 {
598 int len = 0;
599 int stat = 0;
600
601 switch (cmd->requesttype & ~USB_DIR_IN) {
602 case 0:
603 *(uint8_t *)buffer = 0x01;
604 len = 1;
605 break;
606 default:
607 puts("unsupported root hub command\n");
608 stat = USB_ST_STALLED;
609 }
610
611 dev->act_len = min(len, txlen);
612 dev->status = stat;
613
614 return stat;
615 }
616
617 /* Direction: In */
618 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
619 struct usb_device *dev, void *buffer,
620 int txlen, struct devrequest *cmd)
621 {
622 switch (cmd->request) {
623 case USB_REQ_GET_STATUS:
624 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
625 txlen, cmd);
626 case USB_REQ_GET_DESCRIPTOR:
627 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
628 txlen, cmd);
629 case USB_REQ_GET_CONFIGURATION:
630 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
631 txlen, cmd);
632 default:
633 puts("unsupported root hub command\n");
634 return USB_ST_STALLED;
635 }
636 }
637
638 /* Direction: Out */
639 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
640 struct usb_device *dev,
641 void *buffer, int txlen,
642 struct devrequest *cmd)
643 {
644 struct dwc2_core_regs *regs = priv->regs;
645 int len = 0;
646 int stat = 0;
647 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
648 uint16_t wValue = cpu_to_le16(cmd->value);
649
650 switch (bmrtype_breq & ~USB_DIR_IN) {
651 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
652 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
653 break;
654
655 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
656 switch (wValue) {
657 case USB_PORT_FEAT_C_CONNECTION:
658 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
659 break;
660 }
661 break;
662
663 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
664 switch (wValue) {
665 case USB_PORT_FEAT_SUSPEND:
666 break;
667
668 case USB_PORT_FEAT_RESET:
669 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
670 DWC2_HPRT0_PRTCONNDET |
671 DWC2_HPRT0_PRTENCHNG |
672 DWC2_HPRT0_PRTOVRCURRCHNG,
673 DWC2_HPRT0_PRTRST);
674 mdelay(50);
675 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
676 break;
677
678 case USB_PORT_FEAT_POWER:
679 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
680 DWC2_HPRT0_PRTCONNDET |
681 DWC2_HPRT0_PRTENCHNG |
682 DWC2_HPRT0_PRTOVRCURRCHNG,
683 DWC2_HPRT0_PRTRST);
684 break;
685
686 case USB_PORT_FEAT_ENABLE:
687 break;
688 }
689 break;
690 case (USB_REQ_SET_ADDRESS << 8):
691 priv->root_hub_devnum = wValue;
692 break;
693 case (USB_REQ_SET_CONFIGURATION << 8):
694 break;
695 default:
696 puts("unsupported root hub command\n");
697 stat = USB_ST_STALLED;
698 }
699
700 len = min(len, txlen);
701
702 dev->act_len = len;
703 dev->status = stat;
704
705 return stat;
706 }
707
708 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
709 unsigned long pipe, void *buffer, int txlen,
710 struct devrequest *cmd)
711 {
712 int stat = 0;
713
714 if (usb_pipeint(pipe)) {
715 puts("Root-Hub submit IRQ: NOT implemented\n");
716 return 0;
717 }
718
719 if (cmd->requesttype & USB_DIR_IN)
720 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
721 else
722 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
723
724 mdelay(1);
725
726 return stat;
727 }
728
729 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
730 {
731 int ret;
732 uint32_t hcint, hctsiz;
733
734 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
735 1000, false);
736 if (ret)
737 return ret;
738
739 hcint = readl(&hc_regs->hcint);
740 hctsiz = readl(&hc_regs->hctsiz);
741 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
742 DWC2_HCTSIZ_XFERSIZE_OFFSET;
743 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
744
745 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
746 *toggle);
747
748 if (hcint & DWC2_HCINT_XFERCOMP)
749 return 0;
750
751 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
752 return -EAGAIN;
753
754 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
755 return -EINVAL;
756 }
757
758 static int dwc2_eptype[] = {
759 DWC2_HCCHAR_EPTYPE_ISOC,
760 DWC2_HCCHAR_EPTYPE_INTR,
761 DWC2_HCCHAR_EPTYPE_CONTROL,
762 DWC2_HCCHAR_EPTYPE_BULK,
763 };
764
765 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
766 u8 *pid, int in, void *buffer, int num_packets,
767 int xfer_len, int *actual_len, int odd_frame)
768 {
769 int ret = 0;
770 uint32_t sub;
771
772 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
773 *pid, xfer_len, num_packets);
774
775 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
776 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
777 (*pid << DWC2_HCTSIZ_PID_OFFSET),
778 &hc_regs->hctsiz);
779
780 if (!in && xfer_len) {
781 memcpy(aligned_buffer, buffer, xfer_len);
782
783 flush_dcache_range((unsigned long)aligned_buffer,
784 (unsigned long)aligned_buffer +
785 roundup(xfer_len, ARCH_DMA_MINALIGN));
786 }
787
788 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
789
790 /* Clear old interrupt conditions for this host channel. */
791 writel(0x3fff, &hc_regs->hcint);
792
793 /* Set host channel enable after all other setup is complete. */
794 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
795 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
796 DWC2_HCCHAR_ODDFRM,
797 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
798 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
799 DWC2_HCCHAR_CHEN);
800
801 ret = wait_for_chhltd(hc_regs, &sub, pid);
802 if (ret < 0)
803 return ret;
804
805 if (in) {
806 xfer_len -= sub;
807
808 invalidate_dcache_range((unsigned long)aligned_buffer,
809 (unsigned long)aligned_buffer +
810 roundup(xfer_len, ARCH_DMA_MINALIGN));
811
812 memcpy(buffer, aligned_buffer, xfer_len);
813 }
814 *actual_len = xfer_len;
815
816 return ret;
817 }
818
819 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
820 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
821 {
822 struct dwc2_core_regs *regs = priv->regs;
823 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
824 struct dwc2_host_regs *host_regs = &regs->host_regs;
825 int devnum = usb_pipedevice(pipe);
826 int ep = usb_pipeendpoint(pipe);
827 int max = usb_maxpacket(dev, pipe);
828 int eptype = dwc2_eptype[usb_pipetype(pipe)];
829 int done = 0;
830 int ret = 0;
831 int do_split = 0;
832 int complete_split = 0;
833 uint32_t xfer_len;
834 uint32_t num_packets;
835 int stop_transfer = 0;
836 uint32_t max_xfer_len;
837 int ssplit_frame_num = 0;
838
839 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
840 in, len);
841
842 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
843 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
844 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
845 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
846 max_xfer_len = DWC2_DATA_BUF_SIZE;
847
848 /* Make sure that max_xfer_len is a multiple of max packet size. */
849 num_packets = max_xfer_len / max;
850 max_xfer_len = num_packets * max;
851
852 /* Initialize channel */
853 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
854 eptype, max);
855
856 /* Check if the target is a FS/LS device behind a HS hub */
857 if (dev->speed != USB_SPEED_HIGH) {
858 uint8_t hub_addr;
859 uint8_t hub_port;
860 uint32_t hprt0 = readl(&regs->hprt0);
861 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
862 DWC2_HPRT0_PRTSPD_HIGH) {
863 usb_find_usb2_hub_address_port(dev, &hub_addr,
864 &hub_port);
865 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
866
867 do_split = 1;
868 num_packets = 1;
869 max_xfer_len = max;
870 }
871 }
872
873 do {
874 int actual_len = 0;
875 uint32_t hcint;
876 int odd_frame = 0;
877 xfer_len = len - done;
878
879 if (xfer_len > max_xfer_len)
880 xfer_len = max_xfer_len;
881 else if (xfer_len > max)
882 num_packets = (xfer_len + max - 1) / max;
883 else
884 num_packets = 1;
885
886 if (complete_split)
887 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
888 else if (do_split)
889 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
890
891 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
892 int uframe_num = readl(&host_regs->hfnum);
893 if (!(uframe_num & 0x1))
894 odd_frame = 1;
895 }
896
897 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
898 in, (char *)buffer + done, num_packets,
899 xfer_len, &actual_len, odd_frame);
900
901 hcint = readl(&hc_regs->hcint);
902 if (complete_split) {
903 stop_transfer = 0;
904 if (hcint & DWC2_HCINT_NYET) {
905 ret = 0;
906 int frame_num = DWC2_HFNUM_MAX_FRNUM &
907 readl(&host_regs->hfnum);
908 if (((frame_num - ssplit_frame_num) &
909 DWC2_HFNUM_MAX_FRNUM) > 4)
910 ret = -EAGAIN;
911 } else
912 complete_split = 0;
913 } else if (do_split) {
914 if (hcint & DWC2_HCINT_ACK) {
915 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
916 readl(&host_regs->hfnum);
917 ret = 0;
918 complete_split = 1;
919 }
920 }
921
922 if (ret)
923 break;
924
925 if (actual_len < xfer_len)
926 stop_transfer = 1;
927
928 done += actual_len;
929
930 /* Transactions are done when when either all data is transferred or
931 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
932 * is executed.
933 */
934 } while (((done < len) && !stop_transfer) || complete_split);
935
936 writel(0, &hc_regs->hcintmsk);
937 writel(0xFFFFFFFF, &hc_regs->hcint);
938
939 dev->status = 0;
940 dev->act_len = done;
941
942 return ret;
943 }
944
945 /* U-Boot USB transmission interface */
946 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
947 unsigned long pipe, void *buffer, int len)
948 {
949 int devnum = usb_pipedevice(pipe);
950 int ep = usb_pipeendpoint(pipe);
951 u8* pid;
952
953 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
954 dev->status = 0;
955 return -EINVAL;
956 }
957
958 if (usb_pipein(pipe))
959 pid = &priv->in_data_toggle[devnum][ep];
960 else
961 pid = &priv->out_data_toggle[devnum][ep];
962
963 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
964 }
965
966 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
967 unsigned long pipe, void *buffer, int len,
968 struct devrequest *setup)
969 {
970 int devnum = usb_pipedevice(pipe);
971 int ret, act_len;
972 u8 pid;
973 /* For CONTROL endpoint pid should start with DATA1 */
974 int status_direction;
975
976 if (devnum == priv->root_hub_devnum) {
977 dev->status = 0;
978 dev->speed = USB_SPEED_HIGH;
979 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
980 setup);
981 }
982
983 /* SETUP stage */
984 pid = DWC2_HC_PID_SETUP;
985 do {
986 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
987 } while (ret == -EAGAIN);
988 if (ret)
989 return ret;
990
991 /* DATA stage */
992 act_len = 0;
993 if (buffer) {
994 pid = DWC2_HC_PID_DATA1;
995 do {
996 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
997 buffer, len);
998 act_len += dev->act_len;
999 buffer += dev->act_len;
1000 len -= dev->act_len;
1001 } while (ret == -EAGAIN);
1002 if (ret)
1003 return ret;
1004 status_direction = usb_pipeout(pipe);
1005 } else {
1006 /* No-data CONTROL always ends with an IN transaction */
1007 status_direction = 1;
1008 }
1009
1010 /* STATUS stage */
1011 pid = DWC2_HC_PID_DATA1;
1012 do {
1013 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1014 priv->status_buffer, 0);
1015 } while (ret == -EAGAIN);
1016 if (ret)
1017 return ret;
1018
1019 dev->act_len = act_len;
1020
1021 return 0;
1022 }
1023
1024 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1025 unsigned long pipe, void *buffer, int len, int interval)
1026 {
1027 unsigned long timeout;
1028 int ret;
1029
1030 /* FIXME: what is interval? */
1031
1032 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1033 for (;;) {
1034 if (get_timer(0) > timeout) {
1035 printf("Timeout poll on interrupt endpoint\n");
1036 return -ETIMEDOUT;
1037 }
1038 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1039 if (ret != -EAGAIN)
1040 return ret;
1041 }
1042 }
1043
1044 static int dwc2_init_common(struct dwc2_priv *priv)
1045 {
1046 struct dwc2_core_regs *regs = priv->regs;
1047 uint32_t snpsid;
1048 int i, j;
1049
1050 snpsid = readl(&regs->gsnpsid);
1051 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1052
1053 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1054 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1055 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1056 return -ENODEV;
1057 }
1058
1059 dwc_otg_core_init(regs);
1060 dwc_otg_core_host_init(regs);
1061
1062 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1063 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1064 DWC2_HPRT0_PRTOVRCURRCHNG,
1065 DWC2_HPRT0_PRTRST);
1066 mdelay(50);
1067 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1068 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1069 DWC2_HPRT0_PRTRST);
1070
1071 for (i = 0; i < MAX_DEVICE; i++) {
1072 for (j = 0; j < MAX_ENDPOINT; j++) {
1073 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1074 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1075 }
1076 }
1077
1078 return 0;
1079 }
1080
1081 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1082 {
1083 /* Put everything in reset. */
1084 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1085 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1086 DWC2_HPRT0_PRTOVRCURRCHNG,
1087 DWC2_HPRT0_PRTRST);
1088 }
1089
1090 #ifndef CONFIG_DM_USB
1091 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1092 int len, struct devrequest *setup)
1093 {
1094 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1095 }
1096
1097 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1098 int len)
1099 {
1100 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1101 }
1102
1103 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1104 int len, int interval)
1105 {
1106 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1107 }
1108
1109 /* U-Boot USB control interface */
1110 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1111 {
1112 struct dwc2_priv *priv = &local;
1113
1114 memset(priv, '\0', sizeof(*priv));
1115 priv->root_hub_devnum = 0;
1116 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1117 priv->aligned_buffer = aligned_buffer_addr;
1118 priv->status_buffer = status_buffer_addr;
1119
1120 /* board-dependant init */
1121 if (board_usb_init(index, USB_INIT_HOST))
1122 return -1;
1123
1124 return dwc2_init_common(priv);
1125 }
1126
1127 int usb_lowlevel_stop(int index)
1128 {
1129 dwc2_uninit_common(local.regs);
1130
1131 return 0;
1132 }
1133 #endif
1134
1135 #ifdef CONFIG_DM_USB
1136 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1137 unsigned long pipe, void *buffer, int length,
1138 struct devrequest *setup)
1139 {
1140 struct dwc2_priv *priv = dev_get_priv(dev);
1141
1142 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1143 dev->name, udev, udev->dev->name, udev->portnr);
1144
1145 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1146 }
1147
1148 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1149 unsigned long pipe, void *buffer, int length)
1150 {
1151 struct dwc2_priv *priv = dev_get_priv(dev);
1152
1153 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1154
1155 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1156 }
1157
1158 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1159 unsigned long pipe, void *buffer, int length,
1160 int interval)
1161 {
1162 struct dwc2_priv *priv = dev_get_priv(dev);
1163
1164 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1165
1166 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1167 }
1168
1169 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1170 {
1171 struct dwc2_priv *priv = dev_get_priv(dev);
1172 fdt_addr_t addr;
1173
1174 addr = dev_get_addr(dev);
1175 if (addr == FDT_ADDR_T_NONE)
1176 return -EINVAL;
1177 priv->regs = (struct dwc2_core_regs *)addr;
1178
1179 return 0;
1180 }
1181
1182 static int dwc2_usb_probe(struct udevice *dev)
1183 {
1184 struct dwc2_priv *priv = dev_get_priv(dev);
1185
1186 return dwc2_init_common(priv);
1187 }
1188
1189 static int dwc2_usb_remove(struct udevice *dev)
1190 {
1191 struct dwc2_priv *priv = dev_get_priv(dev);
1192
1193 dwc2_uninit_common(priv->regs);
1194
1195 return 0;
1196 }
1197
1198 struct dm_usb_ops dwc2_usb_ops = {
1199 .control = dwc2_submit_control_msg,
1200 .bulk = dwc2_submit_bulk_msg,
1201 .interrupt = dwc2_submit_int_msg,
1202 };
1203
1204 static const struct udevice_id dwc2_usb_ids[] = {
1205 { .compatible = "brcm,bcm2835-usb" },
1206 { .compatible = "snps,dwc2" },
1207 { }
1208 };
1209
1210 U_BOOT_DRIVER(usb_dwc2) = {
1211 .name = "dwc2_usb",
1212 .id = UCLASS_USB,
1213 .of_match = dwc2_usb_ids,
1214 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1215 .probe = dwc2_usb_probe,
1216 .remove = dwc2_usb_remove,
1217 .ops = &dwc2_usb_ops,
1218 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1219 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1220 };
1221 #endif
"Das U-Boot" Source Tree