drivers/usb/host/ehci-exynos.c

   1 /*
   2  * SAMSUNG EXYNOS USB HOST EHCI Controller
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co.Ltd
   5  *      Vivek Gautam <gautam.vivek@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA 02110-1301 USA
  21  */
  22
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <libfdt.h>
  26 #include <malloc.h>
  27 #include <usb.h>
  28 #include <asm/arch/cpu.h>
  29 #include <asm/arch/ehci.h>
  30 #include <asm/arch/system.h>
  31 #include <asm/arch/power.h>
  32 #include <asm-generic/errno.h>
  33 #include <linux/compat.h>
  34 #include "ehci.h"
  35
  36 /* Declare global data pointer */
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 /**
  40  * Contains pointers to register base addresses
  41  * for the usb controller.
  42  */
  43 struct exynos_ehci {
  44         struct exynos_usb_phy *usb;
  45         struct ehci_hccr *hcd;
  46 };
  47
  48 static struct exynos_ehci exynos;
  49
  50 #ifdef CONFIG_OF_CONTROL
  51 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
  52 {
  53         fdt_addr_t addr;
  54         unsigned int node;
  55         int depth;
  56
  57         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
  58         if (node <= 0) {
  59                 debug("EHCI: Can't get device node for ehci\n");
  60                 return -ENODEV;
  61         }
  62
  63         /*
  64          * Get the base address for EHCI controller from the device node
  65          */
  66         addr = fdtdec_get_addr(blob, node, "reg");
  67         if (addr == FDT_ADDR_T_NONE) {
  68                 debug("Can't get the EHCI register address\n");
  69                 return -ENXIO;
  70         }
  71
  72         exynos->hcd = (struct ehci_hccr *)addr;
  73
  74         depth = 0;
  75         node = fdtdec_next_compatible_subnode(blob, node,
  76                                         COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
  77         if (node <= 0) {
  78                 debug("EHCI: Can't get device node for usb-phy controller\n");
  79                 return -ENODEV;
  80         }
  81
  82         /*
  83          * Get the base address for usbphy from the device node
  84          */
  85         exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
  86                                                                 "reg");
  87         if (exynos->usb == NULL) {
  88                 debug("Can't get the usbphy register address\n");
  89                 return -ENXIO;
  90         }
  91
  92         return 0;
  93 }
  94 #endif
  95
  96 /* Setup the EHCI host controller. */
  97 static void setup_usb_phy(struct exynos_usb_phy *usb)
  98 {
  99         set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
 100
 101         set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
 102
 103         clrbits_le32(&usb->usbphyctrl0,
 104                         HOST_CTRL0_FSEL_MASK |
 105                         HOST_CTRL0_COMMONON_N |
 106                         /* HOST Phy setting */
 107                         HOST_CTRL0_PHYSWRST |
 108                         HOST_CTRL0_PHYSWRSTALL |
 109                         HOST_CTRL0_SIDDQ |
 110                         HOST_CTRL0_FORCESUSPEND |
 111                         HOST_CTRL0_FORCESLEEP);
 112
 113         setbits_le32(&usb->usbphyctrl0,
 114                         /* Setting up the ref freq */
 115                         (CLK_24MHZ << 16) |
 116                         /* HOST Phy setting */
 117                         HOST_CTRL0_LINKSWRST |
 118                         HOST_CTRL0_UTMISWRST);
 119         udelay(10);
 120         clrbits_le32(&usb->usbphyctrl0,
 121                         HOST_CTRL0_LINKSWRST |
 122                         HOST_CTRL0_UTMISWRST);
 123         udelay(20);
 124
 125         /* EHCI Ctrl setting */
 126         setbits_le32(&usb->ehcictrl,
 127                         EHCICTRL_ENAINCRXALIGN |
 128                         EHCICTRL_ENAINCR4 |
 129                         EHCICTRL_ENAINCR8 |
 130                         EHCICTRL_ENAINCR16);
 131 }
 132
 133 /* Reset the EHCI host controller. */
 134 static void reset_usb_phy(struct exynos_usb_phy *usb)
 135 {
 136         /* HOST_PHY reset */
 137         setbits_le32(&usb->usbphyctrl0,
 138                         HOST_CTRL0_PHYSWRST |
 139                         HOST_CTRL0_PHYSWRSTALL |
 140                         HOST_CTRL0_SIDDQ |
 141                         HOST_CTRL0_FORCESUSPEND |
 142                         HOST_CTRL0_FORCESLEEP);
 143
 144         set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 145 }
 146
 147 /*
 148  * EHCI-initialization
 149  * Create the appropriate control structures to manage
 150  * a new EHCI host controller.
 151  */
 152 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 153 {
 154         struct exynos_ehci *ctx = &exynos;
 155
 156 #ifdef CONFIG_OF_CONTROL
 157         if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
 158                 debug("Unable to parse device tree for ehci-exynos\n");
 159                 return -ENODEV;
 160         }
 161 #else
 162         ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
 163         ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
 164 #endif
 165
 166         setup_usb_phy(ctx->usb);
 167
 168         *hccr = ctx->hcd;
 169         *hcor = (struct ehci_hcor *)((uint32_t) *hccr
 170                                 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 171
 172         debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
 173                 (uint32_t)*hccr, (uint32_t)*hcor,
 174                 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 175
 176         return 0;
 177 }
 178
 179 /*
 180  * Destroy the appropriate control structures corresponding
 181  * the EHCI host controller.
 182  */
 183 int ehci_hcd_stop(int index)
 184 {
 185         struct exynos_ehci *ctx = &exynos;
 186
 187         reset_usb_phy(ctx->usb);
 188
 189         return 0;
 190 }