drivers/usb/host/ehci-mx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   4  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <log.h>
  10 #include <usb.h>
  11 #include <errno.h>
  12 #include <wait_bit.h>
  13 #include <asm/global_data.h>
  14 #include <linux/compiler.h>
  15 #include <linux/delay.h>
  16 #include <usb/ehci-ci.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/sys_proto.h>
  22 #include <dm.h>
  23 #include <asm/mach-types.h>
  24 #include <power/regulator.h>
  25 #include <linux/usb/otg.h>
  26 #include <linux/usb/phy.h>
  27
  28 #include "ehci.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define USB_OTGREGS_OFFSET      0x000
  33 #define USB_H1REGS_OFFSET       0x200
  34 #define USB_H2REGS_OFFSET       0x400
  35 #define USB_H3REGS_OFFSET       0x600
  36 #define USB_OTHERREGS_OFFSET    0x800
  37
  38 #define USB_H1_CTRL_OFFSET      0x04
  39
  40 #define USBPHY_CTRL                             0x00000030
  41 #define USBPHY_CTRL_SET                         0x00000034
  42 #define USBPHY_CTRL_CLR                         0x00000038
  43 #define USBPHY_CTRL_TOG                         0x0000003c
  44
  45 #define USBPHY_PWD                              0x00000000
  46 #define USBPHY_CTRL_SFTRST                      0x80000000
  47 #define USBPHY_CTRL_CLKGATE                     0x40000000
  48 #define USBPHY_CTRL_ENUTMILEVEL3                0x00008000
  49 #define USBPHY_CTRL_ENUTMILEVEL2                0x00004000
  50 #define USBPHY_CTRL_OTG_ID                      0x08000000
  51
  52 #define ANADIG_USB2_CHRG_DETECT_EN_B            0x00100000
  53 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B      0x00080000
  54
  55 #define ANADIG_USB2_PLL_480_CTRL_BYPASS         0x00010000
  56 #define ANADIG_USB2_PLL_480_CTRL_ENABLE         0x00002000
  57 #define ANADIG_USB2_PLL_480_CTRL_POWER          0x00001000
  58 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS    0x00000040
  59
  60 #define USBNC_OFFSET            0x200
  61 #define USBNC_PHY_STATUS_OFFSET 0x23C
  62 #define USBNC_PHYSTATUS_ID_DIG  (1 << 4) /* otg_id status */
  63 #define USBNC_PHYCFG2_ACAENB    (1 << 4) /* otg_id detection enable */
  64 #define UCTRL_PWR_POL           (1 << 9) /* OTG Polarity of Power Pin */
  65 #define UCTRL_OVER_CUR_POL      (1 << 8) /* OTG Polarity of Overcurrent */
  66 #define UCTRL_OVER_CUR_DIS      (1 << 7) /* Disable OTG Overcurrent Detection */
  67
  68 /* USBCMD */
  69 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
  70 #define UCMD_RESET              (1 << 1) /* controller reset */
  71
  72 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
  73 #ifndef CFG_MXC_USB_PORTSC
  74 #define CFG_MXC_USB_PORTSC      (PORT_PTS_UTMI | PORT_PTS_PTW)
  75 #endif
  76
  77 /* Base address for this IP block is 0x02184800 */
  78 struct usbnc_regs {
  79         u32 ctrl[4]; /* otg/host1-3 */
  80         u32 uh2_hsic_ctrl;
  81         u32 uh3_hsic_ctrl;
  82         u32 otg_phy_ctrl_0;
  83         u32 uh1_phy_ctrl_0;
  84         u32 reserve1[4];
  85         u32 phy_cfg1;
  86         u32 phy_cfg2;
  87         u32 reserve2;
  88         u32 phy_status;
  89         u32 reserve3[4];
  90         u32 adp_cfg1;
  91         u32 adp_cfg2;
  92         u32 adp_status;
  93 };
  94
  95 #if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
  96 static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
  97                                  int anatop_bits_index)
  98 {
  99         void __iomem *chrg_detect;
 100         void __iomem *pll_480_ctrl_clr;
 101         void __iomem *pll_480_ctrl_set;
 102
 103         if (!is_mx6())
 104                 return;
 105
 106         switch (anatop_bits_index) {
 107         case 0:
 108                 chrg_detect = &anatop->usb1_chrg_detect;
 109                 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
 110                 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
 111                 break;
 112         case 1:
 113                 chrg_detect = &anatop->usb2_chrg_detect;
 114                 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
 115                 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
 116                 break;
 117         default:
 118                 return;
 119         }
 120         /*
 121          * Some phy and power's special controls
 122          * 1. The external charger detector needs to be disabled
 123          * or the signal at DP will be poor
 124          * 2. The PLL's power and output to usb
 125          * is totally controlled by IC, so the Software only needs
 126          * to enable them at initializtion.
 127          */
 128         writel(ANADIG_USB2_CHRG_DETECT_EN_B |
 129                      ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
 130                      chrg_detect);
 131
 132         writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
 133                      pll_480_ctrl_clr);
 134
 135         writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
 136                      ANADIG_USB2_PLL_480_CTRL_POWER |
 137                      ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
 138                      pll_480_ctrl_set);
 139 }
 140 #else
 141 static void __maybe_unused
 142 usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
 143 #endif
 144
 145 #if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
 146 static void usb_power_config_mx7(struct usbnc_regs *usbnc)
 147 {
 148         void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
 149
 150         if (!is_mx7())
 151                 return;
 152
 153         /*
 154          * Clear the ACAENB to enable usb_otg_id detection,
 155          * otherwise it is the ACA detection enabled.
 156          */
 157         clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
 158 }
 159 #else
 160 static void __maybe_unused
 161 usb_power_config_mx7(void *usbnc) { }
 162 #endif
 163
 164 #if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
 165 static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
 166 {
 167         if (!is_mx7ulp())
 168                 return;
 169
 170         writel(ANADIG_USB2_CHRG_DETECT_EN_B |
 171                ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
 172                &usbphy->usb1_chrg_detect);
 173
 174         scg_enable_usb_pll(true);
 175 }
 176 #else
 177 static void __maybe_unused
 178 usb_power_config_mx7ulp(void *usbphy) { }
 179 #endif
 180
 181 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
 182 static const unsigned phy_bases[] = {
 183         USB_PHY0_BASE_ADDR,
 184 #if defined(USB_PHY1_BASE_ADDR)
 185         USB_PHY1_BASE_ADDR,
 186 #endif
 187 };
 188
 189 #if !defined(CONFIG_PHY)
 190 static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
 191 {
 192         phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
 193         writel(USBPHY_CTRL_CLKGATE, phy_reg);
 194 }
 195
 196 /* Return 0 : host node, <>0 : device mode */
 197 static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
 198 {
 199         void __iomem *phy_ctrl;
 200         void __iomem *usb_cmd;
 201         int ret;
 202
 203         phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 204         usb_cmd = (void __iomem *)&ehci->usbcmd;
 205
 206         /* Stop then Reset */
 207         clrbits_le32(usb_cmd, UCMD_RUN_STOP);
 208         ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
 209         if (ret)
 210                 return ret;
 211
 212         setbits_le32(usb_cmd, UCMD_RESET);
 213         ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
 214         if (ret)
 215                 return ret;
 216
 217         /* Reset USBPHY module */
 218         setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
 219         udelay(10);
 220
 221         /* Remove CLKGATE and SFTRST */
 222         clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
 223         udelay(10);
 224
 225         /* Power up the PHY */
 226         writel(0, phy_reg + USBPHY_PWD);
 227         /* enable FS/LS device */
 228         setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
 229                         USBPHY_CTRL_ENUTMILEVEL3);
 230
 231         return 0;
 232 }
 233 #endif
 234
 235 int usb_phy_mode(int port)
 236 {
 237         void __iomem *phy_reg;
 238         void __iomem *phy_ctrl;
 239         u32 val;
 240
 241         phy_reg = (void __iomem *)phy_bases[port];
 242         phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 243
 244         val = readl(phy_ctrl);
 245
 246         if (val & USBPHY_CTRL_OTG_ID)
 247                 return USB_INIT_DEVICE;
 248         else
 249                 return USB_INIT_HOST;
 250 }
 251
 252 #elif defined(CONFIG_MX7)
 253 int usb_phy_mode(int port)
 254 {
 255         struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 256                         (0x10000 * port) + USBNC_OFFSET);
 257         void __iomem *status = (void __iomem *)(&usbnc->phy_status);
 258         u32 val;
 259
 260         val = readl(status);
 261
 262         if (val & USBNC_PHYSTATUS_ID_DIG)
 263                 return USB_INIT_DEVICE;
 264         else
 265                 return USB_INIT_HOST;
 266 }
 267 #endif
 268
 269 #if !defined(CONFIG_PHY)
 270 /* Should be done in the MXS PHY driver */
 271 static void usb_oc_config(struct usbnc_regs *usbnc, int index)
 272 {
 273         void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
 274
 275         setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
 276
 277         setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
 278
 279         /* Set power polarity to high active */
 280 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
 281         setbits_le32(ctrl, UCTRL_PWR_POL);
 282 #else
 283         clrbits_le32(ctrl, UCTRL_PWR_POL);
 284 #endif
 285 }
 286 #endif
 287
 288 #if !CONFIG_IS_ENABLED(DM_USB)
 289 /**
 290  * board_usb_phy_mode - override usb phy mode
 291  * @port:       usb host/otg port
 292  *
 293  * Target board specific, override usb_phy_mode.
 294  * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
 295  * left disconnected in this case usb_phy_mode will not be able to identify
 296  * the phy mode that usb port is used.
 297  * Machine file overrides board_usb_phy_mode.
 298  *
 299  * Return: USB_INIT_DEVICE or USB_INIT_HOST
 300  */
 301 int __weak board_usb_phy_mode(int port)
 302 {
 303         return usb_phy_mode(port);
 304 }
 305
 306 /**
 307  * board_ehci_hcd_init - set usb vbus voltage
 308  * @port:      usb otg port
 309  *
 310  * Target board specific, setup iomux pad to setup supply vbus voltage
 311  * for usb otg port. Machine board file overrides board_ehci_hcd_init
 312  *
 313  * Return: 0 Success
 314  */
 315 int __weak board_ehci_hcd_init(int port)
 316 {
 317         return 0;
 318 }
 319
 320 /**
 321  * board_ehci_power - enables/disables usb vbus voltage
 322  * @port:      usb otg port
 323  * @on:        on/off vbus voltage
 324  *
 325  * Enables/disables supply vbus voltage for usb otg port.
 326  * Machine board file overrides board_ehci_power
 327  *
 328  * Return: 0 Success
 329  */
 330 int __weak board_ehci_power(int port, int on)
 331 {
 332         return 0;
 333 }
 334
 335 int ehci_hcd_init(int index, enum usb_init_type init,
 336                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 337 {
 338         enum usb_init_type type;
 339 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
 340         u32 controller_spacing = 0x200;
 341         struct anatop_regs __iomem *anatop =
 342                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 343         struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 344                         USB_OTHERREGS_OFFSET);
 345 #elif defined(CONFIG_MX7)
 346         u32 controller_spacing = 0x10000;
 347         struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 348                         (0x10000 * index) + USBNC_OFFSET);
 349 #elif defined(CONFIG_MX7ULP)
 350         u32 controller_spacing = 0x10000;
 351         struct usbphy_regs __iomem *usbphy =
 352                 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
 353         struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
 354                         (0x10000 * index) + USBNC_OFFSET);
 355 #endif
 356         struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
 357                 (controller_spacing * index));
 358         int ret;
 359
 360         if (index > 3)
 361                 return -EINVAL;
 362
 363         if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
 364                 if (usb_fused((ulong)ehci)) {
 365                         printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
 366                                (ulong)ehci);
 367                         return  -ENODEV;
 368                 }
 369         }
 370
 371         enable_usboh3_clk(1);
 372         mdelay(1);
 373
 374         /* Do board specific initialization */
 375         ret = board_ehci_hcd_init(index);
 376         if (ret) {
 377                 enable_usboh3_clk(0);
 378                 return ret;
 379         }
 380
 381 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
 382         usb_power_config_mx6(anatop, index);
 383 #elif defined (CONFIG_MX7)
 384         usb_power_config_mx7(usbnc);
 385 #elif defined (CONFIG_MX7ULP)
 386         usb_power_config_mx7ulp(usbphy);
 387 #endif
 388
 389         usb_oc_config(usbnc, index);
 390
 391 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
 392         if (index < ARRAY_SIZE(phy_bases)) {
 393                 usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
 394                 usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
 395         }
 396 #endif
 397
 398         type = board_usb_phy_mode(index);
 399
 400         if (hccr && hcor) {
 401                 *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
 402                 *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
 403                                 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 404         }
 405
 406         if ((type == init) || (type == USB_INIT_DEVICE))
 407                 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
 408         if (type != init)
 409                 return -ENODEV;
 410         if (type == USB_INIT_DEVICE)
 411                 return 0;
 412
 413         setbits_le32(&ehci->usbmode, CM_HOST);
 414         writel(CFG_MXC_USB_PORTSC, &ehci->portsc);
 415         setbits_le32(&ehci->portsc, USB_EN);
 416
 417         mdelay(10);
 418
 419         return 0;
 420 }
 421
 422 int ehci_hcd_stop(int index)
 423 {
 424         return 0;
 425 }
 426 #else
 427 struct ehci_mx6_priv_data {
 428         struct ehci_ctrl ctrl;
 429         struct usb_ehci *ehci;
 430         struct udevice *vbus_supply;
 431         struct clk clk;
 432         struct phy phy;
 433         enum usb_init_type init_type;
 434         enum usb_phy_interface phy_type;
 435 #if !defined(CONFIG_PHY)
 436         int portnr;
 437         void __iomem *phy_addr;
 438         void __iomem *misc_addr;
 439         void __iomem *anatop_addr;
 440 #endif
 441 };
 442
 443 static u32 mx6_portsc(enum usb_phy_interface phy_type)
 444 {
 445         switch (phy_type) {
 446         case USBPHY_INTERFACE_MODE_UTMI:
 447                 return PORT_PTS_UTMI;
 448         case USBPHY_INTERFACE_MODE_UTMIW:
 449                 return PORT_PTS_UTMI | PORT_PTS_PTW;
 450         case USBPHY_INTERFACE_MODE_ULPI:
 451                 return PORT_PTS_ULPI;
 452         case USBPHY_INTERFACE_MODE_SERIAL:
 453                 return PORT_PTS_SERIAL;
 454         case USBPHY_INTERFACE_MODE_HSIC:
 455                 return PORT_PTS_HSIC;
 456         default:
 457                 return CFG_MXC_USB_PORTSC;
 458         }
 459 }
 460
 461 static int mx6_init_after_reset(struct ehci_ctrl *dev)
 462 {
 463         struct ehci_mx6_priv_data *priv = dev->priv;
 464         enum usb_init_type type = priv->init_type;
 465         struct usb_ehci *ehci = priv->ehci;
 466
 467 #if !defined(CONFIG_PHY)
 468         usb_power_config_mx6(priv->anatop_addr, priv->portnr);
 469         usb_power_config_mx7(priv->misc_addr);
 470         usb_power_config_mx7ulp(priv->phy_addr);
 471
 472         usb_oc_config(priv->misc_addr, priv->portnr);
 473
 474 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
 475         usb_internal_phy_clock_gate(priv->phy_addr, 1);
 476         usb_phy_enable(ehci, priv->phy_addr);
 477 #endif
 478 #endif
 479
 480 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 481         if (priv->vbus_supply) {
 482                 int ret;
 483                 ret = regulator_set_enable(priv->vbus_supply,
 484                                            (type == USB_INIT_DEVICE) ?
 485                                            false : true);
 486                 if (ret && ret != -ENOSYS) {
 487                         printf("Error enabling VBUS supply (ret=%i)\n", ret);
 488                         return ret;
 489                 }
 490         }
 491 #endif
 492
 493         if (type == USB_INIT_DEVICE)
 494                 return 0;
 495
 496         setbits_le32(&ehci->usbmode, CM_HOST);
 497         writel(mx6_portsc(priv->phy_type), &ehci->portsc);
 498         setbits_le32(&ehci->portsc, USB_EN);
 499
 500         mdelay(10);
 501
 502         return 0;
 503 }
 504
 505 static const struct ehci_ops mx6_ehci_ops = {
 506         .init_after_reset = mx6_init_after_reset
 507 };
 508
 509 static int ehci_usb_phy_mode(struct udevice *dev)
 510 {
 511         struct usb_plat *plat = dev_get_plat(dev);
 512         void *__iomem addr = dev_read_addr_ptr(dev);
 513         void *__iomem phy_ctrl, *__iomem phy_status;
 514         const void *blob = gd->fdt_blob;
 515         int offset = dev_of_offset(dev), phy_off;
 516         u32 val;
 517
 518         /*
 519          * About fsl,usbphy, Refer to
 520          * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
 521          */
 522         if (is_mx6() || is_mx7ulp() || is_imxrt()) {
 523                 phy_off = fdtdec_lookup_phandle(blob,
 524                                                 offset,
 525                                                 "fsl,usbphy");
 526                 if (phy_off < 0)
 527                         return -EINVAL;
 528
 529                 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
 530                                                        "reg");
 531                 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 532                         return -EINVAL;
 533
 534                 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
 535                 val = readl(phy_ctrl);
 536
 537                 if (val & USBPHY_CTRL_OTG_ID)
 538                         plat->init_type = USB_INIT_DEVICE;
 539                 else
 540                         plat->init_type = USB_INIT_HOST;
 541         } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
 542                 phy_status = (void __iomem *)(addr +
 543                                               USBNC_PHY_STATUS_OFFSET);
 544                 val = readl(phy_status);
 545
 546                 if (val & USBNC_PHYSTATUS_ID_DIG)
 547                         plat->init_type = USB_INIT_DEVICE;
 548                 else
 549                         plat->init_type = USB_INIT_HOST;
 550         } else {
 551                 return -EINVAL;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static int ehci_usb_of_to_plat(struct udevice *dev)
 558 {
 559         struct usb_plat *plat = dev_get_plat(dev);
 560         enum usb_dr_mode dr_mode;
 561
 562         dr_mode = usb_get_dr_mode(dev_ofnode(dev));
 563
 564         switch (dr_mode) {
 565         case USB_DR_MODE_HOST:
 566                 plat->init_type = USB_INIT_HOST;
 567                 break;
 568         case USB_DR_MODE_PERIPHERAL:
 569                 plat->init_type = USB_INIT_DEVICE;
 570                 break;
 571         default:
 572                 plat->init_type = USB_INIT_UNKNOWN;
 573         };
 574
 575         return 0;
 576 }
 577
 578 static int mx6_parse_dt_addrs(struct udevice *dev)
 579 {
 580 #if !defined(CONFIG_PHY)
 581         struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
 582         int phy_off, misc_off;
 583         const void *blob = gd->fdt_blob;
 584         int offset = dev_of_offset(dev);
 585         void *__iomem addr;
 586
 587         phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
 588         if (phy_off < 0) {
 589                 phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
 590                 if (phy_off < 0)
 591                         return -EINVAL;
 592         }
 593
 594         misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
 595         if (misc_off < 0)
 596                 return -EINVAL;
 597
 598         addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
 599         if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 600                 addr = NULL;
 601
 602         priv->phy_addr = addr;
 603
 604         addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
 605         if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 606                 return -EINVAL;
 607
 608         priv->misc_addr = addr;
 609
 610 #if defined(CONFIG_MX6)
 611         int anatop_off, ret, devnump;
 612
 613         ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
 614                                    phy_off, &devnump);
 615         if (ret < 0)
 616                 return ret;
 617         priv->portnr = devnump;
 618
 619         /* Resolve ANATOP offset through USB PHY node */
 620         anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
 621         if (anatop_off < 0)
 622                 return -EINVAL;
 623
 624         addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
 625         if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 626                 return -EINVAL;
 627
 628         priv->anatop_addr = addr;
 629 #endif
 630 #endif
 631         return 0;
 632 }
 633
 634 static int ehci_usb_probe(struct udevice *dev)
 635 {
 636         struct usb_plat *plat = dev_get_plat(dev);
 637         struct usb_ehci *ehci = dev_read_addr_ptr(dev);
 638         struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
 639         enum usb_init_type type = plat->init_type;
 640         struct ehci_hccr *hccr;
 641         struct ehci_hcor *hcor;
 642         int ret;
 643
 644         if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
 645                 if (usb_fused((ulong)ehci)) {
 646                         printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
 647                                (ulong)ehci);
 648                         return -ENODEV;
 649                 }
 650         }
 651
 652         ret = mx6_parse_dt_addrs(dev);
 653         if (ret)
 654                 return ret;
 655
 656         priv->ehci = ehci;
 657         priv->init_type = type;
 658         priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
 659
 660 #if CONFIG_IS_ENABLED(CLK)
 661         ret = clk_get_by_index(dev, 0, &priv->clk);
 662         if (ret < 0)
 663                 return ret;
 664
 665         ret = clk_enable(&priv->clk);
 666         if (ret)
 667                 return ret;
 668 #else
 669         /* Compatibility with DM_USB and !CLK */
 670         enable_usboh3_clk(1);
 671         mdelay(1);
 672 #endif
 673
 674         /*
 675          * If the device tree didn't specify host or device,
 676          * the default is USB_INIT_UNKNOWN, so we need to check
 677          * the register. For imx8mm and imx8mn, the clocks need to be
 678          * running first, so we defer the check until they are.
 679          */
 680         if (priv->init_type == USB_INIT_UNKNOWN) {
 681                 ret = ehci_usb_phy_mode(dev);
 682                 if (ret)
 683                         goto err_clk;
 684                 else
 685                         priv->init_type = plat->init_type;
 686         }
 687
 688 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 689         ret = device_get_supply_regulator(dev, "vbus-supply",
 690                                           &priv->vbus_supply);
 691         if (ret)
 692                 debug("%s: No vbus supply\n", dev->name);
 693 #endif
 694
 695 #if !defined(CONFIG_PHY)
 696         usb_power_config_mx6(priv->anatop_addr, priv->portnr);
 697         usb_power_config_mx7(priv->misc_addr);
 698         usb_power_config_mx7ulp(priv->phy_addr);
 699
 700         usb_oc_config(priv->misc_addr, priv->portnr);
 701
 702 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
 703         usb_internal_phy_clock_gate(priv->phy_addr, 1);
 704         usb_phy_enable(ehci, priv->phy_addr);
 705 #endif
 706 #else
 707         ret = generic_setup_phy(dev, &priv->phy, 0);
 708         if (ret)
 709                 goto err_regulator;
 710 #endif
 711
 712         if (priv->init_type == USB_INIT_HOST) {
 713                 setbits_le32(&ehci->usbmode, CM_HOST);
 714                 writel(mx6_portsc(priv->phy_type), &ehci->portsc);
 715                 setbits_le32(&ehci->portsc, USB_EN);
 716         }
 717
 718         mdelay(10);
 719
 720         hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
 721         hcor = (struct ehci_hcor *)((uintptr_t)hccr +
 722                         HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
 723
 724         ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
 725         if (ret)
 726                 goto err_phy;
 727
 728         return ret;
 729
 730 err_phy:
 731 #if defined(CONFIG_PHY)
 732         generic_shutdown_phy(&priv->phy);
 733 err_regulator:
 734 #endif
 735 err_clk:
 736 #if CONFIG_IS_ENABLED(CLK)
 737         clk_disable(&priv->clk);
 738 #else
 739         /* Compatibility with DM_USB and !CLK */
 740         enable_usboh3_clk(0);
 741 #endif
 742         return ret;
 743 }
 744
 745 int ehci_usb_remove(struct udevice *dev)
 746 {
 747         struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
 748
 749         ehci_deregister(dev);
 750
 751 #if defined(CONFIG_PHY)
 752         generic_shutdown_phy(&priv->phy);
 753 #endif
 754
 755 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 756         if (priv->vbus_supply)
 757                 regulator_set_enable(priv->vbus_supply, false);
 758 #endif
 759
 760 #if CONFIG_IS_ENABLED(CLK)
 761         clk_disable(&priv->clk);
 762 #endif
 763
 764         return 0;
 765 }
 766
 767 static const struct udevice_id mx6_usb_ids[] = {
 768         { .compatible = "fsl,imx27-usb" },
 769         { .compatible = "fsl,imx7d-usb" },
 770         { .compatible = "fsl,imxrt-usb" },
 771         { }
 772 };
 773
 774 U_BOOT_DRIVER(usb_mx6) = {
 775         .name   = "ehci_mx6",
 776         .id     = UCLASS_USB,
 777         .of_match = mx6_usb_ids,
 778         .of_to_plat = ehci_usb_of_to_plat,
 779         .probe  = ehci_usb_probe,
 780         .remove = ehci_usb_remove,
 781         .ops    = &ehci_usb_ops,
 782         .plat_auto      = sizeof(struct usb_plat),
 783         .priv_auto      = sizeof(struct ehci_mx6_priv_data),
 784         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
 785 };
 786 #endif