2 * Freescale i.MX28 USB Host driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/regs-common.h>
25 #include <asm/arch/regs-base.h>
26 #include <asm/arch/regs-clkctrl.h>
27 #include <asm/arch/regs-usb.h>
28 #include <asm/arch/regs-usbphy.h>
30 #include "ehci-core.h"
33 #if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
34 #error "MXS EHCI: Invalid port selected!"
37 #ifndef CONFIG_EHCI_MXS_PORT
38 #error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
41 static struct ehci_mxs
{
42 struct mx28_usb_regs
*usb_regs
;
43 struct mx28_usbphy_regs
*phy_regs
;
46 int mxs_ehci_get_port(struct ehci_mxs
*mxs_usb
, int port
)
48 uint32_t usb_base
, phy_base
;
51 usb_base
= MXS_USBCTRL0_BASE
;
52 phy_base
= MXS_USBPHY0_BASE
;
55 usb_base
= MXS_USBCTRL1_BASE
;
56 phy_base
= MXS_USBPHY1_BASE
;
59 printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port
);
63 mxs_usb
->usb_regs
= (struct mx28_usb_regs
*)usb_base
;
64 mxs_usb
->phy_regs
= (struct mx28_usbphy_regs
*)phy_base
;
68 /* This DIGCTL register ungates clock to USB */
69 #define HW_DIGCTL_CTRL 0x8001c000
70 #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
71 #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
73 int ehci_hcd_init(void)
77 uint32_t usb_base
, cap_base
;
78 struct mx28_register_32
*digctl_ctrl
=
79 (struct mx28_register_32
*)HW_DIGCTL_CTRL
;
80 struct mx28_clkctrl_regs
*clkctrl_regs
=
81 (struct mx28_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
83 ret
= mxs_ehci_get_port(&ehci_mxs
, CONFIG_EHCI_MXS_PORT
);
87 /* Reset the PHY block */
88 writel(USBPHY_CTRL_SFTRST
, &ehci_mxs
.phy_regs
->hw_usbphy_ctrl_set
);
90 writel(USBPHY_CTRL_SFTRST
| USBPHY_CTRL_CLKGATE
,
91 &ehci_mxs
.phy_regs
->hw_usbphy_ctrl_clr
);
93 /* Enable USB clock */
94 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS
| CLKCTRL_PLL0CTRL0_POWER
,
95 &clkctrl_regs
->hw_clkctrl_pll0ctrl0_set
);
96 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS
| CLKCTRL_PLL1CTRL0_POWER
,
97 &clkctrl_regs
->hw_clkctrl_pll1ctrl0_set
);
99 writel(HW_DIGCTL_CTRL_USB0_CLKGATE
| HW_DIGCTL_CTRL_USB1_CLKGATE
,
100 &digctl_ctrl
->reg_clr
);
103 writel(0, &ehci_mxs
.phy_regs
->hw_usbphy_pwd
);
105 /* Enable UTMI+ Level 2 and Level 3 compatibility */
106 writel(USBPHY_CTRL_ENUTMILEVEL3
| USBPHY_CTRL_ENUTMILEVEL2
| 1,
107 &ehci_mxs
.phy_regs
->hw_usbphy_ctrl_set
);
109 usb_base
= ((uint32_t)ehci_mxs
.usb_regs
) + 0x100;
110 hccr
= (struct ehci_hccr
*)usb_base
;
112 cap_base
= ehci_readl(&hccr
->cr_capbase
);
113 hcor
= (struct ehci_hcor
*)(usb_base
+ HC_LENGTH(cap_base
));
118 int ehci_hcd_stop(void)
122 struct mx28_register_32
*digctl_ctrl
=
123 (struct mx28_register_32
*)HW_DIGCTL_CTRL
;
124 struct mx28_clkctrl_regs
*clkctrl_regs
=
125 (struct mx28_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
127 ret
= mxs_ehci_get_port(&ehci_mxs
, CONFIG_EHCI_MXS_PORT
);
131 /* Stop the USB port */
132 tmp
= ehci_readl(&hcor
->or_usbcmd
);
134 ehci_writel(tmp
, &hcor
->or_usbcmd
);
136 /* Disable the PHY */
137 tmp
= USBPHY_PWD_RXPWDRX
| USBPHY_PWD_RXPWDDIFF
|
138 USBPHY_PWD_RXPWD1PT1
| USBPHY_PWD_RXPWDENV
|
139 USBPHY_PWD_TXPWDV2I
| USBPHY_PWD_TXPWDIBIAS
|
141 writel(tmp
, &ehci_mxs
.phy_regs
->hw_usbphy_pwd
);
143 /* Disable USB clock */
144 writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS
,
145 &clkctrl_regs
->hw_clkctrl_pll0ctrl0_clr
);
146 writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS
,
147 &clkctrl_regs
->hw_clkctrl_pll1ctrl0_clr
);
149 /* Gate off the USB clock */
150 writel(HW_DIGCTL_CTRL_USB0_CLKGATE
| HW_DIGCTL_CTRL_USB1_CLKGATE
,
151 &digctl_ctrl
->reg_set
);