drivers/usb/host/ehci.h

   1 /*-
   2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   3  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   4  * All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef USB_EHCI_H
  23 #define USB_EHCI_H
  24
  25 #include <usb.h>
  26
  27 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
  28 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      2
  29 #endif
  30
  31 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
  32 #define DeviceRequest \
  33         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  34
  35 #define DeviceOutRequest \
  36         ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  37
  38 #define InterfaceRequest \
  39         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  40
  41 #define EndpointRequest \
  42         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  43
  44 #define EndpointOutRequest \
  45         ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  46
  47 /*
  48  * Register Space.
  49  */
  50 struct ehci_hccr {
  51         uint32_t cr_capbase;
  52 #define HC_LENGTH(p)            (((p) >> 0) & 0x00ff)
  53 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  54         uint32_t cr_hcsparams;
  55 #define HCS_PPC(p)              ((p) & (1 << 4))
  56 #define HCS_INDICATOR(p)        ((p) & (1 << 16)) /* Port indicators */
  57 #define HCS_N_PORTS(p)          (((p) >> 0) & 0xf)
  58         uint32_t cr_hccparams;
  59         uint8_t cr_hcsp_portrt[8];
  60 } __attribute__ ((packed, aligned(4)));
  61
  62 struct ehci_hcor {
  63         uint32_t or_usbcmd;
  64 #define CMD_PARK        (1 << 11)               /* enable "park" */
  65 #define CMD_PARK_CNT(c) (((c) >> 8) & 3)        /* how many transfers to park */
  66 #define CMD_ASE         (1 << 5)                /* async schedule enable */
  67 #define CMD_LRESET      (1 << 7)                /* partial reset */
  68 #define CMD_IAAD        (1 << 5)                /* "doorbell" interrupt */
  69 #define CMD_PSE         (1 << 4)                /* periodic schedule enable */
  70 #define CMD_RESET       (1 << 1)                /* reset HC not bus */
  71 #define CMD_RUN         (1 << 0)                /* start/stop HC */
  72         uint32_t or_usbsts;
  73 #define STS_ASS         (1 << 15)
  74 #define STS_PSS         (1 << 14)
  75 #define STS_HALT        (1 << 12)
  76         uint32_t or_usbintr;
  77 #define INTR_UE         (1 << 0)                /* USB interrupt enable */
  78 #define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
  79 #define INTR_PCE        (1 << 2)                /* Port change detect enable */
  80 #define INTR_SEE        (1 << 4)                /* system error enable */
  81 #define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
  82         uint32_t or_frindex;
  83         uint32_t or_ctrldssegment;
  84         uint32_t or_periodiclistbase;
  85         uint32_t or_asynclistaddr;
  86         uint32_t _reserved_0_;
  87         uint32_t or_burstsize;
  88         uint32_t or_txfilltuning;
  89 #define TXFIFO_THRESH_MASK              (0x3f << 16)
  90 #define TXFIFO_THRESH(p)                ((p & 0x3f) << 16)
  91         uint32_t _reserved_1_[6];
  92         uint32_t or_configflag;
  93 #define FLAG_CF         (1 << 0)        /* true:  we'll support "high speed" */
  94         uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
  95 #define PORTSC_PSPD(x)          (((x) >> 26) & 0x3)
  96 #define PORTSC_PSPD_FS                  0x0
  97 #define PORTSC_PSPD_LS                  0x1
  98 #define PORTSC_PSPD_HS                  0x2
  99         uint32_t or_systune;
 100 } __attribute__ ((packed, aligned(4)));
 101
 102 #define USBMODE         0x68            /* USB Device mode */
 103 #define USBMODE_SDIS    (1 << 3)        /* Stream disable */
 104 #define USBMODE_BE      (1 << 2)        /* BE/LE endiannes select */
 105 #define USBMODE_CM_HC   (3 << 0)        /* host controller mode */
 106 #define USBMODE_CM_IDLE (0 << 0)        /* idle state */
 107
 108 /* Interface descriptor */
 109 struct usb_linux_interface_descriptor {
 110         unsigned char   bLength;
 111         unsigned char   bDescriptorType;
 112         unsigned char   bInterfaceNumber;
 113         unsigned char   bAlternateSetting;
 114         unsigned char   bNumEndpoints;
 115         unsigned char   bInterfaceClass;
 116         unsigned char   bInterfaceSubClass;
 117         unsigned char   bInterfaceProtocol;
 118         unsigned char   iInterface;
 119 } __attribute__ ((packed));
 120
 121 /* Configuration descriptor information.. */
 122 struct usb_linux_config_descriptor {
 123         unsigned char   bLength;
 124         unsigned char   bDescriptorType;
 125         unsigned short  wTotalLength;
 126         unsigned char   bNumInterfaces;
 127         unsigned char   bConfigurationValue;
 128         unsigned char   iConfiguration;
 129         unsigned char   bmAttributes;
 130         unsigned char   MaxPower;
 131 } __attribute__ ((packed));
 132
 133 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
 134 #define ehci_readl(x)           (*((volatile u32 *)(x)))
 135 #define ehci_writel(a, b)       (*((volatile u32 *)(a)) = ((volatile u32)b))
 136 #else
 137 #define ehci_readl(x)           cpu_to_le32((*((volatile u32 *)(x))))
 138 #define ehci_writel(a, b)       (*((volatile u32 *)(a)) = \
 139                                         cpu_to_le32(((volatile u32)b)))
 140 #endif
 141
 142 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
 143 #define hc32_to_cpu(x)          be32_to_cpu((x))
 144 #define cpu_to_hc32(x)          cpu_to_be32((x))
 145 #else
 146 #define hc32_to_cpu(x)          le32_to_cpu((x))
 147 #define cpu_to_hc32(x)          cpu_to_le32((x))
 148 #endif
 149
 150 #define EHCI_PS_WKOC_E          (1 << 22)       /* RW wake on over current */
 151 #define EHCI_PS_WKDSCNNT_E      (1 << 21)       /* RW wake on disconnect */
 152 #define EHCI_PS_WKCNNT_E        (1 << 20)       /* RW wake on connect */
 153 #define EHCI_PS_PO              (1 << 13)       /* RW port owner */
 154 #define EHCI_PS_PP              (1 << 12)       /* RW,RO port power */
 155 #define EHCI_PS_LS              (3 << 10)       /* RO line status */
 156 #define EHCI_PS_PR              (1 << 8)        /* RW port reset */
 157 #define EHCI_PS_SUSP            (1 << 7)        /* RW suspend */
 158 #define EHCI_PS_FPR             (1 << 6)        /* RW force port resume */
 159 #define EHCI_PS_OCC             (1 << 5)        /* RWC over current change */
 160 #define EHCI_PS_OCA             (1 << 4)        /* RO over current active */
 161 #define EHCI_PS_PEC             (1 << 3)        /* RWC port enable change */
 162 #define EHCI_PS_PE              (1 << 2)        /* RW port enable */
 163 #define EHCI_PS_CSC             (1 << 1)        /* RWC connect status change */
 164 #define EHCI_PS_CS              (1 << 0)        /* RO connect status */
 165 #define EHCI_PS_CLEAR           (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
 166
 167 #define EHCI_PS_IS_LOWSPEED(x)  (((x) & EHCI_PS_LS) == (1 << 10))
 168
 169 /*
 170  * Schedule Interface Space.
 171  *
 172  * IMPORTANT: Software must ensure that no interface data structure
 173  * reachable by the EHCI host controller spans a 4K page boundary!
 174  *
 175  * Periodic transfers (i.e. isochronous and interrupt transfers) are
 176  * not supported.
 177  */
 178
 179 /* Queue Element Transfer Descriptor (qTD). */
 180 struct qTD {
 181         /* this part defined by EHCI spec */
 182         uint32_t qt_next;                       /* see EHCI 3.5.1 */
 183 #define QT_NEXT_TERMINATE       1
 184         uint32_t qt_altnext;                    /* see EHCI 3.5.2 */
 185         uint32_t qt_token;                      /* see EHCI 3.5.3 */
 186 #define QT_TOKEN_DT(x)          (((x) & 0x1) << 31)     /* Data Toggle */
 187 #define QT_TOKEN_GET_DT(x)              (((x) >> 31) & 0x1)
 188 #define QT_TOKEN_TOTALBYTES(x)  (((x) & 0x7fff) << 16)  /* Total Bytes to Transfer */
 189 #define QT_TOKEN_GET_TOTALBYTES(x)      (((x) >> 16) & 0x7fff)
 190 #define QT_TOKEN_IOC(x)         (((x) & 0x1) << 15)     /* Interrupt On Complete */
 191 #define QT_TOKEN_CPAGE(x)       (((x) & 0x7) << 12)     /* Current Page */
 192 #define QT_TOKEN_CERR(x)        (((x) & 0x3) << 10)     /* Error Counter */
 193 #define QT_TOKEN_PID(x)         (((x) & 0x3) << 8)      /* PID Code */
 194 #define QT_TOKEN_PID_OUT                0x0
 195 #define QT_TOKEN_PID_IN                 0x1
 196 #define QT_TOKEN_PID_SETUP              0x2
 197 #define QT_TOKEN_STATUS(x)      (((x) & 0xff) << 0)     /* Status */
 198 #define QT_TOKEN_GET_STATUS(x)          (((x) >> 0) & 0xff)
 199 #define QT_TOKEN_STATUS_ACTIVE          0x80
 200 #define QT_TOKEN_STATUS_HALTED          0x40
 201 #define QT_TOKEN_STATUS_DATBUFERR       0x20
 202 #define QT_TOKEN_STATUS_BABBLEDET       0x10
 203 #define QT_TOKEN_STATUS_XACTERR         0x08
 204 #define QT_TOKEN_STATUS_MISSEDUFRAME    0x04
 205 #define QT_TOKEN_STATUS_SPLITXSTATE     0x02
 206 #define QT_TOKEN_STATUS_PERR            0x01
 207 #define QT_BUFFER_CNT           5
 208         uint32_t qt_buffer[QT_BUFFER_CNT];      /* see EHCI 3.5.4 */
 209         uint32_t qt_buffer_hi[QT_BUFFER_CNT];   /* Appendix B */
 210         /* pad struct for 32 byte alignment */
 211         uint32_t unused[3];
 212 };
 213
 214 #define EHCI_PAGE_SIZE          4096
 215
 216 /* Queue Head (QH). */
 217 struct QH {
 218         uint32_t qh_link;
 219 #define QH_LINK_TERMINATE       1
 220 #define QH_LINK_TYPE_ITD        0
 221 #define QH_LINK_TYPE_QH         2
 222 #define QH_LINK_TYPE_SITD       4
 223 #define QH_LINK_TYPE_FSTN       6
 224         uint32_t qh_endpt1;
 225 #define QH_ENDPT1_RL(x)         (((x) & 0xf) << 28)     /* NAK Count Reload */
 226 #define QH_ENDPT1_C(x)          (((x) & 0x1) << 27)     /* Control Endpoint Flag */
 227 #define QH_ENDPT1_MAXPKTLEN(x)  (((x) & 0x7ff) << 16)   /* Maximum Packet Length */
 228 #define QH_ENDPT1_H(x)          (((x) & 0x1) << 15)     /* Head of Reclamation List Flag */
 229 #define QH_ENDPT1_DTC(x)        (((x) & 0x1) << 14)     /* Data Toggle Control */
 230 #define QH_ENDPT1_DTC_IGNORE_QTD_TD     0x0
 231 #define QH_ENDPT1_DTC_DT_FROM_QTD       0x1
 232 #define QH_ENDPT1_EPS(x)        (((x) & 0x3) << 12)     /* Endpoint Speed */
 233 #define QH_ENDPT1_EPS_FS                0x0
 234 #define QH_ENDPT1_EPS_LS                0x1
 235 #define QH_ENDPT1_EPS_HS                0x2
 236 #define QH_ENDPT1_ENDPT(x)      (((x) & 0xf) << 8)      /* Endpoint Number */
 237 #define QH_ENDPT1_I(x)          (((x) & 0x1) << 7)      /* Inactivate on Next Transaction */
 238 #define QH_ENDPT1_DEVADDR(x)    (((x) & 0x7f) << 0)     /* Device Address */
 239         uint32_t qh_endpt2;
 240 #define QH_ENDPT2_MULT(x)       (((x) & 0x3) << 30)     /* High-Bandwidth Pipe Multiplier */
 241 #define QH_ENDPT2_PORTNUM(x)    (((x) & 0x7f) << 23)    /* Port Number */
 242 #define QH_ENDPT2_HUBADDR(x)    (((x) & 0x7f) << 16)    /* Hub Address */
 243 #define QH_ENDPT2_UFCMASK(x)    (((x) & 0xff) << 8)     /* Split Completion Mask */
 244 #define QH_ENDPT2_UFSMASK(x)    (((x) & 0xff) << 0)     /* Interrupt Schedule Mask */
 245         uint32_t qh_curtd;
 246         struct qTD qh_overlay;
 247         /*
 248          * Add dummy fill value to make the size of this struct
 249          * aligned to 32 bytes
 250          */
 251         union {
 252                 uint32_t fill[4];
 253                 void *buffer;
 254         };
 255 };
 256
 257 struct ehci_ctrl {
 258         struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
 259         struct ehci_hcor *hcor;
 260         int rootdev;
 261         uint16_t portreset;
 262         struct QH qh_list __aligned(USB_DMA_MINALIGN);
 263         struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
 264         uint32_t *periodic_list;
 265         int ntds;
 266 };
 267
 268 /* Low level init functions */
 269 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
 270 int ehci_hcd_stop(int index);
 271
 272 #endif /* USB_EHCI_H */