drivers/usb/host/ehci.h

   1 /*-
   2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   3  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   4  * All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef USB_EHCI_H
  23 #define USB_EHCI_H
  24
  25 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
  26 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      2
  27 #endif
  28
  29 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
  30 #define DeviceRequest \
  31         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  32
  33 #define DeviceOutRequest \
  34         ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  35
  36 #define InterfaceRequest \
  37         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  38
  39 #define EndpointRequest \
  40         ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  41
  42 #define EndpointOutRequest \
  43         ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  44
  45 /*
  46  * Register Space.
  47  */
  48 struct ehci_hccr {
  49         uint32_t cr_capbase;
  50 #define HC_LENGTH(p)            (((p) >> 0) & 0x00ff)
  51 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  52         uint32_t cr_hcsparams;
  53 #define HCS_PPC(p)              ((p) & (1 << 4))
  54 #define HCS_INDICATOR(p)        ((p) & (1 << 16)) /* Port indicators */
  55 #define HCS_N_PORTS(p)          (((p) >> 0) & 0xf)
  56         uint32_t cr_hccparams;
  57         uint8_t cr_hcsp_portrt[8];
  58 } __attribute__ ((packed, aligned(4)));
  59
  60 struct ehci_hcor {
  61         uint32_t or_usbcmd;
  62 #define CMD_PARK        (1 << 11)               /* enable "park" */
  63 #define CMD_PARK_CNT(c) (((c) >> 8) & 3)        /* how many transfers to park */
  64 #define CMD_ASE         (1 << 5)                /* async schedule enable */
  65 #define CMD_LRESET      (1 << 7)                /* partial reset */
  66 #define CMD_IAAD        (1 << 5)                /* "doorbell" interrupt */
  67 #define CMD_PSE         (1 << 4)                /* periodic schedule enable */
  68 #define CMD_RESET       (1 << 1)                /* reset HC not bus */
  69 #define CMD_RUN         (1 << 0)                /* start/stop HC */
  70         uint32_t or_usbsts;
  71 #define STS_ASS         (1 << 15)
  72 #define STS_PSS         (1 << 14)
  73 #define STS_HALT        (1 << 12)
  74         uint32_t or_usbintr;
  75 #define INTR_UE         (1 << 0)                /* USB interrupt enable */
  76 #define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
  77 #define INTR_PCE        (1 << 2)                /* Port change detect enable */
  78 #define INTR_SEE        (1 << 4)                /* system error enable */
  79 #define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
  80         uint32_t or_frindex;
  81         uint32_t or_ctrldssegment;
  82         uint32_t or_periodiclistbase;
  83         uint32_t or_asynclistaddr;
  84         uint32_t _reserved_0_;
  85         uint32_t or_burstsize;
  86         uint32_t or_txfilltuning;
  87 #define TXFIFO_THRESH_MASK              (0x3f << 16)
  88 #define TXFIFO_THRESH(p)                ((p & 0x3f) << 16)
  89         uint32_t _reserved_1_[6];
  90         uint32_t or_configflag;
  91 #define FLAG_CF         (1 << 0)        /* true:  we'll support "high speed" */
  92         uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
  93 #define PORTSC_PSPD(x)          (((x) >> 26) & 0x3)
  94 #define PORTSC_PSPD_FS                  0x0
  95 #define PORTSC_PSPD_LS                  0x1
  96 #define PORTSC_PSPD_HS                  0x2
  97         uint32_t or_systune;
  98 } __attribute__ ((packed, aligned(4)));
  99
 100 #define USBMODE         0x68            /* USB Device mode */
 101 #define USBMODE_SDIS    (1 << 3)        /* Stream disable */
 102 #define USBMODE_BE      (1 << 2)        /* BE/LE endiannes select */
 103 #define USBMODE_CM_HC   (3 << 0)        /* host controller mode */
 104 #define USBMODE_CM_IDLE (0 << 0)        /* idle state */
 105
 106 /* Interface descriptor */
 107 struct usb_linux_interface_descriptor {
 108         unsigned char   bLength;
 109         unsigned char   bDescriptorType;
 110         unsigned char   bInterfaceNumber;
 111         unsigned char   bAlternateSetting;
 112         unsigned char   bNumEndpoints;
 113         unsigned char   bInterfaceClass;
 114         unsigned char   bInterfaceSubClass;
 115         unsigned char   bInterfaceProtocol;
 116         unsigned char   iInterface;
 117 } __attribute__ ((packed));
 118
 119 /* Configuration descriptor information.. */
 120 struct usb_linux_config_descriptor {
 121         unsigned char   bLength;
 122         unsigned char   bDescriptorType;
 123         unsigned short  wTotalLength;
 124         unsigned char   bNumInterfaces;
 125         unsigned char   bConfigurationValue;
 126         unsigned char   iConfiguration;
 127         unsigned char   bmAttributes;
 128         unsigned char   MaxPower;
 129 } __attribute__ ((packed));
 130
 131 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
 132 #define ehci_readl(x)           (*((volatile u32 *)(x)))
 133 #define ehci_writel(a, b)       (*((volatile u32 *)(a)) = ((volatile u32)b))
 134 #else
 135 #define ehci_readl(x)           cpu_to_le32((*((volatile u32 *)(x))))
 136 #define ehci_writel(a, b)       (*((volatile u32 *)(a)) = \
 137                                         cpu_to_le32(((volatile u32)b)))
 138 #endif
 139
 140 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
 141 #define hc32_to_cpu(x)          be32_to_cpu((x))
 142 #define cpu_to_hc32(x)          cpu_to_be32((x))
 143 #else
 144 #define hc32_to_cpu(x)          le32_to_cpu((x))
 145 #define cpu_to_hc32(x)          cpu_to_le32((x))
 146 #endif
 147
 148 #define EHCI_PS_WKOC_E          (1 << 22)       /* RW wake on over current */
 149 #define EHCI_PS_WKDSCNNT_E      (1 << 21)       /* RW wake on disconnect */
 150 #define EHCI_PS_WKCNNT_E        (1 << 20)       /* RW wake on connect */
 151 #define EHCI_PS_PO              (1 << 13)       /* RW port owner */
 152 #define EHCI_PS_PP              (1 << 12)       /* RW,RO port power */
 153 #define EHCI_PS_LS              (3 << 10)       /* RO line status */
 154 #define EHCI_PS_PR              (1 << 8)        /* RW port reset */
 155 #define EHCI_PS_SUSP            (1 << 7)        /* RW suspend */
 156 #define EHCI_PS_FPR             (1 << 6)        /* RW force port resume */
 157 #define EHCI_PS_OCC             (1 << 5)        /* RWC over current change */
 158 #define EHCI_PS_OCA             (1 << 4)        /* RO over current active */
 159 #define EHCI_PS_PEC             (1 << 3)        /* RWC port enable change */
 160 #define EHCI_PS_PE              (1 << 2)        /* RW port enable */
 161 #define EHCI_PS_CSC             (1 << 1)        /* RWC connect status change */
 162 #define EHCI_PS_CS              (1 << 0)        /* RO connect status */
 163 #define EHCI_PS_CLEAR           (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
 164
 165 #define EHCI_PS_IS_LOWSPEED(x)  (((x) & EHCI_PS_LS) == (1 << 10))
 166
 167 /*
 168  * Schedule Interface Space.
 169  *
 170  * IMPORTANT: Software must ensure that no interface data structure
 171  * reachable by the EHCI host controller spans a 4K page boundary!
 172  *
 173  * Periodic transfers (i.e. isochronous and interrupt transfers) are
 174  * not supported.
 175  */
 176
 177 /* Queue Element Transfer Descriptor (qTD). */
 178 struct qTD {
 179         /* this part defined by EHCI spec */
 180         uint32_t qt_next;                       /* see EHCI 3.5.1 */
 181 #define QT_NEXT_TERMINATE       1
 182         uint32_t qt_altnext;                    /* see EHCI 3.5.2 */
 183         uint32_t qt_token;                      /* see EHCI 3.5.3 */
 184 #define QT_TOKEN_DT(x)          (((x) & 0x1) << 31)     /* Data Toggle */
 185 #define QT_TOKEN_GET_DT(x)              (((x) >> 31) & 0x1)
 186 #define QT_TOKEN_TOTALBYTES(x)  (((x) & 0x7fff) << 16)  /* Total Bytes to Transfer */
 187 #define QT_TOKEN_GET_TOTALBYTES(x)      (((x) >> 16) & 0x7fff)
 188 #define QT_TOKEN_IOC(x)         (((x) & 0x1) << 15)     /* Interrupt On Complete */
 189 #define QT_TOKEN_CPAGE(x)       (((x) & 0x7) << 12)     /* Current Page */
 190 #define QT_TOKEN_CERR(x)        (((x) & 0x3) << 10)     /* Error Counter */
 191 #define QT_TOKEN_PID(x)         (((x) & 0x3) << 8)      /* PID Code */
 192 #define QT_TOKEN_PID_OUT                0x0
 193 #define QT_TOKEN_PID_IN                 0x1
 194 #define QT_TOKEN_PID_SETUP              0x2
 195 #define QT_TOKEN_STATUS(x)      (((x) & 0xff) << 0)     /* Status */
 196 #define QT_TOKEN_GET_STATUS(x)          (((x) >> 0) & 0xff)
 197 #define QT_TOKEN_STATUS_ACTIVE          0x80
 198 #define QT_TOKEN_STATUS_HALTED          0x40
 199 #define QT_TOKEN_STATUS_DATBUFERR       0x20
 200 #define QT_TOKEN_STATUS_BABBLEDET       0x10
 201 #define QT_TOKEN_STATUS_XACTERR         0x08
 202 #define QT_TOKEN_STATUS_MISSEDUFRAME    0x04
 203 #define QT_TOKEN_STATUS_SPLITXSTATE     0x02
 204 #define QT_TOKEN_STATUS_PERR            0x01
 205 #define QT_BUFFER_CNT           5
 206         uint32_t qt_buffer[QT_BUFFER_CNT];      /* see EHCI 3.5.4 */
 207         uint32_t qt_buffer_hi[QT_BUFFER_CNT];   /* Appendix B */
 208         /* pad struct for 32 byte alignment */
 209         uint32_t unused[3];
 210 };
 211
 212 #define EHCI_PAGE_SIZE          4096
 213
 214 /* Queue Head (QH). */
 215 struct QH {
 216         uint32_t qh_link;
 217 #define QH_LINK_TERMINATE       1
 218 #define QH_LINK_TYPE_ITD        0
 219 #define QH_LINK_TYPE_QH         2
 220 #define QH_LINK_TYPE_SITD       4
 221 #define QH_LINK_TYPE_FSTN       6
 222         uint32_t qh_endpt1;
 223 #define QH_ENDPT1_RL(x)         (((x) & 0xf) << 28)     /* NAK Count Reload */
 224 #define QH_ENDPT1_C(x)          (((x) & 0x1) << 27)     /* Control Endpoint Flag */
 225 #define QH_ENDPT1_MAXPKTLEN(x)  (((x) & 0x7ff) << 16)   /* Maximum Packet Length */
 226 #define QH_ENDPT1_H(x)          (((x) & 0x1) << 15)     /* Head of Reclamation List Flag */
 227 #define QH_ENDPT1_DTC(x)        (((x) & 0x1) << 14)     /* Data Toggle Control */
 228 #define QH_ENDPT1_DTC_IGNORE_QTD_TD     0x0
 229 #define QH_ENDPT1_DTC_DT_FROM_QTD       0x1
 230 #define QH_ENDPT1_EPS(x)        (((x) & 0x3) << 12)     /* Endpoint Speed */
 231 #define QH_ENDPT1_EPS_FS                0x0
 232 #define QH_ENDPT1_EPS_LS                0x1
 233 #define QH_ENDPT1_EPS_HS                0x2
 234 #define QH_ENDPT1_ENDPT(x)      (((x) & 0xf) << 8)      /* Endpoint Number */
 235 #define QH_ENDPT1_I(x)          (((x) & 0x1) << 7)      /* Inactivate on Next Transaction */
 236 #define QH_ENDPT1_DEVADDR(x)    (((x) & 0x7f) << 0)     /* Device Address */
 237         uint32_t qh_endpt2;
 238 #define QH_ENDPT2_MULT(x)       (((x) & 0x3) << 30)     /* High-Bandwidth Pipe Multiplier */
 239 #define QH_ENDPT2_PORTNUM(x)    (((x) & 0x7f) << 23)    /* Port Number */
 240 #define QH_ENDPT2_HUBADDR(x)    (((x) & 0x7f) << 16)    /* Hub Address */
 241 #define QH_ENDPT2_UFCMASK(x)    (((x) & 0xff) << 8)     /* Split Completion Mask */
 242 #define QH_ENDPT2_UFSMASK(x)    (((x) & 0xff) << 0)     /* Interrupt Schedule Mask */
 243         uint32_t qh_curtd;
 244         struct qTD qh_overlay;
 245         /*
 246          * Add dummy fill value to make the size of this struct
 247          * aligned to 32 bytes
 248          */
 249         union {
 250                 uint32_t fill[4];
 251                 void *buffer;
 252         };
 253 };
 254
 255 /* Low level init functions */
 256 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
 257 int ehci_hcd_stop(int index);
 258
 259 #endif /* USB_EHCI_H */