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powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x
[thirdparty/u-boot.git] / drivers / usb / host / ohci-hcd.c
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
3 *
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
6 *
7 * (C) Copyright 2007
8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
9 *
10 * (C) Copyright 2003
11 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
12 *
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
15 * (C) Copyright 2000-2002 David Brownell
16 *
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * ebenard@eukrea.com - based on s3c24x0's driver
19 *
20 * SPDX-License-Identifier: GPL-2.0+
21 */
22 /*
23 * IMPORTANT NOTES
24 * 1 - Read doc/README.generic_usb_ohci
25 * 2 - this driver is intended for use with USB Mass Storage Devices
26 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
27 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
28 * to activate workaround for bug #41 or this driver will NOT work!
29 */
30
31 #include <common.h>
32 #include <asm/byteorder.h>
33 #include <dm.h>
34 #include <errno.h>
35
36 #if defined(CONFIG_PCI_OHCI)
37 # include <pci.h>
38 #if !defined(CONFIG_PCI_OHCI_DEVNO)
39 #define CONFIG_PCI_OHCI_DEVNO 0
40 #endif
41 #endif
42
43 #include <malloc.h>
44 #include <memalign.h>
45 #include <usb.h>
46
47 #include "ohci.h"
48
49 #ifdef CONFIG_AT91RM9200
50 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
51 #endif
52
53 #if defined(CONFIG_CPU_ARM920T) || \
54 defined(CONFIG_440EP) || \
55 defined(CONFIG_PCI_OHCI) || \
56 defined(CONFIG_SYS_OHCI_USE_NPS)
57 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
58 #endif
59
60 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
61 #undef DEBUG
62 #undef SHOW_INFO
63 #undef OHCI_FILL_TRACE
64
65 /* For initializing controller (mask in an HCFS mode too) */
66 #define OHCI_CONTROL_INIT \
67 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
68
69 #ifdef CONFIG_PCI_OHCI
70 static struct pci_device_id ohci_pci_ids[] = {
71 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
72 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
73 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
74 /* Please add supported PCI OHCI controller ids here */
75 {0, 0}
76 };
77 #endif
78
79 #ifdef CONFIG_PCI_EHCI_DEVNO
80 static struct pci_device_id ehci_pci_ids[] = {
81 {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
82 /* Please add supported PCI EHCI controller ids here */
83 {0, 0}
84 };
85 #endif
86
87 #ifdef DEBUG
88 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
89 #else
90 #define dbg(format, arg...) do {} while (0)
91 #endif /* DEBUG */
92 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
93 #ifdef SHOW_INFO
94 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
95 #else
96 #define info(format, arg...) do {} while (0)
97 #endif
98
99 #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
100 # define m16_swap(x) cpu_to_be16(x)
101 # define m32_swap(x) cpu_to_be32(x)
102 #else
103 # define m16_swap(x) cpu_to_le16(x)
104 # define m32_swap(x) cpu_to_le32(x)
105 #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
106
107 /* We really should do proper cache flushing everywhere */
108 #define flush_dcache_buffer(addr, size) \
109 flush_dcache_range((unsigned long)(addr), \
110 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
111 #define invalidate_dcache_buffer(addr, size) \
112 invalidate_dcache_range((unsigned long)(addr), \
113 ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
114
115 /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
116 #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
117 #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
118 #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
119 #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
120 #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
121 #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
122 #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
123 #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
124
125 #ifdef CONFIG_DM_USB
126 /*
127 * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep
128 * them around when building for older boards not yet converted to the dm
129 * just in case (to avoid regressions), for dm this turns them into nops.
130 */
131 #define ohci_mdelay(x)
132 #else
133 #define ohci_mdelay(x) mdelay(x)
134 #endif
135
136 #ifndef CONFIG_DM_USB
137 /* global ohci_t */
138 static ohci_t gohci;
139 /* this must be aligned to a 256 byte boundary */
140 struct ohci_hcca ghcca[1];
141 #endif
142
143 /* mapping of the OHCI CC status to error codes */
144 static int cc_to_error[16] = {
145 /* No Error */ 0,
146 /* CRC Error */ USB_ST_CRC_ERR,
147 /* Bit Stuff */ USB_ST_BIT_ERR,
148 /* Data Togg */ USB_ST_CRC_ERR,
149 /* Stall */ USB_ST_STALLED,
150 /* DevNotResp */ -1,
151 /* PIDCheck */ USB_ST_BIT_ERR,
152 /* UnExpPID */ USB_ST_BIT_ERR,
153 /* DataOver */ USB_ST_BUF_ERR,
154 /* DataUnder */ USB_ST_BUF_ERR,
155 /* reservd */ -1,
156 /* reservd */ -1,
157 /* BufferOver */ USB_ST_BUF_ERR,
158 /* BuffUnder */ USB_ST_BUF_ERR,
159 /* Not Access */ -1,
160 /* Not Access */ -1
161 };
162
163 static const char *cc_to_string[16] = {
164 "No Error",
165 "CRC: Last data packet from endpoint contained a CRC error.",
166 "BITSTUFFING: Last data packet from endpoint contained a bit " \
167 "stuffing violation",
168 "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
169 "that did not match the expected value.",
170 "STALL: TD was moved to the Done Queue because the endpoint returned" \
171 " a STALL PID",
172 "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
173 "not provide a handshake (OUT)",
174 "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
175 "(IN) or handshake (OUT)",
176 "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
177 "value is not defined.",
178 "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
179 "either the size of the maximum data packet allowed\n" \
180 "from the endpoint (found in MaximumPacketSize field\n" \
181 "of ED) or the remaining buffer size.",
182 "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
183 "and that amount was not sufficient to fill the\n" \
184 "specified buffer",
185 "reserved1",
186 "reserved2",
187 "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
188 "than it could be written to system memory",
189 "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
190 "system memory fast enough to keep up with data USB " \
191 "data rate.",
192 "NOT ACCESSED: This code is set by software before the TD is placed" \
193 "on a list to be processed by the HC.(1)",
194 "NOT ACCESSED: This code is set by software before the TD is placed" \
195 "on a list to be processed by the HC.(2)",
196 };
197
198 static inline u32 roothub_a(struct ohci *hc)
199 { return ohci_readl(&hc->regs->roothub.a); }
200 static inline u32 roothub_b(struct ohci *hc)
201 { return ohci_readl(&hc->regs->roothub.b); }
202 static inline u32 roothub_status(struct ohci *hc)
203 { return ohci_readl(&hc->regs->roothub.status); }
204 static inline u32 roothub_portstatus(struct ohci *hc, int i)
205 { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
206
207 /* forward declaration */
208 static int hc_interrupt(ohci_t *ohci);
209 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
210 unsigned long pipe, void *buffer, int transfer_len,
211 struct devrequest *setup, urb_priv_t *urb,
212 int interval);
213 static int ep_link(ohci_t * ohci, ed_t * ed);
214 static int ep_unlink(ohci_t * ohci, ed_t * ed);
215 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
216 unsigned long pipe, int interval, int load);
217
218 /*-------------------------------------------------------------------------*/
219
220 /* TDs ... */
221 static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
222 {
223 int i;
224 struct td *td;
225
226 td = NULL;
227 for (i = 0; i < NUM_TD; i++)
228 {
229 if (ohci_dev->tds[i].usb_dev == NULL)
230 {
231 td = &ohci_dev->tds[i];
232 td->usb_dev = usb_dev;
233 break;
234 }
235 }
236
237 return td;
238 }
239
240 static inline void ed_free(struct ed *ed)
241 {
242 ed->usb_dev = NULL;
243 }
244
245 /*-------------------------------------------------------------------------*
246 * URB support functions
247 *-------------------------------------------------------------------------*/
248
249 /* free HCD-private data associated with this URB */
250
251 static void urb_free_priv(urb_priv_t *urb)
252 {
253 int i;
254 int last;
255 struct td *td;
256
257 last = urb->length - 1;
258 if (last >= 0) {
259 for (i = 0; i <= last; i++) {
260 td = urb->td[i];
261 if (td) {
262 td->usb_dev = NULL;
263 urb->td[i] = NULL;
264 }
265 }
266 }
267 free(urb);
268 }
269
270 /*-------------------------------------------------------------------------*/
271
272 #ifdef DEBUG
273 static int sohci_get_current_frame_number(ohci_t *ohci);
274
275 /* debug| print the main components of an URB
276 * small: 0) header + data packets 1) just header */
277
278 static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
279 unsigned long pipe, void *buffer, int transfer_len,
280 struct devrequest *setup, char *str, int small)
281 {
282 dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
283 str,
284 sohci_get_current_frame_number(ohci),
285 usb_pipedevice(pipe),
286 usb_pipeendpoint(pipe),
287 usb_pipeout(pipe)? 'O': 'I',
288 usb_pipetype(pipe) < 2 ? \
289 (usb_pipeint(pipe)? "INTR": "ISOC"): \
290 (usb_pipecontrol(pipe)? "CTRL": "BULK"),
291 (purb ? purb->actual_length : 0),
292 transfer_len, dev->status);
293 #ifdef OHCI_VERBOSE_DEBUG
294 if (!small) {
295 int i, len;
296
297 if (usb_pipecontrol(pipe)) {
298 printf(__FILE__ ": cmd(8):");
299 for (i = 0; i < 8 ; i++)
300 printf(" %02x", ((__u8 *) setup) [i]);
301 printf("\n");
302 }
303 if (transfer_len > 0 && buffer) {
304 printf(__FILE__ ": data(%d/%d):",
305 (purb ? purb->actual_length : 0),
306 transfer_len);
307 len = usb_pipeout(pipe)? transfer_len:
308 (purb ? purb->actual_length : 0);
309 for (i = 0; i < 16 && i < len; i++)
310 printf(" %02x", ((__u8 *) buffer) [i]);
311 printf("%s\n", i < len? "...": "");
312 }
313 }
314 #endif
315 }
316
317 /* just for debugging; prints non-empty branches of the int ed tree
318 * inclusive iso eds */
319 void ep_print_int_eds(ohci_t *ohci, char *str)
320 {
321 int i, j;
322 __u32 *ed_p;
323 for (i = 0; i < 32; i++) {
324 j = 5;
325 ed_p = &(ohci->hcca->int_table [i]);
326 if (*ed_p == 0)
327 continue;
328 invalidate_dcache_ed(ed_p);
329 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
330 while (*ed_p != 0 && j--) {
331 ed_t *ed = (ed_t *)m32_swap(ed_p);
332 invalidate_dcache_ed(ed);
333 printf(" ed: %4x;", ed->hwINFO);
334 ed_p = &ed->hwNextED;
335 }
336 printf("\n");
337 }
338 }
339
340 static void ohci_dump_intr_mask(char *label, __u32 mask)
341 {
342 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
343 label,
344 mask,
345 (mask & OHCI_INTR_MIE) ? " MIE" : "",
346 (mask & OHCI_INTR_OC) ? " OC" : "",
347 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
348 (mask & OHCI_INTR_FNO) ? " FNO" : "",
349 (mask & OHCI_INTR_UE) ? " UE" : "",
350 (mask & OHCI_INTR_RD) ? " RD" : "",
351 (mask & OHCI_INTR_SF) ? " SF" : "",
352 (mask & OHCI_INTR_WDH) ? " WDH" : "",
353 (mask & OHCI_INTR_SO) ? " SO" : ""
354 );
355 }
356
357 static void maybe_print_eds(char *label, __u32 value)
358 {
359 ed_t *edp = (ed_t *)value;
360
361 if (value) {
362 dbg("%s %08x", label, value);
363 invalidate_dcache_ed(edp);
364 dbg("%08x", edp->hwINFO);
365 dbg("%08x", edp->hwTailP);
366 dbg("%08x", edp->hwHeadP);
367 dbg("%08x", edp->hwNextED);
368 }
369 }
370
371 static char *hcfs2string(int state)
372 {
373 switch (state) {
374 case OHCI_USB_RESET: return "reset";
375 case OHCI_USB_RESUME: return "resume";
376 case OHCI_USB_OPER: return "operational";
377 case OHCI_USB_SUSPEND: return "suspend";
378 }
379 return "?";
380 }
381
382 /* dump control and status registers */
383 static void ohci_dump_status(ohci_t *controller)
384 {
385 struct ohci_regs *regs = controller->regs;
386 __u32 temp;
387
388 temp = ohci_readl(&regs->revision) & 0xff;
389 if (temp != 0x10)
390 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
391
392 temp = ohci_readl(&regs->control);
393 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
394 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
395 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
396 (temp & OHCI_CTRL_IR) ? " IR" : "",
397 hcfs2string(temp & OHCI_CTRL_HCFS),
398 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
399 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
400 (temp & OHCI_CTRL_IE) ? " IE" : "",
401 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
402 temp & OHCI_CTRL_CBSR
403 );
404
405 temp = ohci_readl(&regs->cmdstatus);
406 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
407 (temp & OHCI_SOC) >> 16,
408 (temp & OHCI_OCR) ? " OCR" : "",
409 (temp & OHCI_BLF) ? " BLF" : "",
410 (temp & OHCI_CLF) ? " CLF" : "",
411 (temp & OHCI_HCR) ? " HCR" : ""
412 );
413
414 ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
415 ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
416
417 maybe_print_eds("ed_periodcurrent",
418 ohci_readl(&regs->ed_periodcurrent));
419
420 maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
421 maybe_print_eds("ed_controlcurrent",
422 ohci_readl(&regs->ed_controlcurrent));
423
424 maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
425 maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
426
427 maybe_print_eds("donehead", ohci_readl(&regs->donehead));
428 }
429
430 static void ohci_dump_roothub(ohci_t *controller, int verbose)
431 {
432 __u32 temp, ndp, i;
433
434 temp = roothub_a(controller);
435 ndp = (temp & RH_A_NDP);
436 #ifdef CONFIG_AT91C_PQFP_UHPBUG
437 ndp = (ndp == 2) ? 1:0;
438 #endif
439 if (verbose) {
440 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
441 ((temp & RH_A_POTPGT) >> 24) & 0xff,
442 (temp & RH_A_NOCP) ? " NOCP" : "",
443 (temp & RH_A_OCPM) ? " OCPM" : "",
444 (temp & RH_A_DT) ? " DT" : "",
445 (temp & RH_A_NPS) ? " NPS" : "",
446 (temp & RH_A_PSM) ? " PSM" : "",
447 ndp
448 );
449 temp = roothub_b(controller);
450 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
451 temp,
452 (temp & RH_B_PPCM) >> 16,
453 (temp & RH_B_DR)
454 );
455 temp = roothub_status(controller);
456 dbg("roothub.status: %08x%s%s%s%s%s%s",
457 temp,
458 (temp & RH_HS_CRWE) ? " CRWE" : "",
459 (temp & RH_HS_OCIC) ? " OCIC" : "",
460 (temp & RH_HS_LPSC) ? " LPSC" : "",
461 (temp & RH_HS_DRWE) ? " DRWE" : "",
462 (temp & RH_HS_OCI) ? " OCI" : "",
463 (temp & RH_HS_LPS) ? " LPS" : ""
464 );
465 }
466
467 for (i = 0; i < ndp; i++) {
468 temp = roothub_portstatus(controller, i);
469 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
470 i,
471 temp,
472 (temp & RH_PS_PRSC) ? " PRSC" : "",
473 (temp & RH_PS_OCIC) ? " OCIC" : "",
474 (temp & RH_PS_PSSC) ? " PSSC" : "",
475 (temp & RH_PS_PESC) ? " PESC" : "",
476 (temp & RH_PS_CSC) ? " CSC" : "",
477
478 (temp & RH_PS_LSDA) ? " LSDA" : "",
479 (temp & RH_PS_PPS) ? " PPS" : "",
480 (temp & RH_PS_PRS) ? " PRS" : "",
481 (temp & RH_PS_POCI) ? " POCI" : "",
482 (temp & RH_PS_PSS) ? " PSS" : "",
483
484 (temp & RH_PS_PES) ? " PES" : "",
485 (temp & RH_PS_CCS) ? " CCS" : ""
486 );
487 }
488 }
489
490 static void ohci_dump(ohci_t *controller, int verbose)
491 {
492 dbg("OHCI controller usb-%s state", controller->slot_name);
493
494 /* dumps some of the state we know about */
495 ohci_dump_status(controller);
496 if (verbose)
497 ep_print_int_eds(controller, "hcca");
498 invalidate_dcache_hcca(controller->hcca);
499 dbg("hcca frame #%04x", controller->hcca->frame_no);
500 ohci_dump_roothub(controller, 1);
501 }
502 #endif /* DEBUG */
503
504 /*-------------------------------------------------------------------------*
505 * Interface functions (URB)
506 *-------------------------------------------------------------------------*/
507
508 /* get a transfer request */
509
510 int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
511 struct devrequest *setup)
512 {
513 ed_t *ed;
514 urb_priv_t *purb_priv = urb;
515 int i, size = 0;
516 struct usb_device *dev = urb->dev;
517 unsigned long pipe = urb->pipe;
518 void *buffer = urb->transfer_buffer;
519 int transfer_len = urb->transfer_buffer_length;
520 int interval = urb->interval;
521
522 /* when controller's hung, permit only roothub cleanup attempts
523 * such as powering down ports */
524 if (ohci->disabled) {
525 err("sohci_submit_job: EPIPE");
526 return -1;
527 }
528
529 /* we're about to begin a new transaction here so mark the
530 * URB unfinished */
531 urb->finished = 0;
532
533 /* every endpoint has a ed, locate and fill it */
534 ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
535 if (!ed) {
536 err("sohci_submit_job: ENOMEM");
537 return -1;
538 }
539
540 /* for the private part of the URB we need the number of TDs (size) */
541 switch (usb_pipetype(pipe)) {
542 case PIPE_BULK: /* one TD for every 4096 Byte */
543 size = (transfer_len - 1) / 4096 + 1;
544 break;
545 case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
546 size = (transfer_len == 0)? 2:
547 (transfer_len - 1) / 4096 + 3;
548 break;
549 case PIPE_INTERRUPT: /* 1 TD */
550 size = 1;
551 break;
552 }
553
554 ed->purb = urb;
555
556 if (size >= (N_URB_TD - 1)) {
557 err("need %d TDs, only have %d", size, N_URB_TD);
558 return -1;
559 }
560 purb_priv->pipe = pipe;
561
562 /* fill the private part of the URB */
563 purb_priv->length = size;
564 purb_priv->ed = ed;
565 purb_priv->actual_length = 0;
566
567 /* allocate the TDs */
568 /* note that td[0] was allocated in ep_add_ed */
569 for (i = 0; i < size; i++) {
570 purb_priv->td[i] = td_alloc(ohci_dev, dev);
571 if (!purb_priv->td[i]) {
572 purb_priv->length = i;
573 urb_free_priv(purb_priv);
574 err("sohci_submit_job: ENOMEM");
575 return -1;
576 }
577 }
578
579 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
580 urb_free_priv(purb_priv);
581 err("sohci_submit_job: EINVAL");
582 return -1;
583 }
584
585 /* link the ed into a chain if is not already */
586 if (ed->state != ED_OPER)
587 ep_link(ohci, ed);
588
589 /* fill the TDs and link it to the ed */
590 td_submit_job(ohci, dev, pipe, buffer, transfer_len,
591 setup, purb_priv, interval);
592
593 return 0;
594 }
595
596 /*-------------------------------------------------------------------------*/
597
598 #ifdef DEBUG
599 /* tell us the current USB frame number */
600 static int sohci_get_current_frame_number(ohci_t *ohci)
601 {
602 invalidate_dcache_hcca(ohci->hcca);
603 return m16_swap(ohci->hcca->frame_no);
604 }
605 #endif
606
607 /*-------------------------------------------------------------------------*
608 * ED handling functions
609 *-------------------------------------------------------------------------*/
610
611 /* search for the right branch to insert an interrupt ed into the int tree
612 * do some load ballancing;
613 * returns the branch and
614 * sets the interval to interval = 2^integer (ld (interval)) */
615
616 static int ep_int_ballance(ohci_t *ohci, int interval, int load)
617 {
618 int i, branch = 0;
619
620 /* search for the least loaded interrupt endpoint
621 * branch of all 32 branches
622 */
623 for (i = 0; i < 32; i++)
624 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
625 branch = i;
626
627 branch = branch % interval;
628 for (i = branch; i < 32; i += interval)
629 ohci->ohci_int_load [i] += load;
630
631 return branch;
632 }
633
634 /*-------------------------------------------------------------------------*/
635
636 /* 2^int( ld (inter)) */
637
638 static int ep_2_n_interval(int inter)
639 {
640 int i;
641 for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
642 return 1 << i;
643 }
644
645 /*-------------------------------------------------------------------------*/
646
647 /* the int tree is a binary tree
648 * in order to process it sequentially the indexes of the branches have to
649 * be mapped the mapping reverses the bits of a word of num_bits length */
650 static int ep_rev(int num_bits, int word)
651 {
652 int i, wout = 0;
653
654 for (i = 0; i < num_bits; i++)
655 wout |= (((word >> i) & 1) << (num_bits - i - 1));
656 return wout;
657 }
658
659 /*-------------------------------------------------------------------------*
660 * ED handling functions
661 *-------------------------------------------------------------------------*/
662
663 /* link an ed into one of the HC chains */
664
665 static int ep_link(ohci_t *ohci, ed_t *edi)
666 {
667 volatile ed_t *ed = edi;
668 int int_branch;
669 int i;
670 int inter;
671 int interval;
672 int load;
673 __u32 *ed_p;
674
675 ed->state = ED_OPER;
676 ed->int_interval = 0;
677
678 switch (ed->type) {
679 case PIPE_CONTROL:
680 ed->hwNextED = 0;
681 flush_dcache_ed(ed);
682 if (ohci->ed_controltail == NULL)
683 ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
684 else
685 ohci->ed_controltail->hwNextED =
686 m32_swap((unsigned long)ed);
687
688 ed->ed_prev = ohci->ed_controltail;
689 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
690 !ohci->ed_rm_list[1] && !ohci->sleeping) {
691 ohci->hc_control |= OHCI_CTRL_CLE;
692 ohci_writel(ohci->hc_control, &ohci->regs->control);
693 }
694 ohci->ed_controltail = edi;
695 break;
696
697 case PIPE_BULK:
698 ed->hwNextED = 0;
699 flush_dcache_ed(ed);
700 if (ohci->ed_bulktail == NULL)
701 ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
702 else
703 ohci->ed_bulktail->hwNextED =
704 m32_swap((unsigned long)ed);
705
706 ed->ed_prev = ohci->ed_bulktail;
707 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
708 !ohci->ed_rm_list[1] && !ohci->sleeping) {
709 ohci->hc_control |= OHCI_CTRL_BLE;
710 ohci_writel(ohci->hc_control, &ohci->regs->control);
711 }
712 ohci->ed_bulktail = edi;
713 break;
714
715 case PIPE_INTERRUPT:
716 load = ed->int_load;
717 interval = ep_2_n_interval(ed->int_period);
718 ed->int_interval = interval;
719 int_branch = ep_int_ballance(ohci, interval, load);
720 ed->int_branch = int_branch;
721
722 for (i = 0; i < ep_rev(6, interval); i += inter) {
723 inter = 1;
724 for (ed_p = &(ohci->hcca->int_table[\
725 ep_rev(5, i) + int_branch]);
726 (*ed_p != 0) &&
727 (((ed_t *)ed_p)->int_interval >= interval);
728 ed_p = &(((ed_t *)ed_p)->hwNextED))
729 inter = ep_rev(6,
730 ((ed_t *)ed_p)->int_interval);
731 ed->hwNextED = *ed_p;
732 flush_dcache_ed(ed);
733 *ed_p = m32_swap((unsigned long)ed);
734 flush_dcache_hcca(ohci->hcca);
735 }
736 break;
737 }
738 return 0;
739 }
740
741 /*-------------------------------------------------------------------------*/
742
743 /* scan the periodic table to find and unlink this ED */
744 static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
745 unsigned index, unsigned period)
746 {
747 __maybe_unused unsigned long aligned_ed_p;
748
749 for (; index < NUM_INTS; index += period) {
750 __u32 *ed_p = &ohci->hcca->int_table [index];
751
752 /* ED might have been unlinked through another path */
753 while (*ed_p != 0) {
754 if (((struct ed *)(uintptr_t)
755 m32_swap((unsigned long)ed_p)) == ed) {
756 *ed_p = ed->hwNextED;
757 aligned_ed_p = (unsigned long)ed_p;
758 aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
759 flush_dcache_range(aligned_ed_p,
760 aligned_ed_p + ARCH_DMA_MINALIGN);
761 break;
762 }
763 ed_p = &(((struct ed *)(uintptr_t)
764 m32_swap((unsigned long)ed_p))->hwNextED);
765 }
766 }
767 }
768
769 /* unlink an ed from one of the HC chains.
770 * just the link to the ed is unlinked.
771 * the link from the ed still points to another operational ed or 0
772 * so the HC can eventually finish the processing of the unlinked ed */
773
774 static int ep_unlink(ohci_t *ohci, ed_t *edi)
775 {
776 volatile ed_t *ed = edi;
777 int i;
778
779 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
780 flush_dcache_ed(ed);
781
782 switch (ed->type) {
783 case PIPE_CONTROL:
784 if (ed->ed_prev == NULL) {
785 if (!ed->hwNextED) {
786 ohci->hc_control &= ~OHCI_CTRL_CLE;
787 ohci_writel(ohci->hc_control,
788 &ohci->regs->control);
789 }
790 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
791 &ohci->regs->ed_controlhead);
792 } else {
793 ed->ed_prev->hwNextED = ed->hwNextED;
794 flush_dcache_ed(ed->ed_prev);
795 }
796 if (ohci->ed_controltail == ed) {
797 ohci->ed_controltail = ed->ed_prev;
798 } else {
799 ((ed_t *)(uintptr_t)m32_swap(
800 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
801 }
802 break;
803
804 case PIPE_BULK:
805 if (ed->ed_prev == NULL) {
806 if (!ed->hwNextED) {
807 ohci->hc_control &= ~OHCI_CTRL_BLE;
808 ohci_writel(ohci->hc_control,
809 &ohci->regs->control);
810 }
811 ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
812 &ohci->regs->ed_bulkhead);
813 } else {
814 ed->ed_prev->hwNextED = ed->hwNextED;
815 flush_dcache_ed(ed->ed_prev);
816 }
817 if (ohci->ed_bulktail == ed) {
818 ohci->ed_bulktail = ed->ed_prev;
819 } else {
820 ((ed_t *)(uintptr_t)m32_swap(
821 *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
822 }
823 break;
824
825 case PIPE_INTERRUPT:
826 periodic_unlink(ohci, ed, 0, 1);
827 for (i = ed->int_branch; i < 32; i += ed->int_interval)
828 ohci->ohci_int_load[i] -= ed->int_load;
829 break;
830 }
831 ed->state = ED_UNLINK;
832 return 0;
833 }
834
835 /*-------------------------------------------------------------------------*/
836
837 /* add/reinit an endpoint; this should be done once at the
838 * usb_set_configuration command, but the USB stack is a little bit
839 * stateless so we do it at every transaction if the state of the ed
840 * is ED_NEW then a dummy td is added and the state is changed to
841 * ED_UNLINK in all other cases the state is left unchanged the ed
842 * info fields are setted anyway even though most of them should not
843 * change
844 */
845 static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
846 unsigned long pipe, int interval, int load)
847 {
848 td_t *td;
849 ed_t *ed_ret;
850 volatile ed_t *ed;
851
852 ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
853 (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
854
855 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
856 err("ep_add_ed: pending delete");
857 /* pending delete request */
858 return NULL;
859 }
860
861 if (ed->state == ED_NEW) {
862 /* dummy td; end of td list for ed */
863 td = td_alloc(ohci_dev, usb_dev);
864 ed->hwTailP = m32_swap((unsigned long)td);
865 ed->hwHeadP = ed->hwTailP;
866 ed->state = ED_UNLINK;
867 ed->type = usb_pipetype(pipe);
868 ohci_dev->ed_cnt++;
869 }
870
871 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
872 | usb_pipeendpoint(pipe) << 7
873 | (usb_pipeisoc(pipe)? 0x8000: 0)
874 | (usb_pipecontrol(pipe)? 0: \
875 (usb_pipeout(pipe)? 0x800: 0x1000))
876 | (usb_dev->speed == USB_SPEED_LOW) << 13
877 | usb_maxpacket(usb_dev, pipe) << 16);
878
879 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
880 ed->int_period = interval;
881 ed->int_load = load;
882 }
883
884 flush_dcache_ed(ed);
885
886 return ed_ret;
887 }
888
889 /*-------------------------------------------------------------------------*
890 * TD handling functions
891 *-------------------------------------------------------------------------*/
892
893 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
894
895 static void td_fill(ohci_t *ohci, unsigned int info,
896 void *data, int len,
897 struct usb_device *dev, int index, urb_priv_t *urb_priv)
898 {
899 volatile td_t *td, *td_pt;
900 #ifdef OHCI_FILL_TRACE
901 int i;
902 #endif
903
904 if (index > urb_priv->length) {
905 err("index > length");
906 return;
907 }
908 /* use this td as the next dummy */
909 td_pt = urb_priv->td [index];
910 td_pt->hwNextTD = 0;
911 flush_dcache_td(td_pt);
912
913 /* fill the old dummy TD */
914 td = urb_priv->td [index] =
915 (td_t *)(uintptr_t)
916 (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
917
918 td->ed = urb_priv->ed;
919 td->next_dl_td = NULL;
920 td->index = index;
921 td->data = (uintptr_t)data;
922 #ifdef OHCI_FILL_TRACE
923 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
924 for (i = 0; i < len; i++)
925 printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
926 printf("\n");
927 }
928 #endif
929 if (!len)
930 data = 0;
931
932 td->hwINFO = m32_swap(info);
933 td->hwCBP = m32_swap((unsigned long)data);
934 if (data)
935 td->hwBE = m32_swap((unsigned long)(data + len - 1));
936 else
937 td->hwBE = 0;
938
939 td->hwNextTD = m32_swap((unsigned long)td_pt);
940 flush_dcache_td(td);
941
942 /* append to queue */
943 td->ed->hwTailP = td->hwNextTD;
944 flush_dcache_ed(td->ed);
945 }
946
947 /*-------------------------------------------------------------------------*/
948
949 /* prepare all TDs of a transfer */
950
951 static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
952 unsigned long pipe, void *buffer, int transfer_len,
953 struct devrequest *setup, urb_priv_t *urb,
954 int interval)
955 {
956 int data_len = transfer_len;
957 void *data;
958 int cnt = 0;
959 __u32 info = 0;
960 unsigned int toggle = 0;
961
962 flush_dcache_buffer(buffer, data_len);
963
964 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
965 * bits for resetting */
966 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
967 toggle = TD_T_TOGGLE;
968 } else {
969 toggle = TD_T_DATA0;
970 usb_settoggle(dev, usb_pipeendpoint(pipe),
971 usb_pipeout(pipe), 1);
972 }
973 urb->td_cnt = 0;
974 if (data_len)
975 data = buffer;
976 else
977 data = 0;
978
979 switch (usb_pipetype(pipe)) {
980 case PIPE_BULK:
981 info = usb_pipeout(pipe)?
982 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
983 while (data_len > 4096) {
984 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
985 data, 4096, dev, cnt, urb);
986 data += 4096; data_len -= 4096; cnt++;
987 }
988 info = usb_pipeout(pipe)?
989 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
990 td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
991 data_len, dev, cnt, urb);
992 cnt++;
993
994 if (!ohci->sleeping) {
995 /* start bulk list */
996 ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
997 }
998 break;
999
1000 case PIPE_CONTROL:
1001 /* Setup phase */
1002 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
1003 flush_dcache_buffer(setup, 8);
1004 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
1005
1006 /* Optional Data phase */
1007 if (data_len > 0) {
1008 info = usb_pipeout(pipe)?
1009 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
1010 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
1011 /* NOTE: mishandles transfers >8K, some >4K */
1012 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1013 }
1014
1015 /* Status phase */
1016 info = (usb_pipeout(pipe) || data_len == 0) ?
1017 TD_CC | TD_DP_IN | TD_T_DATA1:
1018 TD_CC | TD_DP_OUT | TD_T_DATA1;
1019 td_fill(ohci, info, data, 0, dev, cnt++, urb);
1020
1021 if (!ohci->sleeping) {
1022 /* start Control list */
1023 ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
1024 }
1025 break;
1026
1027 case PIPE_INTERRUPT:
1028 info = usb_pipeout(urb->pipe)?
1029 TD_CC | TD_DP_OUT | toggle:
1030 TD_CC | TD_R | TD_DP_IN | toggle;
1031 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
1032 break;
1033 }
1034 if (urb->length != cnt)
1035 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
1036 }
1037
1038 /*-------------------------------------------------------------------------*
1039 * Done List handling functions
1040 *-------------------------------------------------------------------------*/
1041
1042 /* calculate the transfer length and update the urb */
1043
1044 static void dl_transfer_length(td_t *td)
1045 {
1046 __u32 tdBE, tdCBP;
1047 urb_priv_t *lurb_priv = td->ed->purb;
1048
1049 tdBE = m32_swap(td->hwBE);
1050 tdCBP = m32_swap(td->hwCBP);
1051
1052 if (!(usb_pipecontrol(lurb_priv->pipe) &&
1053 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
1054 if (tdBE != 0) {
1055 if (td->hwCBP == 0)
1056 lurb_priv->actual_length += tdBE - td->data + 1;
1057 else
1058 lurb_priv->actual_length += tdCBP - td->data;
1059 }
1060 }
1061 }
1062
1063 /*-------------------------------------------------------------------------*/
1064 static void check_status(td_t *td_list)
1065 {
1066 urb_priv_t *lurb_priv = td_list->ed->purb;
1067 int urb_len = lurb_priv->length;
1068 __u32 *phwHeadP = &td_list->ed->hwHeadP;
1069 int cc;
1070
1071 cc = TD_CC_GET(m32_swap(td_list->hwINFO));
1072 if (cc) {
1073 err(" USB-error: %s (%x)", cc_to_string[cc], cc);
1074
1075 invalidate_dcache_ed(td_list->ed);
1076 if (*phwHeadP & m32_swap(0x1)) {
1077 if (lurb_priv &&
1078 ((td_list->index + 1) < urb_len)) {
1079 *phwHeadP =
1080 (lurb_priv->td[urb_len - 1]->hwNextTD &\
1081 m32_swap(0xfffffff0)) |
1082 (*phwHeadP & m32_swap(0x2));
1083
1084 lurb_priv->td_cnt += urb_len -
1085 td_list->index - 1;
1086 } else
1087 *phwHeadP &= m32_swap(0xfffffff2);
1088 flush_dcache_ed(td_list->ed);
1089 }
1090 }
1091 }
1092
1093 /* replies to the request have to be on a FIFO basis so
1094 * we reverse the reversed done-list */
1095 static td_t *dl_reverse_done_list(ohci_t *ohci)
1096 {
1097 uintptr_t td_list_hc;
1098 td_t *td_rev = NULL;
1099 td_t *td_list = NULL;
1100
1101 invalidate_dcache_hcca(ohci->hcca);
1102 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
1103 ohci->hcca->done_head = 0;
1104 flush_dcache_hcca(ohci->hcca);
1105
1106 while (td_list_hc) {
1107 td_list = (td_t *)td_list_hc;
1108 invalidate_dcache_td(td_list);
1109 check_status(td_list);
1110 td_list->next_dl_td = td_rev;
1111 td_rev = td_list;
1112 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
1113 }
1114 return td_list;
1115 }
1116
1117 /*-------------------------------------------------------------------------*/
1118 /*-------------------------------------------------------------------------*/
1119
1120 static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
1121 {
1122 if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
1123 urb->finished = 1;
1124 else
1125 dbg("finish_urb: strange.., ED state %x, \n", status);
1126 }
1127
1128 /*
1129 * Used to take back a TD from the host controller. This would normally be
1130 * called from within dl_done_list, however it may be called directly if the
1131 * HC no longer sees the TD and it has not appeared on the donelist (after
1132 * two frames). This bug has been observed on ZF Micro systems.
1133 */
1134 static int takeback_td(ohci_t *ohci, td_t *td_list)
1135 {
1136 ed_t *ed;
1137 int cc;
1138 int stat = 0;
1139 /* urb_t *urb; */
1140 urb_priv_t *lurb_priv;
1141 __u32 tdINFO, edHeadP, edTailP;
1142
1143 invalidate_dcache_td(td_list);
1144 tdINFO = m32_swap(td_list->hwINFO);
1145
1146 ed = td_list->ed;
1147 lurb_priv = ed->purb;
1148
1149 dl_transfer_length(td_list);
1150
1151 lurb_priv->td_cnt++;
1152
1153 /* error code of transfer */
1154 cc = TD_CC_GET(tdINFO);
1155 if (cc) {
1156 err("USB-error: %s (%x)", cc_to_string[cc], cc);
1157 stat = cc_to_error[cc];
1158 }
1159
1160 /* see if this done list makes for all TD's of current URB,
1161 * and mark the URB finished if so */
1162 if (lurb_priv->td_cnt == lurb_priv->length)
1163 finish_urb(ohci, lurb_priv, ed->state);
1164
1165 dbg("dl_done_list: processing TD %x, len %x\n",
1166 lurb_priv->td_cnt, lurb_priv->length);
1167
1168 if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
1169 invalidate_dcache_ed(ed);
1170 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
1171 edTailP = m32_swap(ed->hwTailP);
1172
1173 /* unlink eds if they are not busy */
1174 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1175 ep_unlink(ohci, ed);
1176 }
1177 return stat;
1178 }
1179
1180 static int dl_done_list(ohci_t *ohci)
1181 {
1182 int stat = 0;
1183 td_t *td_list = dl_reverse_done_list(ohci);
1184
1185 while (td_list) {
1186 td_t *td_next = td_list->next_dl_td;
1187 stat = takeback_td(ohci, td_list);
1188 td_list = td_next;
1189 }
1190 return stat;
1191 }
1192
1193 /*-------------------------------------------------------------------------*
1194 * Virtual Root Hub
1195 *-------------------------------------------------------------------------*/
1196
1197 #include <usbroothubdes.h>
1198
1199 /* Hub class-specific descriptor is constructed dynamically */
1200
1201 /*-------------------------------------------------------------------------*/
1202
1203 #define OK(x) len = (x); break
1204 #ifdef DEBUG
1205 #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
1206 &ohci->regs->roothub.status); }
1207 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
1208 (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
1209 #else
1210 #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status)
1211 #define WR_RH_PORTSTAT(x) ohci_writel((x), \
1212 &ohci->regs->roothub.portstatus[wIndex-1])
1213 #endif
1214 #define RD_RH_STAT roothub_status(ohci)
1215 #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
1216
1217 /* request to virtual root hub */
1218
1219 int rh_check_port_status(ohci_t *controller)
1220 {
1221 __u32 temp, ndp, i;
1222 int res;
1223
1224 res = -1;
1225 temp = roothub_a(controller);
1226 ndp = (temp & RH_A_NDP);
1227 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1228 ndp = (ndp == 2) ? 1:0;
1229 #endif
1230 for (i = 0; i < ndp; i++) {
1231 temp = roothub_portstatus(controller, i);
1232 /* check for a device disconnect */
1233 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1234 (RH_PS_PESC | RH_PS_CSC)) &&
1235 ((temp & RH_PS_CCS) == 0)) {
1236 res = i;
1237 break;
1238 }
1239 }
1240 return res;
1241 }
1242
1243 static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
1244 unsigned long pipe, void *buffer, int transfer_len,
1245 struct devrequest *cmd)
1246 {
1247 void *data = buffer;
1248 int leni = transfer_len;
1249 int len = 0;
1250 int stat = 0;
1251 __u16 bmRType_bReq;
1252 __u16 wValue;
1253 __u16 wIndex;
1254 __u16 wLength;
1255 ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
1256
1257 #ifdef DEBUG
1258 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1259 cmd, "SUB(rh)", usb_pipein(pipe));
1260 #else
1261 ohci_mdelay(1);
1262 #endif
1263 if (usb_pipeint(pipe)) {
1264 info("Root-Hub submit IRQ: NOT implemented");
1265 return 0;
1266 }
1267
1268 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1269 wValue = le16_to_cpu(cmd->value);
1270 wIndex = le16_to_cpu(cmd->index);
1271 wLength = le16_to_cpu(cmd->length);
1272
1273 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1274 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1275
1276 switch (bmRType_bReq) {
1277 /* Request Destination:
1278 without flags: Device,
1279 RH_INTERFACE: interface,
1280 RH_ENDPOINT: endpoint,
1281 RH_CLASS means HUB here,
1282 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1283 */
1284
1285 case RH_GET_STATUS:
1286 *(u16 *)databuf = cpu_to_le16(1);
1287 OK(2);
1288 case RH_GET_STATUS | RH_INTERFACE:
1289 *(u16 *)databuf = cpu_to_le16(0);
1290 OK(2);
1291 case RH_GET_STATUS | RH_ENDPOINT:
1292 *(u16 *)databuf = cpu_to_le16(0);
1293 OK(2);
1294 case RH_GET_STATUS | RH_CLASS:
1295 *(u32 *)databuf = cpu_to_le32(
1296 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1297 OK(4);
1298 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1299 *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
1300 OK(4);
1301
1302 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1303 switch (wValue) {
1304 case (RH_ENDPOINT_STALL):
1305 OK(0);
1306 }
1307 break;
1308
1309 case RH_CLEAR_FEATURE | RH_CLASS:
1310 switch (wValue) {
1311 case RH_C_HUB_LOCAL_POWER:
1312 OK(0);
1313 case (RH_C_HUB_OVER_CURRENT):
1314 WR_RH_STAT(RH_HS_OCIC);
1315 OK(0);
1316 }
1317 break;
1318
1319 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1320 switch (wValue) {
1321 case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
1322 case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
1323 case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
1324 case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
1325 case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
1326 case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
1327 case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
1328 case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
1329 }
1330 break;
1331
1332 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1333 switch (wValue) {
1334 case (RH_PORT_SUSPEND):
1335 WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
1336 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1337 if (RD_RH_PORTSTAT & RH_PS_CCS)
1338 WR_RH_PORTSTAT(RH_PS_PRS);
1339 OK(0);
1340 case (RH_PORT_POWER):
1341 WR_RH_PORTSTAT(RH_PS_PPS);
1342 OK(0);
1343 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1344 if (RD_RH_PORTSTAT & RH_PS_CCS)
1345 WR_RH_PORTSTAT(RH_PS_PES);
1346 OK(0);
1347 }
1348 break;
1349
1350 case RH_SET_ADDRESS:
1351 ohci->rh.devnum = wValue;
1352 OK(0);
1353
1354 case RH_GET_DESCRIPTOR:
1355 switch ((wValue & 0xff00) >> 8) {
1356 case (0x01): /* device descriptor */
1357 len = min_t(unsigned int,
1358 leni,
1359 min_t(unsigned int,
1360 sizeof(root_hub_dev_des),
1361 wLength));
1362 databuf = root_hub_dev_des; OK(len);
1363 case (0x02): /* configuration descriptor */
1364 len = min_t(unsigned int,
1365 leni,
1366 min_t(unsigned int,
1367 sizeof(root_hub_config_des),
1368 wLength));
1369 databuf = root_hub_config_des; OK(len);
1370 case (0x03): /* string descriptors */
1371 if (wValue == 0x0300) {
1372 len = min_t(unsigned int,
1373 leni,
1374 min_t(unsigned int,
1375 sizeof(root_hub_str_index0),
1376 wLength));
1377 databuf = root_hub_str_index0;
1378 OK(len);
1379 }
1380 if (wValue == 0x0301) {
1381 len = min_t(unsigned int,
1382 leni,
1383 min_t(unsigned int,
1384 sizeof(root_hub_str_index1),
1385 wLength));
1386 databuf = root_hub_str_index1;
1387 OK(len);
1388 }
1389 default:
1390 stat = USB_ST_STALLED;
1391 }
1392 break;
1393
1394 case RH_GET_DESCRIPTOR | RH_CLASS:
1395 {
1396 __u32 temp = roothub_a(ohci);
1397
1398 databuf[0] = 9; /* min length; */
1399 databuf[1] = 0x29;
1400 databuf[2] = temp & RH_A_NDP;
1401 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1402 databuf[2] = (databuf[2] == 2) ? 1 : 0;
1403 #endif
1404 databuf[3] = 0;
1405 if (temp & RH_A_PSM) /* per-port power switching? */
1406 databuf[3] |= 0x1;
1407 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1408 databuf[3] |= 0x10;
1409 else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
1410 databuf[3] |= 0x8;
1411
1412 databuf[4] = 0;
1413 databuf[5] = (temp & RH_A_POTPGT) >> 24;
1414 databuf[6] = 0;
1415 temp = roothub_b(ohci);
1416 databuf[7] = temp & RH_B_DR;
1417 if (databuf[2] < 7) {
1418 databuf[8] = 0xff;
1419 } else {
1420 databuf[0] += 2;
1421 databuf[8] = (temp & RH_B_DR) >> 8;
1422 databuf[10] = databuf[9] = 0xff;
1423 }
1424
1425 len = min_t(unsigned int, leni,
1426 min_t(unsigned int, databuf[0], wLength));
1427 OK(len);
1428 }
1429
1430 case RH_GET_CONFIGURATION:
1431 databuf[0] = 0x01;
1432 OK(1);
1433
1434 case RH_SET_CONFIGURATION:
1435 WR_RH_STAT(0x10000);
1436 OK(0);
1437
1438 default:
1439 dbg("unsupported root hub command");
1440 stat = USB_ST_STALLED;
1441 }
1442
1443 #ifdef DEBUG
1444 ohci_dump_roothub(ohci, 1);
1445 #else
1446 ohci_mdelay(1);
1447 #endif
1448
1449 len = min_t(int, len, leni);
1450 if (data != databuf)
1451 memcpy(data, databuf, len);
1452 dev->act_len = len;
1453 dev->status = stat;
1454
1455 #ifdef DEBUG
1456 pkt_print(ohci, NULL, dev, pipe, buffer,
1457 transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1458 #else
1459 ohci_mdelay(1);
1460 #endif
1461
1462 return stat;
1463 }
1464
1465 /*-------------------------------------------------------------------------*/
1466
1467 static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr)
1468 {
1469 int i;
1470
1471 if (!intr)
1472 return &ohci->ohci_dev;
1473
1474 /* First see if we already have an ohci_dev for this dev. */
1475 for (i = 0; i < NUM_INT_DEVS; i++) {
1476 if (ohci->int_dev[i].devnum == devnum)
1477 return &ohci->int_dev[i];
1478 }
1479
1480 /* If not then find a free one. */
1481 for (i = 0; i < NUM_INT_DEVS; i++) {
1482 if (ohci->int_dev[i].devnum == -1) {
1483 ohci->int_dev[i].devnum = devnum;
1484 return &ohci->int_dev[i];
1485 }
1486 }
1487
1488 printf("ohci: Error out of ohci_devs for interrupt endpoints\n");
1489 return NULL;
1490 }
1491
1492 /* common code for handling submit messages - used for all but root hub */
1493 /* accesses. */
1494 static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe,
1495 void *buffer, int transfer_len, int interval)
1496 {
1497 urb_priv_t *urb;
1498
1499 urb = calloc(1, sizeof(urb_priv_t));
1500 if (!urb) {
1501 printf("ohci: Error out of memory allocating urb\n");
1502 return NULL;
1503 }
1504
1505 urb->dev = dev;
1506 urb->pipe = pipe;
1507 urb->transfer_buffer = buffer;
1508 urb->transfer_buffer_length = transfer_len;
1509 urb->interval = interval;
1510
1511 return urb;
1512 }
1513
1514 static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
1515 unsigned long pipe, void *buffer, int transfer_len,
1516 struct devrequest *setup, int interval)
1517 {
1518 int stat = 0;
1519 int maxsize = usb_maxpacket(dev, pipe);
1520 int timeout;
1521 urb_priv_t *urb;
1522 ohci_dev_t *ohci_dev;
1523
1524 urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval);
1525 if (!urb)
1526 return -ENOMEM;
1527
1528 #ifdef DEBUG
1529 urb->actual_length = 0;
1530 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1531 setup, "SUB", usb_pipein(pipe));
1532 #else
1533 ohci_mdelay(1);
1534 #endif
1535 if (!maxsize) {
1536 err("submit_common_message: pipesize for pipe %lx is zero",
1537 pipe);
1538 return -1;
1539 }
1540
1541 ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe));
1542 if (!ohci_dev)
1543 return -ENOMEM;
1544
1545 if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) {
1546 err("sohci_submit_job failed");
1547 return -1;
1548 }
1549
1550 #if 0
1551 mdelay(10);
1552 /* ohci_dump_status(ohci); */
1553 #endif
1554
1555 timeout = USB_TIMEOUT_MS(pipe);
1556
1557 /* wait for it to complete */
1558 for (;;) {
1559 /* check whether the controller is done */
1560 stat = hc_interrupt(ohci);
1561 if (stat < 0) {
1562 stat = USB_ST_CRC_ERR;
1563 break;
1564 }
1565
1566 /* NOTE: since we are not interrupt driven in U-Boot and always
1567 * handle only one URB at a time, we cannot assume the
1568 * transaction finished on the first successful return from
1569 * hc_interrupt().. unless the flag for current URB is set,
1570 * meaning that all TD's to/from device got actually
1571 * transferred and processed. If the current URB is not
1572 * finished we need to re-iterate this loop so as
1573 * hc_interrupt() gets called again as there needs to be some
1574 * more TD's to process still */
1575 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1576 /* 0xff is returned for an SF-interrupt */
1577 break;
1578 }
1579
1580 if (--timeout) {
1581 mdelay(1);
1582 if (!urb->finished)
1583 dbg("*");
1584
1585 } else {
1586 if (!usb_pipeint(pipe))
1587 err("CTL:TIMEOUT ");
1588 dbg("submit_common_msg: TO status %x\n", stat);
1589 urb->finished = 1;
1590 stat = USB_ST_CRC_ERR;
1591 break;
1592 }
1593 }
1594
1595 dev->status = stat;
1596 dev->act_len = urb->actual_length;
1597
1598 if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
1599 invalidate_dcache_buffer(buffer, dev->act_len);
1600
1601 #ifdef DEBUG
1602 pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
1603 setup, "RET(ctlr)", usb_pipein(pipe));
1604 #else
1605 ohci_mdelay(1);
1606 #endif
1607 urb_free_priv(urb);
1608 return 0;
1609 }
1610
1611 #define MAX_INT_QUEUESIZE 8
1612
1613 struct int_queue {
1614 int queuesize;
1615 int curr_urb;
1616 urb_priv_t *urb[MAX_INT_QUEUESIZE];
1617 };
1618
1619 static struct int_queue *_ohci_create_int_queue(ohci_t *ohci,
1620 struct usb_device *udev, unsigned long pipe, int queuesize,
1621 int elementsize, void *buffer, int interval)
1622 {
1623 struct int_queue *queue;
1624 ohci_dev_t *ohci_dev;
1625 int i;
1626
1627 if (queuesize > MAX_INT_QUEUESIZE)
1628 return NULL;
1629
1630 ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1);
1631 if (!ohci_dev)
1632 return NULL;
1633
1634 queue = malloc(sizeof(*queue));
1635 if (!queue) {
1636 printf("ohci: Error out of memory allocating int queue\n");
1637 return NULL;
1638 }
1639
1640 for (i = 0; i < queuesize; i++) {
1641 queue->urb[i] = ohci_alloc_urb(udev, pipe,
1642 buffer + i * elementsize,
1643 elementsize, interval);
1644 if (!queue->urb[i])
1645 break;
1646
1647 if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) {
1648 printf("ohci: Error submitting int queue job\n");
1649 urb_free_priv(queue->urb[i]);
1650 break;
1651 }
1652 }
1653 if (i == 0) {
1654 /* We did not succeed in submitting even 1 urb */
1655 free(queue);
1656 return NULL;
1657 }
1658
1659 queue->queuesize = i;
1660 queue->curr_urb = 0;
1661
1662 return queue;
1663 }
1664
1665 static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev,
1666 struct int_queue *queue)
1667 {
1668 if (queue->curr_urb == queue->queuesize)
1669 return NULL; /* Queue depleted */
1670
1671 if (hc_interrupt(ohci) < 0)
1672 return NULL;
1673
1674 if (queue->urb[queue->curr_urb]->finished) {
1675 void *ret = queue->urb[queue->curr_urb]->transfer_buffer;
1676 queue->curr_urb++;
1677 return ret;
1678 }
1679
1680 return NULL;
1681 }
1682
1683 static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev,
1684 struct int_queue *queue)
1685 {
1686 int i;
1687
1688 for (i = 0; i < queue->queuesize; i++)
1689 urb_free_priv(queue->urb[i]);
1690
1691 free(queue);
1692
1693 return 0;
1694 }
1695
1696 #ifndef CONFIG_DM_USB
1697 /* submit routines called from usb.c */
1698 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1699 int transfer_len)
1700 {
1701 info("submit_bulk_msg");
1702 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
1703 NULL, 0);
1704 }
1705
1706 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1707 int transfer_len, int interval)
1708 {
1709 info("submit_int_msg");
1710 return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
1711 interval);
1712 }
1713
1714 struct int_queue *create_int_queue(struct usb_device *dev,
1715 unsigned long pipe, int queuesize, int elementsize,
1716 void *buffer, int interval)
1717 {
1718 return _ohci_create_int_queue(&gohci, dev, pipe, queuesize,
1719 elementsize, buffer, interval);
1720 }
1721
1722 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1723 {
1724 return _ohci_poll_int_queue(&gohci, dev, queue);
1725 }
1726
1727 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1728 {
1729 return _ohci_destroy_int_queue(&gohci, dev, queue);
1730 }
1731 #endif
1732
1733 static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
1734 unsigned long pipe, void *buffer, int transfer_len,
1735 struct devrequest *setup)
1736 {
1737 int maxsize = usb_maxpacket(dev, pipe);
1738
1739 info("submit_control_msg");
1740 #ifdef DEBUG
1741 pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
1742 setup, "SUB", usb_pipein(pipe));
1743 #else
1744 ohci_mdelay(1);
1745 #endif
1746 if (!maxsize) {
1747 err("submit_control_message: pipesize for pipe %lx is zero",
1748 pipe);
1749 return -1;
1750 }
1751 if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
1752 ohci->rh.dev = dev;
1753 /* root hub - redirect */
1754 return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
1755 transfer_len, setup);
1756 }
1757
1758 return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
1759 setup, 0);
1760 }
1761
1762 /*-------------------------------------------------------------------------*
1763 * HC functions
1764 *-------------------------------------------------------------------------*/
1765
1766 /* reset the HC and BUS */
1767
1768 static int hc_reset(ohci_t *ohci)
1769 {
1770 #ifdef CONFIG_PCI_EHCI_DEVNO
1771 pci_dev_t pdev;
1772 #endif
1773 int timeout = 30;
1774 int smm_timeout = 50; /* 0,5 sec */
1775
1776 dbg("%s\n", __FUNCTION__);
1777
1778 #ifdef CONFIG_PCI_EHCI_DEVNO
1779 /*
1780 * Some multi-function controllers (e.g. ISP1562) allow root hub
1781 * resetting via EHCI registers only.
1782 */
1783 pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
1784 if (pdev != -1) {
1785 u32 base;
1786 int timeout = 1000;
1787
1788 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1789 base += EHCI_USBCMD_OFF;
1790 ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
1791
1792 while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
1793 if (timeout-- <= 0) {
1794 printf("USB RootHub reset timed out!");
1795 break;
1796 }
1797 udelay(1);
1798 }
1799 } else
1800 printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
1801 #endif
1802 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1803 /* SMM owns the HC, request ownership */
1804 ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
1805 info("USB HC TakeOver from SMM");
1806 while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1807 mdelay(10);
1808 if (--smm_timeout == 0) {
1809 err("USB HC TakeOver failed!");
1810 return -1;
1811 }
1812 }
1813 }
1814
1815 /* Disable HC interrupts */
1816 ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1817
1818 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1819 ohci->slot_name,
1820 ohci_readl(&ohci->regs->control));
1821
1822 /* Reset USB (needed by some controllers) */
1823 ohci->hc_control = 0;
1824 ohci_writel(ohci->hc_control, &ohci->regs->control);
1825
1826 /* HC Reset requires max 10 us delay */
1827 ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
1828 while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1829 if (--timeout == 0) {
1830 err("USB HC reset timed out!");
1831 return -1;
1832 }
1833 udelay(1);
1834 }
1835 return 0;
1836 }
1837
1838 /*-------------------------------------------------------------------------*/
1839
1840 /* Start an OHCI controller, set the BUS operational
1841 * enable interrupts
1842 * connect the virtual root hub */
1843
1844 static int hc_start(ohci_t *ohci)
1845 {
1846 __u32 mask;
1847 unsigned int fminterval;
1848 int i;
1849
1850 ohci->disabled = 1;
1851 for (i = 0; i < NUM_INT_DEVS; i++)
1852 ohci->int_dev[i].devnum = -1;
1853
1854 /* Tell the controller where the control and bulk lists are
1855 * The lists are empty now. */
1856
1857 ohci_writel(0, &ohci->regs->ed_controlhead);
1858 ohci_writel(0, &ohci->regs->ed_bulkhead);
1859
1860 ohci_writel((uintptr_t)ohci->hcca,
1861 &ohci->regs->hcca); /* reset clears this */
1862
1863 fminterval = 0x2edf;
1864 ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1865 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1866 ohci_writel(fminterval, &ohci->regs->fminterval);
1867 ohci_writel(0x628, &ohci->regs->lsthresh);
1868
1869 /* start controller operations */
1870 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1871 ohci->disabled = 0;
1872 ohci_writel(ohci->hc_control, &ohci->regs->control);
1873
1874 /* disable all interrupts */
1875 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1876 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1877 OHCI_INTR_OC | OHCI_INTR_MIE);
1878 ohci_writel(mask, &ohci->regs->intrdisable);
1879 /* clear all interrupts */
1880 mask &= ~OHCI_INTR_MIE;
1881 ohci_writel(mask, &ohci->regs->intrstatus);
1882 /* Choose the interrupts we care about now - but w/o MIE */
1883 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1884 ohci_writel(mask, &ohci->regs->intrenable);
1885
1886 #ifdef OHCI_USE_NPS
1887 /* required for AMD-756 and some Mac platforms */
1888 ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1889 &ohci->regs->roothub.a);
1890 ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1891 #endif /* OHCI_USE_NPS */
1892
1893 /* connect the virtual root hub */
1894 ohci->rh.devnum = 0;
1895
1896 return 0;
1897 }
1898
1899 /*-------------------------------------------------------------------------*/
1900
1901 /* an interrupt happens */
1902
1903 static int hc_interrupt(ohci_t *ohci)
1904 {
1905 struct ohci_regs *regs = ohci->regs;
1906 int ints;
1907 int stat = -1;
1908
1909 invalidate_dcache_hcca(ohci->hcca);
1910
1911 if ((ohci->hcca->done_head != 0) &&
1912 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1913 ints = OHCI_INTR_WDH;
1914 } else {
1915 ints = ohci_readl(&regs->intrstatus);
1916 if (ints == ~(u32)0) {
1917 ohci->disabled++;
1918 err("%s device removed!", ohci->slot_name);
1919 return -1;
1920 } else {
1921 ints &= ohci_readl(&regs->intrenable);
1922 if (ints == 0) {
1923 dbg("hc_interrupt: returning..\n");
1924 return 0xff;
1925 }
1926 }
1927 }
1928
1929 /* dbg("Interrupt: %x frame: %x", ints,
1930 le16_to_cpu(ohci->hcca->frame_no)); */
1931
1932 if (ints & OHCI_INTR_RHSC)
1933 stat = 0xff;
1934
1935 if (ints & OHCI_INTR_UE) {
1936 ohci->disabled++;
1937 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1938 ohci->slot_name);
1939 /* e.g. due to PCI Master/Target Abort */
1940
1941 #ifdef DEBUG
1942 ohci_dump(ohci, 1);
1943 #else
1944 ohci_mdelay(1);
1945 #endif
1946 /* FIXME: be optimistic, hope that bug won't repeat often. */
1947 /* Make some non-interrupt context restart the controller. */
1948 /* Count and limit the retries though; either hardware or */
1949 /* software errors can go forever... */
1950 hc_reset(ohci);
1951 return -1;
1952 }
1953
1954 if (ints & OHCI_INTR_WDH) {
1955 ohci_mdelay(1);
1956 ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
1957 (void)ohci_readl(&regs->intrdisable); /* flush */
1958 stat = dl_done_list(ohci);
1959 ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
1960 (void)ohci_readl(&regs->intrdisable); /* flush */
1961 }
1962
1963 if (ints & OHCI_INTR_SO) {
1964 dbg("USB Schedule overrun\n");
1965 ohci_writel(OHCI_INTR_SO, &regs->intrenable);
1966 stat = -1;
1967 }
1968
1969 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1970 if (ints & OHCI_INTR_SF) {
1971 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1972 mdelay(1);
1973 ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
1974 if (ohci->ed_rm_list[frame] != NULL)
1975 ohci_writel(OHCI_INTR_SF, &regs->intrenable);
1976 stat = 0xff;
1977 }
1978
1979 ohci_writel(ints, &regs->intrstatus);
1980 return stat;
1981 }
1982
1983 /*-------------------------------------------------------------------------*/
1984
1985 #ifndef CONFIG_DM_USB
1986
1987 /*-------------------------------------------------------------------------*/
1988
1989 /* De-allocate all resources.. */
1990
1991 static void hc_release_ohci(ohci_t *ohci)
1992 {
1993 dbg("USB HC release ohci usb-%s", ohci->slot_name);
1994
1995 if (!ohci->disabled)
1996 hc_reset(ohci);
1997 }
1998
1999 /*-------------------------------------------------------------------------*/
2000
2001 /*
2002 * low level initalisation routine, called from usb.c
2003 */
2004 static char ohci_inited = 0;
2005
2006 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
2007 {
2008 #ifdef CONFIG_PCI_OHCI
2009 pci_dev_t pdev;
2010 #endif
2011
2012 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2013 /* cpu dependant init */
2014 if (usb_cpu_init())
2015 return -1;
2016 #endif
2017
2018 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2019 /* board dependant init */
2020 if (board_usb_init(index, USB_INIT_HOST))
2021 return -1;
2022 #endif
2023 memset(&gohci, 0, sizeof(ohci_t));
2024
2025 /* align the storage */
2026 if ((__u32)&ghcca[0] & 0xff) {
2027 err("HCCA not aligned!!");
2028 return -1;
2029 }
2030 gohci.hcca = &ghcca[0];
2031 info("aligned ghcca %p", gohci.hcca);
2032 memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
2033
2034 gohci.disabled = 1;
2035 gohci.sleeping = 0;
2036 gohci.irq = -1;
2037 #ifdef CONFIG_PCI_OHCI
2038 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
2039
2040 if (pdev != -1) {
2041 u16 vid, did;
2042 u32 base;
2043 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
2044 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
2045 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
2046 vid, did, (pdev >> 16) & 0xff,
2047 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
2048 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
2049 printf("OHCI regs address 0x%08x\n", base);
2050 gohci.regs = (struct ohci_regs *)base;
2051 } else
2052 return -1;
2053 #else
2054 gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
2055 #endif
2056
2057 gohci.flags = 0;
2058 gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
2059
2060 if (hc_reset (&gohci) < 0) {
2061 hc_release_ohci (&gohci);
2062 err ("can't reset usb-%s", gohci.slot_name);
2063 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2064 /* board dependant cleanup */
2065 board_usb_cleanup(index, USB_INIT_HOST);
2066 #endif
2067
2068 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2069 /* cpu dependant cleanup */
2070 usb_cpu_init_fail();
2071 #endif
2072 return -1;
2073 }
2074
2075 if (hc_start(&gohci) < 0) {
2076 err("can't start usb-%s", gohci.slot_name);
2077 hc_release_ohci(&gohci);
2078 /* Initialization failed */
2079 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2080 /* board dependant cleanup */
2081 usb_board_stop();
2082 #endif
2083
2084 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2085 /* cpu dependant cleanup */
2086 usb_cpu_stop();
2087 #endif
2088 return -1;
2089 }
2090
2091 #ifdef DEBUG
2092 ohci_dump(&gohci, 1);
2093 #else
2094 ohci_mdelay(1);
2095 #endif
2096 ohci_inited = 1;
2097 return 0;
2098 }
2099
2100 int usb_lowlevel_stop(int index)
2101 {
2102 /* this gets called really early - before the controller has */
2103 /* even been initialized! */
2104 if (!ohci_inited)
2105 return 0;
2106 /* TODO release any interrupts, etc. */
2107 /* call hc_release_ohci() here ? */
2108 hc_reset(&gohci);
2109
2110 #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
2111 /* board dependant cleanup */
2112 if (usb_board_stop())
2113 return -1;
2114 #endif
2115
2116 #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
2117 /* cpu dependant cleanup */
2118 if (usb_cpu_stop())
2119 return -1;
2120 #endif
2121 /* This driver is no longer initialised. It needs a new low-level
2122 * init (board/cpu) before it can be used again. */
2123 ohci_inited = 0;
2124 return 0;
2125 }
2126
2127 int submit_control_msg(struct usb_device *dev, unsigned long pipe,
2128 void *buffer, int transfer_len, struct devrequest *setup)
2129 {
2130 return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
2131 transfer_len, setup);
2132 }
2133 #endif
2134
2135 #ifdef CONFIG_DM_USB
2136 static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
2137 unsigned long pipe, void *buffer, int length,
2138 struct devrequest *setup)
2139 {
2140 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2141
2142 return _ohci_submit_control_msg(ohci, udev, pipe, buffer,
2143 length, setup);
2144 }
2145
2146 static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
2147 unsigned long pipe, void *buffer, int length)
2148 {
2149 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2150
2151 return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0);
2152 }
2153
2154 static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
2155 unsigned long pipe, void *buffer, int length,
2156 int interval)
2157 {
2158 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2159
2160 return submit_common_msg(ohci, udev, pipe, buffer, length,
2161 NULL, interval);
2162 }
2163
2164 static struct int_queue *ohci_create_int_queue(struct udevice *dev,
2165 struct usb_device *udev, unsigned long pipe, int queuesize,
2166 int elementsize, void *buffer, int interval)
2167 {
2168 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2169
2170 return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize,
2171 buffer, interval);
2172 }
2173
2174 static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
2175 struct int_queue *queue)
2176 {
2177 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2178
2179 return _ohci_poll_int_queue(ohci, udev, queue);
2180 }
2181
2182 static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
2183 struct int_queue *queue)
2184 {
2185 ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
2186
2187 return _ohci_destroy_int_queue(ohci, udev, queue);
2188 }
2189
2190 int ohci_register(struct udevice *dev, struct ohci_regs *regs)
2191 {
2192 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
2193 ohci_t *ohci = dev_get_priv(dev);
2194 u32 reg;
2195
2196 priv->desc_before_addr = true;
2197
2198 ohci->regs = regs;
2199 ohci->hcca = memalign(256, sizeof(struct ohci_hcca));
2200 if (!ohci->hcca)
2201 return -ENOMEM;
2202 memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
2203 flush_dcache_hcca(ohci->hcca);
2204
2205 if (hc_reset(ohci) < 0)
2206 return -EIO;
2207
2208 if (hc_start(ohci) < 0)
2209 return -EIO;
2210
2211 reg = ohci_readl(&regs->revision);
2212 printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf);
2213
2214 return 0;
2215 }
2216
2217 int ohci_deregister(struct udevice *dev)
2218 {
2219 ohci_t *ohci = dev_get_priv(dev);
2220
2221 if (hc_reset(ohci) < 0)
2222 return -EIO;
2223
2224 free(ohci->hcca);
2225
2226 return 0;
2227 }
2228
2229 struct dm_usb_ops ohci_usb_ops = {
2230 .control = ohci_submit_control_msg,
2231 .bulk = ohci_submit_bulk_msg,
2232 .interrupt = ohci_submit_int_msg,
2233 .create_int_queue = ohci_create_int_queue,
2234 .poll_int_queue = ohci_poll_int_queue,
2235 .destroy_int_queue = ohci_destroy_int_queue,
2236 };
2237
2238 #endif
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