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[thirdparty/linux.git] / drivers / usb / host / ohci-hcd.c
1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * Open Host Controller Interface (OHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ohci fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 *
16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
17 * interfaces (though some non-x86 Intel chips use it). It supports
18 * smarter hardware than UHCI. A download link for the spec available
19 * through the http://www.usb.org website.
20 *
21 * This file is licenced under the GPL.
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/delay.h>
29 #include <linux/ioport.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/timer.h>
35 #include <linux/list.h>
36 #include <linux/usb.h>
37 #include <linux/usb/otg.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmapool.h>
41 #include <linux/workqueue.h>
42 #include <linux/debugfs.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/unaligned.h>
47 #include <asm/byteorder.h>
48
49
50 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
51 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52
53 /*-------------------------------------------------------------------------*/
54
55 /* For initializing controller (mask in an HCFS mode too) */
56 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
57 #define OHCI_INTR_INIT \
58 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
59 | OHCI_INTR_RD | OHCI_INTR_WDH)
60
61 #ifdef __hppa__
62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
63 #define IR_DISABLE
64 #endif
65
66 #ifdef CONFIG_ARCH_OMAP
67 /* OMAP doesn't support IR (no SMM; not needed) */
68 #define IR_DISABLE
69 #endif
70
71 /*-------------------------------------------------------------------------*/
72
73 static const char hcd_name [] = "ohci_hcd";
74
75 #define STATECHANGE_DELAY msecs_to_jiffies(300)
76 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
77
78 #include "ohci.h"
79 #include "pci-quirks.h"
80
81 static void ohci_dump(struct ohci_hcd *ohci);
82 static void ohci_stop(struct usb_hcd *hcd);
83 static void io_watchdog_func(struct timer_list *t);
84
85 #include "ohci-hub.c"
86 #include "ohci-dbg.c"
87 #include "ohci-mem.c"
88 #include "ohci-q.c"
89
90
91 /*
92 * On architectures with edge-triggered interrupts we must never return
93 * IRQ_NONE.
94 */
95 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
96 #define IRQ_NOTMINE IRQ_HANDLED
97 #else
98 #define IRQ_NOTMINE IRQ_NONE
99 #endif
100
101
102 /* Some boards misreport power switching/overcurrent */
103 static bool distrust_firmware = true;
104 module_param (distrust_firmware, bool, 0);
105 MODULE_PARM_DESC (distrust_firmware,
106 "true to distrust firmware power/overcurrent setup");
107
108 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
109 static bool no_handshake;
110 module_param (no_handshake, bool, 0);
111 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
112
113 /*-------------------------------------------------------------------------*/
114
115 static int number_of_tds(struct urb *urb)
116 {
117 int len, i, num, this_sg_len;
118 struct scatterlist *sg;
119
120 len = urb->transfer_buffer_length;
121 i = urb->num_mapped_sgs;
122
123 if (len > 0 && i > 0) { /* Scatter-gather transfer */
124 num = 0;
125 sg = urb->sg;
126 for (;;) {
127 this_sg_len = min_t(int, sg_dma_len(sg), len);
128 num += DIV_ROUND_UP(this_sg_len, 4096);
129 len -= this_sg_len;
130 if (--i <= 0 || len <= 0)
131 break;
132 sg = sg_next(sg);
133 }
134
135 } else { /* Non-SG transfer */
136 /* one TD for every 4096 Bytes (could be up to 8K) */
137 num = DIV_ROUND_UP(len, 4096);
138 }
139 return num;
140 }
141
142 /*
143 * queue up an urb for anything except the root hub
144 */
145 static int ohci_urb_enqueue (
146 struct usb_hcd *hcd,
147 struct urb *urb,
148 gfp_t mem_flags
149 ) {
150 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
151 struct ed *ed;
152 urb_priv_t *urb_priv;
153 unsigned int pipe = urb->pipe;
154 int i, size = 0;
155 unsigned long flags;
156 int retval = 0;
157
158 /* every endpoint has a ed, locate and maybe (re)initialize it */
159 ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
160 if (! ed)
161 return -ENOMEM;
162
163 /* for the private part of the URB we need the number of TDs (size) */
164 switch (ed->type) {
165 case PIPE_CONTROL:
166 /* td_submit_urb() doesn't yet handle these */
167 if (urb->transfer_buffer_length > 4096)
168 return -EMSGSIZE;
169
170 /* 1 TD for setup, 1 for ACK, plus ... */
171 size = 2;
172 /* FALLTHROUGH */
173 // case PIPE_INTERRUPT:
174 // case PIPE_BULK:
175 default:
176 size += number_of_tds(urb);
177 /* maybe a zero-length packet to wrap it up */
178 if (size == 0)
179 size++;
180 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
181 && (urb->transfer_buffer_length
182 % usb_maxpacket (urb->dev, pipe,
183 usb_pipeout (pipe))) == 0)
184 size++;
185 break;
186 case PIPE_ISOCHRONOUS: /* number of packets from URB */
187 size = urb->number_of_packets;
188 break;
189 }
190
191 /* allocate the private part of the URB */
192 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
193 mem_flags);
194 if (!urb_priv)
195 return -ENOMEM;
196 INIT_LIST_HEAD (&urb_priv->pending);
197 urb_priv->length = size;
198 urb_priv->ed = ed;
199
200 /* allocate the TDs (deferring hash chain updates) */
201 for (i = 0; i < size; i++) {
202 urb_priv->td [i] = td_alloc (ohci, mem_flags);
203 if (!urb_priv->td [i]) {
204 urb_priv->length = i;
205 urb_free_priv (ohci, urb_priv);
206 return -ENOMEM;
207 }
208 }
209
210 spin_lock_irqsave (&ohci->lock, flags);
211
212 /* don't submit to a dead HC */
213 if (!HCD_HW_ACCESSIBLE(hcd)) {
214 retval = -ENODEV;
215 goto fail;
216 }
217 if (ohci->rh_state != OHCI_RH_RUNNING) {
218 retval = -ENODEV;
219 goto fail;
220 }
221 retval = usb_hcd_link_urb_to_ep(hcd, urb);
222 if (retval)
223 goto fail;
224
225 /* schedule the ed if needed */
226 if (ed->state == ED_IDLE) {
227 retval = ed_schedule (ohci, ed);
228 if (retval < 0) {
229 usb_hcd_unlink_urb_from_ep(hcd, urb);
230 goto fail;
231 }
232
233 /* Start up the I/O watchdog timer, if it's not running */
234 if (!timer_pending(&ohci->io_watchdog) &&
235 list_empty(&ohci->eds_in_use) &&
236 !(ohci->flags & OHCI_QUIRK_QEMU)) {
237 ohci->prev_frame_no = ohci_frame_no(ohci);
238 mod_timer(&ohci->io_watchdog,
239 jiffies + IO_WATCHDOG_DELAY);
240 }
241 list_add(&ed->in_use_list, &ohci->eds_in_use);
242
243 if (ed->type == PIPE_ISOCHRONOUS) {
244 u16 frame = ohci_frame_no(ohci);
245
246 /* delay a few frames before the first TD */
247 frame += max_t (u16, 8, ed->interval);
248 frame &= ~(ed->interval - 1);
249 frame |= ed->branch;
250 urb->start_frame = frame;
251 ed->last_iso = frame + ed->interval * (size - 1);
252 }
253 } else if (ed->type == PIPE_ISOCHRONOUS) {
254 u16 next = ohci_frame_no(ohci) + 1;
255 u16 frame = ed->last_iso + ed->interval;
256 u16 length = ed->interval * (size - 1);
257
258 /* Behind the scheduling threshold? */
259 if (unlikely(tick_before(frame, next))) {
260
261 /* URB_ISO_ASAP: Round up to the first available slot */
262 if (urb->transfer_flags & URB_ISO_ASAP) {
263 frame += (next - frame + ed->interval - 1) &
264 -ed->interval;
265
266 /*
267 * Not ASAP: Use the next slot in the stream,
268 * no matter what.
269 */
270 } else {
271 /*
272 * Some OHCI hardware doesn't handle late TDs
273 * correctly. After retiring them it proceeds
274 * to the next ED instead of the next TD.
275 * Therefore we have to omit the late TDs
276 * entirely.
277 */
278 urb_priv->td_cnt = DIV_ROUND_UP(
279 (u16) (next - frame),
280 ed->interval);
281 if (urb_priv->td_cnt >= urb_priv->length) {
282 ++urb_priv->td_cnt; /* Mark it */
283 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
284 urb, frame, length,
285 next);
286 }
287 }
288 }
289 urb->start_frame = frame;
290 ed->last_iso = frame + length;
291 }
292
293 /* fill the TDs and link them to the ed; and
294 * enable that part of the schedule, if needed
295 * and update count of queued periodic urbs
296 */
297 urb->hcpriv = urb_priv;
298 td_submit_urb (ohci, urb);
299
300 fail:
301 if (retval)
302 urb_free_priv (ohci, urb_priv);
303 spin_unlock_irqrestore (&ohci->lock, flags);
304 return retval;
305 }
306
307 /*
308 * decouple the URB from the HC queues (TDs, urb_priv).
309 * reporting is always done
310 * asynchronously, and we might be dealing with an urb that's
311 * partially transferred, or an ED with other urbs being unlinked.
312 */
313 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
314 {
315 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
316 unsigned long flags;
317 int rc;
318 urb_priv_t *urb_priv;
319
320 spin_lock_irqsave (&ohci->lock, flags);
321 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
322 if (rc == 0) {
323
324 /* Unless an IRQ completed the unlink while it was being
325 * handed to us, flag it for unlink and giveback, and force
326 * some upcoming INTR_SF to call finish_unlinks()
327 */
328 urb_priv = urb->hcpriv;
329 if (urb_priv->ed->state == ED_OPER)
330 start_ed_unlink(ohci, urb_priv->ed);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333 /* With HC dead, we can clean up right away */
334 ohci_work(ohci);
335 }
336 }
337 spin_unlock_irqrestore (&ohci->lock, flags);
338 return rc;
339 }
340
341 /*-------------------------------------------------------------------------*/
342
343 /* frees config/altsetting state for endpoints,
344 * including ED memory, dummy TD, and bulk/intr data toggle
345 */
346
347 static void
348 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
349 {
350 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
351 unsigned long flags;
352 struct ed *ed = ep->hcpriv;
353 unsigned limit = 1000;
354
355 /* ASSERT: any requests/urbs are being unlinked */
356 /* ASSERT: nobody can be submitting urbs for this any more */
357
358 if (!ed)
359 return;
360
361 rescan:
362 spin_lock_irqsave (&ohci->lock, flags);
363
364 if (ohci->rh_state != OHCI_RH_RUNNING) {
365 sanitize:
366 ed->state = ED_IDLE;
367 ohci_work(ohci);
368 }
369
370 switch (ed->state) {
371 case ED_UNLINK: /* wait for hw to finish? */
372 /* major IRQ delivery trouble loses INTR_SF too... */
373 if (limit-- == 0) {
374 ohci_warn(ohci, "ED unlink timeout\n");
375 goto sanitize;
376 }
377 spin_unlock_irqrestore (&ohci->lock, flags);
378 schedule_timeout_uninterruptible(1);
379 goto rescan;
380 case ED_IDLE: /* fully unlinked */
381 if (list_empty (&ed->td_list)) {
382 td_free (ohci, ed->dummy);
383 ed_free (ohci, ed);
384 break;
385 }
386 /* fall through */
387 default:
388 /* caller was supposed to have unlinked any requests;
389 * that's not our job. can't recover; must leak ed.
390 */
391 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
392 ed, ep->desc.bEndpointAddress, ed->state,
393 list_empty (&ed->td_list) ? "" : " (has tds)");
394 td_free (ohci, ed->dummy);
395 break;
396 }
397 ep->hcpriv = NULL;
398 spin_unlock_irqrestore (&ohci->lock, flags);
399 }
400
401 static int ohci_get_frame (struct usb_hcd *hcd)
402 {
403 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
404
405 return ohci_frame_no(ohci);
406 }
407
408 static void ohci_usb_reset (struct ohci_hcd *ohci)
409 {
410 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
411 ohci->hc_control &= OHCI_CTRL_RWC;
412 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
413 ohci->rh_state = OHCI_RH_HALTED;
414 }
415
416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
417 * other cases where the next software may expect clean state from the
418 * "firmware". this is bus-neutral, unlike shutdown() methods.
419 */
420 static void
421 ohci_shutdown (struct usb_hcd *hcd)
422 {
423 struct ohci_hcd *ohci;
424
425 ohci = hcd_to_ohci (hcd);
426 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
427
428 /* Software reset, after which the controller goes into SUSPEND */
429 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
430 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
431 udelay(10);
432
433 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
434 ohci->rh_state = OHCI_RH_HALTED;
435 }
436
437 /*-------------------------------------------------------------------------*
438 * HC functions
439 *-------------------------------------------------------------------------*/
440
441 /* init memory, and kick BIOS/SMM off */
442
443 static int ohci_init (struct ohci_hcd *ohci)
444 {
445 int ret;
446 struct usb_hcd *hcd = ohci_to_hcd(ohci);
447
448 /* Accept arbitrarily long scatter-gather lists */
449 hcd->self.sg_tablesize = ~0;
450
451 if (distrust_firmware)
452 ohci->flags |= OHCI_QUIRK_HUB_POWER;
453
454 ohci->rh_state = OHCI_RH_HALTED;
455 ohci->regs = hcd->regs;
456
457 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
458 * was never needed for most non-PCI systems ... remove the code?
459 */
460
461 #ifndef IR_DISABLE
462 /* SMM owns the HC? not for long! */
463 if (!no_handshake && ohci_readl (ohci,
464 &ohci->regs->control) & OHCI_CTRL_IR) {
465 u32 temp;
466
467 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
468
469 /* this timeout is arbitrary. we make it long, so systems
470 * depending on usb keyboards may be usable even if the
471 * BIOS/SMM code seems pretty broken.
472 */
473 temp = 500; /* arbitrary: five seconds */
474
475 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
476 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
477 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
478 msleep (10);
479 if (--temp == 0) {
480 ohci_err (ohci, "USB HC takeover failed!"
481 " (BIOS/SMM bug)\n");
482 return -EBUSY;
483 }
484 }
485 ohci_usb_reset (ohci);
486 }
487 #endif
488
489 /* Disable HC interrupts */
490 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
491
492 /* flush the writes, and save key bits like RWC */
493 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
494 ohci->hc_control |= OHCI_CTRL_RWC;
495
496 /* Read the number of ports unless overridden */
497 if (ohci->num_ports == 0)
498 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
499
500 if (ohci->hcca)
501 return 0;
502
503 timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
504
505 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
506 sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
507 if (!ohci->hcca)
508 return -ENOMEM;
509
510 if ((ret = ohci_mem_init (ohci)) < 0)
511 ohci_stop (hcd);
512 else {
513 create_debug_files (ohci);
514 }
515
516 return ret;
517 }
518
519 /*-------------------------------------------------------------------------*/
520
521 /* Start an OHCI controller, set the BUS operational
522 * resets USB and controller
523 * enable interrupts
524 */
525 static int ohci_run (struct ohci_hcd *ohci)
526 {
527 u32 mask, val;
528 int first = ohci->fminterval == 0;
529 struct usb_hcd *hcd = ohci_to_hcd(ohci);
530
531 ohci->rh_state = OHCI_RH_HALTED;
532
533 /* boot firmware should have set this up (5.1.1.3.1) */
534 if (first) {
535
536 val = ohci_readl (ohci, &ohci->regs->fminterval);
537 ohci->fminterval = val & 0x3fff;
538 if (ohci->fminterval != FI)
539 ohci_dbg (ohci, "fminterval delta %d\n",
540 ohci->fminterval - FI);
541 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
542 /* also: power/overcurrent flags in roothub.a */
543 }
544
545 /* Reset USB nearly "by the book". RemoteWakeupConnected has
546 * to be checked in case boot firmware (BIOS/SMM/...) has set up
547 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
548 * If the bus glue detected wakeup capability then it should
549 * already be enabled; if so we'll just enable it again.
550 */
551 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
552 device_set_wakeup_capable(hcd->self.controller, 1);
553
554 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
555 case OHCI_USB_OPER:
556 val = 0;
557 break;
558 case OHCI_USB_SUSPEND:
559 case OHCI_USB_RESUME:
560 ohci->hc_control &= OHCI_CTRL_RWC;
561 ohci->hc_control |= OHCI_USB_RESUME;
562 val = 10 /* msec wait */;
563 break;
564 // case OHCI_USB_RESET:
565 default:
566 ohci->hc_control &= OHCI_CTRL_RWC;
567 ohci->hc_control |= OHCI_USB_RESET;
568 val = 50 /* msec wait */;
569 break;
570 }
571 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
572 // flush the writes
573 (void) ohci_readl (ohci, &ohci->regs->control);
574 msleep(val);
575
576 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
577
578 /* 2msec timelimit here means no irqs/preempt */
579 spin_lock_irq (&ohci->lock);
580
581 retry:
582 /* HC Reset requires max 10 us delay */
583 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
584 val = 30; /* ... allow extra time */
585 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
586 if (--val == 0) {
587 spin_unlock_irq (&ohci->lock);
588 ohci_err (ohci, "USB HC reset timed out!\n");
589 return -1;
590 }
591 udelay (1);
592 }
593
594 /* now we're in the SUSPEND state ... must go OPERATIONAL
595 * within 2msec else HC enters RESUME
596 *
597 * ... but some hardware won't init fmInterval "by the book"
598 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
599 * this if we write fmInterval after we're OPERATIONAL.
600 * Unclear about ALi, ServerWorks, and others ... this could
601 * easily be a longstanding bug in chip init on Linux.
602 */
603 if (ohci->flags & OHCI_QUIRK_INITRESET) {
604 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
605 // flush those writes
606 (void) ohci_readl (ohci, &ohci->regs->control);
607 }
608
609 /* Tell the controller where the control and bulk lists are
610 * The lists are empty now. */
611 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
612 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
613
614 /* a reset clears this */
615 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
616
617 periodic_reinit (ohci);
618
619 /* some OHCI implementations are finicky about how they init.
620 * bogus values here mean not even enumeration could work.
621 */
622 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
623 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
624 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
625 ohci->flags |= OHCI_QUIRK_INITRESET;
626 ohci_dbg (ohci, "enabling initreset quirk\n");
627 goto retry;
628 }
629 spin_unlock_irq (&ohci->lock);
630 ohci_err (ohci, "init err (%08x %04x)\n",
631 ohci_readl (ohci, &ohci->regs->fminterval),
632 ohci_readl (ohci, &ohci->regs->periodicstart));
633 return -EOVERFLOW;
634 }
635
636 /* use rhsc irqs after hub_wq is allocated */
637 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
638 hcd->uses_new_polling = 1;
639
640 /* start controller operations */
641 ohci->hc_control &= OHCI_CTRL_RWC;
642 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
643 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
644 ohci->rh_state = OHCI_RH_RUNNING;
645
646 /* wake on ConnectStatusChange, matching external hubs */
647 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
648
649 /* Choose the interrupts we care about now, others later on demand */
650 mask = OHCI_INTR_INIT;
651 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
652 ohci_writel (ohci, mask, &ohci->regs->intrenable);
653
654 /* handle root hub init quirks ... */
655 val = roothub_a (ohci);
656 val &= ~(RH_A_PSM | RH_A_OCPM);
657 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
658 /* NSC 87560 and maybe others */
659 val |= RH_A_NOCP;
660 val &= ~(RH_A_POTPGT | RH_A_NPS);
661 ohci_writel (ohci, val, &ohci->regs->roothub.a);
662 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
663 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
664 /* hub power always on; required for AMD-756 and some
665 * Mac platforms. ganged overcurrent reporting, if any.
666 */
667 val |= RH_A_NPS;
668 ohci_writel (ohci, val, &ohci->regs->roothub.a);
669 }
670 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
671 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
672 &ohci->regs->roothub.b);
673 // flush those writes
674 (void) ohci_readl (ohci, &ohci->regs->control);
675
676 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
677 spin_unlock_irq (&ohci->lock);
678
679 // POTPGT delay is bits 24-31, in 2 ms units.
680 mdelay ((val >> 23) & 0x1fe);
681
682 ohci_dump(ohci);
683
684 return 0;
685 }
686
687 /* ohci_setup routine for generic controller initialization */
688
689 int ohci_setup(struct usb_hcd *hcd)
690 {
691 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
692
693 ohci_hcd_init(ohci);
694
695 return ohci_init(ohci);
696 }
697 EXPORT_SYMBOL_GPL(ohci_setup);
698
699 /* ohci_start routine for generic controller start of all OHCI bus glue */
700 static int ohci_start(struct usb_hcd *hcd)
701 {
702 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
703 int ret;
704
705 ret = ohci_run(ohci);
706 if (ret < 0) {
707 ohci_err(ohci, "can't start\n");
708 ohci_stop(hcd);
709 }
710 return ret;
711 }
712
713 /*-------------------------------------------------------------------------*/
714
715 /*
716 * Some OHCI controllers are known to lose track of completed TDs. They
717 * don't add the TDs to the hardware done queue, which means we never see
718 * them as being completed.
719 *
720 * This watchdog routine checks for such problems. Without some way to
721 * tell when those TDs have completed, we would never take their EDs off
722 * the unlink list. As a result, URBs could never be dequeued and
723 * endpoints could never be released.
724 */
725 static void io_watchdog_func(struct timer_list *t)
726 {
727 struct ohci_hcd *ohci = from_timer(ohci, t, io_watchdog);
728 bool takeback_all_pending = false;
729 u32 status;
730 u32 head;
731 struct ed *ed;
732 struct td *td, *td_start, *td_next;
733 unsigned frame_no;
734 unsigned long flags;
735
736 spin_lock_irqsave(&ohci->lock, flags);
737
738 /*
739 * One way to lose track of completed TDs is if the controller
740 * never writes back the done queue head. If it hasn't been
741 * written back since the last time this function ran and if it
742 * was non-empty at that time, something is badly wrong with the
743 * hardware.
744 */
745 status = ohci_readl(ohci, &ohci->regs->intrstatus);
746 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
747 if (ohci->prev_donehead) {
748 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
749 died:
750 usb_hc_died(ohci_to_hcd(ohci));
751 ohci_dump(ohci);
752 ohci_shutdown(ohci_to_hcd(ohci));
753 goto done;
754 } else {
755 /* No write back because the done queue was empty */
756 takeback_all_pending = true;
757 }
758 }
759
760 /* Check every ED which might have pending TDs */
761 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
762 if (ed->pending_td) {
763 if (takeback_all_pending ||
764 OKAY_TO_TAKEBACK(ohci, ed)) {
765 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
766
767 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
768 0x007f & tmp,
769 (0x000f & (tmp >> 7)) +
770 ((tmp & ED_IN) >> 5));
771 add_to_done_list(ohci, ed->pending_td);
772 }
773 }
774
775 /* Starting from the latest pending TD, */
776 td = ed->pending_td;
777
778 /* or the last TD on the done list, */
779 if (!td) {
780 list_for_each_entry(td_next, &ed->td_list, td_list) {
781 if (!td_next->next_dl_td)
782 break;
783 td = td_next;
784 }
785 }
786
787 /* find the last TD processed by the controller. */
788 head = hc32_to_cpu(ohci, READ_ONCE(ed->hwHeadP)) & TD_MASK;
789 td_start = td;
790 td_next = list_prepare_entry(td, &ed->td_list, td_list);
791 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
792 if (head == (u32) td_next->td_dma)
793 break;
794 td = td_next; /* head pointer has passed this TD */
795 }
796 if (td != td_start) {
797 /*
798 * In case a WDH cycle is in progress, we will wait
799 * for the next two cycles to complete before assuming
800 * this TD will never get on the done queue.
801 */
802 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
803 ed->pending_td = td;
804 }
805 }
806
807 ohci_work(ohci);
808
809 if (ohci->rh_state == OHCI_RH_RUNNING) {
810
811 /*
812 * Sometimes a controller just stops working. We can tell
813 * by checking that the frame counter has advanced since
814 * the last time we ran.
815 *
816 * But be careful: Some controllers violate the spec by
817 * stopping their frame counter when no ports are active.
818 */
819 frame_no = ohci_frame_no(ohci);
820 if (frame_no == ohci->prev_frame_no) {
821 int active_cnt = 0;
822 int i;
823 unsigned tmp;
824
825 for (i = 0; i < ohci->num_ports; ++i) {
826 tmp = roothub_portstatus(ohci, i);
827 /* Enabled and not suspended? */
828 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
829 ++active_cnt;
830 }
831
832 if (active_cnt > 0) {
833 ohci_err(ohci, "frame counter not updating; disabled\n");
834 goto died;
835 }
836 }
837 if (!list_empty(&ohci->eds_in_use)) {
838 ohci->prev_frame_no = frame_no;
839 ohci->prev_wdh_cnt = ohci->wdh_cnt;
840 ohci->prev_donehead = ohci_readl(ohci,
841 &ohci->regs->donehead);
842 mod_timer(&ohci->io_watchdog,
843 jiffies + IO_WATCHDOG_DELAY);
844 }
845 }
846
847 done:
848 spin_unlock_irqrestore(&ohci->lock, flags);
849 }
850
851 /* an interrupt happens */
852
853 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
854 {
855 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
856 struct ohci_regs __iomem *regs = ohci->regs;
857 int ints;
858
859 /* Read interrupt status (and flush pending writes). We ignore the
860 * optimization of checking the LSB of hcca->done_head; it doesn't
861 * work on all systems (edge triggering for OHCI can be a factor).
862 */
863 ints = ohci_readl(ohci, &regs->intrstatus);
864
865 /* Check for an all 1's result which is a typical consequence
866 * of dead, unclocked, or unplugged (CardBus...) devices
867 */
868 if (ints == ~(u32)0) {
869 ohci->rh_state = OHCI_RH_HALTED;
870 ohci_dbg (ohci, "device removed!\n");
871 usb_hc_died(hcd);
872 return IRQ_HANDLED;
873 }
874
875 /* We only care about interrupts that are enabled */
876 ints &= ohci_readl(ohci, &regs->intrenable);
877
878 /* interrupt for some other device? */
879 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
880 return IRQ_NOTMINE;
881
882 if (ints & OHCI_INTR_UE) {
883 // e.g. due to PCI Master/Target Abort
884 if (quirk_nec(ohci)) {
885 /* Workaround for a silicon bug in some NEC chips used
886 * in Apple's PowerBooks. Adapted from Darwin code.
887 */
888 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
889
890 ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
891
892 schedule_work (&ohci->nec_work);
893 } else {
894 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
895 ohci->rh_state = OHCI_RH_HALTED;
896 usb_hc_died(hcd);
897 }
898
899 ohci_dump(ohci);
900 ohci_usb_reset (ohci);
901 }
902
903 if (ints & OHCI_INTR_RHSC) {
904 ohci_dbg(ohci, "rhsc\n");
905 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
906 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
907 &regs->intrstatus);
908
909 /* NOTE: Vendors didn't always make the same implementation
910 * choices for RHSC. Many followed the spec; RHSC triggers
911 * on an edge, like setting and maybe clearing a port status
912 * change bit. With others it's level-triggered, active
913 * until hub_wq clears all the port status change bits. We'll
914 * always disable it here and rely on polling until hub_wq
915 * re-enables it.
916 */
917 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
918 usb_hcd_poll_rh_status(hcd);
919 }
920
921 /* For connect and disconnect events, we expect the controller
922 * to turn on RHSC along with RD. But for remote wakeup events
923 * this might not happen.
924 */
925 else if (ints & OHCI_INTR_RD) {
926 ohci_dbg(ohci, "resume detect\n");
927 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
928 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
929 if (ohci->autostop) {
930 spin_lock (&ohci->lock);
931 ohci_rh_resume (ohci);
932 spin_unlock (&ohci->lock);
933 } else
934 usb_hcd_resume_root_hub(hcd);
935 }
936
937 spin_lock(&ohci->lock);
938 if (ints & OHCI_INTR_WDH)
939 update_done_list(ohci);
940
941 /* could track INTR_SO to reduce available PCI/... bandwidth */
942
943 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
944 * when there's still unlinking to be done (next frame).
945 */
946 ohci_work(ohci);
947 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
948 && ohci->rh_state == OHCI_RH_RUNNING)
949 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
950
951 if (ohci->rh_state == OHCI_RH_RUNNING) {
952 ohci_writel (ohci, ints, &regs->intrstatus);
953 if (ints & OHCI_INTR_WDH)
954 ++ohci->wdh_cnt;
955
956 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
957 // flush those writes
958 (void) ohci_readl (ohci, &ohci->regs->control);
959 }
960 spin_unlock(&ohci->lock);
961
962 return IRQ_HANDLED;
963 }
964
965 /*-------------------------------------------------------------------------*/
966
967 static void ohci_stop (struct usb_hcd *hcd)
968 {
969 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
970
971 ohci_dump(ohci);
972
973 if (quirk_nec(ohci))
974 flush_work(&ohci->nec_work);
975 del_timer_sync(&ohci->io_watchdog);
976
977 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
978 ohci_usb_reset(ohci);
979 free_irq(hcd->irq, hcd);
980 hcd->irq = 0;
981
982 if (quirk_amdiso(ohci))
983 usb_amd_dev_put();
984
985 remove_debug_files (ohci);
986 ohci_mem_cleanup (ohci);
987 if (ohci->hcca) {
988 dma_free_coherent (hcd->self.controller,
989 sizeof *ohci->hcca,
990 ohci->hcca, ohci->hcca_dma);
991 ohci->hcca = NULL;
992 ohci->hcca_dma = 0;
993 }
994 }
995
996 /*-------------------------------------------------------------------------*/
997
998 #if defined(CONFIG_PM) || defined(CONFIG_USB_PCI)
999
1000 /* must not be called from interrupt context */
1001 int ohci_restart(struct ohci_hcd *ohci)
1002 {
1003 int temp;
1004 int i;
1005 struct urb_priv *priv;
1006
1007 ohci_init(ohci);
1008 spin_lock_irq(&ohci->lock);
1009 ohci->rh_state = OHCI_RH_HALTED;
1010
1011 /* Recycle any "live" eds/tds (and urbs). */
1012 if (!list_empty (&ohci->pending))
1013 ohci_dbg(ohci, "abort schedule...\n");
1014 list_for_each_entry (priv, &ohci->pending, pending) {
1015 struct urb *urb = priv->td[0]->urb;
1016 struct ed *ed = priv->ed;
1017
1018 switch (ed->state) {
1019 case ED_OPER:
1020 ed->state = ED_UNLINK;
1021 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1022 ed_deschedule (ohci, ed);
1023
1024 ed->ed_next = ohci->ed_rm_list;
1025 ed->ed_prev = NULL;
1026 ohci->ed_rm_list = ed;
1027 /* FALLTHROUGH */
1028 case ED_UNLINK:
1029 break;
1030 default:
1031 ohci_dbg(ohci, "bogus ed %p state %d\n",
1032 ed, ed->state);
1033 }
1034
1035 if (!urb->unlinked)
1036 urb->unlinked = -ESHUTDOWN;
1037 }
1038 ohci_work(ohci);
1039 spin_unlock_irq(&ohci->lock);
1040
1041 /* paranoia, in case that didn't work: */
1042
1043 /* empty the interrupt branches */
1044 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1045 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1046
1047 /* no EDs to remove */
1048 ohci->ed_rm_list = NULL;
1049
1050 /* empty control and bulk lists */
1051 ohci->ed_controltail = NULL;
1052 ohci->ed_bulktail = NULL;
1053
1054 if ((temp = ohci_run (ohci)) < 0) {
1055 ohci_err (ohci, "can't restart, %d\n", temp);
1056 return temp;
1057 }
1058 ohci_dbg(ohci, "restart complete\n");
1059 return 0;
1060 }
1061 EXPORT_SYMBOL_GPL(ohci_restart);
1062
1063 #endif
1064
1065 #ifdef CONFIG_PM
1066
1067 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1068 {
1069 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1070 unsigned long flags;
1071 int rc = 0;
1072
1073 /* Disable irq emission and mark HW unaccessible. Use
1074 * the spinlock to properly synchronize with possible pending
1075 * RH suspend or resume activity.
1076 */
1077 spin_lock_irqsave (&ohci->lock, flags);
1078 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1079 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1080
1081 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1082 spin_unlock_irqrestore (&ohci->lock, flags);
1083
1084 synchronize_irq(hcd->irq);
1085
1086 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1087 ohci_resume(hcd, false);
1088 rc = -EBUSY;
1089 }
1090 return rc;
1091 }
1092 EXPORT_SYMBOL_GPL(ohci_suspend);
1093
1094
1095 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1096 {
1097 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1098 int port;
1099 bool need_reinit = false;
1100
1101 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1102
1103 /* Make sure resume from hibernation re-enumerates everything */
1104 if (hibernated)
1105 ohci_usb_reset(ohci);
1106
1107 /* See if the controller is already running or has been reset */
1108 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1109 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1110 need_reinit = true;
1111 } else {
1112 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1113 case OHCI_USB_OPER:
1114 case OHCI_USB_RESET:
1115 need_reinit = true;
1116 }
1117 }
1118
1119 /* If needed, reinitialize and suspend the root hub */
1120 if (need_reinit) {
1121 spin_lock_irq(&ohci->lock);
1122 ohci_rh_resume(ohci);
1123 ohci_rh_suspend(ohci, 0);
1124 spin_unlock_irq(&ohci->lock);
1125 }
1126
1127 /* Normally just turn on port power and enable interrupts */
1128 else {
1129 ohci_dbg(ohci, "powerup ports\n");
1130 for (port = 0; port < ohci->num_ports; port++)
1131 ohci_writel(ohci, RH_PS_PPS,
1132 &ohci->regs->roothub.portstatus[port]);
1133
1134 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1135 ohci_readl(ohci, &ohci->regs->intrenable);
1136 msleep(20);
1137 }
1138
1139 usb_hcd_resume_root_hub(hcd);
1140
1141 return 0;
1142 }
1143 EXPORT_SYMBOL_GPL(ohci_resume);
1144
1145 #endif
1146
1147 /*-------------------------------------------------------------------------*/
1148
1149 /*
1150 * Generic structure: This gets copied for platform drivers so that
1151 * individual entries can be overridden as needed.
1152 */
1153
1154 static const struct hc_driver ohci_hc_driver = {
1155 .description = hcd_name,
1156 .product_desc = "OHCI Host Controller",
1157 .hcd_priv_size = sizeof(struct ohci_hcd),
1158
1159 /*
1160 * generic hardware linkage
1161 */
1162 .irq = ohci_irq,
1163 .flags = HCD_MEMORY | HCD_USB11,
1164
1165 /*
1166 * basic lifecycle operations
1167 */
1168 .reset = ohci_setup,
1169 .start = ohci_start,
1170 .stop = ohci_stop,
1171 .shutdown = ohci_shutdown,
1172
1173 /*
1174 * managing i/o requests and associated device resources
1175 */
1176 .urb_enqueue = ohci_urb_enqueue,
1177 .urb_dequeue = ohci_urb_dequeue,
1178 .endpoint_disable = ohci_endpoint_disable,
1179
1180 /*
1181 * scheduling support
1182 */
1183 .get_frame_number = ohci_get_frame,
1184
1185 /*
1186 * root hub support
1187 */
1188 .hub_status_data = ohci_hub_status_data,
1189 .hub_control = ohci_hub_control,
1190 #ifdef CONFIG_PM
1191 .bus_suspend = ohci_bus_suspend,
1192 .bus_resume = ohci_bus_resume,
1193 #endif
1194 .start_port_reset = ohci_start_port_reset,
1195 };
1196
1197 void ohci_init_driver(struct hc_driver *drv,
1198 const struct ohci_driver_overrides *over)
1199 {
1200 /* Copy the generic table to drv and then apply the overrides */
1201 *drv = ohci_hc_driver;
1202
1203 if (over) {
1204 drv->product_desc = over->product_desc;
1205 drv->hcd_priv_size += over->extra_priv_size;
1206 if (over->reset)
1207 drv->reset = over->reset;
1208 }
1209 }
1210 EXPORT_SYMBOL_GPL(ohci_init_driver);
1211
1212 /*-------------------------------------------------------------------------*/
1213
1214 MODULE_AUTHOR (DRIVER_AUTHOR);
1215 MODULE_DESCRIPTION(DRIVER_DESC);
1216 MODULE_LICENSE ("GPL");
1217
1218 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1219 #include "ohci-sa1111.c"
1220 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1221 #endif
1222
1223 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1224 #include "ohci-ppc-of.c"
1225 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1226 #endif
1227
1228 #ifdef CONFIG_PPC_PS3
1229 #include "ohci-ps3.c"
1230 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1231 #endif
1232
1233 #ifdef CONFIG_MFD_SM501
1234 #include "ohci-sm501.c"
1235 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1236 #endif
1237
1238 #ifdef CONFIG_MFD_TC6393XB
1239 #include "ohci-tmio.c"
1240 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1241 #endif
1242
1243 #ifdef CONFIG_TILE_USB
1244 #include "ohci-tilegx.c"
1245 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1246 #endif
1247
1248 static int __init ohci_hcd_mod_init(void)
1249 {
1250 int retval = 0;
1251
1252 if (usb_disabled())
1253 return -ENODEV;
1254
1255 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1256 pr_debug ("%s: block sizes: ed %zd td %zd\n", hcd_name,
1257 sizeof (struct ed), sizeof (struct td));
1258 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1259
1260 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1261 if (!ohci_debug_root) {
1262 retval = -ENOENT;
1263 goto error_debug;
1264 }
1265
1266 #ifdef PS3_SYSTEM_BUS_DRIVER
1267 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1268 if (retval < 0)
1269 goto error_ps3;
1270 #endif
1271
1272 #ifdef PLATFORM_DRIVER
1273 retval = platform_driver_register(&PLATFORM_DRIVER);
1274 if (retval < 0)
1275 goto error_platform;
1276 #endif
1277
1278 #ifdef OF_PLATFORM_DRIVER
1279 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1280 if (retval < 0)
1281 goto error_of_platform;
1282 #endif
1283
1284 #ifdef SA1111_DRIVER
1285 retval = sa1111_driver_register(&SA1111_DRIVER);
1286 if (retval < 0)
1287 goto error_sa1111;
1288 #endif
1289
1290 #ifdef SM501_OHCI_DRIVER
1291 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1292 if (retval < 0)
1293 goto error_sm501;
1294 #endif
1295
1296 #ifdef TMIO_OHCI_DRIVER
1297 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1298 if (retval < 0)
1299 goto error_tmio;
1300 #endif
1301
1302 return retval;
1303
1304 /* Error path */
1305 #ifdef TMIO_OHCI_DRIVER
1306 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1307 error_tmio:
1308 #endif
1309 #ifdef SM501_OHCI_DRIVER
1310 platform_driver_unregister(&SM501_OHCI_DRIVER);
1311 error_sm501:
1312 #endif
1313 #ifdef SA1111_DRIVER
1314 sa1111_driver_unregister(&SA1111_DRIVER);
1315 error_sa1111:
1316 #endif
1317 #ifdef OF_PLATFORM_DRIVER
1318 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1319 error_of_platform:
1320 #endif
1321 #ifdef PLATFORM_DRIVER
1322 platform_driver_unregister(&PLATFORM_DRIVER);
1323 error_platform:
1324 #endif
1325 #ifdef PS3_SYSTEM_BUS_DRIVER
1326 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1327 error_ps3:
1328 #endif
1329 debugfs_remove(ohci_debug_root);
1330 ohci_debug_root = NULL;
1331 error_debug:
1332
1333 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1334 return retval;
1335 }
1336 module_init(ohci_hcd_mod_init);
1337
1338 static void __exit ohci_hcd_mod_exit(void)
1339 {
1340 #ifdef TMIO_OHCI_DRIVER
1341 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1342 #endif
1343 #ifdef SM501_OHCI_DRIVER
1344 platform_driver_unregister(&SM501_OHCI_DRIVER);
1345 #endif
1346 #ifdef SA1111_DRIVER
1347 sa1111_driver_unregister(&SA1111_DRIVER);
1348 #endif
1349 #ifdef OF_PLATFORM_DRIVER
1350 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1351 #endif
1352 #ifdef PLATFORM_DRIVER
1353 platform_driver_unregister(&PLATFORM_DRIVER);
1354 #endif
1355 #ifdef PS3_SYSTEM_BUS_DRIVER
1356 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1357 #endif
1358 debugfs_remove(ohci_debug_root);
1359 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1360 }
1361 module_exit(ohci_hcd_mod_exit);
1362
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