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Merge branch 'master' of git://git.denx.de/u-boot-i2c
[people/ms/u-boot.git] / drivers / usb / host / ohci-s3c24xx.c
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
6 *
7 * Note: Much of this code has been derived from Linux 2.4
8 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
9 * (C) Copyright 2000-2002 David Brownell
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13 /*
14 * IMPORTANT NOTES
15 * 1 - this driver is intended for use with USB Mass Storage Devices
16 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
17 */
18
19 #include <common.h>
20 /* #include <pci.h> no PCI on the S3C24X0 */
21
22 #if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
23
24 #include <asm/arch/s3c24x0_cpu.h>
25 #include <asm/io.h>
26 #include <malloc.h>
27 #include <usb.h>
28 #include "ohci-s3c24xx.h"
29
30 #define OHCI_USE_NPS /* force NoPowerSwitching mode */
31 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
32
33
34 /* For initializing controller (mask in an HCFS mode too) */
35 #define OHCI_CONTROL_INIT \
36 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
37
38 #define min_t(type, x, y) \
39 ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
40
41 #undef DEBUG
42 #ifdef DEBUG
43 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
44 #else
45 #define dbg(format, arg...) do {} while(0)
46 #endif /* DEBUG */
47 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
48 #undef SHOW_INFO
49 #ifdef SHOW_INFO
50 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
51 #else
52 #define info(format, arg...) do {} while(0)
53 #endif
54
55 #define m16_swap(x) swap_16(x)
56 #define m32_swap(x) swap_32(x)
57
58 /* global struct ohci */
59 static struct ohci gohci;
60 /* this must be aligned to a 256 byte boundary */
61 struct ohci_hcca ghcca[1];
62 /* a pointer to the aligned storage */
63 struct ohci_hcca *phcca;
64 /* this allocates EDs for all possible endpoints */
65 struct ohci_device ohci_dev;
66 /* urb_priv */
67 struct urb_priv urb_priv;
68 /* RHSC flag */
69 int got_rhsc;
70 /* device which was disconnected */
71 struct usb_device *devgone;
72 /* flag guarding URB transation */
73 int urb_finished = 0;
74
75 /*-------------------------------------------------------------------------*/
76
77 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
78 * The erratum (#4) description is incorrect. AMD's workaround waits
79 * till some bits (mostly reserved) are clear; ok for all revs.
80 */
81 #define OHCI_QUIRK_AMD756 0xabcd
82 #define read_roothub(hc, register, mask) ({ \
83 u32 temp = readl (&hc->regs->roothub.register); \
84 if (hc->flags & OHCI_QUIRK_AMD756) \
85 while (temp & mask) \
86 temp = readl (&hc->regs->roothub.register); \
87 temp; })
88
89 static u32 roothub_a(struct ohci *hc)
90 {
91 return read_roothub(hc, a, 0xfc0fe000);
92 }
93 static inline u32 roothub_b(struct ohci *hc)
94 {
95 return readl(&hc->regs->roothub.b);
96 }
97 static inline u32 roothub_status(struct ohci *hc)
98 {
99 return readl(&hc->regs->roothub.status);
100 }
101 static u32 roothub_portstatus(struct ohci *hc, int i)
102 {
103 return read_roothub(hc, portstatus[i], 0xffe0fce0);
104 }
105
106 /* forward declaration */
107 static int hc_interrupt(void);
108 static void td_submit_job(struct usb_device *dev, unsigned long pipe,
109 void *buffer, int transfer_len,
110 struct devrequest *setup, struct urb_priv *urb,
111 int interval);
112
113 /*-------------------------------------------------------------------------*
114 * URB support functions
115 *-------------------------------------------------------------------------*/
116
117 /* free HCD-private data associated with this URB */
118
119 static void urb_free_priv(struct urb_priv *urb)
120 {
121 int i;
122 int last;
123 struct td *td;
124
125 last = urb->length - 1;
126 if (last >= 0) {
127 for (i = 0; i <= last; i++) {
128 td = urb->td[i];
129 if (td) {
130 td->usb_dev = NULL;
131 urb->td[i] = NULL;
132 }
133 }
134 }
135 }
136
137 /*-------------------------------------------------------------------------*/
138
139 #ifdef DEBUG
140 static int sohci_get_current_frame_number(struct usb_device *dev);
141
142 /* debug| print the main components of an URB
143 * small: 0) header + data packets 1) just header */
144
145 static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
146 int transfer_len, struct devrequest *setup, char *str,
147 int small)
148 {
149 struct urb_priv *purb = &urb_priv;
150
151 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
152 str,
153 sohci_get_current_frame_number(dev),
154 usb_pipedevice(pipe),
155 usb_pipeendpoint(pipe),
156 usb_pipeout(pipe) ? 'O' : 'I',
157 usb_pipetype(pipe) < 2 ?
158 (usb_pipeint(pipe) ? "INTR" : "ISOC") :
159 (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
160 purb->actual_length, transfer_len, dev->status);
161 #ifdef OHCI_VERBOSE_DEBUG
162 if (!small) {
163 int i, len;
164
165 if (usb_pipecontrol(pipe)) {
166 printf(__FILE__ ": cmd(8):");
167 for (i = 0; i < 8; i++)
168 printf(" %02x", ((__u8 *) setup)[i]);
169 printf("\n");
170 }
171 if (transfer_len > 0 && buffer) {
172 printf(__FILE__ ": data(%d/%d):",
173 purb->actual_length, transfer_len);
174 len = usb_pipeout(pipe) ?
175 transfer_len : purb->actual_length;
176 for (i = 0; i < 16 && i < len; i++)
177 printf(" %02x", ((__u8 *) buffer)[i]);
178 printf("%s\n", i < len ? "..." : "");
179 }
180 }
181 #endif
182 }
183
184 /* just for debugging; prints non-empty branches of the
185 int ed tree inclusive iso eds*/
186 void ep_print_int_eds(struct ohci *ohci, char *str)
187 {
188 int i, j;
189 __u32 *ed_p;
190 for (i = 0; i < 32; i++) {
191 j = 5;
192 ed_p = &(ohci->hcca->int_table[i]);
193 if (*ed_p == 0)
194 continue;
195 printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
196 while (*ed_p != 0 && j--) {
197 struct ed *ed = (struct ed *) m32_swap(ed_p);
198 printf(" ed: %4x;", ed->hwINFO);
199 ed_p = &ed->hwNextED;
200 }
201 printf("\n");
202 }
203 }
204
205 static void ohci_dump_intr_mask(char *label, __u32 mask)
206 {
207 dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
208 label,
209 mask,
210 (mask & OHCI_INTR_MIE) ? " MIE" : "",
211 (mask & OHCI_INTR_OC) ? " OC" : "",
212 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
213 (mask & OHCI_INTR_FNO) ? " FNO" : "",
214 (mask & OHCI_INTR_UE) ? " UE" : "",
215 (mask & OHCI_INTR_RD) ? " RD" : "",
216 (mask & OHCI_INTR_SF) ? " SF" : "",
217 (mask & OHCI_INTR_WDH) ? " WDH" : "",
218 (mask & OHCI_INTR_SO) ? " SO" : "");
219 }
220
221 static void maybe_print_eds(char *label, __u32 value)
222 {
223 struct ed *edp = (struct ed *) value;
224
225 if (value) {
226 dbg("%s %08x", label, value);
227 dbg("%08x", edp->hwINFO);
228 dbg("%08x", edp->hwTailP);
229 dbg("%08x", edp->hwHeadP);
230 dbg("%08x", edp->hwNextED);
231 }
232 }
233
234 static char *hcfs2string(int state)
235 {
236 switch (state) {
237 case OHCI_USB_RESET:
238 return "reset";
239 case OHCI_USB_RESUME:
240 return "resume";
241 case OHCI_USB_OPER:
242 return "operational";
243 case OHCI_USB_SUSPEND:
244 return "suspend";
245 }
246 return "?";
247 }
248
249 /* dump control and status registers */
250 static void ohci_dump_status(struct ohci *controller)
251 {
252 struct ohci_regs *regs = controller->regs;
253 __u32 temp;
254
255 temp = readl(&regs->revision) & 0xff;
256 if (temp != 0x10)
257 dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
258
259 temp = readl(&regs->control);
260 dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
261 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
262 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
263 (temp & OHCI_CTRL_IR) ? " IR" : "",
264 hcfs2string(temp & OHCI_CTRL_HCFS),
265 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
266 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
267 (temp & OHCI_CTRL_IE) ? " IE" : "",
268 (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
269
270 temp = readl(&regs->cmdstatus);
271 dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
272 (temp & OHCI_SOC) >> 16,
273 (temp & OHCI_OCR) ? " OCR" : "",
274 (temp & OHCI_BLF) ? " BLF" : "",
275 (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
276
277 ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
278 ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
279
280 maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
281
282 maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
283 maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
284
285 maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
286 maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
287
288 maybe_print_eds("donehead", readl(&regs->donehead));
289 }
290
291 static void ohci_dump_roothub(struct ohci *controller, int verbose)
292 {
293 __u32 temp, ndp, i;
294
295 temp = roothub_a(controller);
296 ndp = (temp & RH_A_NDP);
297
298 if (verbose) {
299 dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
300 ((temp & RH_A_POTPGT) >> 24) & 0xff,
301 (temp & RH_A_NOCP) ? " NOCP" : "",
302 (temp & RH_A_OCPM) ? " OCPM" : "",
303 (temp & RH_A_DT) ? " DT" : "",
304 (temp & RH_A_NPS) ? " NPS" : "",
305 (temp & RH_A_PSM) ? " PSM" : "", ndp);
306 temp = roothub_b(controller);
307 dbg("roothub.b: %08x PPCM=%04x DR=%04x",
308 temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
309 );
310 temp = roothub_status(controller);
311 dbg("roothub.status: %08x%s%s%s%s%s%s",
312 temp,
313 (temp & RH_HS_CRWE) ? " CRWE" : "",
314 (temp & RH_HS_OCIC) ? " OCIC" : "",
315 (temp & RH_HS_LPSC) ? " LPSC" : "",
316 (temp & RH_HS_DRWE) ? " DRWE" : "",
317 (temp & RH_HS_OCI) ? " OCI" : "",
318 (temp & RH_HS_LPS) ? " LPS" : "");
319 }
320
321 for (i = 0; i < ndp; i++) {
322 temp = roothub_portstatus(controller, i);
323 dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
324 i,
325 temp,
326 (temp & RH_PS_PRSC) ? " PRSC" : "",
327 (temp & RH_PS_OCIC) ? " OCIC" : "",
328 (temp & RH_PS_PSSC) ? " PSSC" : "",
329 (temp & RH_PS_PESC) ? " PESC" : "",
330 (temp & RH_PS_CSC) ? " CSC" : "",
331 (temp & RH_PS_LSDA) ? " LSDA" : "",
332 (temp & RH_PS_PPS) ? " PPS" : "",
333 (temp & RH_PS_PRS) ? " PRS" : "",
334 (temp & RH_PS_POCI) ? " POCI" : "",
335 (temp & RH_PS_PSS) ? " PSS" : "",
336 (temp & RH_PS_PES) ? " PES" : "",
337 (temp & RH_PS_CCS) ? " CCS" : "");
338 }
339 }
340
341 static void ohci_dump(struct ohci *controller, int verbose)
342 {
343 dbg("OHCI controller usb-%s state", controller->slot_name);
344
345 /* dumps some of the state we know about */
346 ohci_dump_status(controller);
347 if (verbose)
348 ep_print_int_eds(controller, "hcca");
349 dbg("hcca frame #%04x", controller->hcca->frame_no);
350 ohci_dump_roothub(controller, 1);
351 }
352
353 #endif /* DEBUG */
354
355 /*-------------------------------------------------------------------------*
356 * Interface functions (URB)
357 *-------------------------------------------------------------------------*/
358
359 /* get a transfer request */
360
361 int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
362 int transfer_len, struct devrequest *setup, int interval)
363 {
364 struct ohci *ohci;
365 struct ed *ed;
366 struct urb_priv *purb_priv;
367 int i, size = 0;
368
369 ohci = &gohci;
370
371 /* when controller's hung, permit only roothub cleanup attempts
372 * such as powering down ports */
373 if (ohci->disabled) {
374 err("sohci_submit_job: EPIPE");
375 return -1;
376 }
377
378 /* if we have an unfinished URB from previous transaction let's
379 * fail and scream as quickly as possible so as not to corrupt
380 * further communication */
381 if (!urb_finished) {
382 err("sohci_submit_job: URB NOT FINISHED");
383 return -1;
384 }
385 /* we're about to begin a new transaction here
386 so mark the URB unfinished */
387 urb_finished = 0;
388
389 /* every endpoint has a ed, locate and fill it */
390 ed = ep_add_ed(dev, pipe);
391 if (!ed) {
392 err("sohci_submit_job: ENOMEM");
393 return -1;
394 }
395
396 /* for the private part of the URB we need the number of TDs (size) */
397 switch (usb_pipetype(pipe)) {
398 case PIPE_BULK:
399 /* one TD for every 4096 Byte */
400 size = (transfer_len - 1) / 4096 + 1;
401 break;
402 case PIPE_CONTROL:
403 /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
404 size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
405 break;
406 }
407
408 if (size >= (N_URB_TD - 1)) {
409 err("need %d TDs, only have %d", size, N_URB_TD);
410 return -1;
411 }
412 purb_priv = &urb_priv;
413 purb_priv->pipe = pipe;
414
415 /* fill the private part of the URB */
416 purb_priv->length = size;
417 purb_priv->ed = ed;
418 purb_priv->actual_length = 0;
419
420 /* allocate the TDs */
421 /* note that td[0] was allocated in ep_add_ed */
422 for (i = 0; i < size; i++) {
423 purb_priv->td[i] = td_alloc(dev);
424 if (!purb_priv->td[i]) {
425 purb_priv->length = i;
426 urb_free_priv(purb_priv);
427 err("sohci_submit_job: ENOMEM");
428 return -1;
429 }
430 }
431
432 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
433 urb_free_priv(purb_priv);
434 err("sohci_submit_job: EINVAL");
435 return -1;
436 }
437
438 /* link the ed into a chain if is not already */
439 if (ed->state != ED_OPER)
440 ep_link(ohci, ed);
441
442 /* fill the TDs and link it to the ed */
443 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
444 interval);
445
446 return 0;
447 }
448
449 /*-------------------------------------------------------------------------*/
450
451 #ifdef DEBUG
452 /* tell us the current USB frame number */
453
454 static int sohci_get_current_frame_number(struct usb_device *usb_dev)
455 {
456 struct ohci *ohci = &gohci;
457
458 return m16_swap(ohci->hcca->frame_no);
459 }
460 #endif
461
462 /*-------------------------------------------------------------------------*
463 * ED handling functions
464 *-------------------------------------------------------------------------*/
465
466 /* link an ed into one of the HC chains */
467
468 static int ep_link(struct ohci *ohci, struct ed *edi)
469 {
470 struct ed *ed = edi;
471
472 ed->state = ED_OPER;
473
474 switch (ed->type) {
475 case PIPE_CONTROL:
476 ed->hwNextED = 0;
477 if (ohci->ed_controltail == NULL) {
478 writel((u32)ed, &ohci->regs->ed_controlhead);
479 } else {
480 ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
481 }
482 ed->ed_prev = ohci->ed_controltail;
483 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
484 !ohci->ed_rm_list[1] && !ohci->sleeping) {
485 ohci->hc_control |= OHCI_CTRL_CLE;
486 writel(ohci->hc_control, &ohci->regs->control);
487 }
488 ohci->ed_controltail = edi;
489 break;
490
491 case PIPE_BULK:
492 ed->hwNextED = 0;
493 if (ohci->ed_bulktail == NULL) {
494 writel((u32)ed, &ohci->regs->ed_bulkhead);
495 } else {
496 ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
497 }
498 ed->ed_prev = ohci->ed_bulktail;
499 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
500 !ohci->ed_rm_list[1] && !ohci->sleeping) {
501 ohci->hc_control |= OHCI_CTRL_BLE;
502 writel(ohci->hc_control, &ohci->regs->control);
503 }
504 ohci->ed_bulktail = edi;
505 break;
506 }
507 return 0;
508 }
509
510 /*-------------------------------------------------------------------------*/
511
512 /* unlink an ed from one of the HC chains.
513 * just the link to the ed is unlinked.
514 * the link from the ed still points to another operational ed or 0
515 * so the HC can eventually finish the processing of the unlinked ed */
516
517 static int ep_unlink(struct ohci *ohci, struct ed *ed)
518 {
519 struct ed *next;
520 ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
521
522 switch (ed->type) {
523 case PIPE_CONTROL:
524 if (ed->ed_prev == NULL) {
525 if (!ed->hwNextED) {
526 ohci->hc_control &= ~OHCI_CTRL_CLE;
527 writel(ohci->hc_control, &ohci->regs->control);
528 }
529 writel(m32_swap(*((__u32 *) &ed->hwNextED)),
530 &ohci->regs->ed_controlhead);
531 } else {
532 ed->ed_prev->hwNextED = ed->hwNextED;
533 }
534 if (ohci->ed_controltail == ed) {
535 ohci->ed_controltail = ed->ed_prev;
536 } else {
537 next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
538 next->ed_prev = ed->ed_prev;
539 }
540 break;
541
542 case PIPE_BULK:
543 if (ed->ed_prev == NULL) {
544 if (!ed->hwNextED) {
545 ohci->hc_control &= ~OHCI_CTRL_BLE;
546 writel(ohci->hc_control, &ohci->regs->control);
547 }
548 writel(m32_swap(*((__u32 *) &ed->hwNextED)),
549 &ohci->regs->ed_bulkhead);
550 } else {
551 ed->ed_prev->hwNextED = ed->hwNextED;
552 }
553 if (ohci->ed_bulktail == ed) {
554 ohci->ed_bulktail = ed->ed_prev;
555 } else {
556 next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
557 next->ed_prev = ed->ed_prev;
558 }
559 break;
560 }
561 ed->state = ED_UNLINK;
562 return 0;
563 }
564
565 /*-------------------------------------------------------------------------*/
566
567 /* add/reinit an endpoint; this should be done once at the usb_set_configuration
568 * command, but the USB stack is a little bit stateless so we do it at every
569 * transaction. If the state of the ed is ED_NEW then a dummy td is added and
570 * the state is changed to ED_UNLINK. In all other cases the state is left
571 * unchanged. The ed info fields are setted anyway even though most of them
572 * should not change */
573
574 static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
575 {
576 struct td *td;
577 struct ed *ed_ret;
578 struct ed *ed;
579
580 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
581 (usb_pipecontrol(pipe) ? 0 :
582 usb_pipeout(pipe))];
583
584 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
585 err("ep_add_ed: pending delete");
586 /* pending delete request */
587 return NULL;
588 }
589
590 if (ed->state == ED_NEW) {
591 ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
592 /* dummy td; end of td list for ed */
593 td = td_alloc(usb_dev);
594 ed->hwTailP = (__u32) m32_swap(td);
595 ed->hwHeadP = ed->hwTailP;
596 ed->state = ED_UNLINK;
597 ed->type = usb_pipetype(pipe);
598 ohci_dev.ed_cnt++;
599 }
600
601 ed->hwINFO = m32_swap(usb_pipedevice(pipe)
602 | usb_pipeendpoint(pipe) << 7
603 | (usb_pipeisoc(pipe) ? 0x8000 : 0)
604 | (usb_pipecontrol(pipe) ? 0 :
605 (usb_pipeout(pipe) ? 0x800 : 0x1000))
606 | (usb_dev->speed == USB_SPEED_LOW) << 13 |
607 usb_maxpacket(usb_dev, pipe) << 16);
608
609 return ed_ret;
610 }
611
612 /*-------------------------------------------------------------------------*
613 * TD handling functions
614 *-------------------------------------------------------------------------*/
615
616 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
617
618 static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
619 struct usb_device *dev, int index,
620 struct urb_priv *urb_priv)
621 {
622 struct td *td, *td_pt;
623 #ifdef OHCI_FILL_TRACE
624 int i;
625 #endif
626
627 if (index > urb_priv->length) {
628 err("index > length");
629 return;
630 }
631 /* use this td as the next dummy */
632 td_pt = urb_priv->td[index];
633 td_pt->hwNextTD = 0;
634
635 /* fill the old dummy TD */
636 td = urb_priv->td[index] =
637 (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
638
639 td->ed = urb_priv->ed;
640 td->next_dl_td = NULL;
641 td->index = index;
642 td->data = (__u32) data;
643 #ifdef OHCI_FILL_TRACE
644 if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
645 for (i = 0; i < len; i++)
646 printf("td->data[%d] %#2x ", i,
647 ((unsigned char *)td->data)[i]);
648 printf("\n");
649 }
650 #endif
651 if (!len)
652 data = 0;
653
654 td->hwINFO = (__u32) m32_swap(info);
655 td->hwCBP = (__u32) m32_swap(data);
656 if (data)
657 td->hwBE = (__u32) m32_swap(data + len - 1);
658 else
659 td->hwBE = 0;
660 td->hwNextTD = (__u32) m32_swap(td_pt);
661
662 /* append to queue */
663 td->ed->hwTailP = td->hwNextTD;
664 }
665
666 /*-------------------------------------------------------------------------*/
667
668 /* prepare all TDs of a transfer */
669
670 static void td_submit_job(struct usb_device *dev, unsigned long pipe,
671 void *buffer, int transfer_len,
672 struct devrequest *setup, struct urb_priv *urb,
673 int interval)
674 {
675 struct ohci *ohci = &gohci;
676 int data_len = transfer_len;
677 void *data;
678 int cnt = 0;
679 __u32 info = 0;
680 unsigned int toggle = 0;
681
682 /* OHCI handles the DATA-toggles itself, we just
683 use the USB-toggle bits for reseting */
684 if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
685 toggle = TD_T_TOGGLE;
686 } else {
687 toggle = TD_T_DATA0;
688 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
689 1);
690 }
691 urb->td_cnt = 0;
692 if (data_len)
693 data = buffer;
694 else
695 data = 0;
696
697 switch (usb_pipetype(pipe)) {
698 case PIPE_BULK:
699 info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
700 while (data_len > 4096) {
701 td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
702 4096, dev, cnt, urb);
703 data += 4096;
704 data_len -= 4096;
705 cnt++;
706 }
707 info = usb_pipeout(pipe) ?
708 TD_CC | TD_DP_OUT :
709 TD_CC | TD_R | TD_DP_IN;
710 td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
711 data_len, dev, cnt, urb);
712 cnt++;
713
714 if (!ohci->sleeping)
715 /* start bulk list */
716 writel(OHCI_BLF, &ohci->regs->cmdstatus);
717 break;
718
719 case PIPE_CONTROL:
720 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
721 td_fill(ohci, info, setup, 8, dev, cnt++, urb);
722 if (data_len > 0) {
723 info = usb_pipeout(pipe) ?
724 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
725 TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
726 /* NOTE: mishandles transfers >8K, some >4K */
727 td_fill(ohci, info, data, data_len, dev, cnt++, urb);
728 }
729 info = usb_pipeout(pipe) ?
730 TD_CC | TD_DP_IN | TD_T_DATA1 :
731 TD_CC | TD_DP_OUT | TD_T_DATA1;
732 td_fill(ohci, info, data, 0, dev, cnt++, urb);
733 if (!ohci->sleeping)
734 /* start Control list */
735 writel(OHCI_CLF, &ohci->regs->cmdstatus);
736 break;
737 }
738 if (urb->length != cnt)
739 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
740 }
741
742 /*-------------------------------------------------------------------------*
743 * Done List handling functions
744 *-------------------------------------------------------------------------*/
745
746
747 /* calculate the transfer length and update the urb */
748
749 static void dl_transfer_length(struct td *td)
750 {
751 __u32 tdBE, tdCBP;
752 struct urb_priv *lurb_priv = &urb_priv;
753
754 tdBE = m32_swap(td->hwBE);
755 tdCBP = m32_swap(td->hwCBP);
756
757 if (!(usb_pipecontrol(lurb_priv->pipe) &&
758 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
759 if (tdBE != 0) {
760 if (td->hwCBP == 0)
761 lurb_priv->actual_length += tdBE - td->data + 1;
762 else
763 lurb_priv->actual_length += tdCBP - td->data;
764 }
765 }
766 }
767
768 /*-------------------------------------------------------------------------*/
769
770 /* replies to the request have to be on a FIFO basis so
771 * we reverse the reversed done-list */
772
773 static struct td *dl_reverse_done_list(struct ohci *ohci)
774 {
775 __u32 td_list_hc;
776 __u32 tmp;
777 struct td *td_rev = NULL;
778 struct td *td_list = NULL;
779 struct urb_priv *lurb_priv = NULL;
780
781 td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
782 ohci->hcca->done_head = 0;
783
784 while (td_list_hc) {
785 td_list = (struct td *) td_list_hc;
786
787 if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
788 lurb_priv = &urb_priv;
789 dbg(" USB-error/status: %x : %p",
790 TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
791 if (td_list->ed->hwHeadP & m32_swap(0x1)) {
792 if (lurb_priv &&
793 ((td_list->index+1) < lurb_priv->length)) {
794 tmp = lurb_priv->length - 1;
795 td_list->ed->hwHeadP =
796 (lurb_priv->td[tmp]->hwNextTD &
797 m32_swap(0xfffffff0)) |
798 (td_list->ed->hwHeadP &
799 m32_swap(0x2));
800 lurb_priv->td_cnt += lurb_priv->length -
801 td_list->index - 1;
802 } else
803 td_list->ed->hwHeadP &=
804 m32_swap(0xfffffff2);
805 }
806 }
807
808 td_list->next_dl_td = td_rev;
809 td_rev = td_list;
810 td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
811 }
812
813 return td_list;
814 }
815
816 /*-------------------------------------------------------------------------*/
817
818 /* td done list */
819 static int dl_done_list(struct ohci *ohci, struct td *td_list)
820 {
821 struct td *td_list_next = NULL;
822 struct ed *ed;
823 int cc = 0;
824 int stat = 0;
825 /* urb_t *urb; */
826 struct urb_priv *lurb_priv;
827 __u32 tdINFO, edHeadP, edTailP;
828
829 while (td_list) {
830 td_list_next = td_list->next_dl_td;
831
832 lurb_priv = &urb_priv;
833 tdINFO = m32_swap(td_list->hwINFO);
834
835 ed = td_list->ed;
836
837 dl_transfer_length(td_list);
838
839 /* error code of transfer */
840 cc = TD_CC_GET(tdINFO);
841 if (cc != 0) {
842 dbg("ConditionCode %#x", cc);
843 stat = cc_to_error[cc];
844 }
845
846 /* see if this done list makes for all TD's of current URB,
847 * and mark the URB finished if so */
848 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
849 if ((ed->state & (ED_OPER | ED_UNLINK)))
850 urb_finished = 1;
851 else
852 dbg("dl_done_list: strange.., ED state %x, "
853 "ed->state\n");
854 } else
855 dbg("dl_done_list: processing TD %x, len %x\n",
856 lurb_priv->td_cnt, lurb_priv->length);
857
858 if (ed->state != ED_NEW) {
859 edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
860 edTailP = m32_swap(ed->hwTailP);
861
862 /* unlink eds if they are not busy */
863 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
864 ep_unlink(ohci, ed);
865 }
866
867 td_list = td_list_next;
868 }
869 return stat;
870 }
871
872 /*-------------------------------------------------------------------------*
873 * Virtual Root Hub
874 *-------------------------------------------------------------------------*/
875
876 /* Device descriptor */
877 static __u8 root_hub_dev_des[] = {
878 0x12, /* __u8 bLength; */
879 0x01, /* __u8 bDescriptorType; Device */
880 0x10, /* __u16 bcdUSB; v1.1 */
881 0x01,
882 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
883 0x00, /* __u8 bDeviceSubClass; */
884 0x00, /* __u8 bDeviceProtocol; */
885 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
886 0x00, /* __u16 idVendor; */
887 0x00,
888 0x00, /* __u16 idProduct; */
889 0x00,
890 0x00, /* __u16 bcdDevice; */
891 0x00,
892 0x00, /* __u8 iManufacturer; */
893 0x01, /* __u8 iProduct; */
894 0x00, /* __u8 iSerialNumber; */
895 0x01 /* __u8 bNumConfigurations; */
896 };
897
898 /* Configuration descriptor */
899 static __u8 root_hub_config_des[] = {
900 0x09, /* __u8 bLength; */
901 0x02, /* __u8 bDescriptorType; Configuration */
902 0x19, /* __u16 wTotalLength; */
903 0x00,
904 0x01, /* __u8 bNumInterfaces; */
905 0x01, /* __u8 bConfigurationValue; */
906 0x00, /* __u8 iConfiguration; */
907 0x40, /* __u8 bmAttributes;
908 Bit 7: Bus-powered, 6: Self-powered,
909 5 Remote-wakwup, 4..0: resvd */
910 0x00, /* __u8 MaxPower; */
911
912 /* interface */
913 0x09, /* __u8 if_bLength; */
914 0x04, /* __u8 if_bDescriptorType; Interface */
915 0x00, /* __u8 if_bInterfaceNumber; */
916 0x00, /* __u8 if_bAlternateSetting; */
917 0x01, /* __u8 if_bNumEndpoints; */
918 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
919 0x00, /* __u8 if_bInterfaceSubClass; */
920 0x00, /* __u8 if_bInterfaceProtocol; */
921 0x00, /* __u8 if_iInterface; */
922
923 /* endpoint */
924 0x07, /* __u8 ep_bLength; */
925 0x05, /* __u8 ep_bDescriptorType; Endpoint */
926 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
927 0x03, /* __u8 ep_bmAttributes; Interrupt */
928 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
929 0x00,
930 0xff /* __u8 ep_bInterval; 255 ms */
931 };
932
933 static unsigned char root_hub_str_index0[] = {
934 0x04, /* __u8 bLength; */
935 0x03, /* __u8 bDescriptorType; String-descriptor */
936 0x09, /* __u8 lang ID */
937 0x04, /* __u8 lang ID */
938 };
939
940 static unsigned char root_hub_str_index1[] = {
941 28, /* __u8 bLength; */
942 0x03, /* __u8 bDescriptorType; String-descriptor */
943 'O', /* __u8 Unicode */
944 0, /* __u8 Unicode */
945 'H', /* __u8 Unicode */
946 0, /* __u8 Unicode */
947 'C', /* __u8 Unicode */
948 0, /* __u8 Unicode */
949 'I', /* __u8 Unicode */
950 0, /* __u8 Unicode */
951 ' ', /* __u8 Unicode */
952 0, /* __u8 Unicode */
953 'R', /* __u8 Unicode */
954 0, /* __u8 Unicode */
955 'o', /* __u8 Unicode */
956 0, /* __u8 Unicode */
957 'o', /* __u8 Unicode */
958 0, /* __u8 Unicode */
959 't', /* __u8 Unicode */
960 0, /* __u8 Unicode */
961 ' ', /* __u8 Unicode */
962 0, /* __u8 Unicode */
963 'H', /* __u8 Unicode */
964 0, /* __u8 Unicode */
965 'u', /* __u8 Unicode */
966 0, /* __u8 Unicode */
967 'b', /* __u8 Unicode */
968 0, /* __u8 Unicode */
969 };
970
971 /* Hub class-specific descriptor is constructed dynamically */
972
973
974 /*-------------------------------------------------------------------------*/
975
976 #define OK(x) len = (x); break
977 #ifdef DEBUG
978 #define WR_RH_STAT(x) \
979 { \
980 info("WR:status %#8x", (x)); \
981 writel((x), &gohci.regs->roothub.status); \
982 }
983 #define WR_RH_PORTSTAT(x) \
984 { \
985 info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
986 writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
987 }
988 #else
989 #define WR_RH_STAT(x) \
990 writel((x), &gohci.regs->roothub.status)
991 #define WR_RH_PORTSTAT(x)\
992 writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
993 #endif
994 #define RD_RH_STAT roothub_status(&gohci)
995 #define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
996
997 /* request to virtual root hub */
998
999 int rh_check_port_status(struct ohci *controller)
1000 {
1001 __u32 temp, ndp, i;
1002 int res;
1003
1004 res = -1;
1005 temp = roothub_a(controller);
1006 ndp = (temp & RH_A_NDP);
1007 for (i = 0; i < ndp; i++) {
1008 temp = roothub_portstatus(controller, i);
1009 /* check for a device disconnect */
1010 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1011 (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
1012 res = i;
1013 break;
1014 }
1015 }
1016 return res;
1017 }
1018
1019 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1020 void *buffer, int transfer_len,
1021 struct devrequest *cmd)
1022 {
1023 void *data = buffer;
1024 int leni = transfer_len;
1025 int len = 0;
1026 int stat = 0;
1027 union {
1028 __u32 word[4];
1029 __u16 hword[8];
1030 __u8 byte[16];
1031 } datab;
1032 __u8 *data_buf = datab.byte;
1033 __u16 bmRType_bReq;
1034 __u16 wValue;
1035 __u16 wIndex;
1036 __u16 wLength;
1037
1038 #ifdef DEBUG
1039 urb_priv.actual_length = 0;
1040 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
1041 usb_pipein(pipe));
1042 #else
1043 mdelay(1);
1044 #endif
1045 if (usb_pipeint(pipe)) {
1046 info("Root-Hub submit IRQ: NOT implemented");
1047 return 0;
1048 }
1049
1050 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1051 wValue = m16_swap(cmd->value);
1052 wIndex = m16_swap(cmd->index);
1053 wLength = m16_swap(cmd->length);
1054
1055 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1056 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1057
1058 switch (bmRType_bReq) {
1059 /* Request Destination:
1060 without flags: Device,
1061 RH_INTERFACE: interface,
1062 RH_ENDPOINT: endpoint,
1063 RH_CLASS means HUB here,
1064 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1065 */
1066
1067 case RH_GET_STATUS:
1068 datab.hword[0] = m16_swap(1);
1069 OK(2);
1070 case RH_GET_STATUS | RH_INTERFACE:
1071 datab.hword[0] = m16_swap(0);
1072 OK(2);
1073 case RH_GET_STATUS | RH_ENDPOINT:
1074 datab.hword[0] = m16_swap(0);
1075 OK(2);
1076 case RH_GET_STATUS | RH_CLASS:
1077 datab.word[0] =
1078 m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1079 OK(4);
1080 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1081 datab.word[0] = m32_swap(RD_RH_PORTSTAT);
1082 OK(4);
1083
1084 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1085 switch (wValue) {
1086 case (RH_ENDPOINT_STALL):
1087 OK(0);
1088 }
1089 break;
1090
1091 case RH_CLEAR_FEATURE | RH_CLASS:
1092 switch (wValue) {
1093 case RH_C_HUB_LOCAL_POWER:
1094 OK(0);
1095 case (RH_C_HUB_OVER_CURRENT):
1096 WR_RH_STAT(RH_HS_OCIC);
1097 OK(0);
1098 }
1099 break;
1100
1101 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1102 switch (wValue) {
1103 case (RH_PORT_ENABLE):
1104 WR_RH_PORTSTAT(RH_PS_CCS);
1105 OK(0);
1106 case (RH_PORT_SUSPEND):
1107 WR_RH_PORTSTAT(RH_PS_POCI);
1108 OK(0);
1109 case (RH_PORT_POWER):
1110 WR_RH_PORTSTAT(RH_PS_LSDA);
1111 OK(0);
1112 case (RH_C_PORT_CONNECTION):
1113 WR_RH_PORTSTAT(RH_PS_CSC);
1114 OK(0);
1115 case (RH_C_PORT_ENABLE):
1116 WR_RH_PORTSTAT(RH_PS_PESC);
1117 OK(0);
1118 case (RH_C_PORT_SUSPEND):
1119 WR_RH_PORTSTAT(RH_PS_PSSC);
1120 OK(0);
1121 case (RH_C_PORT_OVER_CURRENT):
1122 WR_RH_PORTSTAT(RH_PS_OCIC);
1123 OK(0);
1124 case (RH_C_PORT_RESET):
1125 WR_RH_PORTSTAT(RH_PS_PRSC);
1126 OK(0);
1127 }
1128 break;
1129
1130 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1131 switch (wValue) {
1132 case (RH_PORT_SUSPEND):
1133 WR_RH_PORTSTAT(RH_PS_PSS);
1134 OK(0);
1135 case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
1136 if (RD_RH_PORTSTAT & RH_PS_CCS)
1137 WR_RH_PORTSTAT(RH_PS_PRS);
1138 OK(0);
1139 case (RH_PORT_POWER):
1140 WR_RH_PORTSTAT(RH_PS_PPS);
1141 OK(0);
1142 case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
1143 if (RD_RH_PORTSTAT & RH_PS_CCS)
1144 WR_RH_PORTSTAT(RH_PS_PES);
1145 OK(0);
1146 }
1147 break;
1148
1149 case RH_SET_ADDRESS:
1150 gohci.rh.devnum = wValue;
1151 OK(0);
1152
1153 case RH_GET_DESCRIPTOR:
1154 switch ((wValue & 0xff00) >> 8) {
1155 case (0x01): /* device descriptor */
1156 len = min_t(unsigned int,
1157 leni,
1158 min_t(unsigned int,
1159 sizeof(root_hub_dev_des), wLength));
1160 data_buf = root_hub_dev_des;
1161 OK(len);
1162 case (0x02): /* configuration descriptor */
1163 len = min_t(unsigned int,
1164 leni,
1165 min_t(unsigned int,
1166 sizeof(root_hub_config_des),
1167 wLength));
1168 data_buf = root_hub_config_des;
1169 OK(len);
1170 case (0x03): /* string descriptors */
1171 if (wValue == 0x0300) {
1172 len = min_t(unsigned int,
1173 leni,
1174 min_t(unsigned int,
1175 sizeof(root_hub_str_index0),
1176 wLength));
1177 data_buf = root_hub_str_index0;
1178 OK(len);
1179 }
1180 if (wValue == 0x0301) {
1181 len = min_t(unsigned int,
1182 leni,
1183 min_t(unsigned int,
1184 sizeof(root_hub_str_index1),
1185 wLength));
1186 data_buf = root_hub_str_index1;
1187 OK(len);
1188 }
1189 default:
1190 stat = USB_ST_STALLED;
1191 }
1192 break;
1193
1194 case RH_GET_DESCRIPTOR | RH_CLASS:
1195 {
1196 __u32 temp = roothub_a(&gohci);
1197
1198 data_buf[0] = 9; /* min length; */
1199 data_buf[1] = 0x29;
1200 data_buf[2] = temp & RH_A_NDP;
1201 data_buf[3] = 0;
1202 if (temp & RH_A_PSM)
1203 /* per-port power switching? */
1204 data_buf[3] |= 0x1;
1205 if (temp & RH_A_NOCP)
1206 /* no overcurrent reporting? */
1207 data_buf[3] |= 0x10;
1208 else if (temp & RH_A_OCPM)
1209 /* per-port overcurrent reporting? */
1210 data_buf[3] |= 0x8;
1211
1212 /* corresponds to data_buf[4-7] */
1213 datab.word[1] = 0;
1214 data_buf[5] = (temp & RH_A_POTPGT) >> 24;
1215 temp = roothub_b(&gohci);
1216 data_buf[7] = temp & RH_B_DR;
1217 if (data_buf[2] < 7) {
1218 data_buf[8] = 0xff;
1219 } else {
1220 data_buf[0] += 2;
1221 data_buf[8] = (temp & RH_B_DR) >> 8;
1222 data_buf[10] = data_buf[9] = 0xff;
1223 }
1224
1225 len = min_t(unsigned int, leni,
1226 min_t(unsigned int, data_buf[0], wLength));
1227 OK(len);
1228 }
1229
1230 case RH_GET_CONFIGURATION:
1231 *(__u8 *) data_buf = 0x01;
1232 OK(1);
1233
1234 case RH_SET_CONFIGURATION:
1235 WR_RH_STAT(0x10000);
1236 OK(0);
1237
1238 default:
1239 dbg("unsupported root hub command");
1240 stat = USB_ST_STALLED;
1241 }
1242
1243 #ifdef DEBUG
1244 ohci_dump_roothub(&gohci, 1);
1245 #else
1246 mdelay(1);
1247 #endif
1248
1249 len = min_t(int, len, leni);
1250 if (data != data_buf)
1251 memcpy(data, data_buf, len);
1252 dev->act_len = len;
1253 dev->status = stat;
1254
1255 #ifdef DEBUG
1256 if (transfer_len)
1257 urb_priv.actual_length = transfer_len;
1258 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
1259 0 /*usb_pipein(pipe) */);
1260 #else
1261 mdelay(1);
1262 #endif
1263
1264 return stat;
1265 }
1266
1267 /*-------------------------------------------------------------------------*/
1268
1269 /* common code for handling submit messages - used for all but root hub */
1270 /* accesses. */
1271 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1272 int transfer_len, struct devrequest *setup, int interval)
1273 {
1274 int stat = 0;
1275 int maxsize = usb_maxpacket(dev, pipe);
1276 int timeout;
1277
1278 /* device pulled? Shortcut the action. */
1279 if (devgone == dev) {
1280 dev->status = USB_ST_CRC_ERR;
1281 return 0;
1282 }
1283 #ifdef DEBUG
1284 urb_priv.actual_length = 0;
1285 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
1286 usb_pipein(pipe));
1287 #else
1288 mdelay(1);
1289 #endif
1290 if (!maxsize) {
1291 err("submit_common_message: pipesize for pipe %lx is zero",
1292 pipe);
1293 return -1;
1294 }
1295
1296 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
1297 0) {
1298 err("sohci_submit_job failed");
1299 return -1;
1300 }
1301
1302 mdelay(10);
1303 /* ohci_dump_status(&gohci); */
1304
1305 /* allow more time for a BULK device to react - some are slow */
1306 #define BULK_TO 5000 /* timeout in milliseconds */
1307 if (usb_pipebulk(pipe))
1308 timeout = BULK_TO;
1309 else
1310 timeout = 100;
1311
1312 /* wait for it to complete */
1313 for (;;) {
1314 /* check whether the controller is done */
1315 stat = hc_interrupt();
1316
1317 if (stat < 0) {
1318 stat = USB_ST_CRC_ERR;
1319 break;
1320 }
1321
1322 /* NOTE: since we are not interrupt driven in U-Boot and always
1323 * handle only one URB at a time, we cannot assume the
1324 * transaction finished on the first successful return from
1325 * hc_interrupt().. unless the flag for current URB is set,
1326 * meaning that all TD's to/from device got actually
1327 * transferred and processed. If the current URB is not
1328 * finished we need to re-iterate this loop so as
1329 * hc_interrupt() gets called again as there needs to be some
1330 * more TD's to process still */
1331 if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
1332 /* 0xff is returned for an SF-interrupt */
1333 break;
1334 }
1335
1336 if (--timeout) {
1337 mdelay(1);
1338 if (!urb_finished)
1339 dbg("\%");
1340
1341 } else {
1342 err("CTL:TIMEOUT ");
1343 dbg("submit_common_msg: TO status %x\n", stat);
1344 stat = USB_ST_CRC_ERR;
1345 urb_finished = 1;
1346 break;
1347 }
1348 }
1349
1350 #if 0
1351 /* we got an Root Hub Status Change interrupt */
1352 if (got_rhsc) {
1353 #ifdef DEBUG
1354 ohci_dump_roothub(&gohci, 1);
1355 #endif
1356 got_rhsc = 0;
1357 /* abuse timeout */
1358 timeout = rh_check_port_status(&gohci);
1359 if (timeout >= 0) {
1360 #if 0 /* this does nothing useful, but leave it here
1361 in case that changes */
1362 /* the called routine adds 1 to the passed value */
1363 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1364 #endif
1365 /*
1366 * XXX
1367 * This is potentially dangerous because it assumes
1368 * that only one device is ever plugged in!
1369 */
1370 devgone = dev;
1371 }
1372 }
1373 #endif
1374
1375 dev->status = stat;
1376 dev->act_len = transfer_len;
1377
1378 #ifdef DEBUG
1379 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
1380 usb_pipein(pipe));
1381 #else
1382 mdelay(1);
1383 #endif
1384
1385 /* free TDs in urb_priv */
1386 urb_free_priv(&urb_priv);
1387 return 0;
1388 }
1389
1390 /* submit routines called from usb.c */
1391 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1392 int transfer_len)
1393 {
1394 info("submit_bulk_msg");
1395 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1396 }
1397
1398 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1399 int transfer_len, struct devrequest *setup)
1400 {
1401 int maxsize = usb_maxpacket(dev, pipe);
1402
1403 info("submit_control_msg");
1404 #ifdef DEBUG
1405 urb_priv.actual_length = 0;
1406 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
1407 usb_pipein(pipe));
1408 #else
1409 mdelay(1);
1410 #endif
1411 if (!maxsize) {
1412 err("submit_control_message: pipesize for pipe %lx is zero",
1413 pipe);
1414 return -1;
1415 }
1416 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1417 gohci.rh.dev = dev;
1418 /* root hub - redirect */
1419 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1420 setup);
1421 }
1422
1423 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1424 }
1425
1426 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1427 int transfer_len, int interval)
1428 {
1429 info("submit_int_msg");
1430 return -1;
1431 }
1432
1433 /*-------------------------------------------------------------------------*
1434 * HC functions
1435 *-------------------------------------------------------------------------*/
1436
1437 /* reset the HC and BUS */
1438
1439 static int hc_reset(struct ohci *ohci)
1440 {
1441 int timeout = 30;
1442 int smm_timeout = 50; /* 0,5 sec */
1443
1444 if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1445 /* SMM owns the HC - request ownership */
1446 writel(OHCI_OCR, &ohci->regs->cmdstatus);
1447 info("USB HC TakeOver from SMM");
1448 while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
1449 mdelay(10);
1450 if (--smm_timeout == 0) {
1451 err("USB HC TakeOver failed!");
1452 return -1;
1453 }
1454 }
1455 }
1456
1457 /* Disable HC interrupts */
1458 writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
1459
1460 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1461 ohci->slot_name, readl(&ohci->regs->control));
1462
1463 /* Reset USB (needed by some controllers) */
1464 writel(0, &ohci->regs->control);
1465
1466 /* HC Reset requires max 10 us delay */
1467 writel(OHCI_HCR, &ohci->regs->cmdstatus);
1468 while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1469 if (--timeout == 0) {
1470 err("USB HC reset timed out!");
1471 return -1;
1472 }
1473 udelay(1);
1474 }
1475 return 0;
1476 }
1477
1478 /*-------------------------------------------------------------------------*/
1479
1480 /* Start an OHCI controller, set the BUS operational
1481 * enable interrupts
1482 * connect the virtual root hub */
1483
1484 static int hc_start(struct ohci *ohci)
1485 {
1486 __u32 mask;
1487 unsigned int fminterval;
1488
1489 ohci->disabled = 1;
1490
1491 /* Tell the controller where the control and bulk lists are
1492 * The lists are empty now. */
1493
1494 writel(0, &ohci->regs->ed_controlhead);
1495 writel(0, &ohci->regs->ed_bulkhead);
1496
1497 /* a reset clears this */
1498 writel((__u32) ohci->hcca, &ohci->regs->hcca);
1499
1500 fminterval = 0x2edf;
1501 writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
1502 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1503 writel(fminterval, &ohci->regs->fminterval);
1504 writel(0x628, &ohci->regs->lsthresh);
1505
1506 /* start controller operations */
1507 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1508 ohci->disabled = 0;
1509 writel(ohci->hc_control, &ohci->regs->control);
1510
1511 /* disable all interrupts */
1512 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1513 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1514 OHCI_INTR_OC | OHCI_INTR_MIE);
1515 writel(mask, &ohci->regs->intrdisable);
1516 /* clear all interrupts */
1517 mask &= ~OHCI_INTR_MIE;
1518 writel(mask, &ohci->regs->intrstatus);
1519 /* Choose the interrupts we care about now - but w/o MIE */
1520 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1521 writel(mask, &ohci->regs->intrenable);
1522
1523 #ifdef OHCI_USE_NPS
1524 /* required for AMD-756 and some Mac platforms */
1525 writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
1526 &ohci->regs->roothub.a);
1527 writel(RH_HS_LPSC, &ohci->regs->roothub.status);
1528 #endif /* OHCI_USE_NPS */
1529
1530 /* POTPGT delay is bits 24-31, in 2 ms units. */
1531 mdelay((roothub_a(ohci) >> 23) & 0x1fe);
1532
1533 /* connect the virtual root hub */
1534 ohci->rh.devnum = 0;
1535
1536 return 0;
1537 }
1538
1539 /*-------------------------------------------------------------------------*/
1540
1541 /* an interrupt happens */
1542
1543 static int hc_interrupt(void)
1544 {
1545 struct ohci *ohci = &gohci;
1546 struct ohci_regs *regs = ohci->regs;
1547 int ints;
1548 int stat = -1;
1549
1550 if ((ohci->hcca->done_head != 0) &&
1551 !(m32_swap(ohci->hcca->done_head) & 0x01)) {
1552
1553 ints = OHCI_INTR_WDH;
1554
1555 } else {
1556 ints = readl(&regs->intrstatus);
1557 if (ints == ~(u32) 0) {
1558 ohci->disabled++;
1559 err("%s device removed!", ohci->slot_name);
1560 return -1;
1561 }
1562 ints &= readl(&regs->intrenable);
1563 if (ints == 0) {
1564 dbg("hc_interrupt: returning..\n");
1565 return 0xff;
1566 }
1567 }
1568
1569 /* dbg("Interrupt: %x frame: %x", ints,
1570 le16_to_cpu(ohci->hcca->frame_no)); */
1571
1572 if (ints & OHCI_INTR_RHSC) {
1573 got_rhsc = 1;
1574 stat = 0xff;
1575 }
1576
1577 if (ints & OHCI_INTR_UE) {
1578 ohci->disabled++;
1579 err("OHCI Unrecoverable Error, controller usb-%s disabled",
1580 ohci->slot_name);
1581 /* e.g. due to PCI Master/Target Abort */
1582
1583 #ifdef DEBUG
1584 ohci_dump(ohci, 1);
1585 #else
1586 mdelay(1);
1587 #endif
1588 /* FIXME: be optimistic, hope that bug won't repeat often. */
1589 /* Make some non-interrupt context restart the controller. */
1590 /* Count and limit the retries though; either hardware or */
1591 /* software errors can go forever... */
1592 hc_reset(ohci);
1593 return -1;
1594 }
1595
1596 if (ints & OHCI_INTR_WDH) {
1597 mdelay(1);
1598
1599 writel(OHCI_INTR_WDH, &regs->intrdisable);
1600 stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
1601 writel(OHCI_INTR_WDH, &regs->intrenable);
1602 }
1603
1604 if (ints & OHCI_INTR_SO) {
1605 dbg("USB Schedule overrun\n");
1606 writel(OHCI_INTR_SO, &regs->intrenable);
1607 stat = -1;
1608 }
1609
1610 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1611 if (ints & OHCI_INTR_SF) {
1612 unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
1613 mdelay(1);
1614 writel(OHCI_INTR_SF, &regs->intrdisable);
1615 if (ohci->ed_rm_list[frame] != NULL)
1616 writel(OHCI_INTR_SF, &regs->intrenable);
1617 stat = 0xff;
1618 }
1619
1620 writel(ints, &regs->intrstatus);
1621 return stat;
1622 }
1623
1624 /*-------------------------------------------------------------------------*/
1625
1626 /*-------------------------------------------------------------------------*/
1627
1628 /* De-allocate all resources.. */
1629
1630 static void hc_release_ohci(struct ohci *ohci)
1631 {
1632 dbg("USB HC release ohci usb-%s", ohci->slot_name);
1633
1634 if (!ohci->disabled)
1635 hc_reset(ohci);
1636 }
1637
1638 /*-------------------------------------------------------------------------*/
1639
1640 /*
1641 * low level initalisation routine, called from usb.c
1642 */
1643 static char ohci_inited = 0;
1644
1645 int usb_lowlevel_init(int index, void **controller)
1646 {
1647 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1648 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
1649
1650 /*
1651 * Set the 48 MHz UPLL clocking. Values are taken from
1652 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1653 */
1654 clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
1655 gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
1656
1657 /*
1658 * Enable USB host clock.
1659 */
1660 clk_power->clkcon |= (1 << 4);
1661
1662 memset(&gohci, 0, sizeof(struct ohci));
1663 memset(&urb_priv, 0, sizeof(struct urb_priv));
1664
1665 /* align the storage */
1666 if ((__u32) &ghcca[0] & 0xff) {
1667 err("HCCA not aligned!!");
1668 return -1;
1669 }
1670 phcca = &ghcca[0];
1671 info("aligned ghcca %p", phcca);
1672 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1673 if ((__u32) &ohci_dev.ed[0] & 0x7) {
1674 err("EDs not aligned!!");
1675 return -1;
1676 }
1677 memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
1678 if ((__u32) gtd & 0x7) {
1679 err("TDs not aligned!!");
1680 return -1;
1681 }
1682 ptd = gtd;
1683 gohci.hcca = phcca;
1684 memset(phcca, 0, sizeof(struct ohci_hcca));
1685
1686 gohci.disabled = 1;
1687 gohci.sleeping = 0;
1688 gohci.irq = -1;
1689 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1690
1691 gohci.flags = 0;
1692 gohci.slot_name = "s3c2400";
1693
1694 if (hc_reset(&gohci) < 0) {
1695 hc_release_ohci(&gohci);
1696 /* Initialization failed */
1697 clk_power->clkcon &= ~(1 << 4);
1698 return -1;
1699 }
1700
1701 /* FIXME this is a second HC reset; why?? */
1702 gohci.hc_control = OHCI_USB_RESET;
1703 writel(gohci.hc_control, &gohci.regs->control);
1704 mdelay(10);
1705
1706 if (hc_start(&gohci) < 0) {
1707 err("can't start usb-%s", gohci.slot_name);
1708 hc_release_ohci(&gohci);
1709 /* Initialization failed */
1710 clk_power->clkcon &= ~(1 << 4);
1711 return -1;
1712 }
1713 #ifdef DEBUG
1714 ohci_dump(&gohci, 1);
1715 #else
1716 mdelay(1);
1717 #endif
1718 ohci_inited = 1;
1719 urb_finished = 1;
1720
1721 return 0;
1722 }
1723
1724 int usb_lowlevel_stop(int index)
1725 {
1726 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1727
1728 /* this gets called really early - before the controller has */
1729 /* even been initialized! */
1730 if (!ohci_inited)
1731 return 0;
1732 /* TODO release any interrupts, etc. */
1733 /* call hc_release_ohci() here ? */
1734 hc_reset(&gohci);
1735 /* may not want to do this */
1736 clk_power->clkcon &= ~(1 << 4);
1737 return 0;
1738 }
1739
1740 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
1741
1742 #if defined(CONFIG_USB_OHCI_NEW) && \
1743 defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
1744 defined(CONFIG_S3C24X0)
1745
1746 int usb_cpu_init(void)
1747 {
1748 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1749 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
1750
1751 /*
1752 * Set the 48 MHz UPLL clocking. Values are taken from
1753 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1754 */
1755 writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
1756 /* 1 = use pads related USB for USB host */
1757 writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
1758
1759 /*
1760 * Enable USB host clock.
1761 */
1762 writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
1763
1764 return 0;
1765 }
1766
1767 int usb_cpu_stop(void)
1768 {
1769 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1770 /* may not want to do this */
1771 writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
1772 return 0;
1773 }
1774
1775 int usb_cpu_init_fail(void)
1776 {
1777 struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
1778 writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
1779 return 0;
1780 }
1781
1782 #endif /* defined(CONFIG_USB_OHCI_NEW) && \
1783 defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
1784 defined(CONFIG_S3C24X0) */
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