drivers/usb/host/xhci-dwc3.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * DWC3 controller driver
   5  *
   6  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fdtdec.h>
  14 #include <generic-phy.h>
  15 #include <usb.h>
  16
  17 #include "xhci.h"
  18 #include <asm/io.h>
  19 #include <linux/usb/dwc3.h>
  20 #include <linux/usb/otg.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct xhci_dwc3_platdata {
  25         struct phy usb_phy;
  26 };
  27
  28 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  29 {
  30         clrsetbits_le32(&dwc3_reg->g_ctl,
  31                         DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  32                         DWC3_GCTL_PRTCAPDIR(mode));
  33 }
  34
  35 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  36 {
  37         /* Assert USB3 PHY reset */
  38         setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  39
  40         /* Assert USB2 PHY reset */
  41         setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  42
  43         mdelay(100);
  44
  45         /* Clear USB3 PHY reset */
  46         clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  47
  48         /* Clear USB2 PHY reset */
  49         clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  50 }
  51
  52 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  53 {
  54         /* Before Resetting PHY, put Core in Reset */
  55         setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  56
  57         /* reset USB3 phy - if required */
  58         dwc3_phy_reset(dwc3_reg);
  59
  60         mdelay(100);
  61
  62         /* After PHYs are stable we can take Core out of reset state */
  63         clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  64 }
  65
  66 int dwc3_core_init(struct dwc3 *dwc3_reg)
  67 {
  68         u32 reg;
  69         u32 revision;
  70         unsigned int dwc3_hwparams1;
  71
  72         revision = readl(&dwc3_reg->g_snpsid);
  73         /* This should read as U3 followed by revision number */
  74         if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
  75                 puts("this is not a DesignWare USB3 DRD Core\n");
  76                 return -1;
  77         }
  78
  79         dwc3_core_soft_reset(dwc3_reg);
  80
  81         dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  82
  83         reg = readl(&dwc3_reg->g_ctl);
  84         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  85         reg &= ~DWC3_GCTL_DISSCRAMBLE;
  86         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  87         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  88                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  89                 break;
  90         default:
  91                 debug("No power optimization available\n");
  92         }
  93
  94         /*
  95          * WORKAROUND: DWC3 revisions <1.90a have a bug
  96          * where the device can fail to connect at SuperSpeed
  97          * and falls back to high-speed mode which causes
  98          * the device to enter a Connect/Disconnect loop
  99          */
 100         if ((revision & DWC3_REVISION_MASK) < 0x190a)
 101                 reg |= DWC3_GCTL_U2RSTECN;
 102
 103         writel(reg, &dwc3_reg->g_ctl);
 104
 105         return 0;
 106 }
 107
 108 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 109 {
 110         setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
 111                         GFLADJ_30MHZ(val));
 112 }
 113
 114 #ifdef CONFIG_DM_USB
 115 static int xhci_dwc3_probe(struct udevice *dev)
 116 {
 117         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 118         struct xhci_hcor *hcor;
 119         struct xhci_hccr *hccr;
 120         struct dwc3 *dwc3_reg;
 121         enum usb_dr_mode dr_mode;
 122         int ret;
 123
 124         hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
 125         hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 126                         HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 127
 128         ret = generic_phy_get_by_index(dev, 0, &plat->usb_phy);
 129         if (ret) {
 130                 if (ret != -ENOENT) {
 131                         pr_err("Failed to get USB PHY for %s\n", dev->name);
 132                         return ret;
 133                 }
 134         } else {
 135                 ret = generic_phy_init(&plat->usb_phy);
 136                 if (ret) {
 137                         pr_err("Can't init USB PHY for %s\n", dev->name);
 138                         return ret;
 139                 }
 140         }
 141
 142         dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 143
 144         dwc3_core_init(dwc3_reg);
 145
 146         dr_mode = usb_get_dr_mode(dev_of_offset(dev));
 147         if (dr_mode == USB_DR_MODE_UNKNOWN)
 148                 /* by default set dual role mode to HOST */
 149                 dr_mode = USB_DR_MODE_HOST;
 150
 151         dwc3_set_mode(dwc3_reg, dr_mode);
 152
 153         return xhci_register(dev, hccr, hcor);
 154 }
 155
 156 static int xhci_dwc3_remove(struct udevice *dev)
 157 {
 158         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 159         int ret;
 160
 161         if (generic_phy_valid(&plat->usb_phy)) {
 162                 ret = generic_phy_exit(&plat->usb_phy);
 163                 if (ret) {
 164                         pr_err("Can't deinit USB PHY for %s\n", dev->name);
 165                         return ret;
 166                 }
 167         }
 168
 169         return xhci_deregister(dev);
 170 }
 171
 172 static const struct udevice_id xhci_dwc3_ids[] = {
 173         { .compatible = "snps,dwc3" },
 174         { }
 175 };
 176
 177 U_BOOT_DRIVER(xhci_dwc3) = {
 178         .name = "xhci-dwc3",
 179         .id = UCLASS_USB,
 180         .of_match = xhci_dwc3_ids,
 181         .probe = xhci_dwc3_probe,
 182         .remove = xhci_dwc3_remove,
 183         .ops = &xhci_usb_ops,
 184         .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
 185         .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
 186         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 187 };
 188 #endif