1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
17 #include "xhci-trace.h"
19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 PORT_RC | PORT_PLC | PORT_PE)
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa
[] = {
25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd
*xhci
, char *buf
,
38 struct usb_bos_descriptor
*bos
;
39 struct usb_ss_cap_descriptor
*ss_cap
;
40 struct usb_ssp_cap_descriptor
*ssp_cap
;
41 struct xhci_port_cap
*port_cap
= NULL
;
52 bos
= (struct usb_bos_descriptor
*)buf
;
53 bos
->bLength
= USB_DT_BOS_SIZE
;
54 bos
->bDescriptorType
= USB_DT_BOS
;
55 bos
->wTotalLength
= cpu_to_le16(USB_DT_BOS_SIZE
+
56 USB_DT_USB_SS_CAP_SIZE
);
57 bos
->bNumDeviceCaps
= 1;
59 /* Create the descriptor for port with the highest revision */
60 for (i
= 0; i
< xhci
->num_port_caps
; i
++) {
61 u8 major
= xhci
->port_caps
[i
].maj_rev
;
62 u8 minor
= xhci
->port_caps
[i
].min_rev
;
63 u16 rev
= (major
<< 8) | minor
;
65 if (i
== 0 || bcdUSB
< rev
) {
67 port_cap
= &xhci
->port_caps
[i
];
71 if (bcdUSB
>= 0x0310) {
72 if (port_cap
->psi_count
) {
75 for (i
= 0; i
< port_cap
->psi_count
; i
++) {
76 if ((port_cap
->psi
[i
] & PLT_MASK
) == PLT_SYM
)
80 ssac
= port_cap
->psi_count
+ num_sym_ssa
- 1;
81 ssic
= port_cap
->psi_uid_count
- 1;
88 ssic
= (ssac
+ 1) / 2 - 1;
91 bos
->bNumDeviceCaps
++;
92 bos
->wTotalLength
= cpu_to_le16(USB_DT_BOS_SIZE
+
93 USB_DT_USB_SS_CAP_SIZE
+
94 USB_DT_USB_SSP_CAP_SIZE(ssac
));
97 if (wLength
< USB_DT_BOS_SIZE
+ USB_DT_USB_SS_CAP_SIZE
)
100 /* SuperSpeed USB Device Capability */
101 ss_cap
= (struct usb_ss_cap_descriptor
*)&buf
[USB_DT_BOS_SIZE
];
102 ss_cap
->bLength
= USB_DT_USB_SS_CAP_SIZE
;
103 ss_cap
->bDescriptorType
= USB_DT_DEVICE_CAPABILITY
;
104 ss_cap
->bDevCapabilityType
= USB_SS_CAP_TYPE
;
105 ss_cap
->bmAttributes
= 0; /* set later */
106 ss_cap
->wSpeedSupported
= cpu_to_le16(USB_5GBPS_OPERATION
);
107 ss_cap
->bFunctionalitySupport
= USB_LOW_SPEED_OPERATION
;
108 ss_cap
->bU1devExitLat
= 0; /* set later */
109 ss_cap
->bU2DevExitLat
= 0; /* set later */
111 reg
= readl(&xhci
->cap_regs
->hcc_params
);
113 ss_cap
->bmAttributes
|= USB_LTM_SUPPORT
;
115 if ((xhci
->quirks
& XHCI_LPM_SUPPORT
)) {
116 reg
= readl(&xhci
->cap_regs
->hcs_params3
);
117 ss_cap
->bU1devExitLat
= HCS_U1_LATENCY(reg
);
118 ss_cap
->bU2DevExitLat
= cpu_to_le16(HCS_U2_LATENCY(reg
));
121 if (wLength
< le16_to_cpu(bos
->wTotalLength
))
125 return le16_to_cpu(bos
->wTotalLength
);
127 ssp_cap
= (struct usb_ssp_cap_descriptor
*)&buf
[USB_DT_BOS_SIZE
+
128 USB_DT_USB_SS_CAP_SIZE
];
129 ssp_cap
->bLength
= USB_DT_USB_SSP_CAP_SIZE(ssac
);
130 ssp_cap
->bDescriptorType
= USB_DT_DEVICE_CAPABILITY
;
131 ssp_cap
->bDevCapabilityType
= USB_SSP_CAP_TYPE
;
132 ssp_cap
->bReserved
= 0;
133 ssp_cap
->wReserved
= 0;
134 ssp_cap
->bmAttributes
=
135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS
, ssac
) |
136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS
, ssic
));
138 if (!port_cap
->psi_count
) {
139 for (i
= 0; i
< ssac
+ 1; i
++)
140 ssp_cap
->bmSublinkSpeedAttr
[i
] =
141 cpu_to_le32(ssp_cap_default_ssa
[i
]);
148 for (i
= 0; i
< port_cap
->psi_count
; i
++) {
159 psi
= port_cap
->psi
[i
];
160 ssid
= XHCI_EXT_PORT_PSIV(psi
);
161 lp
= XHCI_EXT_PORT_LP(psi
);
162 psie
= XHCI_EXT_PORT_PSIE(psi
);
163 psim
= XHCI_EXT_PORT_PSIM(psi
);
164 plt
= psi
& PLT_MASK
;
167 lane_mantissa
= psim
;
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 for (; psie
< USB_SSP_SUBLINK_SPEED_LSE_GBPS
; psie
++)
173 if (!min_rate
|| psim
< min_rate
) {
178 /* Some host controllers don't set the link protocol for SSP */
180 lp
= USB_SSP_SUBLINK_SPEED_LP_SSP
;
183 * PSIM and PSIE represent the total speed of PSI. The BOS
184 * descriptor SSP sublink speed attribute lane mantissa
185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 * 10Gbps. Check and modify the mantissa value to match the
190 if (bcdUSB
== 0x0320 && plt
== PLT_SYM
) {
192 * The PSI dword for gen1x2 and gen2x1 share the same
193 * values. But the lane speed for gen1x2 is 5Gbps while
194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 * 5 and the PSIE and PSIM match with SSID 6, let's
196 * assume that the controller follows the default speed
197 * id with SSID 6 for gen1x2.
199 if (ssid
== 6 && psie
== 3 && psim
== 10 && i
) {
200 u32 prev
= port_cap
->psi
[i
- 1];
202 if ((prev
& PLT_MASK
) == PLT_SYM
&&
203 XHCI_EXT_PORT_PSIV(prev
) == 5 &&
204 XHCI_EXT_PORT_PSIE(prev
) == 3 &&
205 XHCI_EXT_PORT_PSIM(prev
) == 10) {
206 lse
= USB_SSP_SUBLINK_SPEED_LSE_GBPS
;
211 if (psie
== 3 && psim
> 10) {
212 lse
= USB_SSP_SUBLINK_SPEED_LSE_GBPS
;
217 attr
= (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID
, ssid
) |
218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP
, lp
) |
219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE
, lse
) |
220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM
, lane_mantissa
));
224 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX
);
226 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
228 attr
&= ~USB_SSP_SUBLINK_SPEED_ST
;
229 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX
);
231 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
234 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX
);
236 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
239 attr
|= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST
,
240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX
);
241 ssp_cap
->bmSublinkSpeedAttr
[offset
++] = cpu_to_le32(attr
);
246 ssp_cap
->wFunctionalitySupport
=
247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID
,
249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT
, 1) |
250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT
, 1));
252 return le16_to_cpu(bos
->wTotalLength
);
255 static void xhci_common_hub_descriptor(struct xhci_hcd
*xhci
,
256 struct usb_hub_descriptor
*desc
, int ports
)
260 desc
->bHubContrCurrent
= 0;
262 desc
->bNbrPorts
= ports
;
264 /* Bits 1:0 - support per-port power switching, or power always on */
265 if (HCC_PPC(xhci
->hcc_params
))
266 temp
|= HUB_CHAR_INDV_PORT_LPSM
;
268 temp
|= HUB_CHAR_NO_LPSM
;
269 /* Bit 2 - root hubs are not part of a compound device */
270 /* Bits 4:3 - individual port over current protection */
271 temp
|= HUB_CHAR_INDV_PORT_OCPM
;
272 /* Bits 6:5 - no TTs in root ports */
273 /* Bit 7 - no port indicators */
274 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
277 /* Fill in the USB 2.0 roothub descriptor */
278 static void xhci_usb2_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
279 struct usb_hub_descriptor
*desc
)
283 __u8 port_removable
[(USB_MAXCHILDREN
+ 1 + 7) / 8];
286 struct xhci_hub
*rhub
;
288 rhub
= &xhci
->usb2_rhub
;
289 ports
= rhub
->num_ports
;
290 xhci_common_hub_descriptor(xhci
, desc
, ports
);
291 desc
->bDescriptorType
= USB_DT_HUB
;
292 temp
= 1 + (ports
/ 8);
293 desc
->bDescLength
= USB_DT_HUB_NONVAR_SIZE
+ 2 * temp
;
294 desc
->bPwrOn2PwrGood
= 10; /* xhci section 5.4.8 says 20ms */
296 /* The Device Removable bits are reported on a byte granularity.
297 * If the port doesn't exist within that byte, the bit is set to 0.
299 memset(port_removable
, 0, sizeof(port_removable
));
300 for (i
= 0; i
< ports
; i
++) {
301 portsc
= readl(rhub
->ports
[i
]->addr
);
302 /* If a device is removable, PORTSC reports a 0, same as in the
303 * hub descriptor DeviceRemovable bits.
305 if (portsc
& PORT_DEV_REMOVE
)
306 /* This math is hairy because bit 0 of DeviceRemovable
307 * is reserved, and bit 1 is for port 1, etc.
309 port_removable
[(i
+ 1) / 8] |= 1 << ((i
+ 1) % 8);
312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 * ports on it. The USB 2.0 specification says that there are two
314 * variable length fields at the end of the hub descriptor:
315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
318 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
320 * set of ports that actually exist.
322 memset(desc
->u
.hs
.DeviceRemovable
, 0xff,
323 sizeof(desc
->u
.hs
.DeviceRemovable
));
324 memset(desc
->u
.hs
.PortPwrCtrlMask
, 0xff,
325 sizeof(desc
->u
.hs
.PortPwrCtrlMask
));
327 for (i
= 0; i
< (ports
+ 1 + 7) / 8; i
++)
328 memset(&desc
->u
.hs
.DeviceRemovable
[i
], port_removable
[i
],
332 /* Fill in the USB 3.0 roothub descriptor */
333 static void xhci_usb3_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
334 struct usb_hub_descriptor
*desc
)
340 struct xhci_hub
*rhub
;
342 rhub
= &xhci
->usb3_rhub
;
343 ports
= rhub
->num_ports
;
344 xhci_common_hub_descriptor(xhci
, desc
, ports
);
345 desc
->bDescriptorType
= USB_DT_SS_HUB
;
346 desc
->bDescLength
= USB_DT_SS_HUB_SIZE
;
347 desc
->bPwrOn2PwrGood
= 50; /* usb 3.1 may fail if less than 100ms */
349 /* header decode latency should be zero for roothubs,
350 * see section 4.23.5.2.
352 desc
->u
.ss
.bHubHdrDecLat
= 0;
353 desc
->u
.ss
.wHubDelay
= 0;
356 /* bit 0 is reserved, bit 1 is for port 1, etc. */
357 for (i
= 0; i
< ports
; i
++) {
358 portsc
= readl(rhub
->ports
[i
]->addr
);
359 if (portsc
& PORT_DEV_REMOVE
)
360 port_removable
|= 1 << (i
+ 1);
363 desc
->u
.ss
.DeviceRemovable
= cpu_to_le16(port_removable
);
366 static void xhci_hub_descriptor(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
367 struct usb_hub_descriptor
*desc
)
370 if (hcd
->speed
>= HCD_USB3
)
371 xhci_usb3_hub_descriptor(hcd
, xhci
, desc
);
373 xhci_usb2_hub_descriptor(hcd
, xhci
, desc
);
377 static unsigned int xhci_port_speed(unsigned int port_status
)
379 if (DEV_LOWSPEED(port_status
))
380 return USB_PORT_STAT_LOW_SPEED
;
381 if (DEV_HIGHSPEED(port_status
))
382 return USB_PORT_STAT_HIGH_SPEED
;
384 * FIXME: Yes, we should check for full speed, but the core uses that as
385 * a default in portspeed() in usb/core/hub.c (which is the only place
386 * USB_PORT_STAT_*_SPEED is used).
392 * These bits are Read Only (RO) and should be saved and written to the
393 * registers: 0, 3, 10:13, 30
394 * connect status, over-current status, port speed, and device removable.
395 * connect status and port speed are also sticky - meaning they're in
396 * the AUX well and they aren't changed by a hot, warm, or cold reset.
398 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
400 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
401 * bits 5:8, 9, 14:15, 25:27
402 * link state, port power, port indicator state, "wake on" enable state
404 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
406 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
409 #define XHCI_PORT_RW1S ((1<<4))
411 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
412 * bits 1, 17, 18, 19, 20, 21, 22, 23
413 * port enable/disable, and
414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
415 * over-current, reset, link state, and L1 change
417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
419 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
422 #define XHCI_PORT_RW ((1<<16))
424 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
427 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
430 * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
431 * @state: u32 port value read from portsc register to be cleanup up
433 * Given a port state, this function returns a value that would result in the
434 * port being in the same state, if the value was written to the port status
436 * Save Read Only (RO) bits and save read/write bits where
437 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
438 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
440 * Return: u32 value that can be written back to portsc register without
441 * changing port state.
444 u32
xhci_port_state_to_neutral(u32 state
)
446 /* Save read-only status and port state */
447 return (state
& XHCI_PORT_RO
) | (state
& XHCI_PORT_RWS
);
449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral
);
452 * xhci_find_slot_id_by_port() - Find slot id of a usb device on a roothub port
453 * @hcd: pointer to hcd of the roothub
454 * @xhci: pointer to xhci structure
455 * @port: one-based port number of the port in this roothub.
457 * Return: Slot id of the usb device connected to the root port, 0 if not found
460 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
465 enum usb_device_speed speed
;
468 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
469 if (!xhci
->devs
[i
] || !xhci
->devs
[i
]->udev
)
471 speed
= xhci
->devs
[i
]->udev
->speed
;
472 if (((speed
>= USB_SPEED_SUPER
) == (hcd
->speed
>= HCD_USB3
))
473 && xhci
->devs
[i
]->fake_port
== port
) {
481 EXPORT_SYMBOL_GPL(xhci_find_slot_id_by_port
);
485 * It issues stop endpoint command for EP 0 to 30. And wait the last command
487 * suspend will set to 1, if suspend bit need to set in command.
489 static int xhci_stop_device(struct xhci_hcd
*xhci
, int slot_id
, int suspend
)
491 struct xhci_virt_device
*virt_dev
;
492 struct xhci_command
*cmd
;
498 virt_dev
= xhci
->devs
[slot_id
];
502 trace_xhci_stop_device(virt_dev
);
504 cmd
= xhci_alloc_command(xhci
, true, GFP_NOIO
);
508 spin_lock_irqsave(&xhci
->lock
, flags
);
509 for (i
= LAST_EP_INDEX
; i
> 0; i
--) {
510 if (virt_dev
->eps
[i
].ring
&& virt_dev
->eps
[i
].ring
->dequeue
) {
511 struct xhci_ep_ctx
*ep_ctx
;
512 struct xhci_command
*command
;
514 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->out_ctx
, i
);
516 /* Check ep is running, required by AMD SNPS 3.1 xHC */
517 if (GET_EP_CTX_STATE(ep_ctx
) != EP_STATE_RUNNING
)
520 command
= xhci_alloc_command(xhci
, false, GFP_NOWAIT
);
522 spin_unlock_irqrestore(&xhci
->lock
, flags
);
527 ret
= xhci_queue_stop_endpoint(xhci
, command
, slot_id
,
530 spin_unlock_irqrestore(&xhci
->lock
, flags
);
531 xhci_free_command(xhci
, command
);
536 ret
= xhci_queue_stop_endpoint(xhci
, cmd
, slot_id
, 0, suspend
);
538 spin_unlock_irqrestore(&xhci
->lock
, flags
);
542 xhci_ring_cmd_db(xhci
);
543 spin_unlock_irqrestore(&xhci
->lock
, flags
);
545 /* Wait for last stop endpoint command to finish */
546 wait_for_completion(cmd
->completion
);
548 if (cmd
->status
== COMP_COMMAND_ABORTED
||
549 cmd
->status
== COMP_COMMAND_RING_STOPPED
) {
550 xhci_warn(xhci
, "Timeout while waiting for stop endpoint command\n");
555 xhci_free_command(xhci
, cmd
);
560 * Ring device, it rings the all doorbells unconditionally.
562 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
)
565 struct xhci_virt_ep
*ep
;
567 for (i
= 0; i
< LAST_EP_INDEX
+ 1; i
++) {
568 ep
= &xhci
->devs
[slot_id
]->eps
[i
];
570 if (ep
->ep_state
& EP_HAS_STREAMS
) {
571 for (s
= 1; s
< ep
->stream_info
->num_streams
; s
++)
572 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, s
);
573 } else if (ep
->ring
&& ep
->ring
->dequeue
) {
574 xhci_ring_ep_doorbell(xhci
, slot_id
, i
, 0);
581 static void xhci_disable_port(struct xhci_hcd
*xhci
, struct xhci_port
*port
)
586 hcd
= port
->rhub
->hcd
;
588 /* Don't allow the USB core to disable SuperSpeed ports. */
589 if (hcd
->speed
>= HCD_USB3
) {
590 xhci_dbg(xhci
, "Ignoring request to disable SuperSpeed port.\n");
594 if (xhci
->quirks
& XHCI_BROKEN_PORT_PED
) {
596 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
600 portsc
= readl(port
->addr
);
601 portsc
= xhci_port_state_to_neutral(portsc
);
603 /* Write 1 to disable the port */
604 writel(portsc
| PORT_PE
, port
->addr
);
606 portsc
= readl(port
->addr
);
607 xhci_dbg(xhci
, "disable port %d-%d, portsc: 0x%x\n",
608 hcd
->self
.busnum
, port
->hcd_portnum
+ 1, portsc
);
611 static void xhci_clear_port_change_bit(struct xhci_hcd
*xhci
, u16 wValue
,
612 u16 wIndex
, __le32 __iomem
*addr
, u32 port_status
)
614 char *port_change_bit
;
618 case USB_PORT_FEAT_C_RESET
:
620 port_change_bit
= "reset";
622 case USB_PORT_FEAT_C_BH_PORT_RESET
:
624 port_change_bit
= "warm(BH) reset";
626 case USB_PORT_FEAT_C_CONNECTION
:
628 port_change_bit
= "connect";
630 case USB_PORT_FEAT_C_OVER_CURRENT
:
632 port_change_bit
= "over-current";
634 case USB_PORT_FEAT_C_ENABLE
:
636 port_change_bit
= "enable/disable";
638 case USB_PORT_FEAT_C_SUSPEND
:
640 port_change_bit
= "suspend/resume";
642 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
644 port_change_bit
= "link state";
646 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
648 port_change_bit
= "config error";
651 /* Should never happen */
654 /* Change bits are all write 1 to clear */
655 writel(port_status
| status
, addr
);
656 port_status
= readl(addr
);
658 xhci_dbg(xhci
, "clear port%d %s change, portsc: 0x%x\n",
659 wIndex
+ 1, port_change_bit
, port_status
);
662 struct xhci_hub
*xhci_get_rhub(struct usb_hcd
*hcd
)
664 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
666 if (hcd
->speed
>= HCD_USB3
)
667 return &xhci
->usb3_rhub
;
668 return &xhci
->usb2_rhub
;
672 * xhci_set_port_power() must be called with xhci->lock held.
673 * It will release and re-aquire the lock while calling ACPI
676 static void xhci_set_port_power(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
677 bool on
, unsigned long *flags
)
678 __must_hold(&xhci
->lock
)
683 hcd
= port
->rhub
->hcd
;
684 temp
= readl(port
->addr
);
686 xhci_dbg(xhci
, "set port power %d-%d %s, portsc: 0x%x\n",
687 hcd
->self
.busnum
, port
->hcd_portnum
+ 1, on
? "ON" : "OFF", temp
);
689 temp
= xhci_port_state_to_neutral(temp
);
693 writel(temp
| PORT_POWER
, port
->addr
);
697 writel(temp
& ~PORT_POWER
, port
->addr
);
700 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
701 temp
= usb_acpi_power_manageable(hcd
->self
.root_hub
,
704 usb_acpi_set_power_state(hcd
->self
.root_hub
,
705 port
->hcd_portnum
, on
);
706 spin_lock_irqsave(&xhci
->lock
, *flags
);
709 static void xhci_port_set_test_mode(struct xhci_hcd
*xhci
,
710 u16 test_mode
, u16 wIndex
)
713 struct xhci_port
*port
;
715 /* xhci only supports test mode for usb2 ports */
716 port
= xhci
->usb2_rhub
.ports
[wIndex
];
717 temp
= readl(port
->addr
+ PORTPMSC
);
718 temp
|= test_mode
<< PORT_TEST_MODE_SHIFT
;
719 writel(temp
, port
->addr
+ PORTPMSC
);
720 xhci
->test_mode
= test_mode
;
721 if (test_mode
== USB_TEST_FORCE_ENABLE
)
725 static int xhci_enter_test_mode(struct xhci_hcd
*xhci
,
726 u16 test_mode
, u16 wIndex
, unsigned long *flags
)
727 __must_hold(&xhci
->lock
)
731 /* Disable all Device Slots */
732 xhci_dbg(xhci
, "Disable all slots\n");
733 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
734 for (i
= 1; i
<= HCS_MAX_SLOTS(xhci
->hcs_params1
); i
++) {
738 retval
= xhci_disable_slot(xhci
, i
);
739 xhci_free_virt_device(xhci
, i
);
741 xhci_err(xhci
, "Failed to disable slot %d, %d. Enter test mode anyway\n",
744 spin_lock_irqsave(&xhci
->lock
, *flags
);
745 /* Put all ports to the Disable state by clear PP */
746 xhci_dbg(xhci
, "Disable all port (PP = 0)\n");
747 /* Power off USB3 ports*/
748 for (i
= 0; i
< xhci
->usb3_rhub
.num_ports
; i
++)
749 xhci_set_port_power(xhci
, xhci
->usb3_rhub
.ports
[i
], false, flags
);
750 /* Power off USB2 ports*/
751 for (i
= 0; i
< xhci
->usb2_rhub
.num_ports
; i
++)
752 xhci_set_port_power(xhci
, xhci
->usb2_rhub
.ports
[i
], false, flags
);
753 /* Stop the controller */
754 xhci_dbg(xhci
, "Stop controller\n");
755 retval
= xhci_halt(xhci
);
758 /* Disable runtime PM for test mode */
759 pm_runtime_forbid(xhci_to_hcd(xhci
)->self
.controller
);
760 /* Set PORTPMSC.PTC field to enter selected test mode */
761 /* Port is selected by wIndex. port_id = wIndex + 1 */
762 xhci_dbg(xhci
, "Enter Test Mode: %d, Port_id=%d\n",
763 test_mode
, wIndex
+ 1);
764 xhci_port_set_test_mode(xhci
, test_mode
, wIndex
);
768 static int xhci_exit_test_mode(struct xhci_hcd
*xhci
)
772 if (!xhci
->test_mode
) {
773 xhci_err(xhci
, "Not in test mode, do nothing.\n");
776 if (xhci
->test_mode
== USB_TEST_FORCE_ENABLE
&&
777 !(xhci
->xhc_state
& XHCI_STATE_HALTED
)) {
778 retval
= xhci_halt(xhci
);
782 pm_runtime_allow(xhci_to_hcd(xhci
)->self
.controller
);
784 return xhci_reset(xhci
, XHCI_RESET_SHORT_USEC
);
787 void xhci_set_link_state(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
793 portsc
= readl(port
->addr
);
794 temp
= xhci_port_state_to_neutral(portsc
);
795 temp
&= ~PORT_PLS_MASK
;
796 temp
|= PORT_LINK_STROBE
| link_state
;
797 writel(temp
, port
->addr
);
799 xhci_dbg(xhci
, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
800 port
->rhub
->hcd
->self
.busnum
, port
->hcd_portnum
+ 1,
804 static void xhci_set_remote_wake_mask(struct xhci_hcd
*xhci
,
805 struct xhci_port
*port
, u16 wake_mask
)
809 temp
= readl(port
->addr
);
810 temp
= xhci_port_state_to_neutral(temp
);
812 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_CONNECT
)
813 temp
|= PORT_WKCONN_E
;
815 temp
&= ~PORT_WKCONN_E
;
817 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
)
818 temp
|= PORT_WKDISC_E
;
820 temp
&= ~PORT_WKDISC_E
;
822 if (wake_mask
& USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
)
825 temp
&= ~PORT_WKOC_E
;
827 writel(temp
, port
->addr
);
830 /* Test and clear port RWC bit */
831 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, struct xhci_port
*port
,
836 temp
= readl(port
->addr
);
837 if (temp
& port_bit
) {
838 temp
= xhci_port_state_to_neutral(temp
);
840 writel(temp
, port
->addr
);
844 /* Updates Link Status for super Speed port */
845 static void xhci_hub_report_usb3_link_state(struct xhci_hcd
*xhci
,
846 u32
*status
, u32 status_reg
)
848 u32 pls
= status_reg
& PORT_PLS_MASK
;
850 /* When the CAS bit is set then warm reset
851 * should be performed on port
853 if (status_reg
& PORT_CAS
) {
854 /* The CAS bit can be set while the port is
856 * Only roothubs have CAS bit, so we
857 * pretend to be in compliance mode
858 * unless we're already in compliance
859 * or the inactive state.
861 if (pls
!= USB_SS_PORT_LS_COMP_MOD
&&
862 pls
!= USB_SS_PORT_LS_SS_INACTIVE
) {
863 pls
= USB_SS_PORT_LS_COMP_MOD
;
865 /* Return also connection bit -
866 * hub state machine resets port
867 * when this bit is set.
869 pls
|= USB_PORT_STAT_CONNECTION
;
872 * Resume state is an xHCI internal state. Do not report it to
873 * usb core, instead, pretend to be U3, thus usb core knows
874 * it's not ready for transfer.
876 if (pls
== XDEV_RESUME
) {
877 *status
|= USB_SS_PORT_LS_U3
;
882 * If CAS bit isn't set but the Port is already at
883 * Compliance Mode, fake a connection so the USB core
884 * notices the Compliance state and resets the port.
885 * This resolves an issue generated by the SN65LVPE502CP
886 * in which sometimes the port enters compliance mode
887 * caused by a delay on the host-device negotiation.
889 if ((xhci
->quirks
& XHCI_COMP_MODE_QUIRK
) &&
890 (pls
== USB_SS_PORT_LS_COMP_MOD
))
891 pls
|= USB_PORT_STAT_CONNECTION
;
894 /* update status field */
899 * Function for Compliance Mode Quirk.
901 * This Function verifies if all xhc USB3 ports have entered U0, if so,
902 * the compliance mode timer is deleted. A port won't enter
903 * compliance mode if it has previously entered U0.
905 static void xhci_del_comp_mod_timer(struct xhci_hcd
*xhci
, u32 status
,
908 u32 all_ports_seen_u0
= ((1 << xhci
->usb3_rhub
.num_ports
) - 1);
909 bool port_in_u0
= ((status
& PORT_PLS_MASK
) == XDEV_U0
);
911 if (!(xhci
->quirks
& XHCI_COMP_MODE_QUIRK
))
914 if ((xhci
->port_status_u0
!= all_ports_seen_u0
) && port_in_u0
) {
915 xhci
->port_status_u0
|= 1 << wIndex
;
916 if (xhci
->port_status_u0
== all_ports_seen_u0
) {
917 del_timer_sync(&xhci
->comp_mode_recovery_timer
);
918 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
919 "All USB3 ports have entered U0 already!");
920 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
921 "Compliance Mode Recovery Timer Deleted.");
926 static int xhci_handle_usb2_port_link_resume(struct xhci_port
*port
,
928 unsigned long *flags
)
930 struct xhci_bus_state
*bus_state
;
931 struct xhci_hcd
*xhci
;
936 hcd
= port
->rhub
->hcd
;
937 bus_state
= &port
->rhub
->bus_state
;
938 xhci
= hcd_to_xhci(hcd
);
939 wIndex
= port
->hcd_portnum
;
941 if ((portsc
& PORT_RESET
) || !(portsc
& PORT_PE
)) {
944 /* did port event handler already start resume timing? */
945 if (!port
->resume_timestamp
) {
946 /* If not, maybe we are in a host initated resume? */
947 if (test_bit(wIndex
, &bus_state
->resuming_ports
)) {
948 /* Host initated resume doesn't time the resume
949 * signalling using resume_done[].
950 * It manually sets RESUME state, sleeps 20ms
951 * and sets U0 state. This should probably be
952 * changed, but not right now.
955 /* port resume was discovered now and here,
956 * start resume timing
958 unsigned long timeout
= jiffies
+
959 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
961 set_bit(wIndex
, &bus_state
->resuming_ports
);
962 port
->resume_timestamp
= timeout
;
963 mod_timer(&hcd
->rh_timer
, timeout
);
964 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
966 /* Has resume been signalled for USB_RESUME_TIME yet? */
967 } else if (time_after_eq(jiffies
, port
->resume_timestamp
)) {
970 xhci_dbg(xhci
, "resume USB2 port %d-%d\n",
971 hcd
->self
.busnum
, wIndex
+ 1);
973 port
->resume_timestamp
= 0;
974 clear_bit(wIndex
, &bus_state
->resuming_ports
);
976 reinit_completion(&port
->rexit_done
);
977 port
->rexit_active
= true;
979 xhci_test_and_clear_bit(xhci
, port
, PORT_PLC
);
980 xhci_set_link_state(xhci
, port
, XDEV_U0
);
982 spin_unlock_irqrestore(&xhci
->lock
, *flags
);
983 time_left
= wait_for_completion_timeout(
985 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS
));
986 spin_lock_irqsave(&xhci
->lock
, *flags
);
989 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
992 xhci_dbg(xhci
, "slot_id is zero\n");
995 xhci_ring_device(xhci
, slot_id
);
997 int port_status
= readl(port
->addr
);
999 xhci_warn(xhci
, "Port resume timed out, port %d-%d: 0x%x\n",
1000 hcd
->self
.busnum
, wIndex
+ 1, port_status
);
1002 * keep rexit_active set if U0 transition failed so we
1003 * know to report PORT_STAT_SUSPEND status back to
1004 * usbcore. It will be cleared later once the port is
1005 * out of RESUME/U3 state
1009 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1010 bus_state
->port_c_suspend
|= 1 << wIndex
;
1011 bus_state
->suspended_ports
&= ~(1 << wIndex
);
1017 static u32
xhci_get_ext_port_status(u32 raw_port_status
, u32 port_li
)
1022 /* only support rx and tx lane counts of 1 in usb3.1 spec */
1023 speed_id
= DEV_PORT_SPEED(raw_port_status
);
1024 ext_stat
|= speed_id
; /* bits 3:0, RX speed id */
1025 ext_stat
|= speed_id
<< 4; /* bits 7:4, TX speed id */
1027 ext_stat
|= PORT_RX_LANES(port_li
) << 8; /* bits 11:8 Rx lane count */
1028 ext_stat
|= PORT_TX_LANES(port_li
) << 12; /* bits 15:12 Tx lane count */
1033 static void xhci_get_usb3_port_status(struct xhci_port
*port
, u32
*status
,
1036 struct xhci_bus_state
*bus_state
;
1037 struct xhci_hcd
*xhci
;
1038 struct usb_hcd
*hcd
;
1042 bus_state
= &port
->rhub
->bus_state
;
1043 xhci
= hcd_to_xhci(port
->rhub
->hcd
);
1044 hcd
= port
->rhub
->hcd
;
1045 link_state
= portsc
& PORT_PLS_MASK
;
1046 portnum
= port
->hcd_portnum
;
1048 /* USB3 specific wPortChange bits
1050 * Port link change with port in resume state should not be
1051 * reported to usbcore, as this is an internal state to be
1052 * handled by xhci driver. Reporting PLC to usbcore may
1053 * cause usbcore clearing PLC first and port change event
1054 * irq won't be generated.
1057 if (portsc
& PORT_PLC
&& (link_state
!= XDEV_RESUME
))
1058 *status
|= USB_PORT_STAT_C_LINK_STATE
<< 16;
1059 if (portsc
& PORT_WRC
)
1060 *status
|= USB_PORT_STAT_C_BH_RESET
<< 16;
1061 if (portsc
& PORT_CEC
)
1062 *status
|= USB_PORT_STAT_C_CONFIG_ERROR
<< 16;
1064 /* USB3 specific wPortStatus bits */
1065 if (portsc
& PORT_POWER
) {
1066 *status
|= USB_SS_PORT_STAT_POWER
;
1067 /* link state handling */
1068 if (link_state
== XDEV_U0
)
1069 bus_state
->suspended_ports
&= ~(1 << portnum
);
1072 /* remote wake resume signaling complete */
1073 if (bus_state
->port_remote_wakeup
& (1 << portnum
) &&
1074 link_state
!= XDEV_RESUME
&&
1075 link_state
!= XDEV_RECOVERY
) {
1076 bus_state
->port_remote_wakeup
&= ~(1 << portnum
);
1077 usb_hcd_end_port_resume(&hcd
->self
, portnum
);
1080 xhci_hub_report_usb3_link_state(xhci
, status
, portsc
);
1081 xhci_del_comp_mod_timer(xhci
, portsc
, portnum
);
1084 static void xhci_get_usb2_port_status(struct xhci_port
*port
, u32
*status
,
1085 u32 portsc
, unsigned long *flags
)
1087 struct xhci_bus_state
*bus_state
;
1092 bus_state
= &port
->rhub
->bus_state
;
1093 link_state
= portsc
& PORT_PLS_MASK
;
1094 portnum
= port
->hcd_portnum
;
1096 /* USB2 wPortStatus bits */
1097 if (portsc
& PORT_POWER
) {
1098 *status
|= USB_PORT_STAT_POWER
;
1100 /* link state is only valid if port is powered */
1101 if (link_state
== XDEV_U3
)
1102 *status
|= USB_PORT_STAT_SUSPEND
;
1103 if (link_state
== XDEV_U2
)
1104 *status
|= USB_PORT_STAT_L1
;
1105 if (link_state
== XDEV_U0
) {
1106 if (bus_state
->suspended_ports
& (1 << portnum
)) {
1107 bus_state
->suspended_ports
&= ~(1 << portnum
);
1108 bus_state
->port_c_suspend
|= 1 << portnum
;
1111 if (link_state
== XDEV_RESUME
) {
1112 err
= xhci_handle_usb2_port_link_resume(port
, portsc
,
1115 *status
= 0xffffffff;
1116 else if (port
->resume_timestamp
|| port
->rexit_active
)
1117 *status
|= USB_PORT_STAT_SUSPEND
;
1122 * Clear usb2 resume signalling variables if port is no longer suspended
1123 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a
1124 * error state. Resume related variables should be cleared in all those cases.
1126 if (link_state
!= XDEV_U3
&& link_state
!= XDEV_RESUME
) {
1127 if (port
->resume_timestamp
||
1128 test_bit(portnum
, &bus_state
->resuming_ports
)) {
1129 port
->resume_timestamp
= 0;
1130 clear_bit(portnum
, &bus_state
->resuming_ports
);
1131 usb_hcd_end_port_resume(&port
->rhub
->hcd
->self
, portnum
);
1133 port
->rexit_active
= 0;
1138 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1141 * Possible side effects:
1142 * - Mark a port as being done with device resume,
1143 * and ring the endpoint doorbells.
1144 * - Stop the Synopsys redriver Compliance Mode polling.
1145 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1147 static u32
xhci_get_port_status(struct usb_hcd
*hcd
,
1148 struct xhci_bus_state
*bus_state
,
1149 u16 wIndex
, u32 raw_port_status
,
1150 unsigned long *flags
)
1151 __releases(&xhci
->lock
)
1152 __acquires(&xhci
->lock
)
1155 struct xhci_hub
*rhub
;
1156 struct xhci_port
*port
;
1158 rhub
= xhci_get_rhub(hcd
);
1159 port
= rhub
->ports
[wIndex
];
1161 /* common wPortChange bits */
1162 if (raw_port_status
& PORT_CSC
)
1163 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1164 if (raw_port_status
& PORT_PEC
)
1165 status
|= USB_PORT_STAT_C_ENABLE
<< 16;
1166 if ((raw_port_status
& PORT_OCC
))
1167 status
|= USB_PORT_STAT_C_OVERCURRENT
<< 16;
1168 if ((raw_port_status
& PORT_RC
))
1169 status
|= USB_PORT_STAT_C_RESET
<< 16;
1171 /* common wPortStatus bits */
1172 if (raw_port_status
& PORT_CONNECT
) {
1173 status
|= USB_PORT_STAT_CONNECTION
;
1174 status
|= xhci_port_speed(raw_port_status
);
1176 if (raw_port_status
& PORT_PE
)
1177 status
|= USB_PORT_STAT_ENABLE
;
1178 if (raw_port_status
& PORT_OC
)
1179 status
|= USB_PORT_STAT_OVERCURRENT
;
1180 if (raw_port_status
& PORT_RESET
)
1181 status
|= USB_PORT_STAT_RESET
;
1183 /* USB2 and USB3 specific bits, including Port Link State */
1184 if (hcd
->speed
>= HCD_USB3
)
1185 xhci_get_usb3_port_status(port
, &status
, raw_port_status
);
1187 xhci_get_usb2_port_status(port
, &status
, raw_port_status
,
1190 if (bus_state
->port_c_suspend
& (1 << wIndex
))
1191 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1196 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
1197 u16 wIndex
, char *buf
, u16 wLength
)
1199 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1201 unsigned long flags
;
1205 struct xhci_bus_state
*bus_state
;
1210 struct xhci_hub
*rhub
;
1211 struct xhci_port
**ports
;
1212 struct xhci_port
*port
;
1215 rhub
= xhci_get_rhub(hcd
);
1216 ports
= rhub
->ports
;
1217 max_ports
= rhub
->num_ports
;
1218 bus_state
= &rhub
->bus_state
;
1219 portnum1
= wIndex
& 0xff;
1221 spin_lock_irqsave(&xhci
->lock
, flags
);
1224 /* No power source, over-current reported per port */
1227 case GetHubDescriptor
:
1228 /* Check to make sure userspace is asking for the USB 3.0 hub
1229 * descriptor for the USB 3.0 roothub. If not, we stall the
1230 * endpoint, like external hubs do.
1232 if (hcd
->speed
>= HCD_USB3
&&
1233 (wLength
< USB_DT_SS_HUB_SIZE
||
1234 wValue
!= (USB_DT_SS_HUB
<< 8))) {
1235 xhci_dbg(xhci
, "Wrong hub descriptor type for "
1236 "USB 3.0 roothub.\n");
1239 xhci_hub_descriptor(hcd
, xhci
,
1240 (struct usb_hub_descriptor
*) buf
);
1242 case DeviceRequest
| USB_REQ_GET_DESCRIPTOR
:
1243 if ((wValue
& 0xff00) != (USB_DT_BOS
<< 8))
1246 if (hcd
->speed
< HCD_USB3
)
1249 retval
= xhci_create_usb3x_bos_desc(xhci
, buf
, wLength
);
1250 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1253 if (!portnum1
|| portnum1
> max_ports
)
1257 port
= ports
[portnum1
- 1];
1258 temp
= readl(port
->addr
);
1259 if (temp
== ~(u32
)0) {
1264 trace_xhci_get_port_status(wIndex
, temp
);
1265 status
= xhci_get_port_status(hcd
, bus_state
, wIndex
, temp
,
1267 if (status
== 0xffffffff)
1270 xhci_dbg(xhci
, "Get port status %d-%d read: 0x%x, return 0x%x",
1271 hcd
->self
.busnum
, portnum1
, temp
, status
);
1273 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1274 /* if USB 3.1 extended port status return additional 4 bytes */
1275 if (wValue
== 0x02) {
1278 if (hcd
->speed
< HCD_USB31
|| wLength
!= 8) {
1279 xhci_err(xhci
, "get ext port status invalid parameter\n");
1283 port_li
= readl(port
->addr
+ PORTLI
);
1284 status
= xhci_get_ext_port_status(temp
, port_li
);
1285 put_unaligned_le32(status
, &buf
[4]);
1288 case SetPortFeature
:
1289 if (wValue
== USB_PORT_FEAT_LINK_STATE
)
1290 link_state
= (wIndex
& 0xff00) >> 3;
1291 if (wValue
== USB_PORT_FEAT_REMOTE_WAKE_MASK
)
1292 wake_mask
= wIndex
& 0xff00;
1293 if (wValue
== USB_PORT_FEAT_TEST
)
1294 test_mode
= (wIndex
& 0xff00) >> 8;
1295 /* The MSB of wIndex is the U1/U2 timeout */
1296 timeout
= (wIndex
& 0xff00) >> 8;
1299 if (!portnum1
|| portnum1
> max_ports
)
1302 port
= ports
[portnum1
- 1];
1304 temp
= readl(port
->addr
);
1305 if (temp
== ~(u32
)0) {
1310 temp
= xhci_port_state_to_neutral(temp
);
1311 /* FIXME: What new port features do we need to support? */
1313 case USB_PORT_FEAT_SUSPEND
:
1314 temp
= readl(port
->addr
);
1315 if ((temp
& PORT_PLS_MASK
) != XDEV_U0
) {
1316 /* Resume the port to U0 first */
1317 xhci_set_link_state(xhci
, port
, XDEV_U0
);
1318 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1320 spin_lock_irqsave(&xhci
->lock
, flags
);
1322 /* In spec software should not attempt to suspend
1323 * a port unless the port reports that it is in the
1324 * enabled (PED = ‘1’,PLS < ‘3’) state.
1326 temp
= readl(port
->addr
);
1327 if ((temp
& PORT_PE
) == 0 || (temp
& PORT_RESET
)
1328 || (temp
& PORT_PLS_MASK
) >= XDEV_U3
) {
1329 xhci_warn(xhci
, "USB core suspending port %d-%d not in U0/U1/U2\n",
1330 hcd
->self
.busnum
, portnum1
);
1334 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1337 xhci_warn(xhci
, "slot_id is zero\n");
1340 /* unlock to execute stop endpoint commands */
1341 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1342 xhci_stop_device(xhci
, slot_id
, 1);
1343 spin_lock_irqsave(&xhci
->lock
, flags
);
1345 xhci_set_link_state(xhci
, port
, XDEV_U3
);
1347 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1348 msleep(10); /* wait device to enter */
1349 spin_lock_irqsave(&xhci
->lock
, flags
);
1351 temp
= readl(port
->addr
);
1352 bus_state
->suspended_ports
|= 1 << wIndex
;
1354 case USB_PORT_FEAT_LINK_STATE
:
1355 temp
= readl(port
->addr
);
1357 if (link_state
== USB_SS_PORT_LS_SS_DISABLED
) {
1358 xhci_dbg(xhci
, "Disable port %d-%d\n",
1359 hcd
->self
.busnum
, portnum1
);
1360 temp
= xhci_port_state_to_neutral(temp
);
1362 * Clear all change bits, so that we get a new
1365 temp
|= PORT_CSC
| PORT_PEC
| PORT_WRC
|
1366 PORT_OCC
| PORT_RC
| PORT_PLC
|
1368 writel(temp
| PORT_PE
, port
->addr
);
1369 temp
= readl(port
->addr
);
1373 /* Put link in RxDetect (enable port) */
1374 if (link_state
== USB_SS_PORT_LS_RX_DETECT
) {
1375 xhci_dbg(xhci
, "Enable port %d-%d\n",
1376 hcd
->self
.busnum
, portnum1
);
1377 xhci_set_link_state(xhci
, port
, link_state
);
1378 temp
= readl(port
->addr
);
1383 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1384 * root hub port's transition to compliance mode upon
1385 * detecting LFPS timeout may be controlled by an
1386 * Compliance Transition Enabled (CTE) flag (not
1387 * software visible). This flag is set by writing 0xA
1388 * to PORTSC PLS field which will allow transition to
1389 * compliance mode the next time LFPS timeout is
1390 * encountered. A warm reset will clear it.
1392 * The CTE flag is only supported if the HCCPARAMS2 CTC
1393 * flag is set, otherwise, the compliance substate is
1394 * automatically entered as on 1.0 and prior.
1396 if (link_state
== USB_SS_PORT_LS_COMP_MOD
) {
1397 if (!HCC2_CTC(xhci
->hcc_params2
)) {
1398 xhci_dbg(xhci
, "CTC flag is 0, port already supports entering compliance mode\n");
1402 if ((temp
& PORT_CONNECT
)) {
1403 xhci_warn(xhci
, "Can't set compliance mode when port is connected\n");
1407 xhci_dbg(xhci
, "Enable compliance mode transition for port %d-%d\n",
1408 hcd
->self
.busnum
, portnum1
);
1409 xhci_set_link_state(xhci
, port
, link_state
);
1411 temp
= readl(port
->addr
);
1414 /* Port must be enabled */
1415 if (!(temp
& PORT_PE
)) {
1419 /* Can't set port link state above '3' (U3) */
1420 if (link_state
> USB_SS_PORT_LS_U3
) {
1421 xhci_warn(xhci
, "Cannot set port %d-%d link state %d\n",
1422 hcd
->self
.busnum
, portnum1
, link_state
);
1427 * set link to U0, steps depend on current link state.
1428 * U3: set link to U0 and wait for u3exit completion.
1429 * U1/U2: no PLC complete event, only set link to U0.
1430 * Resume/Recovery: device initiated U0, only wait for
1433 if (link_state
== USB_SS_PORT_LS_U0
) {
1434 u32 pls
= temp
& PORT_PLS_MASK
;
1435 bool wait_u0
= false;
1440 if (pls
== XDEV_U3
||
1441 pls
== XDEV_RESUME
||
1442 pls
== XDEV_RECOVERY
) {
1444 reinit_completion(&port
->u3exit_done
);
1446 if (pls
<= XDEV_U3
) /* U1, U2, U3 */
1447 xhci_set_link_state(xhci
, port
, USB_SS_PORT_LS_U0
);
1453 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1454 if (!wait_for_completion_timeout(&port
->u3exit_done
,
1455 msecs_to_jiffies(500)))
1456 xhci_dbg(xhci
, "missing U0 port change event for port %d-%d\n",
1457 hcd
->self
.busnum
, portnum1
);
1458 spin_lock_irqsave(&xhci
->lock
, flags
);
1459 temp
= readl(port
->addr
);
1463 if (link_state
== USB_SS_PORT_LS_U3
) {
1465 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1468 /* unlock to execute stop endpoint
1470 spin_unlock_irqrestore(&xhci
->lock
,
1472 xhci_stop_device(xhci
, slot_id
, 1);
1473 spin_lock_irqsave(&xhci
->lock
, flags
);
1475 xhci_set_link_state(xhci
, port
, USB_SS_PORT_LS_U3
);
1476 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1478 usleep_range(4000, 8000);
1479 temp
= readl(port
->addr
);
1480 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
)
1483 spin_lock_irqsave(&xhci
->lock
, flags
);
1484 temp
= readl(port
->addr
);
1485 bus_state
->suspended_ports
|= 1 << wIndex
;
1488 case USB_PORT_FEAT_POWER
:
1490 * Turn on ports, even if there isn't per-port switching.
1491 * HC will report connect events even before this is set.
1492 * However, hub_wq will ignore the roothub events until
1493 * the roothub is registered.
1495 xhci_set_port_power(xhci
, port
, true, &flags
);
1497 case USB_PORT_FEAT_RESET
:
1498 temp
= (temp
| PORT_RESET
);
1499 writel(temp
, port
->addr
);
1501 temp
= readl(port
->addr
);
1502 xhci_dbg(xhci
, "set port reset, actual port %d-%d status = 0x%x\n",
1503 hcd
->self
.busnum
, portnum1
, temp
);
1505 case USB_PORT_FEAT_REMOTE_WAKE_MASK
:
1506 xhci_set_remote_wake_mask(xhci
, port
, wake_mask
);
1507 temp
= readl(port
->addr
);
1508 xhci_dbg(xhci
, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1509 hcd
->self
.busnum
, portnum1
, temp
);
1511 case USB_PORT_FEAT_BH_PORT_RESET
:
1513 writel(temp
, port
->addr
);
1514 temp
= readl(port
->addr
);
1516 case USB_PORT_FEAT_U1_TIMEOUT
:
1517 if (hcd
->speed
< HCD_USB3
)
1519 temp
= readl(port
->addr
+ PORTPMSC
);
1520 temp
&= ~PORT_U1_TIMEOUT_MASK
;
1521 temp
|= PORT_U1_TIMEOUT(timeout
);
1522 writel(temp
, port
->addr
+ PORTPMSC
);
1524 case USB_PORT_FEAT_U2_TIMEOUT
:
1525 if (hcd
->speed
< HCD_USB3
)
1527 temp
= readl(port
->addr
+ PORTPMSC
);
1528 temp
&= ~PORT_U2_TIMEOUT_MASK
;
1529 temp
|= PORT_U2_TIMEOUT(timeout
);
1530 writel(temp
, port
->addr
+ PORTPMSC
);
1532 case USB_PORT_FEAT_TEST
:
1533 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1534 if (hcd
->speed
!= HCD_USB2
)
1536 if (test_mode
> USB_TEST_FORCE_ENABLE
||
1537 test_mode
< USB_TEST_J
)
1539 retval
= xhci_enter_test_mode(xhci
, test_mode
, wIndex
,
1545 /* unblock any posted writes */
1546 temp
= readl(port
->addr
);
1548 case ClearPortFeature
:
1549 if (!portnum1
|| portnum1
> max_ports
)
1552 port
= ports
[portnum1
- 1];
1555 temp
= readl(port
->addr
);
1556 if (temp
== ~(u32
)0) {
1561 /* FIXME: What new port features do we need to support? */
1562 temp
= xhci_port_state_to_neutral(temp
);
1564 case USB_PORT_FEAT_SUSPEND
:
1565 temp
= readl(port
->addr
);
1566 xhci_dbg(xhci
, "clear USB_PORT_FEAT_SUSPEND\n");
1567 xhci_dbg(xhci
, "PORTSC %04x\n", temp
);
1568 if (temp
& PORT_RESET
)
1570 if ((temp
& PORT_PLS_MASK
) == XDEV_U3
) {
1571 if ((temp
& PORT_PE
) == 0)
1574 set_bit(wIndex
, &bus_state
->resuming_ports
);
1575 usb_hcd_start_port_resume(&hcd
->self
, wIndex
);
1576 xhci_set_link_state(xhci
, port
, XDEV_RESUME
);
1577 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1578 msleep(USB_RESUME_TIMEOUT
);
1579 spin_lock_irqsave(&xhci
->lock
, flags
);
1580 xhci_set_link_state(xhci
, port
, XDEV_U0
);
1581 clear_bit(wIndex
, &bus_state
->resuming_ports
);
1582 usb_hcd_end_port_resume(&hcd
->self
, wIndex
);
1584 bus_state
->port_c_suspend
|= 1 << wIndex
;
1586 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1589 xhci_dbg(xhci
, "slot_id is zero\n");
1592 xhci_ring_device(xhci
, slot_id
);
1594 case USB_PORT_FEAT_C_SUSPEND
:
1595 bus_state
->port_c_suspend
&= ~(1 << wIndex
);
1597 case USB_PORT_FEAT_C_RESET
:
1598 case USB_PORT_FEAT_C_BH_PORT_RESET
:
1599 case USB_PORT_FEAT_C_CONNECTION
:
1600 case USB_PORT_FEAT_C_OVER_CURRENT
:
1601 case USB_PORT_FEAT_C_ENABLE
:
1602 case USB_PORT_FEAT_C_PORT_LINK_STATE
:
1603 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR
:
1604 xhci_clear_port_change_bit(xhci
, wValue
, wIndex
,
1607 case USB_PORT_FEAT_ENABLE
:
1608 xhci_disable_port(xhci
, port
);
1610 case USB_PORT_FEAT_POWER
:
1611 xhci_set_port_power(xhci
, port
, false, &flags
);
1613 case USB_PORT_FEAT_TEST
:
1614 retval
= xhci_exit_test_mode(xhci
);
1622 /* "stall" on error */
1625 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1628 EXPORT_SYMBOL_GPL(xhci_hub_control
);
1631 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1632 * Ports are 0-indexed from the HCD point of view,
1633 * and 1-indexed from the USB core pointer of view.
1635 * Note that the status change bits will be cleared as soon as a port status
1636 * change event is generated, so we use the saved status from that event.
1638 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1640 unsigned long flags
;
1644 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1646 struct xhci_bus_state
*bus_state
;
1647 bool reset_change
= false;
1648 struct xhci_hub
*rhub
;
1649 struct xhci_port
**ports
;
1651 rhub
= xhci_get_rhub(hcd
);
1652 ports
= rhub
->ports
;
1653 max_ports
= rhub
->num_ports
;
1654 bus_state
= &rhub
->bus_state
;
1656 /* Initial status is no changes */
1657 retval
= (max_ports
+ 8) / 8;
1658 memset(buf
, 0, retval
);
1661 * Inform the usbcore about resume-in-progress by returning
1662 * a non-zero value even if there are no status changes.
1664 spin_lock_irqsave(&xhci
->lock
, flags
);
1666 status
= bus_state
->resuming_ports
;
1669 * SS devices are only visible to roothub after link training completes.
1670 * Keep polling roothubs for a grace period after xHC start
1672 if (xhci
->run_graceperiod
) {
1673 if (time_before(jiffies
, xhci
->run_graceperiod
))
1676 xhci
->run_graceperiod
= 0;
1679 mask
= PORT_CSC
| PORT_PEC
| PORT_OCC
| PORT_PLC
| PORT_WRC
| PORT_CEC
;
1681 /* For each port, did anything change? If so, set that bit in buf. */
1682 for (i
= 0; i
< max_ports
; i
++) {
1683 temp
= readl(ports
[i
]->addr
);
1684 if (temp
== ~(u32
)0) {
1689 trace_xhci_hub_status_data(i
, temp
);
1691 if ((temp
& mask
) != 0 ||
1692 (bus_state
->port_c_suspend
& 1 << i
) ||
1693 (ports
[i
]->resume_timestamp
&& time_after_eq(
1694 jiffies
, ports
[i
]->resume_timestamp
))) {
1695 buf
[(i
+ 1) / 8] |= 1 << (i
+ 1) % 8;
1698 if ((temp
& PORT_RC
))
1699 reset_change
= true;
1703 if (!status
&& !reset_change
) {
1704 xhci_dbg(xhci
, "%s: stopping usb%d port polling\n",
1705 __func__
, hcd
->self
.busnum
);
1706 clear_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1708 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1709 return status
? retval
: 0;
1714 int xhci_bus_suspend(struct usb_hcd
*hcd
)
1716 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1717 int max_ports
, port_index
;
1718 struct xhci_bus_state
*bus_state
;
1719 unsigned long flags
;
1720 struct xhci_hub
*rhub
;
1721 struct xhci_port
**ports
;
1722 u32 portsc_buf
[USB_MAXCHILDREN
];
1725 rhub
= xhci_get_rhub(hcd
);
1726 ports
= rhub
->ports
;
1727 max_ports
= rhub
->num_ports
;
1728 bus_state
= &rhub
->bus_state
;
1729 wake_enabled
= hcd
->self
.root_hub
->do_remote_wakeup
;
1731 spin_lock_irqsave(&xhci
->lock
, flags
);
1734 if (bus_state
->resuming_ports
|| /* USB2 */
1735 bus_state
->port_remote_wakeup
) { /* USB3 */
1736 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1737 xhci_dbg(xhci
, "usb%d bus suspend to fail because a port is resuming\n",
1743 * Prepare ports for suspend, but don't write anything before all ports
1744 * are checked and we know bus suspend can proceed
1746 bus_state
->bus_suspended
= 0;
1747 port_index
= max_ports
;
1748 while (port_index
--) {
1752 t1
= readl(ports
[port_index
]->addr
);
1753 t2
= xhci_port_state_to_neutral(t1
);
1754 portsc_buf
[port_index
] = 0;
1757 * Give a USB3 port in link training time to finish, but don't
1758 * prevent suspend as port might be stuck
1760 if ((hcd
->speed
>= HCD_USB3
) && retries
-- &&
1761 (t1
& PORT_PLS_MASK
) == XDEV_POLLING
) {
1762 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1763 msleep(XHCI_PORT_POLLING_LFPS_TIME
);
1764 spin_lock_irqsave(&xhci
->lock
, flags
);
1765 xhci_dbg(xhci
, "port %d-%d polling in bus suspend, waiting\n",
1766 hcd
->self
.busnum
, port_index
+ 1);
1769 /* bail out if port detected a over-current condition */
1771 bus_state
->bus_suspended
= 0;
1772 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1773 xhci_dbg(xhci
, "Bus suspend bailout, port over-current detected\n");
1776 /* suspend ports in U0, or bail out for new connect changes */
1777 if ((t1
& PORT_PE
) && (t1
& PORT_PLS_MASK
) == XDEV_U0
) {
1778 if ((t1
& PORT_CSC
) && wake_enabled
) {
1779 bus_state
->bus_suspended
= 0;
1780 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1781 xhci_dbg(xhci
, "Bus suspend bailout, port connect change\n");
1784 xhci_dbg(xhci
, "port %d-%d not suspended\n",
1785 hcd
->self
.busnum
, port_index
+ 1);
1786 t2
&= ~PORT_PLS_MASK
;
1787 t2
|= PORT_LINK_STROBE
| XDEV_U3
;
1788 set_bit(port_index
, &bus_state
->bus_suspended
);
1790 /* USB core sets remote wake mask for USB 3.0 hubs,
1791 * including the USB 3.0 roothub, but only if CONFIG_PM
1792 * is enabled, so also enable remote wake here.
1795 if (t1
& PORT_CONNECT
) {
1796 t2
|= PORT_WKOC_E
| PORT_WKDISC_E
;
1797 t2
&= ~PORT_WKCONN_E
;
1799 t2
|= PORT_WKOC_E
| PORT_WKCONN_E
;
1800 t2
&= ~PORT_WKDISC_E
;
1803 if ((xhci
->quirks
& XHCI_U2_DISABLE_WAKE
) &&
1804 (hcd
->speed
< HCD_USB3
)) {
1805 if (usb_amd_pt_check_port(hcd
->self
.controller
,
1807 t2
&= ~PORT_WAKE_BITS
;
1810 t2
&= ~PORT_WAKE_BITS
;
1812 t1
= xhci_port_state_to_neutral(t1
);
1814 portsc_buf
[port_index
] = t2
;
1817 /* write port settings, stopping and suspending ports if needed */
1818 port_index
= max_ports
;
1819 while (port_index
--) {
1820 if (!portsc_buf
[port_index
])
1822 if (test_bit(port_index
, &bus_state
->bus_suspended
)) {
1825 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1828 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1829 xhci_stop_device(xhci
, slot_id
, 1);
1830 spin_lock_irqsave(&xhci
->lock
, flags
);
1833 writel(portsc_buf
[port_index
], ports
[port_index
]->addr
);
1835 hcd
->state
= HC_STATE_SUSPENDED
;
1836 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(10);
1837 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1839 if (bus_state
->bus_suspended
)
1840 usleep_range(5000, 10000);
1846 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1847 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1848 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1850 static bool xhci_port_missing_cas_quirk(struct xhci_port
*port
)
1854 portsc
= readl(port
->addr
);
1856 /* if any of these are set we are not stuck */
1857 if (portsc
& (PORT_CONNECT
| PORT_CAS
))
1860 if (((portsc
& PORT_PLS_MASK
) != XDEV_POLLING
) &&
1861 ((portsc
& PORT_PLS_MASK
) != XDEV_COMP_MODE
))
1864 /* clear wakeup/change bits, and do a warm port reset */
1865 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1867 writel(portsc
, port
->addr
);
1873 int xhci_bus_resume(struct usb_hcd
*hcd
)
1875 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
1876 struct xhci_bus_state
*bus_state
;
1877 unsigned long flags
;
1878 int max_ports
, port_index
;
1883 struct xhci_hub
*rhub
;
1884 struct xhci_port
**ports
;
1886 rhub
= xhci_get_rhub(hcd
);
1887 ports
= rhub
->ports
;
1888 max_ports
= rhub
->num_ports
;
1889 bus_state
= &rhub
->bus_state
;
1891 if (time_before(jiffies
, bus_state
->next_statechange
))
1894 spin_lock_irqsave(&xhci
->lock
, flags
);
1895 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1896 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1900 /* delay the irqs */
1901 temp
= readl(&xhci
->op_regs
->command
);
1903 writel(temp
, &xhci
->op_regs
->command
);
1905 /* bus specific resume for ports we suspended at bus_suspend */
1906 if (hcd
->speed
>= HCD_USB3
)
1907 next_state
= XDEV_U0
;
1909 next_state
= XDEV_RESUME
;
1911 port_index
= max_ports
;
1912 while (port_index
--) {
1913 portsc
= readl(ports
[port_index
]->addr
);
1915 /* warm reset CAS limited ports stuck in polling/compliance */
1916 if ((xhci
->quirks
& XHCI_MISSING_CAS
) &&
1917 (hcd
->speed
>= HCD_USB3
) &&
1918 xhci_port_missing_cas_quirk(ports
[port_index
])) {
1919 xhci_dbg(xhci
, "reset stuck port %d-%d\n",
1920 hcd
->self
.busnum
, port_index
+ 1);
1921 clear_bit(port_index
, &bus_state
->bus_suspended
);
1924 /* resume if we suspended the link, and it is still suspended */
1925 if (test_bit(port_index
, &bus_state
->bus_suspended
))
1926 switch (portsc
& PORT_PLS_MASK
) {
1928 portsc
= xhci_port_state_to_neutral(portsc
);
1929 portsc
&= ~PORT_PLS_MASK
;
1930 portsc
|= PORT_LINK_STROBE
| next_state
;
1933 /* resume already initiated */
1936 /* not in a resumeable state, ignore it */
1937 clear_bit(port_index
,
1938 &bus_state
->bus_suspended
);
1941 /* disable wake for all ports, write new link state if needed */
1942 portsc
&= ~(PORT_RWC_BITS
| PORT_CEC
| PORT_WAKE_BITS
);
1943 writel(portsc
, ports
[port_index
]->addr
);
1946 /* USB2 specific resume signaling delay and U0 link state transition */
1947 if (hcd
->speed
< HCD_USB3
) {
1948 if (bus_state
->bus_suspended
) {
1949 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1950 msleep(USB_RESUME_TIMEOUT
);
1951 spin_lock_irqsave(&xhci
->lock
, flags
);
1953 for_each_set_bit(port_index
, &bus_state
->bus_suspended
,
1955 /* Clear PLC to poll it later for U0 transition */
1956 xhci_test_and_clear_bit(xhci
, ports
[port_index
],
1958 xhci_set_link_state(xhci
, ports
[port_index
], XDEV_U0
);
1962 /* poll for U0 link state complete, both USB2 and USB3 */
1963 for_each_set_bit(port_index
, &bus_state
->bus_suspended
, BITS_PER_LONG
) {
1964 sret
= xhci_handshake(ports
[port_index
]->addr
, PORT_PLC
,
1965 PORT_PLC
, 10 * 1000);
1967 xhci_warn(xhci
, "port %d-%d resume PLC timeout\n",
1968 hcd
->self
.busnum
, port_index
+ 1);
1971 xhci_test_and_clear_bit(xhci
, ports
[port_index
], PORT_PLC
);
1972 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
, port_index
+ 1);
1974 xhci_ring_device(xhci
, slot_id
);
1976 (void) readl(&xhci
->op_regs
->command
);
1978 bus_state
->next_statechange
= jiffies
+ msecs_to_jiffies(5);
1979 /* re-enable irqs */
1980 temp
= readl(&xhci
->op_regs
->command
);
1982 writel(temp
, &xhci
->op_regs
->command
);
1983 temp
= readl(&xhci
->op_regs
->command
);
1985 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1989 unsigned long xhci_get_resuming_ports(struct usb_hcd
*hcd
)
1991 struct xhci_hub
*rhub
= xhci_get_rhub(hcd
);
1993 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1994 return rhub
->bus_state
.resuming_ports
; /* USB2 ports only */
1997 #endif /* CONFIG_PM */