2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
94 #include <linux/module.h>
95 #include <linux/kernel.h>
96 #include <linux/sched.h>
97 #include <linux/slab.h>
98 #include <linux/init.h>
99 #include <linux/list.h>
100 #include <linux/kobject.h>
101 #include <linux/prefetch.h>
102 #include <linux/platform_device.h>
103 #include <linux/io.h>
107 #include <asm/errno.h>
108 #include <linux/usb/ch9.h>
109 #include <linux/usb/gadget.h>
110 #include <linux/usb/musb.h>
112 #include "linux-compat.h"
113 #include "usb-compat.h"
116 #include "musb_core.h"
118 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
121 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
122 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
124 #define MUSB_VERSION "6.0"
126 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
128 #define MUSB_DRIVER_NAME "musb-hdrc"
129 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
131 MODULE_DESCRIPTION(DRIVER_INFO
);
132 MODULE_AUTHOR(DRIVER_AUTHOR
);
133 MODULE_LICENSE("GPL");
134 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
138 /*-------------------------------------------------------------------------*/
140 static inline struct musb
*dev_to_musb(struct device
*dev
)
142 return dev_get_drvdata(dev
);
146 /*-------------------------------------------------------------------------*/
149 #ifndef CONFIG_BLACKFIN
150 static int musb_ulpi_read(struct usb_phy
*phy
, u32 offset
)
152 void __iomem
*addr
= phy
->io_priv
;
158 pm_runtime_get_sync(phy
->io_dev
);
160 /* Make sure the transceiver is not in low power mode */
161 power
= musb_readb(addr
, MUSB_POWER
);
162 power
&= ~MUSB_POWER_SUSPENDM
;
163 musb_writeb(addr
, MUSB_POWER
, power
);
165 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
166 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
169 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
170 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
,
171 MUSB_ULPI_REG_REQ
| MUSB_ULPI_RDN_WR
);
173 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
174 & MUSB_ULPI_REG_CMPLT
)) {
182 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
183 r
&= ~MUSB_ULPI_REG_CMPLT
;
184 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
186 ret
= musb_readb(addr
, MUSB_ULPI_REG_DATA
);
189 pm_runtime_put(phy
->io_dev
);
194 static int musb_ulpi_write(struct usb_phy
*phy
, u32 offset
, u32 data
)
196 void __iomem
*addr
= phy
->io_priv
;
202 pm_runtime_get_sync(phy
->io_dev
);
204 /* Make sure the transceiver is not in low power mode */
205 power
= musb_readb(addr
, MUSB_POWER
);
206 power
&= ~MUSB_POWER_SUSPENDM
;
207 musb_writeb(addr
, MUSB_POWER
, power
);
209 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
210 musb_writeb(addr
, MUSB_ULPI_REG_DATA
, (u8
)data
);
211 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, MUSB_ULPI_REG_REQ
);
213 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
214 & MUSB_ULPI_REG_CMPLT
)) {
222 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
223 r
&= ~MUSB_ULPI_REG_CMPLT
;
224 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
227 pm_runtime_put(phy
->io_dev
);
232 #define musb_ulpi_read NULL
233 #define musb_ulpi_write NULL
236 static struct usb_phy_io_ops musb_ulpi_access
= {
237 .read
= musb_ulpi_read
,
238 .write
= musb_ulpi_write
,
242 /*-------------------------------------------------------------------------*/
244 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
247 * Load an endpoint's FIFO
249 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
251 struct musb
*musb
= hw_ep
->musb
;
252 void __iomem
*fifo
= hw_ep
->fifo
;
256 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
257 'T', hw_ep
->epnum
, fifo
, len
, src
);
259 /* we can't assume unaligned reads work */
260 if (likely((0x01 & (unsigned long) src
) == 0)) {
263 /* best case is 32bit-aligned source address */
264 if ((0x02 & (unsigned long) src
) == 0) {
266 writesl(fifo
, src
+ index
, len
>> 2);
267 index
+= len
& ~0x03;
270 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
275 writesw(fifo
, src
+ index
, len
>> 1);
276 index
+= len
& ~0x01;
280 musb_writeb(fifo
, 0, src
[index
]);
283 writesb(fifo
, src
, len
);
287 #if !defined(CONFIG_USB_MUSB_AM35X)
289 * Unload an endpoint's FIFO
291 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
293 struct musb
*musb
= hw_ep
->musb
;
294 void __iomem
*fifo
= hw_ep
->fifo
;
296 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
297 'R', hw_ep
->epnum
, fifo
, len
, dst
);
299 /* we can't assume unaligned writes work */
300 if (likely((0x01 & (unsigned long) dst
) == 0)) {
303 /* best case is 32bit-aligned destination address */
304 if ((0x02 & (unsigned long) dst
) == 0) {
306 readsl(fifo
, dst
, len
>> 2);
310 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
315 readsw(fifo
, dst
, len
>> 1);
320 dst
[index
] = musb_readb(fifo
, 0);
323 readsb(fifo
, dst
, len
);
328 #endif /* normal PIO */
331 /*-------------------------------------------------------------------------*/
333 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
334 static const u8 musb_test_packet
[53] = {
335 /* implicit SYNC then DATA0 to start */
338 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
340 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
342 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
343 /* JJJJJJJKKKKKKK x8 */
344 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
346 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
347 /* JKKKKKKK x10, JK */
348 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
350 /* implicit CRC16 then EOP to end */
353 void musb_load_testpacket(struct musb
*musb
)
355 void __iomem
*regs
= musb
->endpoints
[0].regs
;
357 musb_ep_select(musb
->mregs
, 0);
358 musb_write_fifo(musb
->control_ep
,
359 sizeof(musb_test_packet
), musb_test_packet
);
360 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
364 /*-------------------------------------------------------------------------*/
367 * Handles OTG hnp timeouts, such as b_ase0_brst
369 void musb_otg_timer_func(unsigned long data
)
371 struct musb
*musb
= (struct musb
*)data
;
374 spin_lock_irqsave(&musb
->lock
, flags
);
375 switch (musb
->xceiv
->state
) {
376 case OTG_STATE_B_WAIT_ACON
:
377 dev_dbg(musb
->controller
, "HNP: b_wait_acon timeout; back to b_peripheral\n");
378 musb_g_disconnect(musb
);
379 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
382 case OTG_STATE_A_SUSPEND
:
383 case OTG_STATE_A_WAIT_BCON
:
384 dev_dbg(musb
->controller
, "HNP: %s timeout\n",
385 otg_state_string(musb
->xceiv
->state
));
386 musb_platform_set_vbus(musb
, 0);
387 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
390 dev_dbg(musb
->controller
, "HNP: Unhandled mode %s\n",
391 otg_state_string(musb
->xceiv
->state
));
393 musb
->ignore_disconnect
= 0;
394 spin_unlock_irqrestore(&musb
->lock
, flags
);
398 * Stops the HNP transition. Caller must take care of locking.
400 void musb_hnp_stop(struct musb
*musb
)
402 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
403 void __iomem
*mbase
= musb
->mregs
;
406 dev_dbg(musb
->controller
, "HNP: stop from %s\n", otg_state_string(musb
->xceiv
->state
));
408 switch (musb
->xceiv
->state
) {
409 case OTG_STATE_A_PERIPHERAL
:
410 musb_g_disconnect(musb
);
411 dev_dbg(musb
->controller
, "HNP: back to %s\n",
412 otg_state_string(musb
->xceiv
->state
));
414 case OTG_STATE_B_HOST
:
415 dev_dbg(musb
->controller
, "HNP: Disabling HR\n");
416 hcd
->self
.is_b_host
= 0;
417 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
419 reg
= musb_readb(mbase
, MUSB_POWER
);
420 reg
|= MUSB_POWER_SUSPENDM
;
421 musb_writeb(mbase
, MUSB_POWER
, reg
);
422 /* REVISIT: Start SESSION_REQUEST here? */
425 dev_dbg(musb
->controller
, "HNP: Stopping in unknown state %s\n",
426 otg_state_string(musb
->xceiv
->state
));
430 * When returning to A state after HNP, avoid hub_port_rebounce(),
431 * which cause occasional OPT A "Did not receive reset after connect"
434 musb
->port1_status
&= ~(USB_PORT_STAT_C_CONNECTION
<< 16);
439 * Interrupt Service Routine to record USB "global" interrupts.
440 * Since these do not happen often and signify things of
441 * paramount importance, it seems OK to check them individually;
442 * the order of the tests is specified in the manual
444 * @param musb instance pointer
445 * @param int_usb register contents
450 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
454 struct usb_otg
*otg
= musb
->xceiv
->otg
;
456 irqreturn_t handled
= IRQ_NONE
;
458 dev_dbg(musb
->controller
, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power
, devctl
,
462 /* in host mode, the peripheral may issue remote wakeup.
463 * in peripheral mode, the host may resume the link.
464 * spurious RESUME irqs happen too, paired with SUSPEND.
466 if (int_usb
& MUSB_INTR_RESUME
) {
467 handled
= IRQ_HANDLED
;
468 dev_dbg(musb
->controller
, "RESUME (%s)\n", otg_state_string(musb
->xceiv
->state
));
470 if (devctl
& MUSB_DEVCTL_HM
) {
471 void __iomem
*mbase
= musb
->mregs
;
473 switch (musb
->xceiv
->state
) {
474 case OTG_STATE_A_SUSPEND
:
475 /* remote wakeup? later, GetPortStatus
476 * will stop RESUME signaling
479 if (power
& MUSB_POWER_SUSPENDM
) {
481 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
482 dev_dbg(musb
->controller
, "Spurious SUSPENDM\n");
486 power
&= ~MUSB_POWER_SUSPENDM
;
487 musb_writeb(mbase
, MUSB_POWER
,
488 power
| MUSB_POWER_RESUME
);
490 musb
->port1_status
|=
491 (USB_PORT_STAT_C_SUSPEND
<< 16)
492 | MUSB_PORT_STAT_RESUME
;
493 musb
->rh_timer
= jiffies
494 + msecs_to_jiffies(20);
496 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
498 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
500 case OTG_STATE_B_WAIT_ACON
:
501 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
506 WARNING("bogus %s RESUME (%s)\n",
508 otg_state_string(musb
->xceiv
->state
));
511 switch (musb
->xceiv
->state
) {
512 case OTG_STATE_A_SUSPEND
:
513 /* possibly DISCONNECT is upcoming */
514 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
515 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
517 case OTG_STATE_B_WAIT_ACON
:
518 case OTG_STATE_B_PERIPHERAL
:
519 /* disconnect while suspended? we may
520 * not get a disconnect irq...
522 if ((devctl
& MUSB_DEVCTL_VBUS
)
523 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
525 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
526 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
531 case OTG_STATE_B_IDLE
:
532 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
535 WARNING("bogus %s RESUME (%s)\n",
537 otg_state_string(musb
->xceiv
->state
));
542 /* see manual for the order of the tests */
543 if (int_usb
& MUSB_INTR_SESSREQ
) {
544 void __iomem
*mbase
= musb
->mregs
;
546 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
547 && (devctl
& MUSB_DEVCTL_BDEVICE
)) {
548 dev_dbg(musb
->controller
, "SessReq while on B state\n");
552 dev_dbg(musb
->controller
, "SESSION_REQUEST (%s)\n",
553 otg_state_string(musb
->xceiv
->state
));
555 /* IRQ arrives from ID pin sense or (later, if VBUS power
556 * is removed) SRP. responses are time critical:
557 * - turn on VBUS (with silicon-specific mechanism)
558 * - go through A_WAIT_VRISE
559 * - ... to A_WAIT_BCON.
560 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
562 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
563 musb
->ep0_stage
= MUSB_EP0_START
;
564 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
566 musb_platform_set_vbus(musb
, 1);
568 handled
= IRQ_HANDLED
;
571 if (int_usb
& MUSB_INTR_VBUSERROR
) {
574 /* During connection as an A-Device, we may see a short
575 * current spikes causing voltage drop, because of cable
576 * and peripheral capacitance combined with vbus draw.
577 * (So: less common with truly self-powered devices, where
578 * vbus doesn't act like a power supply.)
580 * Such spikes are short; usually less than ~500 usec, max
581 * of ~2 msec. That is, they're not sustained overcurrent
582 * errors, though they're reported using VBUSERROR irqs.
584 * Workarounds: (a) hardware: use self powered devices.
585 * (b) software: ignore non-repeated VBUS errors.
587 * REVISIT: do delays from lots of DEBUG_KERNEL checks
588 * make trouble here, keeping VBUS < 4.4V ?
590 switch (musb
->xceiv
->state
) {
591 case OTG_STATE_A_HOST
:
592 /* recovery is dicey once we've gotten past the
593 * initial stages of enumeration, but if VBUS
594 * stayed ok at the other end of the link, and
595 * another reset is due (at least for high speed,
596 * to redo the chirp etc), it might work OK...
598 case OTG_STATE_A_WAIT_BCON
:
599 case OTG_STATE_A_WAIT_VRISE
:
600 if (musb
->vbuserr_retry
) {
601 void __iomem
*mbase
= musb
->mregs
;
603 musb
->vbuserr_retry
--;
605 devctl
|= MUSB_DEVCTL_SESSION
;
606 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
608 musb
->port1_status
|=
609 USB_PORT_STAT_OVERCURRENT
610 | (USB_PORT_STAT_C_OVERCURRENT
<< 16);
617 dev_dbg(musb
->controller
, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
618 otg_state_string(musb
->xceiv
->state
),
621 switch (devctl
& MUSB_DEVCTL_VBUS
) {
622 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
623 s
= "<SessEnd"; break;
624 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
625 s
= "<AValid"; break;
626 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
627 s
= "<VBusValid"; break;
628 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
632 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
635 /* go through A_WAIT_VFALL then start a new session */
637 musb_platform_set_vbus(musb
, 0);
638 handled
= IRQ_HANDLED
;
641 if (int_usb
& MUSB_INTR_SUSPEND
) {
642 dev_dbg(musb
->controller
, "SUSPEND (%s) devctl %02x power %02x\n",
643 otg_state_string(musb
->xceiv
->state
), devctl
, power
);
644 handled
= IRQ_HANDLED
;
646 switch (musb
->xceiv
->state
) {
647 case OTG_STATE_A_PERIPHERAL
:
648 /* We also come here if the cable is removed, since
649 * this silicon doesn't report ID-no-longer-grounded.
651 * We depend on T(a_wait_bcon) to shut us down, and
652 * hope users don't do anything dicey during this
653 * undesired detour through A_WAIT_BCON.
656 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
657 musb_root_disconnect(musb
);
658 musb_platform_try_idle(musb
, jiffies
659 + msecs_to_jiffies(musb
->a_wait_bcon
660 ? : OTG_TIME_A_WAIT_BCON
));
663 case OTG_STATE_B_IDLE
:
664 if (!musb
->is_active
)
666 case OTG_STATE_B_PERIPHERAL
:
667 musb_g_suspend(musb
);
668 musb
->is_active
= is_otg_enabled(musb
)
669 && otg
->gadget
->b_hnp_enable
;
670 if (musb
->is_active
) {
671 musb
->xceiv
->state
= OTG_STATE_B_WAIT_ACON
;
672 dev_dbg(musb
->controller
, "HNP: Setting timer for b_ase0_brst\n");
673 mod_timer(&musb
->otg_timer
, jiffies
675 OTG_TIME_B_ASE0_BRST
));
678 case OTG_STATE_A_WAIT_BCON
:
679 if (musb
->a_wait_bcon
!= 0)
680 musb_platform_try_idle(musb
, jiffies
681 + msecs_to_jiffies(musb
->a_wait_bcon
));
683 case OTG_STATE_A_HOST
:
684 musb
->xceiv
->state
= OTG_STATE_A_SUSPEND
;
685 musb
->is_active
= is_otg_enabled(musb
)
686 && otg
->host
->b_hnp_enable
;
688 case OTG_STATE_B_HOST
:
689 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
690 dev_dbg(musb
->controller
, "REVISIT: SUSPEND as B_HOST\n");
693 /* "should not happen" */
700 if (int_usb
& MUSB_INTR_CONNECT
) {
701 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
703 handled
= IRQ_HANDLED
;
706 musb
->ep0_stage
= MUSB_EP0_START
;
708 /* flush endpoints when transitioning from Device Mode */
709 if (is_peripheral_active(musb
)) {
710 /* REVISIT HNP; just force disconnect */
712 musb_writew(musb
->mregs
, MUSB_INTRTXE
, musb
->epmask
);
713 musb_writew(musb
->mregs
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
714 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, 0xf7);
716 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
717 |USB_PORT_STAT_HIGH_SPEED
718 |USB_PORT_STAT_ENABLE
720 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
721 |(USB_PORT_STAT_C_CONNECTION
<< 16);
723 /* high vs full speed is just a guess until after reset */
724 if (devctl
& MUSB_DEVCTL_LSDEV
)
725 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
727 /* indicate new connection to OTG machine */
728 switch (musb
->xceiv
->state
) {
729 case OTG_STATE_B_PERIPHERAL
:
730 if (int_usb
& MUSB_INTR_SUSPEND
) {
731 dev_dbg(musb
->controller
, "HNP: SUSPEND+CONNECT, now b_host\n");
732 int_usb
&= ~MUSB_INTR_SUSPEND
;
735 dev_dbg(musb
->controller
, "CONNECT as b_peripheral???\n");
737 case OTG_STATE_B_WAIT_ACON
:
738 dev_dbg(musb
->controller
, "HNP: CONNECT, now b_host\n");
740 musb
->xceiv
->state
= OTG_STATE_B_HOST
;
741 hcd
->self
.is_b_host
= 1;
742 musb
->ignore_disconnect
= 0;
743 del_timer(&musb
->otg_timer
);
746 if ((devctl
& MUSB_DEVCTL_VBUS
)
747 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
748 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
749 hcd
->self
.is_b_host
= 0;
754 /* poke the root hub */
757 usb_hcd_poll_rh_status(hcd
);
759 usb_hcd_resume_root_hub(hcd
);
761 dev_dbg(musb
->controller
, "CONNECT (%s) devctl %02x\n",
762 otg_state_string(musb
->xceiv
->state
), devctl
);
767 if ((int_usb
& MUSB_INTR_DISCONNECT
) && !musb
->ignore_disconnect
) {
768 dev_dbg(musb
->controller
, "DISCONNECT (%s) as %s, devctl %02x\n",
769 otg_state_string(musb
->xceiv
->state
),
770 MUSB_MODE(musb
), devctl
);
771 handled
= IRQ_HANDLED
;
773 switch (musb
->xceiv
->state
) {
774 case OTG_STATE_A_HOST
:
775 case OTG_STATE_A_SUSPEND
:
776 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
777 musb_root_disconnect(musb
);
778 if (musb
->a_wait_bcon
!= 0 && is_otg_enabled(musb
))
779 musb_platform_try_idle(musb
, jiffies
780 + msecs_to_jiffies(musb
->a_wait_bcon
));
782 case OTG_STATE_B_HOST
:
783 /* REVISIT this behaves for "real disconnect"
784 * cases; make sure the other transitions from
785 * from B_HOST act right too. The B_HOST code
786 * in hnp_stop() is currently not used...
788 musb_root_disconnect(musb
);
789 musb_to_hcd(musb
)->self
.is_b_host
= 0;
790 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
792 musb_g_disconnect(musb
);
794 case OTG_STATE_A_PERIPHERAL
:
796 musb_root_disconnect(musb
);
798 case OTG_STATE_B_WAIT_ACON
:
800 case OTG_STATE_B_PERIPHERAL
:
801 case OTG_STATE_B_IDLE
:
802 musb_g_disconnect(musb
);
805 WARNING("unhandled DISCONNECT transition (%s)\n",
806 otg_state_string(musb
->xceiv
->state
));
811 /* mentor saves a bit: bus reset and babble share the same irq.
812 * only host sees babble; only peripheral sees bus reset.
814 if (int_usb
& MUSB_INTR_RESET
) {
815 handled
= IRQ_HANDLED
;
816 if (is_host_capable() && (devctl
& MUSB_DEVCTL_HM
) != 0) {
818 * Looks like non-HS BABBLE can be ignored, but
819 * HS BABBLE is an error condition. For HS the solution
820 * is to avoid babble in the first place and fix what
821 * caused BABBLE. When HS BABBLE happens we can only
824 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
825 dev_dbg(musb
->controller
, "BABBLE devctl: %02x\n", devctl
);
827 ERR("Stopping host session -- babble\n");
828 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
830 } else if (is_peripheral_capable()) {
831 dev_dbg(musb
->controller
, "BUS RESET as %s\n",
832 otg_state_string(musb
->xceiv
->state
));
833 switch (musb
->xceiv
->state
) {
834 case OTG_STATE_A_SUSPEND
:
835 /* We need to ignore disconnect on suspend
836 * otherwise tusb 2.0 won't reconnect after a
837 * power cycle, which breaks otg compliance.
839 musb
->ignore_disconnect
= 1;
842 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
843 /* never use invalid T(a_wait_bcon) */
844 dev_dbg(musb
->controller
, "HNP: in %s, %d msec timeout\n",
845 otg_state_string(musb
->xceiv
->state
),
847 mod_timer(&musb
->otg_timer
, jiffies
848 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
850 case OTG_STATE_A_PERIPHERAL
:
851 musb
->ignore_disconnect
= 0;
852 del_timer(&musb
->otg_timer
);
855 case OTG_STATE_B_WAIT_ACON
:
856 dev_dbg(musb
->controller
, "HNP: RESET (%s), to b_peripheral\n",
857 otg_state_string(musb
->xceiv
->state
));
858 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
861 case OTG_STATE_B_IDLE
:
862 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
864 case OTG_STATE_B_PERIPHERAL
:
868 dev_dbg(musb
->controller
, "Unhandled BUS RESET as %s\n",
869 otg_state_string(musb
->xceiv
->state
));
876 /* REVISIT ... this would be for multiplexing periodic endpoints, or
877 * supporting transfer phasing to prevent exceeding ISO bandwidth
878 * limits of a given frame or microframe.
880 * It's not needed for peripheral side, which dedicates endpoints;
881 * though it _might_ use SOF irqs for other purposes.
883 * And it's not currently needed for host side, which also dedicates
884 * endpoints, relies on TX/RX interval registers, and isn't claimed
885 * to support ISO transfers yet.
887 if (int_usb
& MUSB_INTR_SOF
) {
888 void __iomem
*mbase
= musb
->mregs
;
889 struct musb_hw_ep
*ep
;
893 dev_dbg(musb
->controller
, "START_OF_FRAME\n");
894 handled
= IRQ_HANDLED
;
896 /* start any periodic Tx transfers waiting for current frame */
897 frame
= musb_readw(mbase
, MUSB_FRAME
);
898 ep
= musb
->endpoints
;
899 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
900 && (musb
->epmask
>= (1 << epnum
));
903 * FIXME handle framecounter wraps (12 bits)
904 * eliminate duplicated StartUrb logic
906 if (ep
->dwWaitFrame
>= frame
) {
908 pr_debug("SOF --> periodic TX%s on %d\n",
909 ep
->tx_channel
? " DMA" : "",
912 musb_h_tx_start(musb
, epnum
);
914 cppi_hostdma_start(musb
, epnum
);
916 } /* end of for loop */
920 schedule_work(&musb
->irq_work
);
925 /*-------------------------------------------------------------------------*/
928 * Program the HDRC to start (enable interrupts, dma, etc.).
930 void musb_start(struct musb
*musb
)
932 void __iomem
*regs
= musb
->mregs
;
933 u8 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
935 dev_dbg(musb
->controller
, "<== devctl %02x\n", devctl
);
937 /* Set INT enable registers, enable interrupts */
938 musb_writew(regs
, MUSB_INTRTXE
, musb
->epmask
);
939 musb_writew(regs
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
940 musb_writeb(regs
, MUSB_INTRUSBE
, 0xf7);
942 musb_writeb(regs
, MUSB_TESTMODE
, 0);
944 /* put into basic highspeed mode and start session */
945 musb_writeb(regs
, MUSB_POWER
, MUSB_POWER_ISOUPDATE
947 /* ENSUSPEND wedges tusb */
948 /* | MUSB_POWER_ENSUSPEND */
952 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
953 devctl
&= ~MUSB_DEVCTL_SESSION
;
955 if (is_otg_enabled(musb
)) {
957 /* session started after:
958 * (a) ID-grounded irq, host mode;
959 * (b) vbus present/connect IRQ, peripheral mode;
960 * (c) peripheral initiates, using SRP
962 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
965 devctl
|= MUSB_DEVCTL_SESSION
;
968 } else if (is_host_enabled(musb
)) {
969 /* assume ID pin is hard-wired to ground */
970 devctl
|= MUSB_DEVCTL_SESSION
;
972 } else /* peripheral is enabled */ {
973 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
976 musb_platform_enable(musb
);
977 musb_writeb(regs
, MUSB_DEVCTL
, devctl
);
981 static void musb_generic_disable(struct musb
*musb
)
983 void __iomem
*mbase
= musb
->mregs
;
986 /* disable interrupts */
987 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
988 musb_writew(mbase
, MUSB_INTRTXE
, 0);
989 musb_writew(mbase
, MUSB_INTRRXE
, 0);
992 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
994 /* flush pending interrupts */
995 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
996 temp
= musb_readw(mbase
, MUSB_INTRTX
);
997 temp
= musb_readw(mbase
, MUSB_INTRRX
);
1002 * Make the HDRC stop (disable interrupts, etc.);
1003 * reversible by musb_start
1004 * called on gadget driver unregister
1005 * with controller locked, irqs blocked
1006 * acts as a NOP unless some role activated the hardware
1008 void musb_stop(struct musb
*musb
)
1010 /* stop IRQs, timers, ... */
1011 musb_platform_disable(musb
);
1012 musb_generic_disable(musb
);
1013 dev_dbg(musb
->controller
, "HDRC disabled\n");
1016 * - mark host and/or peripheral drivers unusable/inactive
1017 * - disable DMA (and enable it in HdrcStart)
1018 * - make sure we can musb_start() after musb_stop(); with
1019 * OTG mode, gadget driver module rmmod/modprobe cycles that
1022 musb_platform_try_idle(musb
, 0);
1026 static void musb_shutdown(struct platform_device
*pdev
)
1028 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
1029 unsigned long flags
;
1031 pm_runtime_get_sync(musb
->controller
);
1033 musb_gadget_cleanup(musb
);
1035 spin_lock_irqsave(&musb
->lock
, flags
);
1036 musb_platform_disable(musb
);
1037 musb_generic_disable(musb
);
1038 spin_unlock_irqrestore(&musb
->lock
, flags
);
1040 if (!is_otg_enabled(musb
) && is_host_enabled(musb
))
1041 usb_remove_hcd(musb_to_hcd(musb
));
1042 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1043 musb_platform_exit(musb
);
1045 pm_runtime_put(musb
->controller
);
1046 /* FIXME power down */
1051 /*-------------------------------------------------------------------------*/
1054 * The silicon either has hard-wired endpoint configurations, or else
1055 * "dynamic fifo" sizing. The driver has support for both, though at this
1056 * writing only the dynamic sizing is very well tested. Since we switched
1057 * away from compile-time hardware parameters, we can no longer rely on
1058 * dead code elimination to leave only the relevant one in the object file.
1060 * We don't currently use dynamic fifo setup capability to do anything
1061 * more than selecting one of a bunch of predefined configurations.
1063 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1064 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1065 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1066 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1067 || defined(CONFIG_USB_MUSB_AM35X) \
1068 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1069 || defined(CONFIG_USB_MUSB_DSPS) \
1070 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1071 static ushort __devinitdata fifo_mode
= 4;
1072 #elif defined(CONFIG_USB_MUSB_UX500) \
1073 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1074 static ushort __devinitdata fifo_mode
= 5;
1076 static ushort __devinitdata fifo_mode
= 2;
1079 /* "modprobe ... fifo_mode=1" etc */
1080 module_param(fifo_mode
, ushort
, 0);
1081 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1084 * tables defining fifo_mode values. define more if you like.
1085 * for host side, make sure both halves of ep1 are set up.
1088 /* mode 0 - fits in 2KB */
1089 static struct musb_fifo_cfg __devinitdata mode_0_cfg
[] = {
1090 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1091 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1092 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1093 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1094 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1097 /* mode 1 - fits in 4KB */
1098 static struct musb_fifo_cfg __devinitdata mode_1_cfg
[] = {
1099 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1100 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1101 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1102 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1103 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1106 /* mode 2 - fits in 4KB */
1107 static struct musb_fifo_cfg __devinitdata mode_2_cfg
[] = {
1108 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1109 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1110 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1111 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1112 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1113 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1116 /* mode 3 - fits in 4KB */
1117 static struct musb_fifo_cfg __devinitdata mode_3_cfg
[] = {
1118 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1119 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1120 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1121 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1122 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1123 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1126 /* mode 4 - fits in 16KB */
1127 static struct musb_fifo_cfg __devinitdata mode_4_cfg
[] = {
1128 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1129 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1130 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1131 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1132 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1133 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1134 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1135 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1136 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1137 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1138 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1139 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1140 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1141 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1142 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1143 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1144 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1145 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1146 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1147 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1148 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1149 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1150 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1151 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1152 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1153 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1154 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1157 /* mode 5 - fits in 8KB */
1158 static struct musb_fifo_cfg __devinitdata mode_5_cfg
[] = {
1159 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1160 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1161 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1162 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1163 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1164 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1165 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1166 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1167 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1168 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1169 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 32, },
1170 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 32, },
1171 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 32, },
1172 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 32, },
1173 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 32, },
1174 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 32, },
1175 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 32, },
1176 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 32, },
1177 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 32, },
1178 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 32, },
1179 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 32, },
1180 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 32, },
1181 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 32, },
1182 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 32, },
1183 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1184 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1185 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1189 * configure a fifo; for non-shared endpoints, this may be called
1190 * once for a tx fifo and once for an rx fifo.
1192 * returns negative errno or offset for next fifo.
1194 static int __devinit
1195 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1196 const struct musb_fifo_cfg
*cfg
, u16 offset
)
1198 void __iomem
*mbase
= musb
->mregs
;
1200 u16 maxpacket
= cfg
->maxpacket
;
1201 u16 c_off
= offset
>> 3;
1204 /* expect hw_ep has already been zero-initialized */
1206 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1207 maxpacket
= 1 << size
;
1210 if (cfg
->mode
== BUF_DOUBLE
) {
1211 if ((offset
+ (maxpacket
<< 1)) >
1212 (1 << (musb
->config
->ram_bits
+ 2)))
1214 c_size
|= MUSB_FIFOSZ_DPB
;
1216 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1220 /* configure the FIFO */
1221 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1223 /* EP0 reserved endpoint for control, bidirectional;
1224 * EP1 reserved for bulk, two unidirection halves.
1226 if (hw_ep
->epnum
== 1)
1227 musb
->bulk_ep
= hw_ep
;
1228 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1229 switch (cfg
->style
) {
1231 musb_write_txfifosz(mbase
, c_size
);
1232 musb_write_txfifoadd(mbase
, c_off
);
1233 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1234 hw_ep
->max_packet_sz_tx
= maxpacket
;
1237 musb_write_rxfifosz(mbase
, c_size
);
1238 musb_write_rxfifoadd(mbase
, c_off
);
1239 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1240 hw_ep
->max_packet_sz_rx
= maxpacket
;
1243 musb_write_txfifosz(mbase
, c_size
);
1244 musb_write_txfifoadd(mbase
, c_off
);
1245 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1246 hw_ep
->max_packet_sz_rx
= maxpacket
;
1248 musb_write_rxfifosz(mbase
, c_size
);
1249 musb_write_rxfifoadd(mbase
, c_off
);
1250 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1251 hw_ep
->max_packet_sz_tx
= maxpacket
;
1253 hw_ep
->is_shared_fifo
= true;
1257 /* NOTE rx and tx endpoint irqs aren't managed separately,
1258 * which happens to be ok
1260 musb
->epmask
|= (1 << hw_ep
->epnum
);
1262 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1265 static struct musb_fifo_cfg __devinitdata ep0_cfg
= {
1266 .style
= FIFO_RXTX
, .maxpacket
= 64,
1269 static int __devinit
ep_config_from_table(struct musb
*musb
)
1271 const struct musb_fifo_cfg
*cfg
;
1274 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1276 if (musb
->config
->fifo_cfg
) {
1277 cfg
= musb
->config
->fifo_cfg
;
1278 n
= musb
->config
->fifo_cfg_size
;
1282 switch (fifo_mode
) {
1288 n
= ARRAY_SIZE(mode_0_cfg
);
1292 n
= ARRAY_SIZE(mode_1_cfg
);
1296 n
= ARRAY_SIZE(mode_2_cfg
);
1300 n
= ARRAY_SIZE(mode_3_cfg
);
1304 n
= ARRAY_SIZE(mode_4_cfg
);
1308 n
= ARRAY_SIZE(mode_5_cfg
);
1312 printk(KERN_DEBUG
"%s: setup fifo_mode %d\n",
1313 musb_driver_name
, fifo_mode
);
1317 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1318 /* assert(offset > 0) */
1320 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1321 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1324 for (i
= 0; i
< n
; i
++) {
1325 u8 epn
= cfg
->hw_ep_num
;
1327 if (epn
>= musb
->config
->num_eps
) {
1328 pr_debug("%s: invalid ep %d\n",
1329 musb_driver_name
, epn
);
1332 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1334 pr_debug("%s: mem overrun, ep %d\n",
1335 musb_driver_name
, epn
);
1339 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1342 printk(KERN_DEBUG
"%s: %d/%d max ep, %d/%d memory\n",
1344 n
+ 1, musb
->config
->num_eps
* 2 - 1,
1345 offset
, (1 << (musb
->config
->ram_bits
+ 2)));
1347 if (!musb
->bulk_ep
) {
1348 pr_debug("%s: missing bulk\n", musb_driver_name
);
1357 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1358 * @param musb the controller
1360 static int __devinit
ep_config_from_hw(struct musb
*musb
)
1363 struct musb_hw_ep
*hw_ep
;
1364 void *mbase
= musb
->mregs
;
1367 dev_dbg(musb
->controller
, "<== static silicon ep config\n");
1369 /* FIXME pick up ep0 maxpacket size */
1371 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1372 musb_ep_select(mbase
, epnum
);
1373 hw_ep
= musb
->endpoints
+ epnum
;
1375 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1379 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1381 /* pick an RX/TX endpoint for bulk */
1382 if (hw_ep
->max_packet_sz_tx
< 512
1383 || hw_ep
->max_packet_sz_rx
< 512)
1386 /* REVISIT: this algorithm is lazy, we should at least
1387 * try to pick a double buffered endpoint.
1391 musb
->bulk_ep
= hw_ep
;
1394 if (!musb
->bulk_ep
) {
1395 pr_debug("%s: missing bulk\n", musb_driver_name
);
1402 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1404 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1405 * configure endpoints, or take their config from silicon
1407 static int __devinit
musb_core_init(u16 musb_type
, struct musb
*musb
)
1411 char aInfo
[90], aRevision
[32], aDate
[12];
1412 void __iomem
*mbase
= musb
->mregs
;
1416 /* log core options (read using indexed model) */
1417 reg
= musb_read_configdata(mbase
);
1419 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1420 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1421 strcat(aInfo
, ", dyn FIFOs");
1422 musb
->dyn_fifo
= true;
1424 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1425 strcat(aInfo
, ", bulk combine");
1426 musb
->bulk_combine
= true;
1428 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1429 strcat(aInfo
, ", bulk split");
1430 musb
->bulk_split
= true;
1432 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1433 strcat(aInfo
, ", HB-ISO Rx");
1434 musb
->hb_iso_rx
= true;
1436 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1437 strcat(aInfo
, ", HB-ISO Tx");
1438 musb
->hb_iso_tx
= true;
1440 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1441 strcat(aInfo
, ", SoftConn");
1443 printk(KERN_DEBUG
"%s: ConfigData=0x%02x (%s)\n",
1444 musb_driver_name
, reg
, aInfo
);
1447 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1448 musb
->is_multipoint
= 1;
1451 musb
->is_multipoint
= 0;
1453 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1455 "%s: kernel must blacklist external hubs\n",
1460 /* log release info */
1461 musb
->hwvers
= musb_read_hwvers(mbase
);
1462 snprintf(aRevision
, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb
->hwvers
),
1463 MUSB_HWVERS_MINOR(musb
->hwvers
),
1464 (musb
->hwvers
& MUSB_HWVERS_RC
) ? "RC" : "");
1465 printk(KERN_DEBUG
"%s: %sHDRC RTL version %s %s\n",
1466 musb_driver_name
, type
, aRevision
, aDate
);
1469 musb_configure_ep0(musb
);
1471 /* discover endpoint configuration */
1472 musb
->nr_endpoints
= 1;
1476 status
= ep_config_from_table(musb
);
1478 status
= ep_config_from_hw(musb
);
1483 /* finish init, and print endpoint config */
1484 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1485 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1487 hw_ep
->fifo
= MUSB_FIFO_OFFSET(i
) + mbase
;
1488 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1489 hw_ep
->fifo_async
= musb
->async
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1490 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1491 hw_ep
->fifo_sync_va
=
1492 musb
->sync_va
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1495 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1497 hw_ep
->conf
= mbase
+ 0x400 + (((i
- 1) & 0xf) << 2);
1500 hw_ep
->regs
= MUSB_EP_OFFSET(i
, 0) + mbase
;
1501 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1502 hw_ep
->rx_reinit
= 1;
1503 hw_ep
->tx_reinit
= 1;
1505 if (hw_ep
->max_packet_sz_tx
) {
1506 dev_dbg(musb
->controller
,
1507 "%s: hw_ep %d%s, %smax %d\n",
1508 musb_driver_name
, i
,
1509 hw_ep
->is_shared_fifo
? "shared" : "tx",
1510 hw_ep
->tx_double_buffered
1511 ? "doublebuffer, " : "",
1512 hw_ep
->max_packet_sz_tx
);
1514 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1515 dev_dbg(musb
->controller
,
1516 "%s: hw_ep %d%s, %smax %d\n",
1517 musb_driver_name
, i
,
1519 hw_ep
->rx_double_buffered
1520 ? "doublebuffer, " : "",
1521 hw_ep
->max_packet_sz_rx
);
1523 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1524 dev_dbg(musb
->controller
, "hw_ep %d not configured\n", i
);
1530 /*-------------------------------------------------------------------------*/
1532 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1533 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1535 static irqreturn_t
generic_interrupt(int irq
, void *__hci
)
1537 unsigned long flags
;
1538 irqreturn_t retval
= IRQ_NONE
;
1539 struct musb
*musb
= __hci
;
1541 spin_lock_irqsave(&musb
->lock
, flags
);
1543 musb
->int_usb
= musb_readb(musb
->mregs
, MUSB_INTRUSB
);
1544 musb
->int_tx
= musb_readw(musb
->mregs
, MUSB_INTRTX
);
1545 musb
->int_rx
= musb_readw(musb
->mregs
, MUSB_INTRRX
);
1547 if (musb
->int_usb
|| musb
->int_tx
|| musb
->int_rx
)
1548 retval
= musb_interrupt(musb
);
1550 spin_unlock_irqrestore(&musb
->lock
, flags
);
1556 #define generic_interrupt NULL
1560 * handle all the irqs defined by the HDRC core. for now we expect: other
1561 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1562 * will be assigned, and the irq will already have been acked.
1564 * called in irq context with spinlock held, irqs blocked
1566 irqreturn_t
musb_interrupt(struct musb
*musb
)
1568 irqreturn_t retval
= IRQ_NONE
;
1573 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1574 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1576 dev_dbg(musb
->controller
, "** IRQ %s usb%04x tx%04x rx%04x\n",
1577 (devctl
& MUSB_DEVCTL_HM
) ? "host" : "peripheral",
1578 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1580 /* the core can interrupt us for multiple reasons; docs have
1581 * a generic interrupt flowchart to follow
1584 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1587 /* "stage 1" is handling endpoint irqs */
1589 /* handle endpoint 0 first */
1590 if (musb
->int_tx
& 1) {
1591 if (devctl
& MUSB_DEVCTL_HM
) {
1592 if (is_host_capable())
1593 retval
|= musb_h_ep0_irq(musb
);
1595 if (is_peripheral_capable())
1596 retval
|= musb_g_ep0_irq(musb
);
1600 /* RX on endpoints 1-15 */
1601 reg
= musb
->int_rx
>> 1;
1605 /* musb_ep_select(musb->mregs, ep_num); */
1606 /* REVISIT just retval = ep->rx_irq(...) */
1607 retval
= IRQ_HANDLED
;
1608 if (devctl
& MUSB_DEVCTL_HM
) {
1609 if (is_host_capable())
1610 musb_host_rx(musb
, ep_num
);
1612 if (is_peripheral_capable())
1613 musb_g_rx(musb
, ep_num
);
1621 /* TX on endpoints 1-15 */
1622 reg
= musb
->int_tx
>> 1;
1626 /* musb_ep_select(musb->mregs, ep_num); */
1627 /* REVISIT just retval |= ep->tx_irq(...) */
1628 retval
= IRQ_HANDLED
;
1629 if (devctl
& MUSB_DEVCTL_HM
) {
1630 if (is_host_capable())
1631 musb_host_tx(musb
, ep_num
);
1633 if (is_peripheral_capable())
1634 musb_g_tx(musb
, ep_num
);
1643 EXPORT_SYMBOL_GPL(musb_interrupt
);
1645 #ifndef CONFIG_MUSB_PIO_ONLY
1646 static bool __devinitdata use_dma
= 1;
1648 /* "modprobe ... use_dma=0" etc */
1649 module_param(use_dma
, bool, 0);
1650 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1652 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1654 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1656 /* called with controller lock already held */
1659 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1660 if (!is_cppi_enabled()) {
1662 if (devctl
& MUSB_DEVCTL_HM
)
1663 musb_h_ep0_irq(musb
);
1665 musb_g_ep0_irq(musb
);
1669 /* endpoints 1..15 */
1671 if (devctl
& MUSB_DEVCTL_HM
) {
1672 if (is_host_capable())
1673 musb_host_tx(musb
, epnum
);
1675 if (is_peripheral_capable())
1676 musb_g_tx(musb
, epnum
);
1680 if (devctl
& MUSB_DEVCTL_HM
) {
1681 if (is_host_capable())
1682 musb_host_rx(musb
, epnum
);
1684 if (is_peripheral_capable())
1685 musb_g_rx(musb
, epnum
);
1690 EXPORT_SYMBOL_GPL(musb_dma_completion
);
1696 /*-------------------------------------------------------------------------*/
1701 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1703 struct musb
*musb
= dev_to_musb(dev
);
1704 unsigned long flags
;
1707 spin_lock_irqsave(&musb
->lock
, flags
);
1708 ret
= sprintf(buf
, "%s\n", otg_state_string(musb
->xceiv
->state
));
1709 spin_unlock_irqrestore(&musb
->lock
, flags
);
1715 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1716 const char *buf
, size_t n
)
1718 struct musb
*musb
= dev_to_musb(dev
);
1719 unsigned long flags
;
1722 spin_lock_irqsave(&musb
->lock
, flags
);
1723 if (sysfs_streq(buf
, "host"))
1724 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1725 else if (sysfs_streq(buf
, "peripheral"))
1726 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1727 else if (sysfs_streq(buf
, "otg"))
1728 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1731 spin_unlock_irqrestore(&musb
->lock
, flags
);
1733 return (status
== 0) ? n
: status
;
1735 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1738 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1739 const char *buf
, size_t n
)
1741 struct musb
*musb
= dev_to_musb(dev
);
1742 unsigned long flags
;
1745 if (sscanf(buf
, "%lu", &val
) < 1) {
1746 dev_err(dev
, "Invalid VBUS timeout ms value\n");
1750 spin_lock_irqsave(&musb
->lock
, flags
);
1751 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1752 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1753 if (musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)
1754 musb
->is_active
= 0;
1755 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1756 spin_unlock_irqrestore(&musb
->lock
, flags
);
1762 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1764 struct musb
*musb
= dev_to_musb(dev
);
1765 unsigned long flags
;
1769 spin_lock_irqsave(&musb
->lock
, flags
);
1770 val
= musb
->a_wait_bcon
;
1771 /* FIXME get_vbus_status() is normally #defined as false...
1772 * and is effectively TUSB-specific.
1774 vbus
= musb_platform_get_vbus_status(musb
);
1775 spin_unlock_irqrestore(&musb
->lock
, flags
);
1777 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1778 vbus
? "on" : "off", val
);
1780 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1782 /* Gadget drivers can't know that a host is connected so they might want
1783 * to start SRP, but users can. This allows userspace to trigger SRP.
1786 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1787 const char *buf
, size_t n
)
1789 struct musb
*musb
= dev_to_musb(dev
);
1792 if (sscanf(buf
, "%hu", &srp
) != 1
1794 dev_err(dev
, "SRP: Value must be 1\n");
1799 musb_g_wakeup(musb
);
1803 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1805 static struct attribute
*musb_attributes
[] = {
1806 &dev_attr_mode
.attr
,
1807 &dev_attr_vbus
.attr
,
1812 static const struct attribute_group musb_attr_group
= {
1813 .attrs
= musb_attributes
,
1819 /* Only used to provide driver mode change events */
1820 static void musb_irq_work(struct work_struct
*data
)
1822 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1823 static int old_state
;
1825 if (musb
->xceiv
->state
!= old_state
) {
1826 old_state
= musb
->xceiv
->state
;
1827 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1832 /* --------------------------------------------------------------------------
1836 static struct musb
*__devinit
1837 allocate_instance(struct device
*dev
,
1838 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1841 struct musb_hw_ep
*ep
;
1844 struct usb_hcd
*hcd
;
1846 hcd
= usb_create_hcd(&musb_hc_driver
, dev
, dev_name(dev
));
1849 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1851 musb
= hcd_to_musb(hcd
);
1853 musb
= calloc(1, sizeof(*musb
));
1857 INIT_LIST_HEAD(&musb
->control
);
1858 INIT_LIST_HEAD(&musb
->in_bulk
);
1859 INIT_LIST_HEAD(&musb
->out_bulk
);
1862 hcd
->uses_new_polling
= 1;
1866 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1867 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1868 dev_set_drvdata(dev
, musb
);
1869 musb
->mregs
= mbase
;
1870 musb
->ctrl_base
= mbase
;
1871 musb
->nIrq
= -ENODEV
;
1872 musb
->config
= config
;
1873 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1874 for (epnum
= 0, ep
= musb
->endpoints
;
1875 epnum
< musb
->config
->num_eps
;
1881 musb
->controller
= dev
;
1886 static void musb_free(struct musb
*musb
)
1888 /* this has multiple entry modes. it handles fault cleanup after
1889 * probe(), where things may be partially set up, as well as rmmod
1890 * cleanup after everything's been de-activated.
1894 sysfs_remove_group(&musb
->controller
->kobj
, &musb_attr_group
);
1897 if (musb
->nIrq
>= 0) {
1899 disable_irq_wake(musb
->nIrq
);
1900 free_irq(musb
->nIrq
, musb
);
1902 if (is_dma_capable() && musb
->dma_controller
) {
1903 struct dma_controller
*c
= musb
->dma_controller
;
1906 dma_controller_destroy(c
);
1913 * Perform generic per-controller initialization.
1915 * @pDevice: the controller (already clocked, etc)
1917 * @mregs: virtual address of controller registers,
1918 * not yet corrected for platform-specific offsets
1921 static int __devinit
1922 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1925 musb_init_controller(struct musb_hdrc_platform_data
*plat
, struct device
*dev
,
1932 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
1937 /* The driver might handle more features than the board; OK.
1938 * Fail when the board needs a feature that's not enabled.
1941 dev_dbg(dev
, "no platform_data?\n");
1947 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1953 pm_runtime_use_autosuspend(musb
->controller
);
1954 pm_runtime_set_autosuspend_delay(musb
->controller
, 200);
1955 pm_runtime_enable(musb
->controller
);
1957 spin_lock_init(&musb
->lock
);
1958 musb
->board_mode
= plat
->mode
;
1959 musb
->board_set_power
= plat
->set_power
;
1960 musb
->min_power
= plat
->min_power
;
1961 musb
->ops
= plat
->platform_ops
;
1963 /* The musb_platform_init() call:
1964 * - adjusts musb->mregs and musb->isr if needed,
1965 * - may initialize an integrated tranceiver
1966 * - initializes musb->xceiv, usually by otg_get_phy()
1967 * - stops powering VBUS
1969 * There are various transceiver configurations. Blackfin,
1970 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1971 * external/discrete ones in various flavors (twl4030 family,
1972 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1974 musb
->isr
= generic_interrupt
;
1975 status
= musb_platform_init(musb
);
1985 if (!musb
->xceiv
->io_ops
) {
1986 musb
->xceiv
->io_dev
= musb
->controller
;
1987 musb
->xceiv
->io_priv
= musb
->mregs
;
1988 musb
->xceiv
->io_ops
= &musb_ulpi_access
;
1992 pm_runtime_get_sync(musb
->controller
);
1994 #ifndef CONFIG_MUSB_PIO_ONLY
1995 if (use_dma
&& dev
->dma_mask
) {
1996 struct dma_controller
*c
;
1998 c
= dma_controller_create(musb
, musb
->mregs
);
1999 musb
->dma_controller
= c
;
2005 /* ideally this would be abstracted in platform setup */
2006 if (!is_dma_capable() || !musb
->dma_controller
)
2007 dev
->dma_mask
= NULL
;
2010 /* be sure interrupts are disabled before connecting ISR */
2011 musb_platform_disable(musb
);
2012 musb_generic_disable(musb
);
2014 /* setup musb parts of the core (especially endpoints) */
2015 status
= musb_core_init(plat
->config
->multipoint
2016 ? MUSB_CONTROLLER_MHDRC
2017 : MUSB_CONTROLLER_HDRC
, musb
);
2021 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
2023 /* Init IRQ workqueue before request_irq */
2024 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
2026 /* attach to the IRQ */
2027 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
2028 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
2033 /* FIXME this handles wakeup irqs wrong */
2034 if (enable_irq_wake(nIrq
) == 0) {
2036 device_init_wakeup(dev
, 1);
2042 /* host side needs more setup */
2043 if (is_host_enabled(musb
)) {
2044 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
2046 otg_set_host(musb
->xceiv
->otg
, &hcd
->self
);
2048 if (is_otg_enabled(musb
))
2049 hcd
->self
.otg_port
= 1;
2050 musb
->xceiv
->otg
->host
= &hcd
->self
;
2051 hcd
->power_budget
= 2 * (plat
->power
? : 250);
2053 /* program PHY to use external vBus if required */
2054 if (plat
->extvbus
) {
2055 u8 busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2056 busctl
|= MUSB_ULPI_USE_EXTVBUS
;
2057 musb_write_ulpi_buscontrol(musb
->mregs
, busctl
);
2062 /* For the host-only role, we can activate right away.
2063 * (We expect the ID pin to be forcibly grounded!!)
2064 * Otherwise, wait till the gadget driver hooks up.
2066 if (!is_otg_enabled(musb
) && is_host_enabled(musb
)) {
2067 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
2069 MUSB_HST_MODE(musb
);
2071 musb
->xceiv
->otg
->default_a
= 1;
2072 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2074 status
= usb_add_hcd(musb_to_hcd(musb
), 0, 0);
2076 hcd
->self
.uses_pio_for_control
= 1;
2077 dev_dbg(musb
->controller
, "%s mode, status %d, devctl %02x %c\n",
2079 musb_readb(musb
->mregs
, MUSB_DEVCTL
),
2080 (musb_readb(musb
->mregs
, MUSB_DEVCTL
)
2081 & MUSB_DEVCTL_BDEVICE
2085 } else /* peripheral is enabled */ {
2086 MUSB_DEV_MODE(musb
);
2088 musb
->xceiv
->otg
->default_a
= 0;
2089 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2092 if (is_peripheral_capable())
2093 status
= musb_gadget_setup(musb
);
2096 dev_dbg(musb
->controller
, "%s mode, status %d, dev%02x\n",
2097 is_otg_enabled(musb
) ? "OTG" : "PERIPHERAL",
2099 musb_readb(musb
->mregs
, MUSB_DEVCTL
));
2106 status
= musb_init_debugfs(musb
);
2111 status
= sysfs_create_group(&musb
->controller
->kobj
, &musb_attr_group
);
2116 pm_runtime_put(musb
->controller
);
2118 dev_info(dev
, "USB %s mode controller at %p using %s, IRQ %d\n",
2120 switch (musb
->board_mode
) {
2121 case MUSB_HOST
: s
= "Host"; break;
2122 case MUSB_PERIPHERAL
: s
= "Peripheral"; break;
2123 default: s
= "OTG"; break;
2126 (is_dma_capable() && musb
->dma_controller
)
2133 return status
== 0 ? musb
: NULL
;
2137 musb_exit_debugfs(musb
);
2141 if (!is_otg_enabled(musb
) && is_host_enabled(musb
))
2142 usb_remove_hcd(musb_to_hcd(musb
));
2145 musb_gadget_cleanup(musb
);
2148 pm_runtime_put_sync(musb
->controller
);
2152 device_init_wakeup(dev
, 0);
2153 musb_platform_exit(musb
);
2156 dev_err(musb
->controller
,
2157 "musb_init_controller failed with status %d\n", status
);
2166 return status
== 0 ? musb
: NULL
;
2171 /*-------------------------------------------------------------------------*/
2173 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2174 * bridge to a platform device; this driver then suffices.
2177 #ifndef CONFIG_MUSB_PIO_ONLY
2178 static u64
*orig_dma_mask
;
2182 static int __devinit
musb_probe(struct platform_device
*pdev
)
2184 struct device
*dev
= &pdev
->dev
;
2185 int irq
= platform_get_irq_byname(pdev
, "mc");
2187 struct resource
*iomem
;
2190 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2191 if (!iomem
|| irq
<= 0)
2194 base
= ioremap(iomem
->start
, resource_size(iomem
));
2196 dev_err(dev
, "ioremap failed\n");
2200 #ifndef CONFIG_MUSB_PIO_ONLY
2201 /* clobbered by use_dma=n */
2202 orig_dma_mask
= dev
->dma_mask
;
2204 status
= musb_init_controller(dev
, irq
, base
);
2211 static int __devexit
musb_remove(struct platform_device
*pdev
)
2213 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
2214 void __iomem
*ctrl_base
= musb
->ctrl_base
;
2216 /* this gets called on rmmod.
2217 * - Host mode: host may still be active
2218 * - Peripheral mode: peripheral is deactivated (or never-activated)
2219 * - OTG mode: both roles are deactivated (or never-activated)
2221 musb_exit_debugfs(musb
);
2222 musb_shutdown(pdev
);
2226 device_init_wakeup(&pdev
->dev
, 0);
2227 #ifndef CONFIG_MUSB_PIO_ONLY
2228 pdev
->dev
.dma_mask
= orig_dma_mask
;
2235 static void musb_save_context(struct musb
*musb
)
2238 void __iomem
*musb_base
= musb
->mregs
;
2241 if (is_host_enabled(musb
)) {
2242 musb
->context
.frame
= musb_readw(musb_base
, MUSB_FRAME
);
2243 musb
->context
.testmode
= musb_readb(musb_base
, MUSB_TESTMODE
);
2244 musb
->context
.busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2246 musb
->context
.power
= musb_readb(musb_base
, MUSB_POWER
);
2247 musb
->context
.intrtxe
= musb_readw(musb_base
, MUSB_INTRTXE
);
2248 musb
->context
.intrrxe
= musb_readw(musb_base
, MUSB_INTRRXE
);
2249 musb
->context
.intrusbe
= musb_readb(musb_base
, MUSB_INTRUSBE
);
2250 musb
->context
.index
= musb_readb(musb_base
, MUSB_INDEX
);
2251 musb
->context
.devctl
= musb_readb(musb_base
, MUSB_DEVCTL
);
2253 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2254 struct musb_hw_ep
*hw_ep
;
2256 hw_ep
= &musb
->endpoints
[i
];
2264 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2265 musb
->context
.index_regs
[i
].txmaxp
=
2266 musb_readw(epio
, MUSB_TXMAXP
);
2267 musb
->context
.index_regs
[i
].txcsr
=
2268 musb_readw(epio
, MUSB_TXCSR
);
2269 musb
->context
.index_regs
[i
].rxmaxp
=
2270 musb_readw(epio
, MUSB_RXMAXP
);
2271 musb
->context
.index_regs
[i
].rxcsr
=
2272 musb_readw(epio
, MUSB_RXCSR
);
2274 if (musb
->dyn_fifo
) {
2275 musb
->context
.index_regs
[i
].txfifoadd
=
2276 musb_read_txfifoadd(musb_base
);
2277 musb
->context
.index_regs
[i
].rxfifoadd
=
2278 musb_read_rxfifoadd(musb_base
);
2279 musb
->context
.index_regs
[i
].txfifosz
=
2280 musb_read_txfifosz(musb_base
);
2281 musb
->context
.index_regs
[i
].rxfifosz
=
2282 musb_read_rxfifosz(musb_base
);
2284 if (is_host_enabled(musb
)) {
2285 musb
->context
.index_regs
[i
].txtype
=
2286 musb_readb(epio
, MUSB_TXTYPE
);
2287 musb
->context
.index_regs
[i
].txinterval
=
2288 musb_readb(epio
, MUSB_TXINTERVAL
);
2289 musb
->context
.index_regs
[i
].rxtype
=
2290 musb_readb(epio
, MUSB_RXTYPE
);
2291 musb
->context
.index_regs
[i
].rxinterval
=
2292 musb_readb(epio
, MUSB_RXINTERVAL
);
2294 musb
->context
.index_regs
[i
].txfunaddr
=
2295 musb_read_txfunaddr(musb_base
, i
);
2296 musb
->context
.index_regs
[i
].txhubaddr
=
2297 musb_read_txhubaddr(musb_base
, i
);
2298 musb
->context
.index_regs
[i
].txhubport
=
2299 musb_read_txhubport(musb_base
, i
);
2301 musb
->context
.index_regs
[i
].rxfunaddr
=
2302 musb_read_rxfunaddr(musb_base
, i
);
2303 musb
->context
.index_regs
[i
].rxhubaddr
=
2304 musb_read_rxhubaddr(musb_base
, i
);
2305 musb
->context
.index_regs
[i
].rxhubport
=
2306 musb_read_rxhubport(musb_base
, i
);
2311 static void musb_restore_context(struct musb
*musb
)
2314 void __iomem
*musb_base
= musb
->mregs
;
2315 void __iomem
*ep_target_regs
;
2318 if (is_host_enabled(musb
)) {
2319 musb_writew(musb_base
, MUSB_FRAME
, musb
->context
.frame
);
2320 musb_writeb(musb_base
, MUSB_TESTMODE
, musb
->context
.testmode
);
2321 musb_write_ulpi_buscontrol(musb
->mregs
, musb
->context
.busctl
);
2323 musb_writeb(musb_base
, MUSB_POWER
, musb
->context
.power
);
2324 musb_writew(musb_base
, MUSB_INTRTXE
, musb
->context
.intrtxe
);
2325 musb_writew(musb_base
, MUSB_INTRRXE
, musb
->context
.intrrxe
);
2326 musb_writeb(musb_base
, MUSB_INTRUSBE
, musb
->context
.intrusbe
);
2327 musb_writeb(musb_base
, MUSB_DEVCTL
, musb
->context
.devctl
);
2329 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2330 struct musb_hw_ep
*hw_ep
;
2332 hw_ep
= &musb
->endpoints
[i
];
2340 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2341 musb_writew(epio
, MUSB_TXMAXP
,
2342 musb
->context
.index_regs
[i
].txmaxp
);
2343 musb_writew(epio
, MUSB_TXCSR
,
2344 musb
->context
.index_regs
[i
].txcsr
);
2345 musb_writew(epio
, MUSB_RXMAXP
,
2346 musb
->context
.index_regs
[i
].rxmaxp
);
2347 musb_writew(epio
, MUSB_RXCSR
,
2348 musb
->context
.index_regs
[i
].rxcsr
);
2350 if (musb
->dyn_fifo
) {
2351 musb_write_txfifosz(musb_base
,
2352 musb
->context
.index_regs
[i
].txfifosz
);
2353 musb_write_rxfifosz(musb_base
,
2354 musb
->context
.index_regs
[i
].rxfifosz
);
2355 musb_write_txfifoadd(musb_base
,
2356 musb
->context
.index_regs
[i
].txfifoadd
);
2357 musb_write_rxfifoadd(musb_base
,
2358 musb
->context
.index_regs
[i
].rxfifoadd
);
2361 if (is_host_enabled(musb
)) {
2362 musb_writeb(epio
, MUSB_TXTYPE
,
2363 musb
->context
.index_regs
[i
].txtype
);
2364 musb_writeb(epio
, MUSB_TXINTERVAL
,
2365 musb
->context
.index_regs
[i
].txinterval
);
2366 musb_writeb(epio
, MUSB_RXTYPE
,
2367 musb
->context
.index_regs
[i
].rxtype
);
2368 musb_writeb(epio
, MUSB_RXINTERVAL
,
2370 musb
->context
.index_regs
[i
].rxinterval
);
2371 musb_write_txfunaddr(musb_base
, i
,
2372 musb
->context
.index_regs
[i
].txfunaddr
);
2373 musb_write_txhubaddr(musb_base
, i
,
2374 musb
->context
.index_regs
[i
].txhubaddr
);
2375 musb_write_txhubport(musb_base
, i
,
2376 musb
->context
.index_regs
[i
].txhubport
);
2379 musb_read_target_reg_base(i
, musb_base
);
2381 musb_write_rxfunaddr(ep_target_regs
,
2382 musb
->context
.index_regs
[i
].rxfunaddr
);
2383 musb_write_rxhubaddr(ep_target_regs
,
2384 musb
->context
.index_regs
[i
].rxhubaddr
);
2385 musb_write_rxhubport(ep_target_regs
,
2386 musb
->context
.index_regs
[i
].rxhubport
);
2389 musb_writeb(musb_base
, MUSB_INDEX
, musb
->context
.index
);
2392 static int musb_suspend(struct device
*dev
)
2394 struct musb
*musb
= dev_to_musb(dev
);
2395 unsigned long flags
;
2397 spin_lock_irqsave(&musb
->lock
, flags
);
2399 if (is_peripheral_active(musb
)) {
2400 /* FIXME force disconnect unless we know USB will wake
2401 * the system up quickly enough to respond ...
2403 } else if (is_host_active(musb
)) {
2404 /* we know all the children are suspended; sometimes
2405 * they will even be wakeup-enabled.
2409 spin_unlock_irqrestore(&musb
->lock
, flags
);
2413 static int musb_resume_noirq(struct device
*dev
)
2415 /* for static cmos like DaVinci, register values were preserved
2416 * unless for some reason the whole soc powered down or the USB
2417 * module got reset through the PSC (vs just being disabled).
2422 static int musb_runtime_suspend(struct device
*dev
)
2424 struct musb
*musb
= dev_to_musb(dev
);
2426 musb_save_context(musb
);
2431 static int musb_runtime_resume(struct device
*dev
)
2433 struct musb
*musb
= dev_to_musb(dev
);
2434 static int first
= 1;
2437 * When pm_runtime_get_sync called for the first time in driver
2438 * init, some of the structure is still not initialized which is
2439 * used in restore function. But clock needs to be
2440 * enabled before any register access, so
2441 * pm_runtime_get_sync has to be called.
2442 * Also context restore without save does not make
2446 musb_restore_context(musb
);
2452 static const struct dev_pm_ops musb_dev_pm_ops
= {
2453 .suspend
= musb_suspend
,
2454 .resume_noirq
= musb_resume_noirq
,
2455 .runtime_suspend
= musb_runtime_suspend
,
2456 .runtime_resume
= musb_runtime_resume
,
2459 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2461 #define MUSB_DEV_PM_OPS NULL
2464 static struct platform_driver musb_driver
= {
2466 .name
= (char *)musb_driver_name
,
2467 .bus
= &platform_bus_type
,
2468 .owner
= THIS_MODULE
,
2469 .pm
= MUSB_DEV_PM_OPS
,
2471 .probe
= musb_probe
,
2472 .remove
= __devexit_p(musb_remove
),
2473 .shutdown
= musb_shutdown
,
2476 /*-------------------------------------------------------------------------*/
2478 static int __init
musb_init(void)
2483 pr_info("%s: version " MUSB_VERSION
", "
2486 "otg (peripheral+host)",
2488 return platform_driver_register(&musb_driver
);
2490 module_init(musb_init
);
2492 static void __exit
musb_cleanup(void)
2494 platform_driver_unregister(&musb_driver
);
2496 module_exit(musb_cleanup
);