2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * SPDX-License-Identifier: GPL-2.0
12 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
14 * This consists of a Host Controller Driver (HCD) and a peripheral
15 * controller driver implementing the "Gadget" API; OTG support is
16 * in the works. These are normal Linux-USB controller drivers which
17 * use IRQs and have no dedicated thread.
19 * This version of the driver has only been used with products from
20 * Texas Instruments. Those products integrate the Inventra logic
21 * with other DMA, IRQ, and bus modules, as well as other logic that
22 * needs to be reflected in this driver.
25 * NOTE: the original Mentor code here was pretty much a collection
26 * of mechanisms that don't seem to have been fully integrated/working
27 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
28 * Key open issues include:
30 * - Lack of host-side transaction scheduling, for all transfer types.
31 * The hardware doesn't do it; instead, software must.
33 * This is not an issue for OTG devices that don't support external
34 * hubs, but for more "normal" USB hosts it's a user issue that the
35 * "multipoint" support doesn't scale in the expected ways. That
36 * includes DaVinci EVM in a common non-OTG mode.
38 * * Control and bulk use dedicated endpoints, and there's as
39 * yet no mechanism to either (a) reclaim the hardware when
40 * peripherals are NAKing, which gets complicated with bulk
41 * endpoints, or (b) use more than a single bulk endpoint in
44 * RESULT: one device may be perceived as blocking another one.
46 * * Interrupt and isochronous will dynamically allocate endpoint
47 * hardware, but (a) there's no record keeping for bandwidth;
48 * (b) in the common case that few endpoints are available, there
49 * is no mechanism to reuse endpoints to talk to multiple devices.
51 * RESULT: At one extreme, bandwidth can be overcommitted in
52 * some hardware configurations, no faults will be reported.
53 * At the other extreme, the bandwidth capabilities which do
54 * exist tend to be severely undercommitted. You can't yet hook
55 * up both a keyboard and a mouse to an external USB hub.
59 * This gets many kinds of configuration information:
60 * - Kconfig for everything user-configurable
61 * - platform_device for addressing, irq, and platform_data
62 * - platform_data is mostly for board-specific informarion
63 * (plus recentrly, SOC or family details)
65 * Most of the conditional compilation will (someday) vanish.
69 #include <linux/module.h>
70 #include <linux/kernel.h>
71 #include <linux/sched.h>
72 #include <linux/slab.h>
73 #include <linux/init.h>
74 #include <linux/list.h>
75 #include <linux/kobject.h>
76 #include <linux/prefetch.h>
77 #include <linux/platform_device.h>
82 #include <linux/errno.h>
83 #include <linux/usb/ch9.h>
84 #include <linux/usb/gadget.h>
85 #include <linux/usb/musb.h>
87 #include "linux-compat.h"
88 #include "usb-compat.h"
91 #include "musb_core.h"
93 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
96 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
97 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
99 #define MUSB_VERSION "6.0"
101 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
103 #define MUSB_DRIVER_NAME "musb-hdrc"
104 const char musb_driver_name
[] = MUSB_DRIVER_NAME
;
106 MODULE_DESCRIPTION(DRIVER_INFO
);
107 MODULE_AUTHOR(DRIVER_AUTHOR
);
108 MODULE_LICENSE("GPL");
109 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME
);
113 /*-------------------------------------------------------------------------*/
115 static inline struct musb
*dev_to_musb(struct device
*dev
)
117 return dev_get_drvdata(dev
);
120 /*-------------------------------------------------------------------------*/
122 static int musb_ulpi_read(struct usb_phy
*phy
, u32 offset
)
124 void __iomem
*addr
= phy
->io_priv
;
130 pm_runtime_get_sync(phy
->io_dev
);
132 /* Make sure the transceiver is not in low power mode */
133 power
= musb_readb(addr
, MUSB_POWER
);
134 power
&= ~MUSB_POWER_SUSPENDM
;
135 musb_writeb(addr
, MUSB_POWER
, power
);
137 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
138 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
141 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
142 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
,
143 MUSB_ULPI_REG_REQ
| MUSB_ULPI_RDN_WR
);
145 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
146 & MUSB_ULPI_REG_CMPLT
)) {
154 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
155 r
&= ~MUSB_ULPI_REG_CMPLT
;
156 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
158 ret
= musb_readb(addr
, MUSB_ULPI_REG_DATA
);
161 pm_runtime_put(phy
->io_dev
);
166 static int musb_ulpi_write(struct usb_phy
*phy
, u32 offset
, u32 data
)
168 void __iomem
*addr
= phy
->io_priv
;
174 pm_runtime_get_sync(phy
->io_dev
);
176 /* Make sure the transceiver is not in low power mode */
177 power
= musb_readb(addr
, MUSB_POWER
);
178 power
&= ~MUSB_POWER_SUSPENDM
;
179 musb_writeb(addr
, MUSB_POWER
, power
);
181 musb_writeb(addr
, MUSB_ULPI_REG_ADDR
, (u8
)offset
);
182 musb_writeb(addr
, MUSB_ULPI_REG_DATA
, (u8
)data
);
183 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, MUSB_ULPI_REG_REQ
);
185 while (!(musb_readb(addr
, MUSB_ULPI_REG_CONTROL
)
186 & MUSB_ULPI_REG_CMPLT
)) {
194 r
= musb_readb(addr
, MUSB_ULPI_REG_CONTROL
);
195 r
&= ~MUSB_ULPI_REG_CMPLT
;
196 musb_writeb(addr
, MUSB_ULPI_REG_CONTROL
, r
);
199 pm_runtime_put(phy
->io_dev
);
204 static struct usb_phy_io_ops musb_ulpi_access
= {
205 .read
= musb_ulpi_read
,
206 .write
= musb_ulpi_write
,
210 /*-------------------------------------------------------------------------*/
212 #if !defined(CONFIG_USB_MUSB_TUSB6010)
215 * Load an endpoint's FIFO
217 void musb_write_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, const u8
*src
)
219 struct musb
*musb
= hw_ep
->musb
;
220 void __iomem
*fifo
= hw_ep
->fifo
;
224 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
225 'T', hw_ep
->epnum
, fifo
, len
, src
);
227 /* we can't assume unaligned reads work */
228 if (likely((0x01 & (unsigned long) src
) == 0)) {
231 /* best case is 32bit-aligned source address */
232 if ((0x02 & (unsigned long) src
) == 0) {
234 writesl(fifo
, src
+ index
, len
>> 2);
235 index
+= len
& ~0x03;
238 musb_writew(fifo
, 0, *(u16
*)&src
[index
]);
243 writesw(fifo
, src
+ index
, len
>> 1);
244 index
+= len
& ~0x01;
248 musb_writeb(fifo
, 0, src
[index
]);
251 writesb(fifo
, src
, len
);
255 #if !defined(CONFIG_USB_MUSB_AM35X) && !defined(CONFIG_USB_MUSB_PIC32)
257 * Unload an endpoint's FIFO
259 void musb_read_fifo(struct musb_hw_ep
*hw_ep
, u16 len
, u8
*dst
)
261 struct musb
*musb
= hw_ep
->musb
;
262 void __iomem
*fifo
= hw_ep
->fifo
;
264 dev_dbg(musb
->controller
, "%cX ep%d fifo %p count %d buf %p\n",
265 'R', hw_ep
->epnum
, fifo
, len
, dst
);
267 /* we can't assume unaligned writes work */
268 if (likely((0x01 & (unsigned long) dst
) == 0)) {
271 /* best case is 32bit-aligned destination address */
272 if ((0x02 & (unsigned long) dst
) == 0) {
274 readsl(fifo
, dst
, len
>> 2);
278 *(u16
*)&dst
[index
] = musb_readw(fifo
, 0);
283 readsw(fifo
, dst
, len
>> 1);
288 dst
[index
] = musb_readb(fifo
, 0);
291 readsb(fifo
, dst
, len
);
296 #endif /* normal PIO */
299 /*-------------------------------------------------------------------------*/
301 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
302 static const u8 musb_test_packet
[53] = {
303 /* implicit SYNC then DATA0 to start */
306 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
308 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
310 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
311 /* JJJJJJJKKKKKKK x8 */
312 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
314 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
315 /* JKKKKKKK x10, JK */
316 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
318 /* implicit CRC16 then EOP to end */
321 void musb_load_testpacket(struct musb
*musb
)
323 void __iomem
*regs
= musb
->endpoints
[0].regs
;
325 musb_ep_select(musb
->mregs
, 0);
326 musb_write_fifo(musb
->control_ep
,
327 sizeof(musb_test_packet
), musb_test_packet
);
328 musb_writew(regs
, MUSB_CSR0
, MUSB_CSR0_TXPKTRDY
);
332 /*-------------------------------------------------------------------------*/
335 * Handles OTG hnp timeouts, such as b_ase0_brst
337 void musb_otg_timer_func(unsigned long data
)
339 struct musb
*musb
= (struct musb
*)data
;
342 spin_lock_irqsave(&musb
->lock
, flags
);
343 switch (musb
->xceiv
->state
) {
344 case OTG_STATE_B_WAIT_ACON
:
345 dev_dbg(musb
->controller
, "HNP: b_wait_acon timeout; back to b_peripheral\n");
346 musb_g_disconnect(musb
);
347 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
350 case OTG_STATE_A_SUSPEND
:
351 case OTG_STATE_A_WAIT_BCON
:
352 dev_dbg(musb
->controller
, "HNP: %s timeout\n",
353 otg_state_string(musb
->xceiv
->state
));
354 musb_platform_set_vbus(musb
, 0);
355 musb
->xceiv
->state
= OTG_STATE_A_WAIT_VFALL
;
358 dev_dbg(musb
->controller
, "HNP: Unhandled mode %s\n",
359 otg_state_string(musb
->xceiv
->state
));
361 musb
->ignore_disconnect
= 0;
362 spin_unlock_irqrestore(&musb
->lock
, flags
);
366 * Stops the HNP transition. Caller must take care of locking.
368 void musb_hnp_stop(struct musb
*musb
)
370 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
371 void __iomem
*mbase
= musb
->mregs
;
374 dev_dbg(musb
->controller
, "HNP: stop from %s\n", otg_state_string(musb
->xceiv
->state
));
376 switch (musb
->xceiv
->state
) {
377 case OTG_STATE_A_PERIPHERAL
:
378 musb_g_disconnect(musb
);
379 dev_dbg(musb
->controller
, "HNP: back to %s\n",
380 otg_state_string(musb
->xceiv
->state
));
382 case OTG_STATE_B_HOST
:
383 dev_dbg(musb
->controller
, "HNP: Disabling HR\n");
384 hcd
->self
.is_b_host
= 0;
385 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
387 reg
= musb_readb(mbase
, MUSB_POWER
);
388 reg
|= MUSB_POWER_SUSPENDM
;
389 musb_writeb(mbase
, MUSB_POWER
, reg
);
390 /* REVISIT: Start SESSION_REQUEST here? */
393 dev_dbg(musb
->controller
, "HNP: Stopping in unknown state %s\n",
394 otg_state_string(musb
->xceiv
->state
));
398 * When returning to A state after HNP, avoid hub_port_rebounce(),
399 * which cause occasional OPT A "Did not receive reset after connect"
402 musb
->port1_status
&= ~(USB_PORT_STAT_C_CONNECTION
<< 16);
407 * Interrupt Service Routine to record USB "global" interrupts.
408 * Since these do not happen often and signify things of
409 * paramount importance, it seems OK to check them individually;
410 * the order of the tests is specified in the manual
412 * @param musb instance pointer
413 * @param int_usb register contents
418 static irqreturn_t
musb_stage0_irq(struct musb
*musb
, u8 int_usb
,
422 struct usb_otg
*otg
= musb
->xceiv
->otg
;
424 irqreturn_t handled
= IRQ_NONE
;
426 dev_dbg(musb
->controller
, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power
, devctl
,
430 /* in host mode, the peripheral may issue remote wakeup.
431 * in peripheral mode, the host may resume the link.
432 * spurious RESUME irqs happen too, paired with SUSPEND.
434 if (int_usb
& MUSB_INTR_RESUME
) {
435 handled
= IRQ_HANDLED
;
436 dev_dbg(musb
->controller
, "RESUME (%s)\n", otg_state_string(musb
->xceiv
->state
));
438 if (devctl
& MUSB_DEVCTL_HM
) {
439 void __iomem
*mbase
= musb
->mregs
;
441 switch (musb
->xceiv
->state
) {
442 case OTG_STATE_A_SUSPEND
:
443 /* remote wakeup? later, GetPortStatus
444 * will stop RESUME signaling
447 if (power
& MUSB_POWER_SUSPENDM
) {
449 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
450 dev_dbg(musb
->controller
, "Spurious SUSPENDM\n");
454 power
&= ~MUSB_POWER_SUSPENDM
;
455 musb_writeb(mbase
, MUSB_POWER
,
456 power
| MUSB_POWER_RESUME
);
458 musb
->port1_status
|=
459 (USB_PORT_STAT_C_SUSPEND
<< 16)
460 | MUSB_PORT_STAT_RESUME
;
461 musb
->rh_timer
= jiffies
462 + msecs_to_jiffies(20);
464 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
466 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
468 case OTG_STATE_B_WAIT_ACON
:
469 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
474 WARNING("bogus %s RESUME (%s)\n",
476 otg_state_string(musb
->xceiv
->state
));
479 switch (musb
->xceiv
->state
) {
480 case OTG_STATE_A_SUSPEND
:
481 /* possibly DISCONNECT is upcoming */
482 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
483 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
485 case OTG_STATE_B_WAIT_ACON
:
486 case OTG_STATE_B_PERIPHERAL
:
487 /* disconnect while suspended? we may
488 * not get a disconnect irq...
490 if ((devctl
& MUSB_DEVCTL_VBUS
)
491 != (3 << MUSB_DEVCTL_VBUS_SHIFT
)
493 musb
->int_usb
|= MUSB_INTR_DISCONNECT
;
494 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
499 case OTG_STATE_B_IDLE
:
500 musb
->int_usb
&= ~MUSB_INTR_SUSPEND
;
503 WARNING("bogus %s RESUME (%s)\n",
505 otg_state_string(musb
->xceiv
->state
));
510 /* see manual for the order of the tests */
511 if (int_usb
& MUSB_INTR_SESSREQ
) {
512 void __iomem
*mbase
= musb
->mregs
;
514 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
515 && (devctl
& MUSB_DEVCTL_BDEVICE
)) {
516 dev_dbg(musb
->controller
, "SessReq while on B state\n");
520 dev_dbg(musb
->controller
, "SESSION_REQUEST (%s)\n",
521 otg_state_string(musb
->xceiv
->state
));
523 /* IRQ arrives from ID pin sense or (later, if VBUS power
524 * is removed) SRP. responses are time critical:
525 * - turn on VBUS (with silicon-specific mechanism)
526 * - go through A_WAIT_VRISE
527 * - ... to A_WAIT_BCON.
528 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
530 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
531 musb
->ep0_stage
= MUSB_EP0_START
;
532 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
534 musb_platform_set_vbus(musb
, 1);
536 handled
= IRQ_HANDLED
;
539 if (int_usb
& MUSB_INTR_VBUSERROR
) {
542 /* During connection as an A-Device, we may see a short
543 * current spikes causing voltage drop, because of cable
544 * and peripheral capacitance combined with vbus draw.
545 * (So: less common with truly self-powered devices, where
546 * vbus doesn't act like a power supply.)
548 * Such spikes are short; usually less than ~500 usec, max
549 * of ~2 msec. That is, they're not sustained overcurrent
550 * errors, though they're reported using VBUSERROR irqs.
552 * Workarounds: (a) hardware: use self powered devices.
553 * (b) software: ignore non-repeated VBUS errors.
555 * REVISIT: do delays from lots of DEBUG_KERNEL checks
556 * make trouble here, keeping VBUS < 4.4V ?
558 switch (musb
->xceiv
->state
) {
559 case OTG_STATE_A_HOST
:
560 /* recovery is dicey once we've gotten past the
561 * initial stages of enumeration, but if VBUS
562 * stayed ok at the other end of the link, and
563 * another reset is due (at least for high speed,
564 * to redo the chirp etc), it might work OK...
566 case OTG_STATE_A_WAIT_BCON
:
567 case OTG_STATE_A_WAIT_VRISE
:
568 if (musb
->vbuserr_retry
) {
569 void __iomem
*mbase
= musb
->mregs
;
571 musb
->vbuserr_retry
--;
573 devctl
|= MUSB_DEVCTL_SESSION
;
574 musb_writeb(mbase
, MUSB_DEVCTL
, devctl
);
576 musb
->port1_status
|=
577 USB_PORT_STAT_OVERCURRENT
578 | (USB_PORT_STAT_C_OVERCURRENT
<< 16);
585 dev_dbg(musb
->controller
, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
586 otg_state_string(musb
->xceiv
->state
),
589 switch (devctl
& MUSB_DEVCTL_VBUS
) {
590 case 0 << MUSB_DEVCTL_VBUS_SHIFT
:
591 s
= "<SessEnd"; break;
592 case 1 << MUSB_DEVCTL_VBUS_SHIFT
:
593 s
= "<AValid"; break;
594 case 2 << MUSB_DEVCTL_VBUS_SHIFT
:
595 s
= "<VBusValid"; break;
596 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
600 VBUSERR_RETRY_COUNT
- musb
->vbuserr_retry
,
603 /* go through A_WAIT_VFALL then start a new session */
605 musb_platform_set_vbus(musb
, 0);
606 handled
= IRQ_HANDLED
;
609 if (int_usb
& MUSB_INTR_SUSPEND
) {
610 dev_dbg(musb
->controller
, "SUSPEND (%s) devctl %02x power %02x\n",
611 otg_state_string(musb
->xceiv
->state
), devctl
, power
);
612 handled
= IRQ_HANDLED
;
614 switch (musb
->xceiv
->state
) {
615 case OTG_STATE_A_PERIPHERAL
:
616 /* We also come here if the cable is removed, since
617 * this silicon doesn't report ID-no-longer-grounded.
619 * We depend on T(a_wait_bcon) to shut us down, and
620 * hope users don't do anything dicey during this
621 * undesired detour through A_WAIT_BCON.
624 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
625 musb_root_disconnect(musb
);
626 musb_platform_try_idle(musb
, jiffies
627 + msecs_to_jiffies(musb
->a_wait_bcon
628 ? : OTG_TIME_A_WAIT_BCON
));
631 case OTG_STATE_B_IDLE
:
632 if (!musb
->is_active
)
634 case OTG_STATE_B_PERIPHERAL
:
635 musb_g_suspend(musb
);
636 musb
->is_active
= is_otg_enabled(musb
)
637 && otg
->gadget
->b_hnp_enable
;
638 if (musb
->is_active
) {
639 musb
->xceiv
->state
= OTG_STATE_B_WAIT_ACON
;
640 dev_dbg(musb
->controller
, "HNP: Setting timer for b_ase0_brst\n");
641 mod_timer(&musb
->otg_timer
, jiffies
643 OTG_TIME_B_ASE0_BRST
));
646 case OTG_STATE_A_WAIT_BCON
:
647 if (musb
->a_wait_bcon
!= 0)
648 musb_platform_try_idle(musb
, jiffies
649 + msecs_to_jiffies(musb
->a_wait_bcon
));
651 case OTG_STATE_A_HOST
:
652 musb
->xceiv
->state
= OTG_STATE_A_SUSPEND
;
653 musb
->is_active
= is_otg_enabled(musb
)
654 && otg
->host
->b_hnp_enable
;
656 case OTG_STATE_B_HOST
:
657 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
658 dev_dbg(musb
->controller
, "REVISIT: SUSPEND as B_HOST\n");
661 /* "should not happen" */
668 if (int_usb
& MUSB_INTR_CONNECT
) {
669 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
671 handled
= IRQ_HANDLED
;
674 musb
->ep0_stage
= MUSB_EP0_START
;
676 /* flush endpoints when transitioning from Device Mode */
677 if (is_peripheral_active(musb
)) {
678 /* REVISIT HNP; just force disconnect */
680 musb_writew(musb
->mregs
, MUSB_INTRTXE
, musb
->epmask
);
681 musb_writew(musb
->mregs
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
682 musb_writeb(musb
->mregs
, MUSB_INTRUSBE
, 0xf7);
684 musb
->port1_status
&= ~(USB_PORT_STAT_LOW_SPEED
685 |USB_PORT_STAT_HIGH_SPEED
686 |USB_PORT_STAT_ENABLE
688 musb
->port1_status
|= USB_PORT_STAT_CONNECTION
689 |(USB_PORT_STAT_C_CONNECTION
<< 16);
691 /* high vs full speed is just a guess until after reset */
692 if (devctl
& MUSB_DEVCTL_LSDEV
)
693 musb
->port1_status
|= USB_PORT_STAT_LOW_SPEED
;
695 /* indicate new connection to OTG machine */
696 switch (musb
->xceiv
->state
) {
697 case OTG_STATE_B_PERIPHERAL
:
698 if (int_usb
& MUSB_INTR_SUSPEND
) {
699 dev_dbg(musb
->controller
, "HNP: SUSPEND+CONNECT, now b_host\n");
700 int_usb
&= ~MUSB_INTR_SUSPEND
;
703 dev_dbg(musb
->controller
, "CONNECT as b_peripheral???\n");
705 case OTG_STATE_B_WAIT_ACON
:
706 dev_dbg(musb
->controller
, "HNP: CONNECT, now b_host\n");
708 musb
->xceiv
->state
= OTG_STATE_B_HOST
;
709 hcd
->self
.is_b_host
= 1;
710 musb
->ignore_disconnect
= 0;
711 del_timer(&musb
->otg_timer
);
714 if ((devctl
& MUSB_DEVCTL_VBUS
)
715 == (3 << MUSB_DEVCTL_VBUS_SHIFT
)) {
716 musb
->xceiv
->state
= OTG_STATE_A_HOST
;
717 hcd
->self
.is_b_host
= 0;
722 /* poke the root hub */
725 usb_hcd_poll_rh_status(hcd
);
727 usb_hcd_resume_root_hub(hcd
);
729 dev_dbg(musb
->controller
, "CONNECT (%s) devctl %02x\n",
730 otg_state_string(musb
->xceiv
->state
), devctl
);
735 if ((int_usb
& MUSB_INTR_DISCONNECT
) && !musb
->ignore_disconnect
) {
736 dev_dbg(musb
->controller
, "DISCONNECT (%s) as %s, devctl %02x\n",
737 otg_state_string(musb
->xceiv
->state
),
738 MUSB_MODE(musb
), devctl
);
739 handled
= IRQ_HANDLED
;
741 switch (musb
->xceiv
->state
) {
742 case OTG_STATE_A_HOST
:
743 case OTG_STATE_A_SUSPEND
:
744 usb_hcd_resume_root_hub(musb_to_hcd(musb
));
745 musb_root_disconnect(musb
);
746 if (musb
->a_wait_bcon
!= 0 && is_otg_enabled(musb
))
747 musb_platform_try_idle(musb
, jiffies
748 + msecs_to_jiffies(musb
->a_wait_bcon
));
750 case OTG_STATE_B_HOST
:
751 /* REVISIT this behaves for "real disconnect"
752 * cases; make sure the other transitions from
753 * from B_HOST act right too. The B_HOST code
754 * in hnp_stop() is currently not used...
756 musb_root_disconnect(musb
);
757 musb_to_hcd(musb
)->self
.is_b_host
= 0;
758 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
760 musb_g_disconnect(musb
);
762 case OTG_STATE_A_PERIPHERAL
:
764 musb_root_disconnect(musb
);
766 case OTG_STATE_B_WAIT_ACON
:
768 case OTG_STATE_B_PERIPHERAL
:
769 case OTG_STATE_B_IDLE
:
770 musb_g_disconnect(musb
);
773 WARNING("unhandled DISCONNECT transition (%s)\n",
774 otg_state_string(musb
->xceiv
->state
));
779 /* mentor saves a bit: bus reset and babble share the same irq.
780 * only host sees babble; only peripheral sees bus reset.
782 if (int_usb
& MUSB_INTR_RESET
) {
783 handled
= IRQ_HANDLED
;
784 if (is_host_capable() && (devctl
& MUSB_DEVCTL_HM
) != 0) {
786 * Looks like non-HS BABBLE can be ignored, but
787 * HS BABBLE is an error condition. For HS the solution
788 * is to avoid babble in the first place and fix what
789 * caused BABBLE. When HS BABBLE happens we can only
792 if (devctl
& (MUSB_DEVCTL_FSDEV
| MUSB_DEVCTL_LSDEV
))
793 dev_dbg(musb
->controller
, "BABBLE devctl: %02x\n", devctl
);
795 ERR("Stopping host session -- babble\n");
796 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
798 } else if (is_peripheral_capable()) {
799 dev_dbg(musb
->controller
, "BUS RESET as %s\n",
800 otg_state_string(musb
->xceiv
->state
));
801 switch (musb
->xceiv
->state
) {
802 case OTG_STATE_A_SUSPEND
:
803 /* We need to ignore disconnect on suspend
804 * otherwise tusb 2.0 won't reconnect after a
805 * power cycle, which breaks otg compliance.
807 musb
->ignore_disconnect
= 1;
810 case OTG_STATE_A_WAIT_BCON
: /* OPT TD.4.7-900ms */
811 /* never use invalid T(a_wait_bcon) */
812 dev_dbg(musb
->controller
, "HNP: in %s, %d msec timeout\n",
813 otg_state_string(musb
->xceiv
->state
),
815 mod_timer(&musb
->otg_timer
, jiffies
816 + msecs_to_jiffies(TA_WAIT_BCON(musb
)));
818 case OTG_STATE_A_PERIPHERAL
:
819 musb
->ignore_disconnect
= 0;
820 del_timer(&musb
->otg_timer
);
823 case OTG_STATE_B_WAIT_ACON
:
824 dev_dbg(musb
->controller
, "HNP: RESET (%s), to b_peripheral\n",
825 otg_state_string(musb
->xceiv
->state
));
826 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
829 case OTG_STATE_B_IDLE
:
830 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
832 case OTG_STATE_B_PERIPHERAL
:
836 dev_dbg(musb
->controller
, "Unhandled BUS RESET as %s\n",
837 otg_state_string(musb
->xceiv
->state
));
844 /* REVISIT ... this would be for multiplexing periodic endpoints, or
845 * supporting transfer phasing to prevent exceeding ISO bandwidth
846 * limits of a given frame or microframe.
848 * It's not needed for peripheral side, which dedicates endpoints;
849 * though it _might_ use SOF irqs for other purposes.
851 * And it's not currently needed for host side, which also dedicates
852 * endpoints, relies on TX/RX interval registers, and isn't claimed
853 * to support ISO transfers yet.
855 if (int_usb
& MUSB_INTR_SOF
) {
856 void __iomem
*mbase
= musb
->mregs
;
857 struct musb_hw_ep
*ep
;
861 dev_dbg(musb
->controller
, "START_OF_FRAME\n");
862 handled
= IRQ_HANDLED
;
864 /* start any periodic Tx transfers waiting for current frame */
865 frame
= musb_readw(mbase
, MUSB_FRAME
);
866 ep
= musb
->endpoints
;
867 for (epnum
= 1; (epnum
< musb
->nr_endpoints
)
868 && (musb
->epmask
>= (1 << epnum
));
871 * FIXME handle framecounter wraps (12 bits)
872 * eliminate duplicated StartUrb logic
874 if (ep
->dwWaitFrame
>= frame
) {
876 pr_debug("SOF --> periodic TX%s on %d\n",
877 ep
->tx_channel
? " DMA" : "",
880 musb_h_tx_start(musb
, epnum
);
882 cppi_hostdma_start(musb
, epnum
);
884 } /* end of for loop */
888 schedule_work(&musb
->irq_work
);
893 /*-------------------------------------------------------------------------*/
896 * Program the HDRC to start (enable interrupts, dma, etc.).
899 void musb_start(struct musb
*musb
)
901 int musb_start(struct musb
*musb
)
904 void __iomem
*regs
= musb
->mregs
;
905 u8 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
910 dev_dbg(musb
->controller
, "<== devctl %02x\n", devctl
);
912 /* Set INT enable registers, enable interrupts */
913 musb_writew(regs
, MUSB_INTRTXE
, musb
->epmask
);
914 musb_writew(regs
, MUSB_INTRRXE
, musb
->epmask
& 0xfffe);
915 musb_writeb(regs
, MUSB_INTRUSBE
, 0xf7);
917 musb_writeb(regs
, MUSB_TESTMODE
, 0);
919 /* put into basic highspeed mode and start session */
920 musb_writeb(regs
, MUSB_POWER
, MUSB_POWER_ISOUPDATE
922 /* ENSUSPEND wedges tusb */
923 /* | MUSB_POWER_ENSUSPEND */
927 devctl
= musb_readb(regs
, MUSB_DEVCTL
);
928 devctl
&= ~MUSB_DEVCTL_SESSION
;
930 if (is_otg_enabled(musb
)) {
932 /* session started after:
933 * (a) ID-grounded irq, host mode;
934 * (b) vbus present/connect IRQ, peripheral mode;
935 * (c) peripheral initiates, using SRP
937 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
940 devctl
|= MUSB_DEVCTL_SESSION
;
943 } else if (is_host_enabled(musb
)) {
944 /* assume ID pin is hard-wired to ground */
945 devctl
|= MUSB_DEVCTL_SESSION
;
947 } else /* peripheral is enabled */ {
948 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
953 musb_platform_enable(musb
);
955 ret
= musb_platform_enable(musb
);
961 musb_writeb(regs
, MUSB_DEVCTL
, devctl
);
969 static void musb_generic_disable(struct musb
*musb
)
971 void __iomem
*mbase
= musb
->mregs
;
974 /* disable interrupts */
975 musb_writeb(mbase
, MUSB_INTRUSBE
, 0);
976 musb_writew(mbase
, MUSB_INTRTXE
, 0);
977 musb_writew(mbase
, MUSB_INTRRXE
, 0);
980 musb_writeb(mbase
, MUSB_DEVCTL
, 0);
982 /* flush pending interrupts */
983 temp
= musb_readb(mbase
, MUSB_INTRUSB
);
984 temp
= musb_readw(mbase
, MUSB_INTRTX
);
985 temp
= musb_readw(mbase
, MUSB_INTRRX
);
990 * Make the HDRC stop (disable interrupts, etc.);
991 * reversible by musb_start
992 * called on gadget driver unregister
993 * with controller locked, irqs blocked
994 * acts as a NOP unless some role activated the hardware
996 void musb_stop(struct musb
*musb
)
998 /* stop IRQs, timers, ... */
999 musb_platform_disable(musb
);
1000 musb_generic_disable(musb
);
1001 dev_dbg(musb
->controller
, "HDRC disabled\n");
1004 * - mark host and/or peripheral drivers unusable/inactive
1005 * - disable DMA (and enable it in HdrcStart)
1006 * - make sure we can musb_start() after musb_stop(); with
1007 * OTG mode, gadget driver module rmmod/modprobe cycles that
1010 musb_platform_try_idle(musb
, 0);
1014 static void musb_shutdown(struct platform_device
*pdev
)
1016 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
1017 unsigned long flags
;
1019 pm_runtime_get_sync(musb
->controller
);
1021 musb_gadget_cleanup(musb
);
1023 spin_lock_irqsave(&musb
->lock
, flags
);
1024 musb_platform_disable(musb
);
1025 musb_generic_disable(musb
);
1026 spin_unlock_irqrestore(&musb
->lock
, flags
);
1028 if (!is_otg_enabled(musb
) && is_host_enabled(musb
))
1029 usb_remove_hcd(musb_to_hcd(musb
));
1030 musb_writeb(musb
->mregs
, MUSB_DEVCTL
, 0);
1031 musb_platform_exit(musb
);
1033 pm_runtime_put(musb
->controller
);
1034 /* FIXME power down */
1039 /*-------------------------------------------------------------------------*/
1042 * The silicon either has hard-wired endpoint configurations, or else
1043 * "dynamic fifo" sizing. The driver has support for both, though at this
1044 * writing only the dynamic sizing is very well tested. Since we switched
1045 * away from compile-time hardware parameters, we can no longer rely on
1046 * dead code elimination to leave only the relevant one in the object file.
1048 * We don't currently use dynamic fifo setup capability to do anything
1049 * more than selecting one of a bunch of predefined configurations.
1051 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1052 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1053 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1054 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1055 || defined(CONFIG_USB_MUSB_AM35X) \
1056 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1057 || defined(CONFIG_USB_MUSB_DSPS) \
1058 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1059 static ushort __devinitdata fifo_mode
= 4;
1060 #elif defined(CONFIG_USB_MUSB_UX500) \
1061 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1062 static ushort __devinitdata fifo_mode
= 5;
1064 static ushort __devinitdata fifo_mode
= 2;
1067 /* "modprobe ... fifo_mode=1" etc */
1068 module_param(fifo_mode
, ushort
, 0);
1069 MODULE_PARM_DESC(fifo_mode
, "initial endpoint configuration");
1072 * tables defining fifo_mode values. define more if you like.
1073 * for host side, make sure both halves of ep1 are set up.
1076 /* mode 0 - fits in 2KB */
1077 static struct musb_fifo_cfg __devinitdata mode_0_cfg
[] = {
1078 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1079 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1080 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1081 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1082 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1085 /* mode 1 - fits in 4KB */
1086 static struct musb_fifo_cfg __devinitdata mode_1_cfg
[] = {
1087 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1088 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1089 { .hw_ep_num
= 2, .style
= FIFO_RXTX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1090 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1091 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1094 /* mode 2 - fits in 4KB */
1095 static struct musb_fifo_cfg __devinitdata mode_2_cfg
[] = {
1096 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1097 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1098 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1099 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1100 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1101 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1104 /* mode 3 - fits in 4KB */
1105 static struct musb_fifo_cfg __devinitdata mode_3_cfg
[] = {
1106 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1107 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, .mode
= BUF_DOUBLE
, },
1108 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1109 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1110 { .hw_ep_num
= 3, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1111 { .hw_ep_num
= 4, .style
= FIFO_RXTX
, .maxpacket
= 256, },
1114 /* mode 4 - fits in 16KB */
1115 static struct musb_fifo_cfg __devinitdata mode_4_cfg
[] = {
1116 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1117 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1118 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1119 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1120 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1121 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1122 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1123 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1124 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1125 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1126 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 512, },
1127 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 512, },
1128 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 512, },
1129 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 512, },
1130 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 512, },
1131 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 512, },
1132 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 512, },
1133 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 512, },
1134 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 256, },
1135 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 64, },
1136 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 256, },
1137 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 64, },
1138 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 256, },
1139 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 64, },
1140 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 4096, },
1141 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1142 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1145 /* mode 5 - fits in 8KB */
1146 static struct musb_fifo_cfg __devinitdata mode_5_cfg
[] = {
1147 { .hw_ep_num
= 1, .style
= FIFO_TX
, .maxpacket
= 512, },
1148 { .hw_ep_num
= 1, .style
= FIFO_RX
, .maxpacket
= 512, },
1149 { .hw_ep_num
= 2, .style
= FIFO_TX
, .maxpacket
= 512, },
1150 { .hw_ep_num
= 2, .style
= FIFO_RX
, .maxpacket
= 512, },
1151 { .hw_ep_num
= 3, .style
= FIFO_TX
, .maxpacket
= 512, },
1152 { .hw_ep_num
= 3, .style
= FIFO_RX
, .maxpacket
= 512, },
1153 { .hw_ep_num
= 4, .style
= FIFO_TX
, .maxpacket
= 512, },
1154 { .hw_ep_num
= 4, .style
= FIFO_RX
, .maxpacket
= 512, },
1155 { .hw_ep_num
= 5, .style
= FIFO_TX
, .maxpacket
= 512, },
1156 { .hw_ep_num
= 5, .style
= FIFO_RX
, .maxpacket
= 512, },
1157 { .hw_ep_num
= 6, .style
= FIFO_TX
, .maxpacket
= 32, },
1158 { .hw_ep_num
= 6, .style
= FIFO_RX
, .maxpacket
= 32, },
1159 { .hw_ep_num
= 7, .style
= FIFO_TX
, .maxpacket
= 32, },
1160 { .hw_ep_num
= 7, .style
= FIFO_RX
, .maxpacket
= 32, },
1161 { .hw_ep_num
= 8, .style
= FIFO_TX
, .maxpacket
= 32, },
1162 { .hw_ep_num
= 8, .style
= FIFO_RX
, .maxpacket
= 32, },
1163 { .hw_ep_num
= 9, .style
= FIFO_TX
, .maxpacket
= 32, },
1164 { .hw_ep_num
= 9, .style
= FIFO_RX
, .maxpacket
= 32, },
1165 { .hw_ep_num
= 10, .style
= FIFO_TX
, .maxpacket
= 32, },
1166 { .hw_ep_num
= 10, .style
= FIFO_RX
, .maxpacket
= 32, },
1167 { .hw_ep_num
= 11, .style
= FIFO_TX
, .maxpacket
= 32, },
1168 { .hw_ep_num
= 11, .style
= FIFO_RX
, .maxpacket
= 32, },
1169 { .hw_ep_num
= 12, .style
= FIFO_TX
, .maxpacket
= 32, },
1170 { .hw_ep_num
= 12, .style
= FIFO_RX
, .maxpacket
= 32, },
1171 { .hw_ep_num
= 13, .style
= FIFO_RXTX
, .maxpacket
= 512, },
1172 { .hw_ep_num
= 14, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1173 { .hw_ep_num
= 15, .style
= FIFO_RXTX
, .maxpacket
= 1024, },
1177 * configure a fifo; for non-shared endpoints, this may be called
1178 * once for a tx fifo and once for an rx fifo.
1180 * returns negative errno or offset for next fifo.
1182 static int __devinit
1183 fifo_setup(struct musb
*musb
, struct musb_hw_ep
*hw_ep
,
1184 const struct musb_fifo_cfg
*cfg
, u16 offset
)
1186 void __iomem
*mbase
= musb
->mregs
;
1188 u16 maxpacket
= cfg
->maxpacket
;
1189 u16 c_off
= offset
>> 3;
1192 /* expect hw_ep has already been zero-initialized */
1194 size
= ffs(max(maxpacket
, (u16
) 8)) - 1;
1195 maxpacket
= 1 << size
;
1198 if (cfg
->mode
== BUF_DOUBLE
) {
1199 if ((offset
+ (maxpacket
<< 1)) >
1200 (1 << (musb
->config
->ram_bits
+ 2)))
1202 c_size
|= MUSB_FIFOSZ_DPB
;
1204 if ((offset
+ maxpacket
) > (1 << (musb
->config
->ram_bits
+ 2)))
1208 /* configure the FIFO */
1209 musb_writeb(mbase
, MUSB_INDEX
, hw_ep
->epnum
);
1211 /* EP0 reserved endpoint for control, bidirectional;
1212 * EP1 reserved for bulk, two unidirection halves.
1214 if (hw_ep
->epnum
== 1)
1215 musb
->bulk_ep
= hw_ep
;
1216 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1217 switch (cfg
->style
) {
1219 musb_write_txfifosz(mbase
, c_size
);
1220 musb_write_txfifoadd(mbase
, c_off
);
1221 hw_ep
->tx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1222 hw_ep
->max_packet_sz_tx
= maxpacket
;
1225 musb_write_rxfifosz(mbase
, c_size
);
1226 musb_write_rxfifoadd(mbase
, c_off
);
1227 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1228 hw_ep
->max_packet_sz_rx
= maxpacket
;
1231 musb_write_txfifosz(mbase
, c_size
);
1232 musb_write_txfifoadd(mbase
, c_off
);
1233 hw_ep
->rx_double_buffered
= !!(c_size
& MUSB_FIFOSZ_DPB
);
1234 hw_ep
->max_packet_sz_rx
= maxpacket
;
1236 musb_write_rxfifosz(mbase
, c_size
);
1237 musb_write_rxfifoadd(mbase
, c_off
);
1238 hw_ep
->tx_double_buffered
= hw_ep
->rx_double_buffered
;
1239 hw_ep
->max_packet_sz_tx
= maxpacket
;
1241 hw_ep
->is_shared_fifo
= true;
1245 /* NOTE rx and tx endpoint irqs aren't managed separately,
1246 * which happens to be ok
1248 musb
->epmask
|= (1 << hw_ep
->epnum
);
1250 return offset
+ (maxpacket
<< ((c_size
& MUSB_FIFOSZ_DPB
) ? 1 : 0));
1253 static struct musb_fifo_cfg __devinitdata ep0_cfg
= {
1254 .style
= FIFO_RXTX
, .maxpacket
= 64,
1257 static int __devinit
ep_config_from_table(struct musb
*musb
)
1259 const struct musb_fifo_cfg
*cfg
;
1262 struct musb_hw_ep
*hw_ep
= musb
->endpoints
;
1264 if (musb
->config
->fifo_cfg
) {
1265 cfg
= musb
->config
->fifo_cfg
;
1266 n
= musb
->config
->fifo_cfg_size
;
1270 switch (fifo_mode
) {
1276 n
= ARRAY_SIZE(mode_0_cfg
);
1280 n
= ARRAY_SIZE(mode_1_cfg
);
1284 n
= ARRAY_SIZE(mode_2_cfg
);
1288 n
= ARRAY_SIZE(mode_3_cfg
);
1292 n
= ARRAY_SIZE(mode_4_cfg
);
1296 n
= ARRAY_SIZE(mode_5_cfg
);
1300 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name
, fifo_mode
);
1303 offset
= fifo_setup(musb
, hw_ep
, &ep0_cfg
, 0);
1304 /* assert(offset > 0) */
1306 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1307 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1310 for (i
= 0; i
< n
; i
++) {
1311 u8 epn
= cfg
->hw_ep_num
;
1313 if (epn
>= musb
->config
->num_eps
) {
1314 pr_debug("%s: invalid ep %d\n",
1315 musb_driver_name
, epn
);
1318 offset
= fifo_setup(musb
, hw_ep
+ epn
, cfg
++, offset
);
1320 pr_debug("%s: mem overrun, ep %d\n",
1321 musb_driver_name
, epn
);
1325 musb
->nr_endpoints
= max(epn
, musb
->nr_endpoints
);
1328 pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name
, n
+ 1,
1329 musb
->config
->num_eps
* 2 - 1, offset
,
1330 (1 << (musb
->config
->ram_bits
+ 2)));
1332 if (!musb
->bulk_ep
) {
1333 pr_debug("%s: missing bulk\n", musb_driver_name
);
1342 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1343 * @param musb the controller
1345 static int __devinit
ep_config_from_hw(struct musb
*musb
)
1348 struct musb_hw_ep
*hw_ep
;
1349 void *mbase
= musb
->mregs
;
1352 dev_dbg(musb
->controller
, "<== static silicon ep config\n");
1354 /* FIXME pick up ep0 maxpacket size */
1356 for (epnum
= 1; epnum
< musb
->config
->num_eps
; epnum
++) {
1357 musb_ep_select(mbase
, epnum
);
1358 hw_ep
= musb
->endpoints
+ epnum
;
1360 ret
= musb_read_fifosize(musb
, hw_ep
, epnum
);
1364 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1366 /* pick an RX/TX endpoint for bulk */
1367 if (hw_ep
->max_packet_sz_tx
< 512
1368 || hw_ep
->max_packet_sz_rx
< 512)
1371 /* REVISIT: this algorithm is lazy, we should at least
1372 * try to pick a double buffered endpoint.
1376 musb
->bulk_ep
= hw_ep
;
1379 if (!musb
->bulk_ep
) {
1380 pr_debug("%s: missing bulk\n", musb_driver_name
);
1387 enum { MUSB_CONTROLLER_MHDRC
, MUSB_CONTROLLER_HDRC
, };
1389 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1390 * configure endpoints, or take their config from silicon
1392 static int __devinit
musb_core_init(u16 musb_type
, struct musb
*musb
)
1396 char aInfo
[90], aRevision
[32], aDate
[12];
1397 void __iomem
*mbase
= musb
->mregs
;
1401 /* log core options (read using indexed model) */
1402 reg
= musb_read_configdata(mbase
);
1404 strcpy(aInfo
, (reg
& MUSB_CONFIGDATA_UTMIDW
) ? "UTMI-16" : "UTMI-8");
1405 if (reg
& MUSB_CONFIGDATA_DYNFIFO
) {
1406 strcat(aInfo
, ", dyn FIFOs");
1407 musb
->dyn_fifo
= true;
1409 #ifndef CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
1410 if (reg
& MUSB_CONFIGDATA_MPRXE
) {
1411 strcat(aInfo
, ", bulk combine");
1412 musb
->bulk_combine
= true;
1414 if (reg
& MUSB_CONFIGDATA_MPTXE
) {
1415 strcat(aInfo
, ", bulk split");
1416 musb
->bulk_split
= true;
1419 musb
->bulk_combine
= false;
1420 musb
->bulk_split
= false;
1422 if (reg
& MUSB_CONFIGDATA_HBRXE
) {
1423 strcat(aInfo
, ", HB-ISO Rx");
1424 musb
->hb_iso_rx
= true;
1426 if (reg
& MUSB_CONFIGDATA_HBTXE
) {
1427 strcat(aInfo
, ", HB-ISO Tx");
1428 musb
->hb_iso_tx
= true;
1430 if (reg
& MUSB_CONFIGDATA_SOFTCONE
)
1431 strcat(aInfo
, ", SoftConn");
1433 pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name
, reg
, aInfo
);
1436 if (MUSB_CONTROLLER_MHDRC
== musb_type
) {
1437 musb
->is_multipoint
= 1;
1440 musb
->is_multipoint
= 0;
1442 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1444 "%s: kernel must blacklist external hubs\n",
1449 /* log release info */
1450 musb
->hwvers
= musb_read_hwvers(mbase
);
1451 snprintf(aRevision
, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb
->hwvers
),
1452 MUSB_HWVERS_MINOR(musb
->hwvers
),
1453 (musb
->hwvers
& MUSB_HWVERS_RC
) ? "RC" : "");
1454 pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name
, type
,
1458 musb_configure_ep0(musb
);
1460 /* discover endpoint configuration */
1461 musb
->nr_endpoints
= 1;
1465 status
= ep_config_from_table(musb
);
1467 status
= ep_config_from_hw(musb
);
1472 /* finish init, and print endpoint config */
1473 for (i
= 0; i
< musb
->nr_endpoints
; i
++) {
1474 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ i
;
1476 hw_ep
->fifo
= MUSB_FIFO_OFFSET(i
) + mbase
;
1477 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1478 hw_ep
->fifo_async
= musb
->async
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1479 hw_ep
->fifo_sync
= musb
->sync
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1480 hw_ep
->fifo_sync_va
=
1481 musb
->sync_va
+ 0x400 + MUSB_FIFO_OFFSET(i
);
1484 hw_ep
->conf
= mbase
- 0x400 + TUSB_EP0_CONF
;
1486 hw_ep
->conf
= mbase
+ 0x400 + (((i
- 1) & 0xf) << 2);
1489 hw_ep
->regs
= MUSB_EP_OFFSET(i
, 0) + mbase
;
1490 hw_ep
->target_regs
= musb_read_target_reg_base(i
, mbase
);
1491 hw_ep
->rx_reinit
= 1;
1492 hw_ep
->tx_reinit
= 1;
1494 if (hw_ep
->max_packet_sz_tx
) {
1495 dev_dbg(musb
->controller
,
1496 "%s: hw_ep %d%s, %smax %d\n",
1497 musb_driver_name
, i
,
1498 hw_ep
->is_shared_fifo
? "shared" : "tx",
1499 hw_ep
->tx_double_buffered
1500 ? "doublebuffer, " : "",
1501 hw_ep
->max_packet_sz_tx
);
1503 if (hw_ep
->max_packet_sz_rx
&& !hw_ep
->is_shared_fifo
) {
1504 dev_dbg(musb
->controller
,
1505 "%s: hw_ep %d%s, %smax %d\n",
1506 musb_driver_name
, i
,
1508 hw_ep
->rx_double_buffered
1509 ? "doublebuffer, " : "",
1510 hw_ep
->max_packet_sz_rx
);
1512 if (!(hw_ep
->max_packet_sz_tx
|| hw_ep
->max_packet_sz_rx
))
1513 dev_dbg(musb
->controller
, "hw_ep %d not configured\n", i
);
1519 /*-------------------------------------------------------------------------*/
1521 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1522 defined(CONFIG_ARCH_OMAP4)
1524 static irqreturn_t
generic_interrupt(int irq
, void *__hci
)
1526 unsigned long flags
;
1527 irqreturn_t retval
= IRQ_NONE
;
1528 struct musb
*musb
= __hci
;
1530 spin_lock_irqsave(&musb
->lock
, flags
);
1532 musb
->int_usb
= musb_readb(musb
->mregs
, MUSB_INTRUSB
);
1533 musb
->int_tx
= musb_readw(musb
->mregs
, MUSB_INTRTX
);
1534 musb
->int_rx
= musb_readw(musb
->mregs
, MUSB_INTRRX
);
1536 if (musb
->int_usb
|| musb
->int_tx
|| musb
->int_rx
)
1537 retval
= musb_interrupt(musb
);
1539 spin_unlock_irqrestore(&musb
->lock
, flags
);
1545 #define generic_interrupt NULL
1549 * handle all the irqs defined by the HDRC core. for now we expect: other
1550 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1551 * will be assigned, and the irq will already have been acked.
1553 * called in irq context with spinlock held, irqs blocked
1555 irqreturn_t
musb_interrupt(struct musb
*musb
)
1557 irqreturn_t retval
= IRQ_NONE
;
1562 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1563 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1565 dev_dbg(musb
->controller
, "** IRQ %s usb%04x tx%04x rx%04x\n",
1566 (devctl
& MUSB_DEVCTL_HM
) ? "host" : "peripheral",
1567 musb
->int_usb
, musb
->int_tx
, musb
->int_rx
);
1569 /* the core can interrupt us for multiple reasons; docs have
1570 * a generic interrupt flowchart to follow
1573 retval
|= musb_stage0_irq(musb
, musb
->int_usb
,
1576 /* "stage 1" is handling endpoint irqs */
1578 /* handle endpoint 0 first */
1579 if (musb
->int_tx
& 1) {
1580 if (devctl
& MUSB_DEVCTL_HM
) {
1581 if (is_host_capable())
1582 retval
|= musb_h_ep0_irq(musb
);
1584 if (is_peripheral_capable())
1585 retval
|= musb_g_ep0_irq(musb
);
1589 /* RX on endpoints 1-15 */
1590 reg
= musb
->int_rx
>> 1;
1594 /* musb_ep_select(musb->mregs, ep_num); */
1595 /* REVISIT just retval = ep->rx_irq(...) */
1596 retval
= IRQ_HANDLED
;
1597 if (devctl
& MUSB_DEVCTL_HM
) {
1598 if (is_host_capable())
1599 musb_host_rx(musb
, ep_num
);
1601 if (is_peripheral_capable())
1602 musb_g_rx(musb
, ep_num
);
1610 /* TX on endpoints 1-15 */
1611 reg
= musb
->int_tx
>> 1;
1615 /* musb_ep_select(musb->mregs, ep_num); */
1616 /* REVISIT just retval |= ep->tx_irq(...) */
1617 retval
= IRQ_HANDLED
;
1618 if (devctl
& MUSB_DEVCTL_HM
) {
1619 if (is_host_capable())
1620 musb_host_tx(musb
, ep_num
);
1622 if (is_peripheral_capable())
1623 musb_g_tx(musb
, ep_num
);
1632 EXPORT_SYMBOL_GPL(musb_interrupt
);
1634 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1635 static bool __devinitdata use_dma
= 1;
1637 /* "modprobe ... use_dma=0" etc */
1638 module_param(use_dma
, bool, 0);
1639 MODULE_PARM_DESC(use_dma
, "enable/disable use of DMA");
1641 void musb_dma_completion(struct musb
*musb
, u8 epnum
, u8 transmit
)
1643 u8 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1645 /* called with controller lock already held */
1648 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1649 if (!is_cppi_enabled()) {
1651 if (devctl
& MUSB_DEVCTL_HM
)
1652 musb_h_ep0_irq(musb
);
1654 musb_g_ep0_irq(musb
);
1658 /* endpoints 1..15 */
1660 if (devctl
& MUSB_DEVCTL_HM
) {
1661 if (is_host_capable())
1662 musb_host_tx(musb
, epnum
);
1664 if (is_peripheral_capable())
1665 musb_g_tx(musb
, epnum
);
1669 if (devctl
& MUSB_DEVCTL_HM
) {
1670 if (is_host_capable())
1671 musb_host_rx(musb
, epnum
);
1673 if (is_peripheral_capable())
1674 musb_g_rx(musb
, epnum
);
1679 EXPORT_SYMBOL_GPL(musb_dma_completion
);
1685 /*-------------------------------------------------------------------------*/
1690 musb_mode_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1692 struct musb
*musb
= dev_to_musb(dev
);
1693 unsigned long flags
;
1696 spin_lock_irqsave(&musb
->lock
, flags
);
1697 ret
= sprintf(buf
, "%s\n", otg_state_string(musb
->xceiv
->state
));
1698 spin_unlock_irqrestore(&musb
->lock
, flags
);
1704 musb_mode_store(struct device
*dev
, struct device_attribute
*attr
,
1705 const char *buf
, size_t n
)
1707 struct musb
*musb
= dev_to_musb(dev
);
1708 unsigned long flags
;
1711 spin_lock_irqsave(&musb
->lock
, flags
);
1712 if (sysfs_streq(buf
, "host"))
1713 status
= musb_platform_set_mode(musb
, MUSB_HOST
);
1714 else if (sysfs_streq(buf
, "peripheral"))
1715 status
= musb_platform_set_mode(musb
, MUSB_PERIPHERAL
);
1716 else if (sysfs_streq(buf
, "otg"))
1717 status
= musb_platform_set_mode(musb
, MUSB_OTG
);
1720 spin_unlock_irqrestore(&musb
->lock
, flags
);
1722 return (status
== 0) ? n
: status
;
1724 static DEVICE_ATTR(mode
, 0644, musb_mode_show
, musb_mode_store
);
1727 musb_vbus_store(struct device
*dev
, struct device_attribute
*attr
,
1728 const char *buf
, size_t n
)
1730 struct musb
*musb
= dev_to_musb(dev
);
1731 unsigned long flags
;
1734 if (sscanf(buf
, "%lu", &val
) < 1) {
1735 dev_err(dev
, "Invalid VBUS timeout ms value\n");
1739 spin_lock_irqsave(&musb
->lock
, flags
);
1740 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1741 musb
->a_wait_bcon
= val
? max_t(int, val
, OTG_TIME_A_WAIT_BCON
) : 0 ;
1742 if (musb
->xceiv
->state
== OTG_STATE_A_WAIT_BCON
)
1743 musb
->is_active
= 0;
1744 musb_platform_try_idle(musb
, jiffies
+ msecs_to_jiffies(val
));
1745 spin_unlock_irqrestore(&musb
->lock
, flags
);
1751 musb_vbus_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
1753 struct musb
*musb
= dev_to_musb(dev
);
1754 unsigned long flags
;
1758 spin_lock_irqsave(&musb
->lock
, flags
);
1759 val
= musb
->a_wait_bcon
;
1760 /* FIXME get_vbus_status() is normally #defined as false...
1761 * and is effectively TUSB-specific.
1763 vbus
= musb_platform_get_vbus_status(musb
);
1764 spin_unlock_irqrestore(&musb
->lock
, flags
);
1766 return sprintf(buf
, "Vbus %s, timeout %lu msec\n",
1767 vbus
? "on" : "off", val
);
1769 static DEVICE_ATTR(vbus
, 0644, musb_vbus_show
, musb_vbus_store
);
1771 /* Gadget drivers can't know that a host is connected so they might want
1772 * to start SRP, but users can. This allows userspace to trigger SRP.
1775 musb_srp_store(struct device
*dev
, struct device_attribute
*attr
,
1776 const char *buf
, size_t n
)
1778 struct musb
*musb
= dev_to_musb(dev
);
1781 if (sscanf(buf
, "%hu", &srp
) != 1
1783 dev_err(dev
, "SRP: Value must be 1\n");
1788 musb_g_wakeup(musb
);
1792 static DEVICE_ATTR(srp
, 0644, NULL
, musb_srp_store
);
1794 static struct attribute
*musb_attributes
[] = {
1795 &dev_attr_mode
.attr
,
1796 &dev_attr_vbus
.attr
,
1801 static const struct attribute_group musb_attr_group
= {
1802 .attrs
= musb_attributes
,
1808 /* Only used to provide driver mode change events */
1809 static void musb_irq_work(struct work_struct
*data
)
1811 struct musb
*musb
= container_of(data
, struct musb
, irq_work
);
1812 static int old_state
;
1814 if (musb
->xceiv
->state
!= old_state
) {
1815 old_state
= musb
->xceiv
->state
;
1816 sysfs_notify(&musb
->controller
->kobj
, NULL
, "mode");
1821 /* --------------------------------------------------------------------------
1825 static struct musb
*__devinit
1826 allocate_instance(struct device
*dev
,
1827 struct musb_hdrc_config
*config
, void __iomem
*mbase
)
1830 struct musb_hw_ep
*ep
;
1833 struct usb_hcd
*hcd
;
1835 hcd
= usb_create_hcd(&musb_hc_driver
, dev
, dev_name(dev
));
1838 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1840 musb
= hcd_to_musb(hcd
);
1842 musb
= calloc(1, sizeof(*musb
));
1846 INIT_LIST_HEAD(&musb
->control
);
1847 INIT_LIST_HEAD(&musb
->in_bulk
);
1848 INIT_LIST_HEAD(&musb
->out_bulk
);
1851 hcd
->uses_new_polling
= 1;
1855 musb
->vbuserr_retry
= VBUSERR_RETRY_COUNT
;
1856 musb
->a_wait_bcon
= OTG_TIME_A_WAIT_BCON
;
1857 dev_set_drvdata(dev
, musb
);
1858 musb
->mregs
= mbase
;
1859 musb
->ctrl_base
= mbase
;
1860 musb
->nIrq
= -ENODEV
;
1861 musb
->config
= config
;
1862 BUG_ON(musb
->config
->num_eps
> MUSB_C_NUM_EPS
);
1863 for (epnum
= 0, ep
= musb
->endpoints
;
1864 epnum
< musb
->config
->num_eps
;
1870 musb
->controller
= dev
;
1875 static void musb_free(struct musb
*musb
)
1877 /* this has multiple entry modes. it handles fault cleanup after
1878 * probe(), where things may be partially set up, as well as rmmod
1879 * cleanup after everything's been de-activated.
1883 sysfs_remove_group(&musb
->controller
->kobj
, &musb_attr_group
);
1886 if (musb
->nIrq
>= 0) {
1888 disable_irq_wake(musb
->nIrq
);
1889 free_irq(musb
->nIrq
, musb
);
1891 if (is_dma_capable() && musb
->dma_controller
) {
1892 struct dma_controller
*c
= musb
->dma_controller
;
1895 dma_controller_destroy(c
);
1902 * Perform generic per-controller initialization.
1904 * @pDevice: the controller (already clocked, etc)
1906 * @mregs: virtual address of controller registers,
1907 * not yet corrected for platform-specific offsets
1910 static int __devinit
1911 musb_init_controller(struct device
*dev
, int nIrq
, void __iomem
*ctrl
)
1914 musb_init_controller(struct musb_hdrc_platform_data
*plat
, struct device
*dev
,
1921 struct musb_hdrc_platform_data
*plat
= dev
->platform_data
;
1926 /* The driver might handle more features than the board; OK.
1927 * Fail when the board needs a feature that's not enabled.
1930 dev_dbg(dev
, "no platform_data?\n");
1936 musb
= allocate_instance(dev
, plat
->config
, ctrl
);
1942 pm_runtime_use_autosuspend(musb
->controller
);
1943 pm_runtime_set_autosuspend_delay(musb
->controller
, 200);
1944 pm_runtime_enable(musb
->controller
);
1946 spin_lock_init(&musb
->lock
);
1947 musb
->board_mode
= plat
->mode
;
1948 musb
->board_set_power
= plat
->set_power
;
1949 musb
->min_power
= plat
->min_power
;
1950 musb
->ops
= plat
->platform_ops
;
1952 /* The musb_platform_init() call:
1953 * - adjusts musb->mregs and musb->isr if needed,
1954 * - may initialize an integrated tranceiver
1955 * - initializes musb->xceiv, usually by otg_get_phy()
1956 * - stops powering VBUS
1958 * There are various transceiver configurations. Blackfin,
1959 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1960 * external/discrete ones in various flavors (twl4030 family,
1961 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1963 musb
->isr
= generic_interrupt
;
1964 status
= musb_platform_init(musb
);
1974 if (!musb
->xceiv
->io_ops
) {
1975 musb
->xceiv
->io_dev
= musb
->controller
;
1976 musb
->xceiv
->io_priv
= musb
->mregs
;
1977 musb
->xceiv
->io_ops
= &musb_ulpi_access
;
1981 pm_runtime_get_sync(musb
->controller
);
1983 #ifndef CONFIG_USB_MUSB_PIO_ONLY
1984 if (use_dma
&& dev
->dma_mask
) {
1985 struct dma_controller
*c
;
1987 c
= dma_controller_create(musb
, musb
->mregs
);
1988 musb
->dma_controller
= c
;
1994 /* ideally this would be abstracted in platform setup */
1995 if (!is_dma_capable() || !musb
->dma_controller
)
1996 dev
->dma_mask
= NULL
;
1999 /* be sure interrupts are disabled before connecting ISR */
2000 musb_platform_disable(musb
);
2001 musb_generic_disable(musb
);
2003 /* setup musb parts of the core (especially endpoints) */
2004 status
= musb_core_init(plat
->config
->multipoint
2005 ? MUSB_CONTROLLER_MHDRC
2006 : MUSB_CONTROLLER_HDRC
, musb
);
2010 setup_timer(&musb
->otg_timer
, musb_otg_timer_func
, (unsigned long) musb
);
2012 /* Init IRQ workqueue before request_irq */
2013 INIT_WORK(&musb
->irq_work
, musb_irq_work
);
2015 /* attach to the IRQ */
2016 if (request_irq(nIrq
, musb
->isr
, 0, dev_name(dev
), musb
)) {
2017 dev_err(dev
, "request_irq %d failed!\n", nIrq
);
2022 /* FIXME this handles wakeup irqs wrong */
2023 if (enable_irq_wake(nIrq
) == 0) {
2025 device_init_wakeup(dev
, 1);
2031 /* host side needs more setup */
2032 if (is_host_enabled(musb
)) {
2033 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
2035 otg_set_host(musb
->xceiv
->otg
, &hcd
->self
);
2037 if (is_otg_enabled(musb
))
2038 hcd
->self
.otg_port
= 1;
2039 musb
->xceiv
->otg
->host
= &hcd
->self
;
2040 hcd
->power_budget
= 2 * (plat
->power
? : 250);
2042 /* program PHY to use external vBus if required */
2043 if (plat
->extvbus
) {
2044 u8 busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2045 busctl
|= MUSB_ULPI_USE_EXTVBUS
;
2046 musb_write_ulpi_buscontrol(musb
->mregs
, busctl
);
2051 /* For the host-only role, we can activate right away.
2052 * (We expect the ID pin to be forcibly grounded!!)
2053 * Otherwise, wait till the gadget driver hooks up.
2055 if (!is_otg_enabled(musb
) && is_host_enabled(musb
)) {
2056 struct usb_hcd
*hcd
= musb_to_hcd(musb
);
2058 MUSB_HST_MODE(musb
);
2060 musb
->xceiv
->otg
->default_a
= 1;
2061 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2063 status
= usb_add_hcd(musb_to_hcd(musb
), 0, 0);
2065 hcd
->self
.uses_pio_for_control
= 1;
2066 dev_dbg(musb
->controller
, "%s mode, status %d, devctl %02x %c\n",
2068 musb_readb(musb
->mregs
, MUSB_DEVCTL
),
2069 (musb_readb(musb
->mregs
, MUSB_DEVCTL
)
2070 & MUSB_DEVCTL_BDEVICE
2074 } else /* peripheral is enabled */ {
2075 MUSB_DEV_MODE(musb
);
2077 musb
->xceiv
->otg
->default_a
= 0;
2078 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2081 if (is_peripheral_capable())
2082 status
= musb_gadget_setup(musb
);
2085 dev_dbg(musb
->controller
, "%s mode, status %d, dev%02x\n",
2086 is_otg_enabled(musb
) ? "OTG" : "PERIPHERAL",
2088 musb_readb(musb
->mregs
, MUSB_DEVCTL
));
2095 status
= musb_init_debugfs(musb
);
2100 status
= sysfs_create_group(&musb
->controller
->kobj
, &musb_attr_group
);
2105 pm_runtime_put(musb
->controller
);
2107 pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
2109 switch (musb
->board_mode
) {
2110 case MUSB_HOST
: s
= "Host"; break;
2111 case MUSB_PERIPHERAL
: s
= "Peripheral"; break;
2112 default: s
= "OTG"; break;
2115 (is_dma_capable() && musb
->dma_controller
)
2122 return status
== 0 ? musb
: NULL
;
2126 musb_exit_debugfs(musb
);
2130 if (!is_otg_enabled(musb
) && is_host_enabled(musb
))
2131 usb_remove_hcd(musb_to_hcd(musb
));
2134 musb_gadget_cleanup(musb
);
2137 pm_runtime_put_sync(musb
->controller
);
2141 device_init_wakeup(dev
, 0);
2142 musb_platform_exit(musb
);
2145 dev_err(musb
->controller
,
2146 "musb_init_controller failed with status %d\n", status
);
2155 return status
== 0 ? musb
: NULL
;
2160 /*-------------------------------------------------------------------------*/
2162 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2163 * bridge to a platform device; this driver then suffices.
2166 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2167 static u64
*orig_dma_mask
;
2171 static int __devinit
musb_probe(struct platform_device
*pdev
)
2173 struct device
*dev
= &pdev
->dev
;
2174 int irq
= platform_get_irq_byname(pdev
, "mc");
2176 struct resource
*iomem
;
2179 iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2180 if (!iomem
|| irq
<= 0)
2183 base
= ioremap(iomem
->start
, resource_size(iomem
));
2185 dev_err(dev
, "ioremap failed\n");
2189 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2190 /* clobbered by use_dma=n */
2191 orig_dma_mask
= dev
->dma_mask
;
2193 status
= musb_init_controller(dev
, irq
, base
);
2200 static int __devexit
musb_remove(struct platform_device
*pdev
)
2202 struct musb
*musb
= dev_to_musb(&pdev
->dev
);
2203 void __iomem
*ctrl_base
= musb
->ctrl_base
;
2205 /* this gets called on rmmod.
2206 * - Host mode: host may still be active
2207 * - Peripheral mode: peripheral is deactivated (or never-activated)
2208 * - OTG mode: both roles are deactivated (or never-activated)
2210 musb_exit_debugfs(musb
);
2211 musb_shutdown(pdev
);
2215 device_init_wakeup(&pdev
->dev
, 0);
2216 #ifndef CONFIG_USB_MUSB_PIO_ONLY
2217 pdev
->dev
.dma_mask
= orig_dma_mask
;
2224 static void musb_save_context(struct musb
*musb
)
2227 void __iomem
*musb_base
= musb
->mregs
;
2230 if (is_host_enabled(musb
)) {
2231 musb
->context
.frame
= musb_readw(musb_base
, MUSB_FRAME
);
2232 musb
->context
.testmode
= musb_readb(musb_base
, MUSB_TESTMODE
);
2233 musb
->context
.busctl
= musb_read_ulpi_buscontrol(musb
->mregs
);
2235 musb
->context
.power
= musb_readb(musb_base
, MUSB_POWER
);
2236 musb
->context
.intrtxe
= musb_readw(musb_base
, MUSB_INTRTXE
);
2237 musb
->context
.intrrxe
= musb_readw(musb_base
, MUSB_INTRRXE
);
2238 musb
->context
.intrusbe
= musb_readb(musb_base
, MUSB_INTRUSBE
);
2239 musb
->context
.index
= musb_readb(musb_base
, MUSB_INDEX
);
2240 musb
->context
.devctl
= musb_readb(musb_base
, MUSB_DEVCTL
);
2242 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2243 struct musb_hw_ep
*hw_ep
;
2245 hw_ep
= &musb
->endpoints
[i
];
2253 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2254 musb
->context
.index_regs
[i
].txmaxp
=
2255 musb_readw(epio
, MUSB_TXMAXP
);
2256 musb
->context
.index_regs
[i
].txcsr
=
2257 musb_readw(epio
, MUSB_TXCSR
);
2258 musb
->context
.index_regs
[i
].rxmaxp
=
2259 musb_readw(epio
, MUSB_RXMAXP
);
2260 musb
->context
.index_regs
[i
].rxcsr
=
2261 musb_readw(epio
, MUSB_RXCSR
);
2263 if (musb
->dyn_fifo
) {
2264 musb
->context
.index_regs
[i
].txfifoadd
=
2265 musb_read_txfifoadd(musb_base
);
2266 musb
->context
.index_regs
[i
].rxfifoadd
=
2267 musb_read_rxfifoadd(musb_base
);
2268 musb
->context
.index_regs
[i
].txfifosz
=
2269 musb_read_txfifosz(musb_base
);
2270 musb
->context
.index_regs
[i
].rxfifosz
=
2271 musb_read_rxfifosz(musb_base
);
2273 if (is_host_enabled(musb
)) {
2274 musb
->context
.index_regs
[i
].txtype
=
2275 musb_readb(epio
, MUSB_TXTYPE
);
2276 musb
->context
.index_regs
[i
].txinterval
=
2277 musb_readb(epio
, MUSB_TXINTERVAL
);
2278 musb
->context
.index_regs
[i
].rxtype
=
2279 musb_readb(epio
, MUSB_RXTYPE
);
2280 musb
->context
.index_regs
[i
].rxinterval
=
2281 musb_readb(epio
, MUSB_RXINTERVAL
);
2283 musb
->context
.index_regs
[i
].txfunaddr
=
2284 musb_read_txfunaddr(musb_base
, i
);
2285 musb
->context
.index_regs
[i
].txhubaddr
=
2286 musb_read_txhubaddr(musb_base
, i
);
2287 musb
->context
.index_regs
[i
].txhubport
=
2288 musb_read_txhubport(musb_base
, i
);
2290 musb
->context
.index_regs
[i
].rxfunaddr
=
2291 musb_read_rxfunaddr(musb_base
, i
);
2292 musb
->context
.index_regs
[i
].rxhubaddr
=
2293 musb_read_rxhubaddr(musb_base
, i
);
2294 musb
->context
.index_regs
[i
].rxhubport
=
2295 musb_read_rxhubport(musb_base
, i
);
2300 static void musb_restore_context(struct musb
*musb
)
2303 void __iomem
*musb_base
= musb
->mregs
;
2304 void __iomem
*ep_target_regs
;
2307 if (is_host_enabled(musb
)) {
2308 musb_writew(musb_base
, MUSB_FRAME
, musb
->context
.frame
);
2309 musb_writeb(musb_base
, MUSB_TESTMODE
, musb
->context
.testmode
);
2310 musb_write_ulpi_buscontrol(musb
->mregs
, musb
->context
.busctl
);
2312 musb_writeb(musb_base
, MUSB_POWER
, musb
->context
.power
);
2313 musb_writew(musb_base
, MUSB_INTRTXE
, musb
->context
.intrtxe
);
2314 musb_writew(musb_base
, MUSB_INTRRXE
, musb
->context
.intrrxe
);
2315 musb_writeb(musb_base
, MUSB_INTRUSBE
, musb
->context
.intrusbe
);
2316 musb_writeb(musb_base
, MUSB_DEVCTL
, musb
->context
.devctl
);
2318 for (i
= 0; i
< musb
->config
->num_eps
; ++i
) {
2319 struct musb_hw_ep
*hw_ep
;
2321 hw_ep
= &musb
->endpoints
[i
];
2329 musb_writeb(musb_base
, MUSB_INDEX
, i
);
2330 musb_writew(epio
, MUSB_TXMAXP
,
2331 musb
->context
.index_regs
[i
].txmaxp
);
2332 musb_writew(epio
, MUSB_TXCSR
,
2333 musb
->context
.index_regs
[i
].txcsr
);
2334 musb_writew(epio
, MUSB_RXMAXP
,
2335 musb
->context
.index_regs
[i
].rxmaxp
);
2336 musb_writew(epio
, MUSB_RXCSR
,
2337 musb
->context
.index_regs
[i
].rxcsr
);
2339 if (musb
->dyn_fifo
) {
2340 musb_write_txfifosz(musb_base
,
2341 musb
->context
.index_regs
[i
].txfifosz
);
2342 musb_write_rxfifosz(musb_base
,
2343 musb
->context
.index_regs
[i
].rxfifosz
);
2344 musb_write_txfifoadd(musb_base
,
2345 musb
->context
.index_regs
[i
].txfifoadd
);
2346 musb_write_rxfifoadd(musb_base
,
2347 musb
->context
.index_regs
[i
].rxfifoadd
);
2350 if (is_host_enabled(musb
)) {
2351 musb_writeb(epio
, MUSB_TXTYPE
,
2352 musb
->context
.index_regs
[i
].txtype
);
2353 musb_writeb(epio
, MUSB_TXINTERVAL
,
2354 musb
->context
.index_regs
[i
].txinterval
);
2355 musb_writeb(epio
, MUSB_RXTYPE
,
2356 musb
->context
.index_regs
[i
].rxtype
);
2357 musb_writeb(epio
, MUSB_RXINTERVAL
,
2359 musb
->context
.index_regs
[i
].rxinterval
);
2360 musb_write_txfunaddr(musb_base
, i
,
2361 musb
->context
.index_regs
[i
].txfunaddr
);
2362 musb_write_txhubaddr(musb_base
, i
,
2363 musb
->context
.index_regs
[i
].txhubaddr
);
2364 musb_write_txhubport(musb_base
, i
,
2365 musb
->context
.index_regs
[i
].txhubport
);
2368 musb_read_target_reg_base(i
, musb_base
);
2370 musb_write_rxfunaddr(ep_target_regs
,
2371 musb
->context
.index_regs
[i
].rxfunaddr
);
2372 musb_write_rxhubaddr(ep_target_regs
,
2373 musb
->context
.index_regs
[i
].rxhubaddr
);
2374 musb_write_rxhubport(ep_target_regs
,
2375 musb
->context
.index_regs
[i
].rxhubport
);
2378 musb_writeb(musb_base
, MUSB_INDEX
, musb
->context
.index
);
2381 static int musb_suspend(struct device
*dev
)
2383 struct musb
*musb
= dev_to_musb(dev
);
2384 unsigned long flags
;
2386 spin_lock_irqsave(&musb
->lock
, flags
);
2388 if (is_peripheral_active(musb
)) {
2389 /* FIXME force disconnect unless we know USB will wake
2390 * the system up quickly enough to respond ...
2392 } else if (is_host_active(musb
)) {
2393 /* we know all the children are suspended; sometimes
2394 * they will even be wakeup-enabled.
2398 spin_unlock_irqrestore(&musb
->lock
, flags
);
2402 static int musb_resume_noirq(struct device
*dev
)
2404 /* for static cmos like DaVinci, register values were preserved
2405 * unless for some reason the whole soc powered down or the USB
2406 * module got reset through the PSC (vs just being disabled).
2411 static int musb_runtime_suspend(struct device
*dev
)
2413 struct musb
*musb
= dev_to_musb(dev
);
2415 musb_save_context(musb
);
2420 static int musb_runtime_resume(struct device
*dev
)
2422 struct musb
*musb
= dev_to_musb(dev
);
2423 static int first
= 1;
2426 * When pm_runtime_get_sync called for the first time in driver
2427 * init, some of the structure is still not initialized which is
2428 * used in restore function. But clock needs to be
2429 * enabled before any register access, so
2430 * pm_runtime_get_sync has to be called.
2431 * Also context restore without save does not make
2435 musb_restore_context(musb
);
2441 static const struct dev_pm_ops musb_dev_pm_ops
= {
2442 .suspend
= musb_suspend
,
2443 .resume_noirq
= musb_resume_noirq
,
2444 .runtime_suspend
= musb_runtime_suspend
,
2445 .runtime_resume
= musb_runtime_resume
,
2448 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2450 #define MUSB_DEV_PM_OPS NULL
2453 static struct platform_driver musb_driver
= {
2455 .name
= (char *)musb_driver_name
,
2456 .bus
= &platform_bus_type
,
2457 .owner
= THIS_MODULE
,
2458 .pm
= MUSB_DEV_PM_OPS
,
2460 .probe
= musb_probe
,
2461 .remove
= __devexit_p(musb_remove
),
2462 .shutdown
= musb_shutdown
,
2465 /*-------------------------------------------------------------------------*/
2467 static int __init
musb_init(void)
2472 pr_info("%s: version " MUSB_VERSION
", "
2475 "otg (peripheral+host)",
2477 return platform_driver_register(&musb_driver
);
2479 module_init(musb_init
);
2481 static void __exit
musb_cleanup(void)
2483 platform_driver_unregister(&musb_driver
);
2485 module_exit(musb_cleanup
);