1 // SPDX-License-Identifier: GPL-2.0
3 * UCSI driver for Cypress CCGx Type-C controller
5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
8 * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
10 #include <linux/acpi.h>
11 #include <linux/delay.h>
12 #include <linux/firmware.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
20 #include <asm/unaligned.h>
24 BOOT
, /* bootloader */
25 FW1
, /* FW partition-1 (contains secondary fw) */
26 FW2
, /* FW partition-2 (contains primary fw) */
30 #define CCGX_RAB_DEVICE_MODE 0x0000
31 #define CCGX_RAB_INTR_REG 0x0006
32 #define DEV_INT BIT(0)
33 #define PORT0_INT BIT(1)
34 #define PORT1_INT BIT(2)
35 #define UCSI_READ_INT BIT(7)
36 #define CCGX_RAB_JUMP_TO_BOOT 0x0007
39 #define CCGX_RAB_RESET_REQ 0x0008
41 #define CMD_RESET_I2C 0x0
42 #define CMD_RESET_DEV 0x1
43 #define CCGX_RAB_ENTER_FLASHING 0x000A
44 #define FLASH_ENTER_SIG 'P'
45 #define CCGX_RAB_VALIDATE_FW 0x000B
46 #define CCGX_RAB_FLASH_ROW_RW 0x000C
48 #define FLASH_RD_CMD 0x0
49 #define FLASH_WR_CMD 0x1
50 #define FLASH_FWCT1_WR_CMD 0x2
51 #define FLASH_FWCT2_WR_CMD 0x3
52 #define FLASH_FWCT_SIG_WR_CMD 0x4
53 #define CCGX_RAB_READ_ALL_VER 0x0010
54 #define CCGX_RAB_READ_FW2_VER 0x0020
55 #define CCGX_RAB_UCSI_CONTROL 0x0039
56 #define CCGX_RAB_UCSI_CONTROL_START BIT(0)
57 #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
58 #define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
59 #define REG_FLASH_RW_MEM 0x0200
60 #define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
61 #define CCGX_RAB_PDPORT_ENABLE 0x002C
62 #define PDPORT_1 BIT(0)
63 #define PDPORT_2 BIT(1)
64 #define CCGX_RAB_RESPONSE 0x007E
65 #define ASYNC_EVENT BIT(7)
67 /* CCGx events & async msg codes */
68 #define RESET_COMPLETE 0x80
69 #define EVENT_INDEX RESET_COMPLETE
70 #define PORT_CONNECT_DET 0x84
71 #define PORT_DISCONNECT_DET 0x85
72 #define ROLE_SWAP_COMPELETE 0x87
75 #define CYACD_LINE_SIZE 527
76 #define CCG4_ROW_SIZE 256
77 #define FW1_METADATA_ROW 0x1FF
78 #define FW2_METADATA_ROW 0x1FE
79 #define FW_CFG_TABLE_SIG_SIZE 256
81 static int secondary_fw_min_ver
= 41;
83 enum enum_flash_mode
{
84 SECONDARY_BL
, /* update secondary using bootloader */
85 PRIMARY
, /* update primary using secondary */
86 SECONDARY
, /* update secondary using primary */
87 FLASH_NOT_NEEDED
, /* update not required */
91 static const char * const ccg_fw_names
[] = {
98 #define CCG_DEVINFO_FWMODE_SHIFT (0)
99 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
100 #define CCG_DEVINFO_PDPORTS_SHIFT (2)
101 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
108 struct version_format
{
112 #define CCG_VERSION_PATCH(x) ((x) << 16)
113 #define CCG_VERSION(x) ((x) << 24)
114 #define CCG_VERSION_MIN_SHIFT (0)
115 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
116 #define CCG_VERSION_MAJ_SHIFT (4)
117 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
121 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
122 * of missing interrupt when a device is connected for runtime resume
124 #define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
125 #define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
127 struct version_info
{
128 struct version_format base
;
129 struct version_format app
;
132 struct fw_config_table
{
138 struct version_format base
;
139 struct version_format app
;
140 u8 primary_fw_digest
[32];
146 /* CCGx response codes */
150 FLASH_DATA_AVAILABLE
= 0x03,
152 FLASH_UPDATE_FAIL
= 0x07,
155 CMD_NOT_SUPPORT
= 0x0A,
156 TRANSACTION_FAIL
= 0x0C,
162 #define CCG_EVENT_MAX (EVENT_INDEX + 43)
168 u32 delay
; /* ms delay for cmd timeout */
180 struct i2c_client
*client
;
181 struct ccg_dev_info info
;
182 /* version info for boot, primary and secondary */
183 struct version_info version
[FW2
+ 1];
185 /* CCG HPI communication flags */
187 #define RESET_PENDING 0
188 #define DEV_CMD_PENDING 1
189 struct ccg_resp dev_resp
;
193 struct work_struct work
;
194 struct mutex lock
; /* to sync between user and driver thread */
196 /* fw build with vendor information */
198 bool run_isr
; /* flag to call ISR routine during resume */
199 struct work_struct pm_work
;
202 static int ccg_read(struct ucsi_ccg
*uc
, u16 rab
, u8
*data
, u32 len
)
204 struct i2c_client
*client
= uc
->client
;
205 const struct i2c_adapter_quirks
*quirks
= client
->adapter
->quirks
;
206 unsigned char buf
[2];
207 struct i2c_msg msgs
[] = {
209 .addr
= client
->addr
,
215 .addr
= client
->addr
,
220 u32 rlen
, rem_len
= len
, max_read_len
= len
;
223 /* check any max_read_len limitation on i2c adapter */
224 if (quirks
&& quirks
->max_read_len
)
225 max_read_len
= quirks
->max_read_len
;
227 if (uc
->fw_build
== CCG_FW_BUILD_NVIDIA
&&
228 uc
->fw_version
<= CCG_OLD_FW_VERSION
) {
229 mutex_lock(&uc
->lock
);
231 * Do not schedule pm_work to run ISR in
232 * ucsi_ccg_runtime_resume() after pm_runtime_get_sync()
233 * since we are already in ISR path.
236 mutex_unlock(&uc
->lock
);
239 pm_runtime_get_sync(uc
->dev
);
240 while (rem_len
> 0) {
241 msgs
[1].buf
= &data
[len
- rem_len
];
242 rlen
= min_t(u16
, rem_len
, max_read_len
);
244 put_unaligned_le16(rab
, buf
);
245 status
= i2c_transfer(client
->adapter
, msgs
, ARRAY_SIZE(msgs
));
247 dev_err(uc
->dev
, "i2c_transfer failed %d\n", status
);
248 pm_runtime_put_sync(uc
->dev
);
255 pm_runtime_put_sync(uc
->dev
);
259 static int ccg_write(struct ucsi_ccg
*uc
, u16 rab
, u8
*data
, u32 len
)
261 struct i2c_client
*client
= uc
->client
;
263 struct i2c_msg msgs
[] = {
265 .addr
= client
->addr
,
271 buf
= kzalloc(len
+ sizeof(rab
), GFP_KERNEL
);
275 put_unaligned_le16(rab
, buf
);
276 memcpy(buf
+ sizeof(rab
), data
, len
);
278 msgs
[0].len
= len
+ sizeof(rab
);
281 if (uc
->fw_build
== CCG_FW_BUILD_NVIDIA
&&
282 uc
->fw_version
<= CCG_OLD_FW_VERSION
) {
283 mutex_lock(&uc
->lock
);
285 * Do not schedule pm_work to run ISR in
286 * ucsi_ccg_runtime_resume() after pm_runtime_get_sync()
287 * since we are already in ISR path.
290 mutex_unlock(&uc
->lock
);
293 pm_runtime_get_sync(uc
->dev
);
294 status
= i2c_transfer(client
->adapter
, msgs
, ARRAY_SIZE(msgs
));
296 dev_err(uc
->dev
, "i2c_transfer failed %d\n", status
);
297 pm_runtime_put_sync(uc
->dev
);
302 pm_runtime_put_sync(uc
->dev
);
307 static int ucsi_ccg_init(struct ucsi_ccg
*uc
)
309 unsigned int count
= 10;
313 data
= CCGX_RAB_UCSI_CONTROL_STOP
;
314 status
= ccg_write(uc
, CCGX_RAB_UCSI_CONTROL
, &data
, sizeof(data
));
318 data
= CCGX_RAB_UCSI_CONTROL_START
;
319 status
= ccg_write(uc
, CCGX_RAB_UCSI_CONTROL
, &data
, sizeof(data
));
324 * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
325 * register write will push response which must be cleared.
328 status
= ccg_read(uc
, CCGX_RAB_INTR_REG
, &data
, sizeof(data
));
335 status
= ccg_write(uc
, CCGX_RAB_INTR_REG
, &data
, sizeof(data
));
339 usleep_range(10000, 11000);
345 static int ucsi_ccg_send_data(struct ucsi_ccg
*uc
)
347 u8
*ppm
= (u8
*)uc
->ppm
.data
;
351 rab
= CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data
, message_out
));
352 status
= ccg_write(uc
, rab
, ppm
+
353 offsetof(struct ucsi_data
, message_out
),
354 sizeof(uc
->ppm
.data
->message_out
));
358 rab
= CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data
, ctrl
));
359 return ccg_write(uc
, rab
, ppm
+ offsetof(struct ucsi_data
, ctrl
),
360 sizeof(uc
->ppm
.data
->ctrl
));
363 static int ucsi_ccg_recv_data(struct ucsi_ccg
*uc
)
365 u8
*ppm
= (u8
*)uc
->ppm
.data
;
369 rab
= CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data
, cci
));
370 status
= ccg_read(uc
, rab
, ppm
+ offsetof(struct ucsi_data
, cci
),
371 sizeof(uc
->ppm
.data
->cci
));
375 rab
= CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data
, message_in
));
376 return ccg_read(uc
, rab
, ppm
+ offsetof(struct ucsi_data
, message_in
),
377 sizeof(uc
->ppm
.data
->message_in
));
380 static int ucsi_ccg_ack_interrupt(struct ucsi_ccg
*uc
)
385 status
= ccg_read(uc
, CCGX_RAB_INTR_REG
, &data
, sizeof(data
));
389 return ccg_write(uc
, CCGX_RAB_INTR_REG
, &data
, sizeof(data
));
392 static int ucsi_ccg_sync(struct ucsi_ppm
*ppm
)
394 struct ucsi_ccg
*uc
= container_of(ppm
, struct ucsi_ccg
, ppm
);
397 status
= ucsi_ccg_recv_data(uc
);
401 /* ack interrupt to allow next command to run */
402 return ucsi_ccg_ack_interrupt(uc
);
405 static int ucsi_ccg_cmd(struct ucsi_ppm
*ppm
, struct ucsi_control
*ctrl
)
407 struct ucsi_ccg
*uc
= container_of(ppm
, struct ucsi_ccg
, ppm
);
409 ppm
->data
->ctrl
.raw_cmd
= ctrl
->raw_cmd
;
410 return ucsi_ccg_send_data(uc
);
413 static irqreturn_t
ccg_irq_handler(int irq
, void *data
)
415 struct ucsi_ccg
*uc
= data
;
417 ucsi_notify(uc
->ucsi
);
422 static void ccg_pm_workaround_work(struct work_struct
*pm_work
)
424 struct ucsi_ccg
*uc
= container_of(pm_work
, struct ucsi_ccg
, pm_work
);
426 ucsi_notify(uc
->ucsi
);
429 static int get_fw_info(struct ucsi_ccg
*uc
)
433 err
= ccg_read(uc
, CCGX_RAB_READ_ALL_VER
, (u8
*)(&uc
->version
),
434 sizeof(uc
->version
));
438 uc
->fw_version
= CCG_VERSION(uc
->version
[FW2
].app
.ver
) |
439 CCG_VERSION_PATCH(uc
->version
[FW2
].app
.patch
);
441 err
= ccg_read(uc
, CCGX_RAB_DEVICE_MODE
, (u8
*)(&uc
->info
),
449 static inline bool invalid_async_evt(int code
)
451 return (code
>= CCG_EVENT_MAX
) || (code
< EVENT_INDEX
);
454 static void ccg_process_response(struct ucsi_ccg
*uc
)
456 struct device
*dev
= uc
->dev
;
458 if (uc
->dev_resp
.code
& ASYNC_EVENT
) {
459 if (uc
->dev_resp
.code
== RESET_COMPLETE
) {
460 if (test_bit(RESET_PENDING
, &uc
->flags
))
461 uc
->cmd_resp
= uc
->dev_resp
.code
;
464 if (invalid_async_evt(uc
->dev_resp
.code
))
465 dev_err(dev
, "invalid async evt %d\n",
468 if (test_bit(DEV_CMD_PENDING
, &uc
->flags
)) {
469 uc
->cmd_resp
= uc
->dev_resp
.code
;
470 clear_bit(DEV_CMD_PENDING
, &uc
->flags
);
472 dev_err(dev
, "dev resp 0x%04x but no cmd pending\n",
478 static int ccg_read_response(struct ucsi_ccg
*uc
)
480 unsigned long target
= jiffies
+ msecs_to_jiffies(1000);
481 struct device
*dev
= uc
->dev
;
485 /* wait for interrupt status to get updated */
487 status
= ccg_read(uc
, CCGX_RAB_INTR_REG
, &intval
,
492 if (intval
& DEV_INT
)
494 usleep_range(500, 600);
495 } while (time_is_after_jiffies(target
));
497 if (time_is_before_jiffies(target
)) {
498 dev_err(dev
, "response timeout error\n");
502 status
= ccg_read(uc
, CCGX_RAB_RESPONSE
, (u8
*)&uc
->dev_resp
,
503 sizeof(uc
->dev_resp
));
507 status
= ccg_write(uc
, CCGX_RAB_INTR_REG
, &intval
, sizeof(intval
));
514 /* Caller must hold uc->lock */
515 static int ccg_send_command(struct ucsi_ccg
*uc
, struct ccg_cmd
*cmd
)
517 struct device
*dev
= uc
->dev
;
520 switch (cmd
->reg
& 0xF000) {
522 set_bit(DEV_CMD_PENDING
, &uc
->flags
);
525 dev_err(dev
, "invalid cmd register\n");
529 ret
= ccg_write(uc
, cmd
->reg
, (u8
*)&cmd
->data
, cmd
->len
);
535 ret
= ccg_read_response(uc
);
537 dev_err(dev
, "response read error\n");
538 switch (cmd
->reg
& 0xF000) {
540 clear_bit(DEV_CMD_PENDING
, &uc
->flags
);
543 dev_err(dev
, "invalid cmd register\n");
548 ccg_process_response(uc
);
553 static int ccg_cmd_enter_flashing(struct ucsi_ccg
*uc
)
558 cmd
.reg
= CCGX_RAB_ENTER_FLASHING
;
559 cmd
.data
= FLASH_ENTER_SIG
;
563 mutex_lock(&uc
->lock
);
565 ret
= ccg_send_command(uc
, &cmd
);
567 mutex_unlock(&uc
->lock
);
569 if (ret
!= CMD_SUCCESS
) {
570 dev_err(uc
->dev
, "enter flashing failed ret=%d\n", ret
);
577 static int ccg_cmd_reset(struct ucsi_ccg
*uc
)
584 cmd
.reg
= CCGX_RAB_RESET_REQ
;
586 p
[1] = CMD_RESET_DEV
;
590 mutex_lock(&uc
->lock
);
592 set_bit(RESET_PENDING
, &uc
->flags
);
594 ret
= ccg_send_command(uc
, &cmd
);
595 if (ret
!= RESET_COMPLETE
)
601 clear_bit(RESET_PENDING
, &uc
->flags
);
603 mutex_unlock(&uc
->lock
);
608 static int ccg_cmd_port_control(struct ucsi_ccg
*uc
, bool enable
)
613 cmd
.reg
= CCGX_RAB_PDPORT_ENABLE
;
615 cmd
.data
= (uc
->port_num
== 1) ?
616 PDPORT_1
: (PDPORT_1
| PDPORT_2
);
622 mutex_lock(&uc
->lock
);
624 ret
= ccg_send_command(uc
, &cmd
);
626 mutex_unlock(&uc
->lock
);
628 if (ret
!= CMD_SUCCESS
) {
629 dev_err(uc
->dev
, "port control failed ret=%d\n", ret
);
635 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg
*uc
, int bl_mode
)
640 cmd
.reg
= CCGX_RAB_JUMP_TO_BOOT
;
645 cmd
.data
= TO_ALT_FW
;
650 mutex_lock(&uc
->lock
);
652 set_bit(RESET_PENDING
, &uc
->flags
);
654 ret
= ccg_send_command(uc
, &cmd
);
655 if (ret
!= RESET_COMPLETE
)
661 clear_bit(RESET_PENDING
, &uc
->flags
);
663 mutex_unlock(&uc
->lock
);
669 ccg_cmd_write_flash_row(struct ucsi_ccg
*uc
, u16 row
,
670 const void *data
, u8 fcmd
)
672 struct i2c_client
*client
= uc
->client
;
674 u8 buf
[CCG4_ROW_SIZE
+ 2];
678 /* Copy the data into the flash read/write memory. */
679 put_unaligned_le16(REG_FLASH_RW_MEM
, buf
);
681 memcpy(buf
+ 2, data
, CCG4_ROW_SIZE
);
683 mutex_lock(&uc
->lock
);
685 ret
= i2c_master_send(client
, buf
, CCG4_ROW_SIZE
+ 2);
686 if (ret
!= CCG4_ROW_SIZE
+ 2) {
687 dev_err(uc
->dev
, "REG_FLASH_RW_MEM write fail %d\n", ret
);
688 mutex_unlock(&uc
->lock
);
689 return ret
< 0 ? ret
: -EIO
;
692 /* Use the FLASH_ROW_READ_WRITE register to trigger */
693 /* writing of data to the desired flash row */
695 cmd
.reg
= CCGX_RAB_FLASH_ROW_RW
;
698 put_unaligned_le16(row
, &p
[2]);
701 if (fcmd
== FLASH_FWCT_SIG_WR_CMD
)
705 ret
= ccg_send_command(uc
, &cmd
);
707 mutex_unlock(&uc
->lock
);
709 if (ret
!= CMD_SUCCESS
) {
710 dev_err(uc
->dev
, "write flash row failed ret=%d\n", ret
);
717 static int ccg_cmd_validate_fw(struct ucsi_ccg
*uc
, unsigned int fwid
)
722 cmd
.reg
= CCGX_RAB_VALIDATE_FW
;
727 mutex_lock(&uc
->lock
);
729 ret
= ccg_send_command(uc
, &cmd
);
731 mutex_unlock(&uc
->lock
);
733 if (ret
!= CMD_SUCCESS
)
739 static bool ccg_check_vendor_version(struct ucsi_ccg
*uc
,
740 struct version_format
*app
,
741 struct fw_config_table
*fw_cfg
)
743 struct device
*dev
= uc
->dev
;
745 /* Check if the fw build is for supported vendors */
746 if (le16_to_cpu(app
->build
) != uc
->fw_build
) {
747 dev_info(dev
, "current fw is not from supported vendor\n");
751 /* Check if the new fw build is for supported vendors */
752 if (le16_to_cpu(fw_cfg
->app
.build
) != uc
->fw_build
) {
753 dev_info(dev
, "new fw is not from supported vendor\n");
759 static bool ccg_check_fw_version(struct ucsi_ccg
*uc
, const char *fw_name
,
760 struct version_format
*app
)
762 const struct firmware
*fw
= NULL
;
763 struct device
*dev
= uc
->dev
;
764 struct fw_config_table fw_cfg
;
765 u32 cur_version
, new_version
;
766 bool is_later
= false;
768 if (request_firmware(&fw
, fw_name
, dev
) != 0) {
769 dev_err(dev
, "error: Failed to open cyacd file %s\n", fw_name
);
775 * last part of fw image is fw cfg table and signature
777 if (fw
->size
< sizeof(fw_cfg
) + FW_CFG_TABLE_SIG_SIZE
)
778 goto out_release_firmware
;
780 memcpy((uint8_t *)&fw_cfg
, fw
->data
+ fw
->size
-
781 sizeof(fw_cfg
) - FW_CFG_TABLE_SIG_SIZE
, sizeof(fw_cfg
));
783 if (fw_cfg
.identity
!= ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
784 dev_info(dev
, "not a signed image\n");
785 goto out_release_firmware
;
788 /* compare input version with FWCT version */
789 cur_version
= le16_to_cpu(app
->build
) | CCG_VERSION_PATCH(app
->patch
) |
790 CCG_VERSION(app
->ver
);
792 new_version
= le16_to_cpu(fw_cfg
.app
.build
) |
793 CCG_VERSION_PATCH(fw_cfg
.app
.patch
) |
794 CCG_VERSION(fw_cfg
.app
.ver
);
796 if (!ccg_check_vendor_version(uc
, app
, &fw_cfg
))
797 goto out_release_firmware
;
799 if (new_version
> cur_version
)
802 out_release_firmware
:
803 release_firmware(fw
);
807 static int ccg_fw_update_needed(struct ucsi_ccg
*uc
,
808 enum enum_flash_mode
*mode
)
810 struct device
*dev
= uc
->dev
;
812 struct version_info version
[3];
814 err
= ccg_read(uc
, CCGX_RAB_DEVICE_MODE
, (u8
*)(&uc
->info
),
817 dev_err(dev
, "read device mode failed\n");
821 err
= ccg_read(uc
, CCGX_RAB_READ_ALL_VER
, (u8
*)version
,
824 dev_err(dev
, "read device mode failed\n");
828 if (memcmp(&version
[FW1
], "\0\0\0\0\0\0\0\0",
829 sizeof(struct version_info
)) == 0) {
830 dev_info(dev
, "secondary fw is not flashed\n");
831 *mode
= SECONDARY_BL
;
832 } else if (le16_to_cpu(version
[FW1
].base
.build
) <
833 secondary_fw_min_ver
) {
834 dev_info(dev
, "secondary fw version is too low (< %d)\n",
835 secondary_fw_min_ver
);
837 } else if (memcmp(&version
[FW2
], "\0\0\0\0\0\0\0\0",
838 sizeof(struct version_info
)) == 0) {
839 dev_info(dev
, "primary fw is not flashed\n");
841 } else if (ccg_check_fw_version(uc
, ccg_fw_names
[PRIMARY
],
842 &version
[FW2
].app
)) {
843 dev_info(dev
, "found primary fw with later version\n");
846 dev_info(dev
, "secondary and primary fw are the latest\n");
847 *mode
= FLASH_NOT_NEEDED
;
852 static int do_flash(struct ucsi_ccg
*uc
, enum enum_flash_mode mode
)
854 struct device
*dev
= uc
->dev
;
855 const struct firmware
*fw
= NULL
;
858 int err
, row
, len
, line_sz
, line_cnt
= 0;
859 unsigned long start_time
= jiffies
;
860 struct fw_config_table fw_cfg
;
861 u8 fw_cfg_sig
[FW_CFG_TABLE_SIG_SIZE
];
864 err
= request_firmware(&fw
, ccg_fw_names
[mode
], dev
);
866 dev_err(dev
, "request %s failed err=%d\n",
867 ccg_fw_names
[mode
], err
);
871 if (((uc
->info
.mode
& CCG_DEVINFO_FWMODE_MASK
) >>
872 CCG_DEVINFO_FWMODE_SHIFT
) == FW2
) {
873 err
= ccg_cmd_port_control(uc
, false);
876 err
= ccg_cmd_jump_boot_mode(uc
, 0);
881 eof
= fw
->data
+ fw
->size
;
885 * last part of fw image is fw cfg table and signature
887 if (fw
->size
< sizeof(fw_cfg
) + sizeof(fw_cfg_sig
))
890 memcpy((uint8_t *)&fw_cfg
, fw
->data
+ fw
->size
-
891 sizeof(fw_cfg
) - sizeof(fw_cfg_sig
), sizeof(fw_cfg
));
893 if (fw_cfg
.identity
!= ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
894 dev_info(dev
, "not a signed image\n");
897 eof
= fw
->data
+ fw
->size
- sizeof(fw_cfg
) - sizeof(fw_cfg_sig
);
899 memcpy((uint8_t *)&fw_cfg_sig
,
900 fw
->data
+ fw
->size
- sizeof(fw_cfg_sig
), sizeof(fw_cfg_sig
));
902 /* flash fw config table and signature first */
903 err
= ccg_cmd_write_flash_row(uc
, 0, (u8
*)&fw_cfg
,
908 err
= ccg_cmd_write_flash_row(uc
, 0, (u8
*)&fw_cfg
+ CCG4_ROW_SIZE
,
913 err
= ccg_cmd_write_flash_row(uc
, 0, &fw_cfg_sig
,
914 FLASH_FWCT_SIG_WR_CMD
);
919 wr_buf
= kzalloc(CCG4_ROW_SIZE
+ 4, GFP_KERNEL
);
925 err
= ccg_cmd_enter_flashing(uc
);
929 /*****************************************************************
930 * CCG firmware image (.cyacd) file line format
932 * :00rrrrllll[dd....]cc/r/n
935 * rrrr is row number to flash (4 char)
936 * llll is data len to flash (4 char)
937 * dd is a data field represents one byte of data (512 char)
938 * cc is checksum (2 char)
941 * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
943 *****************************************************************/
945 p
= strnchr(fw
->data
, fw
->size
, ':');
947 s
= strnchr(p
+ 1, eof
- p
- 1, ':');
954 if (line_sz
!= CYACD_LINE_SIZE
) {
955 dev_err(dev
, "Bad FW format line_sz=%d\n", line_sz
);
960 if (hex2bin(wr_buf
, p
+ 3, CCG4_ROW_SIZE
+ 4)) {
965 row
= get_unaligned_be16(wr_buf
);
966 len
= get_unaligned_be16(&wr_buf
[2]);
968 if (len
!= CCG4_ROW_SIZE
) {
973 err
= ccg_cmd_write_flash_row(uc
, row
, wr_buf
+ 4,
982 dev_info(dev
, "total %d row flashed. time: %dms\n",
983 line_cnt
, jiffies_to_msecs(jiffies
- start_time
));
985 err
= ccg_cmd_validate_fw(uc
, (mode
== PRIMARY
) ? FW2
: FW1
);
987 dev_err(dev
, "%s validation failed err=%d\n",
988 (mode
== PRIMARY
) ? "FW2" : "FW1", err
);
990 dev_info(dev
, "%s validated\n",
991 (mode
== PRIMARY
) ? "FW2" : "FW1");
993 err
= ccg_cmd_port_control(uc
, false);
997 err
= ccg_cmd_reset(uc
);
1001 err
= ccg_cmd_port_control(uc
, true);
1009 release_firmware(fw
);
1013 /*******************************************************************************
1014 * CCG4 has two copies of the firmware in addition to the bootloader.
1015 * If the device is running FW1, FW2 can be updated with the new version.
1016 * Dual firmware mode allows the CCG device to stay in a PD contract and support
1017 * USB PD and Type-C functionality while a firmware update is in progress.
1018 ******************************************************************************/
1019 static int ccg_fw_update(struct ucsi_ccg
*uc
, enum enum_flash_mode flash_mode
)
1023 while (flash_mode
!= FLASH_NOT_NEEDED
) {
1024 err
= do_flash(uc
, flash_mode
);
1027 err
= ccg_fw_update_needed(uc
, &flash_mode
);
1031 dev_info(uc
->dev
, "CCG FW update successful\n");
1036 static int ccg_restart(struct ucsi_ccg
*uc
)
1038 struct device
*dev
= uc
->dev
;
1041 status
= ucsi_ccg_init(uc
);
1043 dev_err(dev
, "ucsi_ccg_start fail, err=%d\n", status
);
1047 status
= request_threaded_irq(uc
->irq
, NULL
, ccg_irq_handler
,
1048 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1051 dev_err(dev
, "request_threaded_irq failed - %d\n", status
);
1055 uc
->ucsi
= ucsi_register_ppm(dev
, &uc
->ppm
);
1056 if (IS_ERR(uc
->ucsi
)) {
1057 dev_err(uc
->dev
, "ucsi_register_ppm failed\n");
1058 return PTR_ERR(uc
->ucsi
);
1064 static void ccg_update_firmware(struct work_struct
*work
)
1066 struct ucsi_ccg
*uc
= container_of(work
, struct ucsi_ccg
, work
);
1067 enum enum_flash_mode flash_mode
;
1070 status
= ccg_fw_update_needed(uc
, &flash_mode
);
1074 if (flash_mode
!= FLASH_NOT_NEEDED
) {
1075 ucsi_unregister_ppm(uc
->ucsi
);
1076 free_irq(uc
->irq
, uc
);
1078 ccg_fw_update(uc
, flash_mode
);
1083 static ssize_t
do_flash_store(struct device
*dev
,
1084 struct device_attribute
*attr
,
1085 const char *buf
, size_t n
)
1087 struct ucsi_ccg
*uc
= i2c_get_clientdata(to_i2c_client(dev
));
1090 if (kstrtobool(buf
, &flash
))
1096 if (uc
->fw_build
== 0x0) {
1097 dev_err(dev
, "fail to flash FW due to missing FW build info\n");
1101 schedule_work(&uc
->work
);
1105 static DEVICE_ATTR_WO(do_flash
);
1107 static struct attribute
*ucsi_ccg_sysfs_attrs
[] = {
1108 &dev_attr_do_flash
.attr
,
1112 static struct attribute_group ucsi_ccg_attr_group
= {
1113 .attrs
= ucsi_ccg_sysfs_attrs
,
1116 static int ucsi_ccg_probe(struct i2c_client
*client
,
1117 const struct i2c_device_id
*id
)
1119 struct device
*dev
= &client
->dev
;
1120 struct ucsi_ccg
*uc
;
1124 uc
= devm_kzalloc(dev
, sizeof(*uc
), GFP_KERNEL
);
1128 uc
->ppm
.data
= devm_kzalloc(dev
, sizeof(struct ucsi_data
), GFP_KERNEL
);
1132 uc
->ppm
.cmd
= ucsi_ccg_cmd
;
1133 uc
->ppm
.sync
= ucsi_ccg_sync
;
1135 uc
->client
= client
;
1137 mutex_init(&uc
->lock
);
1138 INIT_WORK(&uc
->work
, ccg_update_firmware
);
1139 INIT_WORK(&uc
->pm_work
, ccg_pm_workaround_work
);
1141 /* Only fail FW flashing when FW build information is not provided */
1142 status
= device_property_read_u16(dev
, "ccgx,firmware-build",
1145 dev_err(uc
->dev
, "failed to get FW build information\n");
1147 /* reset ccg device and initialize ucsi */
1148 status
= ucsi_ccg_init(uc
);
1150 dev_err(uc
->dev
, "ucsi_ccg_init failed - %d\n", status
);
1154 status
= get_fw_info(uc
);
1156 dev_err(uc
->dev
, "get_fw_info failed - %d\n", status
);
1162 if (uc
->info
.mode
& CCG_DEVINFO_PDPORTS_MASK
)
1165 status
= request_threaded_irq(client
->irq
, NULL
, ccg_irq_handler
,
1166 IRQF_ONESHOT
| IRQF_TRIGGER_HIGH
,
1169 dev_err(uc
->dev
, "request_threaded_irq failed - %d\n", status
);
1173 uc
->irq
= client
->irq
;
1175 uc
->ucsi
= ucsi_register_ppm(dev
, &uc
->ppm
);
1176 if (IS_ERR(uc
->ucsi
)) {
1177 dev_err(uc
->dev
, "ucsi_register_ppm failed\n");
1178 return PTR_ERR(uc
->ucsi
);
1181 rab
= CCGX_RAB_UCSI_DATA_BLOCK(offsetof(struct ucsi_data
, version
));
1182 status
= ccg_read(uc
, rab
, (u8
*)(uc
->ppm
.data
) +
1183 offsetof(struct ucsi_data
, version
),
1184 sizeof(uc
->ppm
.data
->version
));
1186 ucsi_unregister_ppm(uc
->ucsi
);
1190 i2c_set_clientdata(client
, uc
);
1192 status
= sysfs_create_group(&uc
->dev
->kobj
, &ucsi_ccg_attr_group
);
1194 dev_err(uc
->dev
, "cannot create sysfs group: %d\n", status
);
1196 pm_runtime_set_active(uc
->dev
);
1197 pm_runtime_enable(uc
->dev
);
1198 pm_runtime_idle(uc
->dev
);
1203 static int ucsi_ccg_remove(struct i2c_client
*client
)
1205 struct ucsi_ccg
*uc
= i2c_get_clientdata(client
);
1207 cancel_work_sync(&uc
->pm_work
);
1208 cancel_work_sync(&uc
->work
);
1209 ucsi_unregister_ppm(uc
->ucsi
);
1210 pm_runtime_disable(uc
->dev
);
1211 free_irq(uc
->irq
, uc
);
1212 sysfs_remove_group(&uc
->dev
->kobj
, &ucsi_ccg_attr_group
);
1217 static const struct i2c_device_id ucsi_ccg_device_id
[] = {
1221 MODULE_DEVICE_TABLE(i2c
, ucsi_ccg_device_id
);
1223 static int ucsi_ccg_resume(struct device
*dev
)
1225 struct i2c_client
*client
= to_i2c_client(dev
);
1226 struct ucsi_ccg
*uc
= i2c_get_clientdata(client
);
1228 return ucsi_resume(uc
->ucsi
);
1231 static int ucsi_ccg_runtime_suspend(struct device
*dev
)
1236 static int ucsi_ccg_runtime_resume(struct device
*dev
)
1238 struct i2c_client
*client
= to_i2c_client(dev
);
1239 struct ucsi_ccg
*uc
= i2c_get_clientdata(client
);
1240 bool schedule
= true;
1243 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
1244 * of missing interrupt when a device is connected for runtime resume.
1245 * Schedule a work to call ISR as a workaround.
1247 if (uc
->fw_build
== CCG_FW_BUILD_NVIDIA
&&
1248 uc
->fw_version
<= CCG_OLD_FW_VERSION
) {
1249 mutex_lock(&uc
->lock
);
1254 mutex_unlock(&uc
->lock
);
1257 schedule_work(&uc
->pm_work
);
1263 static const struct dev_pm_ops ucsi_ccg_pm
= {
1264 .resume
= ucsi_ccg_resume
,
1265 .runtime_suspend
= ucsi_ccg_runtime_suspend
,
1266 .runtime_resume
= ucsi_ccg_runtime_resume
,
1269 static struct i2c_driver ucsi_ccg_driver
= {
1274 .probe
= ucsi_ccg_probe
,
1275 .remove
= ucsi_ccg_remove
,
1276 .id_table
= ucsi_ccg_device_id
,
1279 module_i2c_driver(ucsi_ccg_driver
);
1281 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1282 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1283 MODULE_LICENSE("GPL v2");