2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
11 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
15 * (C) Copyright 2000-2002 David Brownell
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * ebenard@eukrea.com - based on s3c24x0's driver
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 * 1 - Read doc/README.generic_usb_ohci
42 * 2 - this driver is intended for use with USB Mass Storage Devices
43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
45 * to activate workaround for bug #41 or this driver will NOT work!
50 #ifdef CONFIG_USB_OHCI_NEW
52 #include <asm/byteorder.h>
54 #if defined(CONFIG_PCI_OHCI)
62 #if defined(CONFIG_ARM920T) || \
63 defined(CONFIG_S3C2400) || \
64 defined(CONFIG_S3C2410) || \
65 defined(CONFIG_440EP) || \
66 defined(CONFIG_PCI_OHCI) || \
67 defined(CONFIG_MPC5200)
68 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
71 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
74 #undef OHCI_FILL_TRACE
76 /* For initializing controller (mask in an HCFS mode too) */
77 #define OHCI_CONTROL_INIT \
78 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
81 * e.g. PCI controllers need this
83 #ifdef CFG_OHCI_SWAP_REG_ACCESS
84 # define readl(a) __swap_32(*((vu_long *)(a)))
85 # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
87 # define readl(a) (*((vu_long *)(a)))
88 # define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
89 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
91 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
93 #ifdef CONFIG_PCI_OHCI
94 static struct pci_device_id ohci_pci_ids
[] = {
95 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
96 /* Please add supported PCI OHCI controller ids here */
102 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
104 #define dbg(format, arg...) do {} while(0)
106 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
109 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
111 #define info(format, arg...) do {} while(0)
114 #ifdef CFG_OHCI_BE_CONTROLLER
115 # define m16_swap(x) cpu_to_be16(x)
116 # define m32_swap(x) cpu_to_be32(x)
118 # define m16_swap(x) cpu_to_le16(x)
119 # define m32_swap(x) cpu_to_le32(x)
120 #endif /* CFG_OHCI_BE_CONTROLLER */
124 /* this must be aligned to a 256 byte boundary */
125 struct ohci_hcca ghcca
[1];
126 /* a pointer to the aligned storage */
127 struct ohci_hcca
*phcca
;
128 /* this allocates EDs for all possible endpoints */
129 struct ohci_device ohci_dev
;
132 /* device which was disconnected */
133 struct usb_device
*devgone
;
135 /*-------------------------------------------------------------------------*/
137 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
138 * The erratum (#4) description is incorrect. AMD's workaround waits
139 * till some bits (mostly reserved) are clear; ok for all revs.
141 #define OHCI_QUIRK_AMD756 0xabcd
142 #define read_roothub(hc, register, mask) ({ \
143 u32 temp = readl (&hc->regs->roothub.register); \
144 if (hc->flags & OHCI_QUIRK_AMD756) \
145 while (temp & mask) \
146 temp = readl (&hc->regs->roothub.register); \
149 static u32
roothub_a (struct ohci
*hc
)
150 { return read_roothub (hc
, a
, 0xfc0fe000); }
151 static inline u32
roothub_b (struct ohci
*hc
)
152 { return readl (&hc
->regs
->roothub
.b
); }
153 static inline u32
roothub_status (struct ohci
*hc
)
154 { return readl (&hc
->regs
->roothub
.status
); }
155 static u32
roothub_portstatus (struct ohci
*hc
, int i
)
156 { return read_roothub (hc
, portstatus
[i
], 0xffe0fce0); }
158 /* forward declaration */
159 static int hc_interrupt (void);
161 td_submit_job (struct usb_device
* dev
, unsigned long pipe
, void * buffer
,
162 int transfer_len
, struct devrequest
* setup
, urb_priv_t
* urb
, int interval
);
164 /*-------------------------------------------------------------------------*
165 * URB support functions
166 *-------------------------------------------------------------------------*/
168 /* free HCD-private data associated with this URB */
170 static void urb_free_priv (urb_priv_t
* urb
)
176 last
= urb
->length
- 1;
178 for (i
= 0; i
<= last
; i
++) {
189 /*-------------------------------------------------------------------------*/
192 static int sohci_get_current_frame_number (struct usb_device
* dev
);
194 /* debug| print the main components of an URB
195 * small: 0) header + data packets 1) just header */
197 static void pkt_print (urb_priv_t
*purb
, struct usb_device
* dev
,
198 unsigned long pipe
, void * buffer
,
199 int transfer_len
, struct devrequest
* setup
, char * str
, int small
)
201 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
203 sohci_get_current_frame_number (dev
),
204 usb_pipedevice (pipe
),
205 usb_pipeendpoint (pipe
),
206 usb_pipeout (pipe
)? 'O': 'I',
207 usb_pipetype (pipe
) < 2? (usb_pipeint (pipe
)? "INTR": "ISOC"):
208 (usb_pipecontrol (pipe
)? "CTRL": "BULK"),
209 (purb
? purb
->actual_length
: 0),
210 transfer_len
, dev
->status
);
211 #ifdef OHCI_VERBOSE_DEBUG
215 if (usb_pipecontrol (pipe
)) {
216 printf (__FILE__
": cmd(8):");
217 for (i
= 0; i
< 8 ; i
++)
218 printf (" %02x", ((__u8
*) setup
) [i
]);
221 if (transfer_len
> 0 && buffer
) {
222 printf (__FILE__
": data(%d/%d):",
223 (purb
? purb
->actual_length
: 0),
225 len
= usb_pipeout (pipe
)?
227 (purb
? purb
->actual_length
: 0);
228 for (i
= 0; i
< 16 && i
< len
; i
++)
229 printf (" %02x", ((__u8
*) buffer
) [i
]);
230 printf ("%s\n", i
< len
? "...": "");
236 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
237 void ep_print_int_eds (ohci_t
*ohci
, char * str
) {
240 for (i
= 0; i
< 32; i
++) {
242 ed_p
= &(ohci
->hcca
->int_table
[i
]);
245 printf (__FILE__
": %s branch int %2d(%2x):", str
, i
, i
);
246 while (*ed_p
!= 0 && j
--) {
247 ed_t
*ed
= (ed_t
*)m32_swap(ed_p
);
248 printf (" ed: %4x;", ed
->hwINFO
);
249 ed_p
= &ed
->hwNextED
;
255 static void ohci_dump_intr_mask (char *label
, __u32 mask
)
257 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
260 (mask
& OHCI_INTR_MIE
) ? " MIE" : "",
261 (mask
& OHCI_INTR_OC
) ? " OC" : "",
262 (mask
& OHCI_INTR_RHSC
) ? " RHSC" : "",
263 (mask
& OHCI_INTR_FNO
) ? " FNO" : "",
264 (mask
& OHCI_INTR_UE
) ? " UE" : "",
265 (mask
& OHCI_INTR_RD
) ? " RD" : "",
266 (mask
& OHCI_INTR_SF
) ? " SF" : "",
267 (mask
& OHCI_INTR_WDH
) ? " WDH" : "",
268 (mask
& OHCI_INTR_SO
) ? " SO" : ""
272 static void maybe_print_eds (char *label
, __u32 value
)
274 ed_t
*edp
= (ed_t
*)value
;
277 dbg ("%s %08x", label
, value
);
278 dbg ("%08x", edp
->hwINFO
);
279 dbg ("%08x", edp
->hwTailP
);
280 dbg ("%08x", edp
->hwHeadP
);
281 dbg ("%08x", edp
->hwNextED
);
285 static char * hcfs2string (int state
)
288 case OHCI_USB_RESET
: return "reset";
289 case OHCI_USB_RESUME
: return "resume";
290 case OHCI_USB_OPER
: return "operational";
291 case OHCI_USB_SUSPEND
: return "suspend";
296 /* dump control and status registers */
297 static void ohci_dump_status (ohci_t
*controller
)
299 struct ohci_regs
*regs
= controller
->regs
;
302 temp
= readl (®s
->revision
) & 0xff;
304 dbg ("spec %d.%d", (temp
>> 4), (temp
& 0x0f));
306 temp
= readl (®s
->control
);
307 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp
,
308 (temp
& OHCI_CTRL_RWE
) ? " RWE" : "",
309 (temp
& OHCI_CTRL_RWC
) ? " RWC" : "",
310 (temp
& OHCI_CTRL_IR
) ? " IR" : "",
311 hcfs2string (temp
& OHCI_CTRL_HCFS
),
312 (temp
& OHCI_CTRL_BLE
) ? " BLE" : "",
313 (temp
& OHCI_CTRL_CLE
) ? " CLE" : "",
314 (temp
& OHCI_CTRL_IE
) ? " IE" : "",
315 (temp
& OHCI_CTRL_PLE
) ? " PLE" : "",
316 temp
& OHCI_CTRL_CBSR
319 temp
= readl (®s
->cmdstatus
);
320 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp
,
321 (temp
& OHCI_SOC
) >> 16,
322 (temp
& OHCI_OCR
) ? " OCR" : "",
323 (temp
& OHCI_BLF
) ? " BLF" : "",
324 (temp
& OHCI_CLF
) ? " CLF" : "",
325 (temp
& OHCI_HCR
) ? " HCR" : ""
328 ohci_dump_intr_mask ("intrstatus", readl (®s
->intrstatus
));
329 ohci_dump_intr_mask ("intrenable", readl (®s
->intrenable
));
331 maybe_print_eds ("ed_periodcurrent", readl (®s
->ed_periodcurrent
));
333 maybe_print_eds ("ed_controlhead", readl (®s
->ed_controlhead
));
334 maybe_print_eds ("ed_controlcurrent", readl (®s
->ed_controlcurrent
));
336 maybe_print_eds ("ed_bulkhead", readl (®s
->ed_bulkhead
));
337 maybe_print_eds ("ed_bulkcurrent", readl (®s
->ed_bulkcurrent
));
339 maybe_print_eds ("donehead", readl (®s
->donehead
));
342 static void ohci_dump_roothub (ohci_t
*controller
, int verbose
)
346 temp
= roothub_a (controller
);
347 ndp
= (temp
& RH_A_NDP
);
348 #ifdef CONFIG_AT91C_PQFP_UHPBUG
349 ndp
= (ndp
== 2) ? 1:0;
352 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp
,
353 ((temp
& RH_A_POTPGT
) >> 24) & 0xff,
354 (temp
& RH_A_NOCP
) ? " NOCP" : "",
355 (temp
& RH_A_OCPM
) ? " OCPM" : "",
356 (temp
& RH_A_DT
) ? " DT" : "",
357 (temp
& RH_A_NPS
) ? " NPS" : "",
358 (temp
& RH_A_PSM
) ? " PSM" : "",
361 temp
= roothub_b (controller
);
362 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
364 (temp
& RH_B_PPCM
) >> 16,
367 temp
= roothub_status (controller
);
368 dbg ("roothub.status: %08x%s%s%s%s%s%s",
370 (temp
& RH_HS_CRWE
) ? " CRWE" : "",
371 (temp
& RH_HS_OCIC
) ? " OCIC" : "",
372 (temp
& RH_HS_LPSC
) ? " LPSC" : "",
373 (temp
& RH_HS_DRWE
) ? " DRWE" : "",
374 (temp
& RH_HS_OCI
) ? " OCI" : "",
375 (temp
& RH_HS_LPS
) ? " LPS" : ""
379 for (i
= 0; i
< ndp
; i
++) {
380 temp
= roothub_portstatus (controller
, i
);
381 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
384 (temp
& RH_PS_PRSC
) ? " PRSC" : "",
385 (temp
& RH_PS_OCIC
) ? " OCIC" : "",
386 (temp
& RH_PS_PSSC
) ? " PSSC" : "",
387 (temp
& RH_PS_PESC
) ? " PESC" : "",
388 (temp
& RH_PS_CSC
) ? " CSC" : "",
390 (temp
& RH_PS_LSDA
) ? " LSDA" : "",
391 (temp
& RH_PS_PPS
) ? " PPS" : "",
392 (temp
& RH_PS_PRS
) ? " PRS" : "",
393 (temp
& RH_PS_POCI
) ? " POCI" : "",
394 (temp
& RH_PS_PSS
) ? " PSS" : "",
396 (temp
& RH_PS_PES
) ? " PES" : "",
397 (temp
& RH_PS_CCS
) ? " CCS" : ""
402 static void ohci_dump (ohci_t
*controller
, int verbose
)
404 dbg ("OHCI controller usb-%s state", controller
->slot_name
);
406 /* dumps some of the state we know about */
407 ohci_dump_status (controller
);
409 ep_print_int_eds (controller
, "hcca");
410 dbg ("hcca frame #%04x", controller
->hcca
->frame_no
);
411 ohci_dump_roothub (controller
, 1);
415 /*-------------------------------------------------------------------------*
416 * Interface functions (URB)
417 *-------------------------------------------------------------------------*/
419 /* get a transfer request */
421 int sohci_submit_job(urb_priv_t
*urb
, struct devrequest
*setup
)
425 urb_priv_t
*purb_priv
= urb
;
427 struct usb_device
*dev
= urb
->dev
;
428 unsigned long pipe
= urb
->pipe
;
429 void *buffer
= urb
->transfer_buffer
;
430 int transfer_len
= urb
->transfer_buffer_length
;
431 int interval
= urb
->interval
;
435 /* when controller's hung, permit only roothub cleanup attempts
436 * such as powering down ports */
437 if (ohci
->disabled
) {
438 err("sohci_submit_job: EPIPE");
442 /* we're about to begin a new transaction here so mark the URB unfinished */
445 /* every endpoint has a ed, locate and fill it */
446 if (!(ed
= ep_add_ed (dev
, pipe
, interval
, 1))) {
447 err("sohci_submit_job: ENOMEM");
451 /* for the private part of the URB we need the number of TDs (size) */
452 switch (usb_pipetype (pipe
)) {
453 case PIPE_BULK
: /* one TD for every 4096 Byte */
454 size
= (transfer_len
- 1) / 4096 + 1;
456 case PIPE_CONTROL
: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
457 size
= (transfer_len
== 0)? 2:
458 (transfer_len
- 1) / 4096 + 3;
460 case PIPE_INTERRUPT
: /* 1 TD */
467 if (size
>= (N_URB_TD
- 1)) {
468 err("need %d TDs, only have %d", size
, N_URB_TD
);
471 purb_priv
->pipe
= pipe
;
473 /* fill the private part of the URB */
474 purb_priv
->length
= size
;
476 purb_priv
->actual_length
= 0;
478 /* allocate the TDs */
479 /* note that td[0] was allocated in ep_add_ed */
480 for (i
= 0; i
< size
; i
++) {
481 purb_priv
->td
[i
] = td_alloc (dev
);
482 if (!purb_priv
->td
[i
]) {
483 purb_priv
->length
= i
;
484 urb_free_priv (purb_priv
);
485 err("sohci_submit_job: ENOMEM");
490 if (ed
->state
== ED_NEW
|| (ed
->state
& ED_DEL
)) {
491 urb_free_priv (purb_priv
);
492 err("sohci_submit_job: EINVAL");
496 /* link the ed into a chain if is not already */
497 if (ed
->state
!= ED_OPER
)
500 /* fill the TDs and link it to the ed */
501 td_submit_job(dev
, pipe
, buffer
, transfer_len
, setup
, purb_priv
, interval
);
506 static inline int sohci_return_job(struct ohci
*hc
, urb_priv_t
*urb
)
508 struct ohci_regs
*regs
= hc
->regs
;
510 switch (usb_pipetype (urb
->pipe
)) {
512 /* implicitly requeued */
513 if (urb
->dev
->irq_handle
&&
514 (urb
->dev
->irq_act_len
= urb
->actual_length
)) {
515 writel (OHCI_INTR_WDH
, ®s
->intrenable
);
516 readl (®s
->intrenable
); /* PCI posting flush */
517 urb
->dev
->irq_handle(urb
->dev
);
518 writel (OHCI_INTR_WDH
, ®s
->intrdisable
);
519 readl (®s
->intrdisable
); /* PCI posting flush */
521 urb
->actual_length
= 0;
525 urb
->transfer_buffer
,
526 urb
->transfer_buffer_length
,
540 /*-------------------------------------------------------------------------*/
543 /* tell us the current USB frame number */
545 static int sohci_get_current_frame_number (struct usb_device
*usb_dev
)
547 ohci_t
*ohci
= &gohci
;
549 return m16_swap (ohci
->hcca
->frame_no
);
553 /*-------------------------------------------------------------------------*
554 * ED handling functions
555 *-------------------------------------------------------------------------*/
557 /* search for the right branch to insert an interrupt ed into the int tree
558 * do some load ballancing;
559 * returns the branch and
560 * sets the interval to interval = 2^integer (ld (interval)) */
562 static int ep_int_ballance (ohci_t
* ohci
, int interval
, int load
)
566 /* search for the least loaded interrupt endpoint
567 * branch of all 32 branches
569 for (i
= 0; i
< 32; i
++)
570 if (ohci
->ohci_int_load
[branch
] > ohci
->ohci_int_load
[i
])
573 branch
= branch
% interval
;
574 for (i
= branch
; i
< 32; i
+= interval
)
575 ohci
->ohci_int_load
[i
] += load
;
580 /*-------------------------------------------------------------------------*/
582 /* 2^int( ld (inter)) */
584 static int ep_2_n_interval (int inter
)
587 for (i
= 0; ((inter
>> i
) > 1 ) && (i
< 5); i
++);
591 /*-------------------------------------------------------------------------*/
593 /* the int tree is a binary tree
594 * in order to process it sequentially the indexes of the branches have to be mapped
595 * the mapping reverses the bits of a word of num_bits length */
597 static int ep_rev (int num_bits
, int word
)
601 for (i
= 0; i
< num_bits
; i
++)
602 wout
|= (((word
>> i
) & 1) << (num_bits
- i
- 1));
606 /*-------------------------------------------------------------------------*
607 * ED handling functions
608 *-------------------------------------------------------------------------*/
610 /* link an ed into one of the HC chains */
612 static int ep_link (ohci_t
*ohci
, ed_t
*edi
)
614 volatile ed_t
*ed
= edi
;
623 ed
->int_interval
= 0;
628 if (ohci
->ed_controltail
== NULL
) {
629 writel (ed
, &ohci
->regs
->ed_controlhead
);
631 ohci
->ed_controltail
->hwNextED
= m32_swap ((unsigned long)ed
);
633 ed
->ed_prev
= ohci
->ed_controltail
;
634 if (!ohci
->ed_controltail
&& !ohci
->ed_rm_list
[0] &&
635 !ohci
->ed_rm_list
[1] && !ohci
->sleeping
) {
636 ohci
->hc_control
|= OHCI_CTRL_CLE
;
637 writel (ohci
->hc_control
, &ohci
->regs
->control
);
639 ohci
->ed_controltail
= edi
;
644 if (ohci
->ed_bulktail
== NULL
) {
645 writel (ed
, &ohci
->regs
->ed_bulkhead
);
647 ohci
->ed_bulktail
->hwNextED
= m32_swap ((unsigned long)ed
);
649 ed
->ed_prev
= ohci
->ed_bulktail
;
650 if (!ohci
->ed_bulktail
&& !ohci
->ed_rm_list
[0] &&
651 !ohci
->ed_rm_list
[1] && !ohci
->sleeping
) {
652 ohci
->hc_control
|= OHCI_CTRL_BLE
;
653 writel (ohci
->hc_control
, &ohci
->regs
->control
);
655 ohci
->ed_bulktail
= edi
;
660 interval
= ep_2_n_interval (ed
->int_period
);
661 ed
->int_interval
= interval
;
662 int_branch
= ep_int_ballance (ohci
, interval
, load
);
663 ed
->int_branch
= int_branch
;
665 for (i
= 0; i
< ep_rev (6, interval
); i
+= inter
) {
667 for (ed_p
= &(ohci
->hcca
->int_table
[ep_rev (5, i
) + int_branch
]);
668 (*ed_p
!= 0) && (((ed_t
*)ed_p
)->int_interval
>= interval
);
669 ed_p
= &(((ed_t
*)ed_p
)->hwNextED
))
670 inter
= ep_rev (6, ((ed_t
*)ed_p
)->int_interval
);
671 ed
->hwNextED
= *ed_p
;
672 *ed_p
= m32_swap(ed
);
679 /*-------------------------------------------------------------------------*/
681 /* scan the periodic table to find and unlink this ED */
682 static void periodic_unlink ( struct ohci
*ohci
, volatile struct ed
*ed
,
683 unsigned index
, unsigned period
)
685 for (; index
< NUM_INTS
; index
+= period
) {
686 __u32
*ed_p
= &ohci
->hcca
->int_table
[index
];
688 /* ED might have been unlinked through another path */
690 if (((struct ed
*)m32_swap (ed_p
)) == ed
) {
691 *ed_p
= ed
->hwNextED
;
694 ed_p
= & (((struct ed
*)m32_swap (ed_p
))->hwNextED
);
699 /* unlink an ed from one of the HC chains.
700 * just the link to the ed is unlinked.
701 * the link from the ed still points to another operational ed or 0
702 * so the HC can eventually finish the processing of the unlinked ed */
704 static int ep_unlink (ohci_t
*ohci
, ed_t
*edi
)
706 volatile ed_t
*ed
= edi
;
709 ed
->hwINFO
|= m32_swap (OHCI_ED_SKIP
);
713 if (ed
->ed_prev
== NULL
) {
715 ohci
->hc_control
&= ~OHCI_CTRL_CLE
;
716 writel (ohci
->hc_control
, &ohci
->regs
->control
);
718 writel (m32_swap (*((__u32
*)&ed
->hwNextED
)), &ohci
->regs
->ed_controlhead
);
720 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
722 if (ohci
->ed_controltail
== ed
) {
723 ohci
->ed_controltail
= ed
->ed_prev
;
725 ((ed_t
*)m32_swap (*((__u32
*)&ed
->hwNextED
)))->ed_prev
= ed
->ed_prev
;
730 if (ed
->ed_prev
== NULL
) {
732 ohci
->hc_control
&= ~OHCI_CTRL_BLE
;
733 writel (ohci
->hc_control
, &ohci
->regs
->control
);
735 writel (m32_swap (*((__u32
*)&ed
->hwNextED
)), &ohci
->regs
->ed_bulkhead
);
737 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
739 if (ohci
->ed_bulktail
== ed
) {
740 ohci
->ed_bulktail
= ed
->ed_prev
;
742 ((ed_t
*)m32_swap (*((__u32
*)&ed
->hwNextED
)))->ed_prev
= ed
->ed_prev
;
747 periodic_unlink (ohci
, ed
, 0, 1);
748 for (i
= ed
->int_branch
; i
< 32; i
+= ed
->int_interval
)
749 ohci
->ohci_int_load
[i
] -= ed
->int_load
;
752 ed
->state
= ED_UNLINK
;
756 /*-------------------------------------------------------------------------*/
758 /* add/reinit an endpoint; this should be done once at the
759 * usb_set_configuration command, but the USB stack is a little bit
760 * stateless so we do it at every transaction if the state of the ed
761 * is ED_NEW then a dummy td is added and the state is changed to
762 * ED_UNLINK in all other cases the state is left unchanged the ed
763 * info fields are setted anyway even though most of them should not
766 static ed_t
* ep_add_ed (struct usb_device
*usb_dev
, unsigned long pipe
,
767 int interval
, int load
)
773 ed
= ed_ret
= &ohci_dev
.ed
[(usb_pipeendpoint (pipe
) << 1) |
774 (usb_pipecontrol (pipe
)? 0: usb_pipeout (pipe
))];
776 if ((ed
->state
& ED_DEL
) || (ed
->state
& ED_URB_DEL
)) {
777 err("ep_add_ed: pending delete");
778 /* pending delete request */
782 if (ed
->state
== ED_NEW
) {
783 ed
->hwINFO
= m32_swap (OHCI_ED_SKIP
); /* skip ed */
784 /* dummy td; end of td list for ed */
785 td
= td_alloc (usb_dev
);
786 ed
->hwTailP
= m32_swap ((unsigned long)td
);
787 ed
->hwHeadP
= ed
->hwTailP
;
788 ed
->state
= ED_UNLINK
;
789 ed
->type
= usb_pipetype (pipe
);
793 ed
->hwINFO
= m32_swap (usb_pipedevice (pipe
)
794 | usb_pipeendpoint (pipe
) << 7
795 | (usb_pipeisoc (pipe
)? 0x8000: 0)
796 | (usb_pipecontrol (pipe
)? 0: (usb_pipeout (pipe
)? 0x800: 0x1000))
797 | usb_pipeslow (pipe
) << 13
798 | usb_maxpacket (usb_dev
, pipe
) << 16);
800 if (ed
->type
== PIPE_INTERRUPT
&& ed
->state
== ED_UNLINK
) {
801 ed
->int_period
= interval
;
808 /*-------------------------------------------------------------------------*
809 * TD handling functions
810 *-------------------------------------------------------------------------*/
812 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
814 static void td_fill (ohci_t
*ohci
, unsigned int info
,
816 struct usb_device
*dev
, int index
, urb_priv_t
*urb_priv
)
818 volatile td_t
*td
, *td_pt
;
819 #ifdef OHCI_FILL_TRACE
823 if (index
> urb_priv
->length
) {
824 err("index > length");
827 /* use this td as the next dummy */
828 td_pt
= urb_priv
->td
[index
];
831 /* fill the old dummy TD */
832 td
= urb_priv
->td
[index
] = (td_t
*)(m32_swap (urb_priv
->ed
->hwTailP
) & ~0xf);
834 td
->ed
= urb_priv
->ed
;
835 td
->next_dl_td
= NULL
;
837 td
->data
= (__u32
)data
;
838 #ifdef OHCI_FILL_TRACE
839 if ((usb_pipetype(urb_priv
->pipe
) == PIPE_BULK
) && usb_pipeout(urb_priv
->pipe
)) {
840 for (i
= 0; i
< len
; i
++)
841 printf("td->data[%d] %#2x ",i
, ((unsigned char *)td
->data
)[i
]);
848 td
->hwINFO
= m32_swap (info
);
849 td
->hwCBP
= m32_swap ((unsigned long)data
);
851 td
->hwBE
= m32_swap ((unsigned long)(data
+ len
- 1));
854 td
->hwNextTD
= m32_swap ((unsigned long)td_pt
);
856 /* append to queue */
857 td
->ed
->hwTailP
= td
->hwNextTD
;
860 /*-------------------------------------------------------------------------*/
862 /* prepare all TDs of a transfer */
864 static void td_submit_job (struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
865 int transfer_len
, struct devrequest
*setup
, urb_priv_t
*urb
, int interval
)
867 ohci_t
*ohci
= &gohci
;
868 int data_len
= transfer_len
;
872 unsigned int toggle
= 0;
874 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
875 if(usb_gettoggle(dev
, usb_pipeendpoint(pipe
), usb_pipeout(pipe
))) {
876 toggle
= TD_T_TOGGLE
;
879 usb_settoggle(dev
, usb_pipeendpoint(pipe
), usb_pipeout(pipe
), 1);
887 switch (usb_pipetype (pipe
)) {
889 info
= usb_pipeout (pipe
)?
890 TD_CC
| TD_DP_OUT
: TD_CC
| TD_DP_IN
;
891 while(data_len
> 4096) {
892 td_fill (ohci
, info
| (cnt
? TD_T_TOGGLE
:toggle
), data
, 4096, dev
, cnt
, urb
);
893 data
+= 4096; data_len
-= 4096; cnt
++;
895 info
= usb_pipeout (pipe
)?
896 TD_CC
| TD_DP_OUT
: TD_CC
| TD_R
| TD_DP_IN
;
897 td_fill (ohci
, info
| (cnt
? TD_T_TOGGLE
:toggle
), data
, data_len
, dev
, cnt
, urb
);
901 writel (OHCI_BLF
, &ohci
->regs
->cmdstatus
); /* start bulk list */
905 info
= TD_CC
| TD_DP_SETUP
| TD_T_DATA0
;
906 td_fill (ohci
, info
, setup
, 8, dev
, cnt
++, urb
);
908 info
= usb_pipeout (pipe
)?
909 TD_CC
| TD_R
| TD_DP_OUT
| TD_T_DATA1
: TD_CC
| TD_R
| TD_DP_IN
| TD_T_DATA1
;
910 /* NOTE: mishandles transfers >8K, some >4K */
911 td_fill (ohci
, info
, data
, data_len
, dev
, cnt
++, urb
);
913 info
= usb_pipeout (pipe
)?
914 TD_CC
| TD_DP_IN
| TD_T_DATA1
: TD_CC
| TD_DP_OUT
| TD_T_DATA1
;
915 td_fill (ohci
, info
, data
, 0, dev
, cnt
++, urb
);
917 writel (OHCI_CLF
, &ohci
->regs
->cmdstatus
); /* start Control list */
921 info
= usb_pipeout (urb
->pipe
)?
922 TD_CC
| TD_DP_OUT
| toggle
:
923 TD_CC
| TD_R
| TD_DP_IN
| toggle
;
924 td_fill (ohci
, info
, data
, data_len
, dev
, cnt
++, urb
);
927 if (urb
->length
!= cnt
)
928 dbg("TD LENGTH %d != CNT %d", urb
->length
, cnt
);
931 /*-------------------------------------------------------------------------*
932 * Done List handling functions
933 *-------------------------------------------------------------------------*/
935 /* calculate the transfer length and update the urb */
937 static void dl_transfer_length(td_t
* td
)
939 __u32 tdINFO
, tdBE
, tdCBP
;
940 urb_priv_t
*lurb_priv
= td
->ed
->purb
;
942 tdINFO
= m32_swap (td
->hwINFO
);
943 tdBE
= m32_swap (td
->hwBE
);
944 tdCBP
= m32_swap (td
->hwCBP
);
946 if (!(usb_pipetype (lurb_priv
->pipe
) == PIPE_CONTROL
&&
947 ((td
->index
== 0) || (td
->index
== lurb_priv
->length
- 1)))) {
950 lurb_priv
->actual_length
+= tdBE
- td
->data
+ 1;
952 lurb_priv
->actual_length
+= tdCBP
- td
->data
;
957 /*-------------------------------------------------------------------------*/
959 /* replies to the request have to be on a FIFO basis so
960 * we reverse the reversed done-list */
962 static td_t
* dl_reverse_done_list (ohci_t
*ohci
)
966 td_t
*td_list
= NULL
;
967 urb_priv_t
*lurb_priv
= NULL
;
969 td_list_hc
= m32_swap (ohci
->hcca
->done_head
) & 0xfffffff0;
970 ohci
->hcca
->done_head
= 0;
973 td_list
= (td_t
*)td_list_hc
;
975 if (TD_CC_GET (m32_swap (td_list
->hwINFO
))) {
976 lurb_priv
= td_list
->ed
->purb
;
977 dbg(" USB-error/status: %x : %p",
978 TD_CC_GET (m32_swap (td_list
->hwINFO
)), td_list
);
979 if (td_list
->ed
->hwHeadP
& m32_swap (0x1)) {
980 if (lurb_priv
&& ((td_list
->index
+ 1) < lurb_priv
->length
)) {
981 td_list
->ed
->hwHeadP
=
982 (lurb_priv
->td
[lurb_priv
->length
- 1]->hwNextTD
& m32_swap (0xfffffff0)) |
983 (td_list
->ed
->hwHeadP
& m32_swap (0x2));
984 lurb_priv
->td_cnt
+= lurb_priv
->length
- td_list
->index
- 1;
986 td_list
->ed
->hwHeadP
&= m32_swap (0xfffffff2);
988 #ifdef CONFIG_MPC5200
989 td_list
->hwNextTD
= 0;
993 td_list
->next_dl_td
= td_rev
;
995 td_list_hc
= m32_swap (td_list
->hwNextTD
) & 0xfffffff0;
1000 /*-------------------------------------------------------------------------*/
1003 static int dl_done_list (ohci_t
*ohci
, td_t
*td_list
)
1005 td_t
*td_list_next
= NULL
;
1010 urb_priv_t
*lurb_priv
;
1011 __u32 tdINFO
, edHeadP
, edTailP
;
1014 td_list_next
= td_list
->next_dl_td
;
1016 tdINFO
= m32_swap (td_list
->hwINFO
);
1019 lurb_priv
= ed
->purb
;
1021 dl_transfer_length(td_list
);
1023 /* error code of transfer */
1024 cc
= TD_CC_GET (tdINFO
);
1026 dbg("ConditionCode %#x", cc
);
1027 stat
= cc_to_error
[cc
];
1030 /* see if this done list makes for all TD's of current URB,
1031 * and mark the URB finished if so */
1032 if (++(lurb_priv
->td_cnt
) == lurb_priv
->length
) {
1034 if ((ed
->state
& (ED_OPER
| ED_UNLINK
)) &&
1035 (lurb_priv
->state
!= URB_DEL
))
1037 if ((ed
->state
& (ED_OPER
| ED_UNLINK
)))
1039 lurb_priv
->finished
= sohci_return_job(ohci
,
1042 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
1044 dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv
->td_cnt
,
1046 if (ed
->state
!= ED_NEW
&&
1047 (usb_pipetype (lurb_priv
->pipe
) != PIPE_INTERRUPT
)) {
1048 edHeadP
= m32_swap (ed
->hwHeadP
) & 0xfffffff0;
1049 edTailP
= m32_swap (ed
->hwTailP
);
1051 /* unlink eds if they are not busy */
1052 if ((edHeadP
== edTailP
) && (ed
->state
== ED_OPER
))
1053 ep_unlink (ohci
, ed
);
1056 td_list
= td_list_next
;
1061 /*-------------------------------------------------------------------------*
1063 *-------------------------------------------------------------------------*/
1065 /* Device descriptor */
1066 static __u8 root_hub_dev_des
[] =
1068 0x12, /* __u8 bLength; */
1069 0x01, /* __u8 bDescriptorType; Device */
1070 0x10, /* __u16 bcdUSB; v1.1 */
1072 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1073 0x00, /* __u8 bDeviceSubClass; */
1074 0x00, /* __u8 bDeviceProtocol; */
1075 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1076 0x00, /* __u16 idVendor; */
1078 0x00, /* __u16 idProduct; */
1080 0x00, /* __u16 bcdDevice; */
1082 0x00, /* __u8 iManufacturer; */
1083 0x01, /* __u8 iProduct; */
1084 0x00, /* __u8 iSerialNumber; */
1085 0x01 /* __u8 bNumConfigurations; */
1088 /* Configuration descriptor */
1089 static __u8 root_hub_config_des
[] =
1091 0x09, /* __u8 bLength; */
1092 0x02, /* __u8 bDescriptorType; Configuration */
1093 0x19, /* __u16 wTotalLength; */
1095 0x01, /* __u8 bNumInterfaces; */
1096 0x01, /* __u8 bConfigurationValue; */
1097 0x00, /* __u8 iConfiguration; */
1098 0x40, /* __u8 bmAttributes;
1099 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1100 0x00, /* __u8 MaxPower; */
1103 0x09, /* __u8 if_bLength; */
1104 0x04, /* __u8 if_bDescriptorType; Interface */
1105 0x00, /* __u8 if_bInterfaceNumber; */
1106 0x00, /* __u8 if_bAlternateSetting; */
1107 0x01, /* __u8 if_bNumEndpoints; */
1108 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1109 0x00, /* __u8 if_bInterfaceSubClass; */
1110 0x00, /* __u8 if_bInterfaceProtocol; */
1111 0x00, /* __u8 if_iInterface; */
1114 0x07, /* __u8 ep_bLength; */
1115 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1116 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1117 0x03, /* __u8 ep_bmAttributes; Interrupt */
1118 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1120 0xff /* __u8 ep_bInterval; 255 ms */
1123 static unsigned char root_hub_str_index0
[] =
1125 0x04, /* __u8 bLength; */
1126 0x03, /* __u8 bDescriptorType; String-descriptor */
1127 0x09, /* __u8 lang ID */
1128 0x04, /* __u8 lang ID */
1131 static unsigned char root_hub_str_index1
[] =
1133 28, /* __u8 bLength; */
1134 0x03, /* __u8 bDescriptorType; String-descriptor */
1135 'O', /* __u8 Unicode */
1136 0, /* __u8 Unicode */
1137 'H', /* __u8 Unicode */
1138 0, /* __u8 Unicode */
1139 'C', /* __u8 Unicode */
1140 0, /* __u8 Unicode */
1141 'I', /* __u8 Unicode */
1142 0, /* __u8 Unicode */
1143 ' ', /* __u8 Unicode */
1144 0, /* __u8 Unicode */
1145 'R', /* __u8 Unicode */
1146 0, /* __u8 Unicode */
1147 'o', /* __u8 Unicode */
1148 0, /* __u8 Unicode */
1149 'o', /* __u8 Unicode */
1150 0, /* __u8 Unicode */
1151 't', /* __u8 Unicode */
1152 0, /* __u8 Unicode */
1153 ' ', /* __u8 Unicode */
1154 0, /* __u8 Unicode */
1155 'H', /* __u8 Unicode */
1156 0, /* __u8 Unicode */
1157 'u', /* __u8 Unicode */
1158 0, /* __u8 Unicode */
1159 'b', /* __u8 Unicode */
1160 0, /* __u8 Unicode */
1163 /* Hub class-specific descriptor is constructed dynamically */
1165 /*-------------------------------------------------------------------------*/
1167 #define OK(x) len = (x); break
1169 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
1170 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
1172 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
1173 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
1175 #define RD_RH_STAT roothub_status(&gohci)
1176 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
1178 /* request to virtual root hub */
1180 int rh_check_port_status(ohci_t
*controller
)
1186 temp
= roothub_a (controller
);
1187 ndp
= (temp
& RH_A_NDP
);
1188 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1189 ndp
= (ndp
== 2) ? 1:0;
1191 for (i
= 0; i
< ndp
; i
++) {
1192 temp
= roothub_portstatus (controller
, i
);
1193 /* check for a device disconnect */
1194 if (((temp
& (RH_PS_PESC
| RH_PS_CSC
)) ==
1195 (RH_PS_PESC
| RH_PS_CSC
)) &&
1196 ((temp
& RH_PS_CCS
) == 0)) {
1204 static int ohci_submit_rh_msg(struct usb_device
*dev
, unsigned long pipe
,
1205 void *buffer
, int transfer_len
, struct devrequest
*cmd
)
1207 void * data
= buffer
;
1208 int leni
= transfer_len
;
1212 __u8
*data_buf
= (__u8
*)datab
;
1219 pkt_print(NULL
, dev
, pipe
, buffer
, transfer_len
, cmd
, "SUB(rh)", usb_pipein(pipe
));
1223 if ((pipe
& PIPE_INTERRUPT
) == PIPE_INTERRUPT
) {
1224 info("Root-Hub submit IRQ: NOT implemented");
1228 bmRType_bReq
= cmd
->requesttype
| (cmd
->request
<< 8);
1229 wValue
= cpu_to_le16 (cmd
->value
);
1230 wIndex
= cpu_to_le16 (cmd
->index
);
1231 wLength
= cpu_to_le16 (cmd
->length
);
1233 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1234 dev
->devnum
, 8, bmRType_bReq
, wValue
, wIndex
, wLength
);
1236 switch (bmRType_bReq
) {
1237 /* Request Destination:
1238 without flags: Device,
1239 RH_INTERFACE: interface,
1240 RH_ENDPOINT: endpoint,
1241 RH_CLASS means HUB here,
1242 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1246 *(__u16
*) data_buf
= cpu_to_le16 (1); OK (2);
1247 case RH_GET_STATUS
| RH_INTERFACE
:
1248 *(__u16
*) data_buf
= cpu_to_le16 (0); OK (2);
1249 case RH_GET_STATUS
| RH_ENDPOINT
:
1250 *(__u16
*) data_buf
= cpu_to_le16 (0); OK (2);
1251 case RH_GET_STATUS
| RH_CLASS
:
1252 *(__u32
*) data_buf
= cpu_to_le32 (
1253 RD_RH_STAT
& ~(RH_HS_CRWE
| RH_HS_DRWE
));
1255 case RH_GET_STATUS
| RH_OTHER
| RH_CLASS
:
1256 *(__u32
*) data_buf
= cpu_to_le32 (RD_RH_PORTSTAT
); OK (4);
1258 case RH_CLEAR_FEATURE
| RH_ENDPOINT
:
1260 case (RH_ENDPOINT_STALL
): OK (0);
1264 case RH_CLEAR_FEATURE
| RH_CLASS
:
1266 case RH_C_HUB_LOCAL_POWER
:
1268 case (RH_C_HUB_OVER_CURRENT
):
1269 WR_RH_STAT(RH_HS_OCIC
); OK (0);
1273 case RH_CLEAR_FEATURE
| RH_OTHER
| RH_CLASS
:
1275 case (RH_PORT_ENABLE
):
1276 WR_RH_PORTSTAT (RH_PS_CCS
); OK (0);
1277 case (RH_PORT_SUSPEND
):
1278 WR_RH_PORTSTAT (RH_PS_POCI
); OK (0);
1279 case (RH_PORT_POWER
):
1280 WR_RH_PORTSTAT (RH_PS_LSDA
); OK (0);
1281 case (RH_C_PORT_CONNECTION
):
1282 WR_RH_PORTSTAT (RH_PS_CSC
); OK (0);
1283 case (RH_C_PORT_ENABLE
):
1284 WR_RH_PORTSTAT (RH_PS_PESC
); OK (0);
1285 case (RH_C_PORT_SUSPEND
):
1286 WR_RH_PORTSTAT (RH_PS_PSSC
); OK (0);
1287 case (RH_C_PORT_OVER_CURRENT
):
1288 WR_RH_PORTSTAT (RH_PS_OCIC
); OK (0);
1289 case (RH_C_PORT_RESET
):
1290 WR_RH_PORTSTAT (RH_PS_PRSC
); OK (0);
1294 case RH_SET_FEATURE
| RH_OTHER
| RH_CLASS
:
1296 case (RH_PORT_SUSPEND
):
1297 WR_RH_PORTSTAT (RH_PS_PSS
); OK (0);
1298 case (RH_PORT_RESET
): /* BUG IN HUP CODE *********/
1299 if (RD_RH_PORTSTAT
& RH_PS_CCS
)
1300 WR_RH_PORTSTAT (RH_PS_PRS
);
1302 case (RH_PORT_POWER
):
1303 WR_RH_PORTSTAT (RH_PS_PPS
);
1306 case (RH_PORT_ENABLE
): /* BUG IN HUP CODE *********/
1307 if (RD_RH_PORTSTAT
& RH_PS_CCS
)
1308 WR_RH_PORTSTAT (RH_PS_PES
);
1313 case RH_SET_ADDRESS
: gohci
.rh
.devnum
= wValue
; OK(0);
1315 case RH_GET_DESCRIPTOR
:
1316 switch ((wValue
& 0xff00) >> 8) {
1317 case (0x01): /* device descriptor */
1318 len
= min_t(unsigned int,
1321 sizeof (root_hub_dev_des
),
1323 data_buf
= root_hub_dev_des
; OK(len
);
1324 case (0x02): /* configuration descriptor */
1325 len
= min_t(unsigned int,
1328 sizeof (root_hub_config_des
),
1330 data_buf
= root_hub_config_des
; OK(len
);
1331 case (0x03): /* string descriptors */
1332 if(wValue
==0x0300) {
1333 len
= min_t(unsigned int,
1336 sizeof (root_hub_str_index0
),
1338 data_buf
= root_hub_str_index0
;
1341 if(wValue
==0x0301) {
1342 len
= min_t(unsigned int,
1345 sizeof (root_hub_str_index1
),
1347 data_buf
= root_hub_str_index1
;
1351 stat
= USB_ST_STALLED
;
1355 case RH_GET_DESCRIPTOR
| RH_CLASS
:
1357 __u32 temp
= roothub_a (&gohci
);
1359 data_buf
[0] = 9; /* min length; */
1360 data_buf
[1] = 0x29;
1361 data_buf
[2] = temp
& RH_A_NDP
;
1362 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1363 data_buf
[2] = (data_buf
[2] == 2) ? 1:0;
1366 if (temp
& RH_A_PSM
) /* per-port power switching? */
1367 data_buf
[3] |= 0x1;
1368 if (temp
& RH_A_NOCP
) /* no overcurrent reporting? */
1369 data_buf
[3] |= 0x10;
1370 else if (temp
& RH_A_OCPM
) /* per-port overcurrent reporting? */
1371 data_buf
[3] |= 0x8;
1373 /* corresponds to data_buf[4-7] */
1375 data_buf
[5] = (temp
& RH_A_POTPGT
) >> 24;
1376 temp
= roothub_b (&gohci
);
1377 data_buf
[7] = temp
& RH_B_DR
;
1378 if (data_buf
[2] < 7) {
1379 data_buf
[8] = 0xff;
1382 data_buf
[8] = (temp
& RH_B_DR
) >> 8;
1383 data_buf
[10] = data_buf
[9] = 0xff;
1386 len
= min_t(unsigned int, leni
,
1387 min_t(unsigned int, data_buf
[0], wLength
));
1391 case RH_GET_CONFIGURATION
: *(__u8
*) data_buf
= 0x01; OK (1);
1393 case RH_SET_CONFIGURATION
: WR_RH_STAT (0x10000); OK (0);
1396 dbg ("unsupported root hub command");
1397 stat
= USB_ST_STALLED
;
1401 ohci_dump_roothub (&gohci
, 1);
1406 len
= min_t(int, len
, leni
);
1407 if (data
!= data_buf
)
1408 memcpy (data
, data_buf
, len
);
1413 pkt_print(NULL
, dev
, pipe
, buffer
, transfer_len
, cmd
, "RET(rh)", 0/*usb_pipein(pipe)*/);
1421 /*-------------------------------------------------------------------------*/
1423 /* common code for handling submit messages - used for all but root hub */
1425 int submit_common_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1426 int transfer_len
, struct devrequest
*setup
, int interval
)
1429 int maxsize
= usb_maxpacket(dev
, pipe
);
1433 urb
= malloc(sizeof(urb_priv_t
));
1434 memset(urb
, 0, sizeof(urb_priv_t
));
1438 urb
->transfer_buffer
= buffer
;
1439 urb
->transfer_buffer_length
= transfer_len
;
1440 urb
->interval
= interval
;
1442 /* device pulled? Shortcut the action. */
1443 if (devgone
== dev
) {
1444 dev
->status
= USB_ST_CRC_ERR
;
1449 urb
->actual_length
= 0;
1450 pkt_print(urb
, dev
, pipe
, buffer
, transfer_len
, setup
, "SUB", usb_pipein(pipe
));
1455 err("submit_common_message: pipesize for pipe %lx is zero",
1460 if (sohci_submit_job(urb
, setup
) < 0) {
1461 err("sohci_submit_job failed");
1467 /* ohci_dump_status(&gohci); */
1470 /* allow more time for a BULK device to react - some are slow */
1471 #define BULK_TO 5000 /* timeout in milliseconds */
1472 if (usb_pipetype (pipe
) == PIPE_BULK
)
1477 /* wait for it to complete */
1479 /* check whether the controller is done */
1480 stat
= hc_interrupt();
1482 stat
= USB_ST_CRC_ERR
;
1486 /* NOTE: since we are not interrupt driven in U-Boot and always
1487 * handle only one URB at a time, we cannot assume the
1488 * transaction finished on the first successful return from
1489 * hc_interrupt().. unless the flag for current URB is set,
1490 * meaning that all TD's to/from device got actually
1491 * transferred and processed. If the current URB is not
1492 * finished we need to re-iterate this loop so as
1493 * hc_interrupt() gets called again as there needs to be some
1494 * more TD's to process still */
1495 if ((stat
>= 0) && (stat
!= 0xff) && (urb
->finished
)) {
1496 /* 0xff is returned for an SF-interrupt */
1506 err("CTL:TIMEOUT ");
1507 dbg("submit_common_msg: TO status %x\n", stat
);
1509 stat
= USB_ST_CRC_ERR
;
1515 dev
->act_len
= transfer_len
;
1518 pkt_print(urb
, dev
, pipe
, buffer
, transfer_len
, setup
, "RET(ctlr)", usb_pipein(pipe
));
1523 /* free TDs in urb_priv */
1524 if (usb_pipetype (pipe
) != PIPE_INTERRUPT
)
1525 urb_free_priv (urb
);
1529 /* submit routines called from usb.c */
1530 int submit_bulk_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1533 info("submit_bulk_msg");
1534 return submit_common_msg(dev
, pipe
, buffer
, transfer_len
, NULL
, 0);
1537 int submit_control_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1538 int transfer_len
, struct devrequest
*setup
)
1540 int maxsize
= usb_maxpacket(dev
, pipe
);
1542 info("submit_control_msg");
1544 pkt_print(NULL
, dev
, pipe
, buffer
, transfer_len
, setup
, "SUB", usb_pipein(pipe
));
1549 err("submit_control_message: pipesize for pipe %lx is zero",
1553 if (((pipe
>> 8) & 0x7f) == gohci
.rh
.devnum
) {
1555 /* root hub - redirect */
1556 return ohci_submit_rh_msg(dev
, pipe
, buffer
, transfer_len
,
1560 return submit_common_msg(dev
, pipe
, buffer
, transfer_len
, setup
, 0);
1563 int submit_int_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
1564 int transfer_len
, int interval
)
1566 info("submit_int_msg");
1567 return submit_common_msg(dev
, pipe
, buffer
, transfer_len
, NULL
,
1571 /*-------------------------------------------------------------------------*
1573 *-------------------------------------------------------------------------*/
1575 /* reset the HC and BUS */
1577 static int hc_reset (ohci_t
*ohci
)
1580 int smm_timeout
= 50; /* 0,5 sec */
1582 dbg("%s\n", __FUNCTION__
);
1584 if (readl (&ohci
->regs
->control
) & OHCI_CTRL_IR
) { /* SMM owns the HC */
1585 writel (OHCI_OCR
, &ohci
->regs
->cmdstatus
); /* request ownership */
1586 info("USB HC TakeOver from SMM");
1587 while (readl (&ohci
->regs
->control
) & OHCI_CTRL_IR
) {
1589 if (--smm_timeout
== 0) {
1590 err("USB HC TakeOver failed!");
1596 /* Disable HC interrupts */
1597 writel (OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
1599 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1601 readl(&ohci
->regs
->control
));
1603 /* Reset USB (needed by some controllers) */
1604 ohci
->hc_control
= 0;
1605 writel (ohci
->hc_control
, &ohci
->regs
->control
);
1607 /* HC Reset requires max 10 us delay */
1608 writel (OHCI_HCR
, &ohci
->regs
->cmdstatus
);
1609 while ((readl (&ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
1610 if (--timeout
== 0) {
1611 err("USB HC reset timed out!");
1619 /*-------------------------------------------------------------------------*/
1621 /* Start an OHCI controller, set the BUS operational
1623 * connect the virtual root hub */
1625 static int hc_start (ohci_t
* ohci
)
1628 unsigned int fminterval
;
1632 /* Tell the controller where the control and bulk lists are
1633 * The lists are empty now. */
1635 writel (0, &ohci
->regs
->ed_controlhead
);
1636 writel (0, &ohci
->regs
->ed_bulkhead
);
1638 writel ((__u32
)ohci
->hcca
, &ohci
->regs
->hcca
); /* a reset clears this */
1640 fminterval
= 0x2edf;
1641 writel ((fminterval
* 9) / 10, &ohci
->regs
->periodicstart
);
1642 fminterval
|= ((((fminterval
- 210) * 6) / 7) << 16);
1643 writel (fminterval
, &ohci
->regs
->fminterval
);
1644 writel (0x628, &ohci
->regs
->lsthresh
);
1646 /* start controller operations */
1647 ohci
->hc_control
= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
1649 writel (ohci
->hc_control
, &ohci
->regs
->control
);
1651 /* disable all interrupts */
1652 mask
= (OHCI_INTR_SO
| OHCI_INTR_WDH
| OHCI_INTR_SF
| OHCI_INTR_RD
|
1653 OHCI_INTR_UE
| OHCI_INTR_FNO
| OHCI_INTR_RHSC
|
1654 OHCI_INTR_OC
| OHCI_INTR_MIE
);
1655 writel (mask
, &ohci
->regs
->intrdisable
);
1656 /* clear all interrupts */
1657 mask
&= ~OHCI_INTR_MIE
;
1658 writel (mask
, &ohci
->regs
->intrstatus
);
1659 /* Choose the interrupts we care about now - but w/o MIE */
1660 mask
= OHCI_INTR_RHSC
| OHCI_INTR_UE
| OHCI_INTR_WDH
| OHCI_INTR_SO
;
1661 writel (mask
, &ohci
->regs
->intrenable
);
1664 /* required for AMD-756 and some Mac platforms */
1665 writel ((roothub_a (ohci
) | RH_A_NPS
) & ~RH_A_PSM
,
1666 &ohci
->regs
->roothub
.a
);
1667 writel (RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
1668 #endif /* OHCI_USE_NPS */
1670 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1671 /* POTPGT delay is bits 24-31, in 2 ms units. */
1672 mdelay ((roothub_a (ohci
) >> 23) & 0x1fe);
1674 /* connect the virtual root hub */
1675 ohci
->rh
.devnum
= 0;
1680 /*-------------------------------------------------------------------------*/
1682 /* Poll USB interrupt. */
1683 void usb_event_poll(void)
1688 /* an interrupt happens */
1690 static int hc_interrupt (void)
1692 ohci_t
*ohci
= &gohci
;
1693 struct ohci_regs
*regs
= ohci
->regs
;
1697 if ((ohci
->hcca
->done_head
!= 0) &&
1698 !(m32_swap (ohci
->hcca
->done_head
) & 0x01)) {
1699 ints
= OHCI_INTR_WDH
;
1700 } else if ((ints
= readl (®s
->intrstatus
)) == ~(u32
)0) {
1702 err ("%s device removed!", ohci
->slot_name
);
1704 } else if ((ints
&= readl (®s
->intrenable
)) == 0) {
1705 dbg("hc_interrupt: returning..\n");
1709 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1711 if (ints
& OHCI_INTR_RHSC
) {
1716 if (ints
& OHCI_INTR_UE
) {
1718 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1720 /* e.g. due to PCI Master/Target Abort */
1723 ohci_dump (ohci
, 1);
1727 /* FIXME: be optimistic, hope that bug won't repeat often. */
1728 /* Make some non-interrupt context restart the controller. */
1729 /* Count and limit the retries though; either hardware or */
1730 /* software errors can go forever... */
1735 if (ints
& OHCI_INTR_WDH
) {
1737 writel (OHCI_INTR_WDH
, ®s
->intrdisable
);
1738 (void)readl (®s
->intrdisable
); /* flush */
1739 stat
= dl_done_list (&gohci
, dl_reverse_done_list (&gohci
));
1740 writel (OHCI_INTR_WDH
, ®s
->intrenable
);
1741 (void)readl (®s
->intrdisable
); /* flush */
1744 if (ints
& OHCI_INTR_SO
) {
1745 dbg("USB Schedule overrun\n");
1746 writel (OHCI_INTR_SO
, ®s
->intrenable
);
1750 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1751 if (ints
& OHCI_INTR_SF
) {
1752 unsigned int frame
= m16_swap (ohci
->hcca
->frame_no
) & 1;
1754 writel (OHCI_INTR_SF
, ®s
->intrdisable
);
1755 if (ohci
->ed_rm_list
[frame
] != NULL
)
1756 writel (OHCI_INTR_SF
, ®s
->intrenable
);
1760 writel (ints
, ®s
->intrstatus
);
1764 /*-------------------------------------------------------------------------*/
1766 /*-------------------------------------------------------------------------*/
1768 /* De-allocate all resources.. */
1770 static void hc_release_ohci (ohci_t
*ohci
)
1772 dbg ("USB HC release ohci usb-%s", ohci
->slot_name
);
1774 if (!ohci
->disabled
)
1778 /*-------------------------------------------------------------------------*/
1781 * low level initalisation routine, called from usb.c
1783 static char ohci_inited
= 0;
1785 int usb_lowlevel_init(void)
1787 #ifdef CONFIG_PCI_OHCI
1791 #ifdef CFG_USB_OHCI_CPU_INIT
1792 /* cpu dependant init */
1797 #ifdef CFG_USB_OHCI_BOARD_INIT
1798 /* board dependant init */
1799 if(usb_board_init())
1802 memset (&gohci
, 0, sizeof (ohci_t
));
1804 /* align the storage */
1805 if ((__u32
)&ghcca
[0] & 0xff) {
1806 err("HCCA not aligned!!");
1810 info("aligned ghcca %p", phcca
);
1811 memset(&ohci_dev
, 0, sizeof(struct ohci_device
));
1812 if ((__u32
)&ohci_dev
.ed
[0] & 0x7) {
1813 err("EDs not aligned!!");
1816 memset(gtd
, 0, sizeof(td_t
) * (NUM_TD
+ 1));
1817 if ((__u32
)gtd
& 0x7) {
1818 err("TDs not aligned!!");
1823 memset (phcca
, 0, sizeof (struct ohci_hcca
));
1828 #ifdef CONFIG_PCI_OHCI
1829 pdev
= pci_find_devices(ohci_pci_ids
, 0);
1834 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vid
);
1835 pci_read_config_word(pdev
, PCI_DEVICE_ID
, &did
);
1836 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1837 vid
, did
, (pdev
>> 16) & 0xff,
1838 (pdev
>> 11) & 0x1f, (pdev
>> 8) & 0x7);
1839 pci_read_config_dword(pdev
, PCI_BASE_ADDRESS_0
, &base
);
1840 printf("OHCI regs address 0x%08x\n", base
);
1841 gohci
.regs
= (struct ohci_regs
*)base
;
1845 gohci
.regs
= (struct ohci_regs
*)CFG_USB_OHCI_REGS_BASE
;
1849 gohci
.slot_name
= CFG_USB_OHCI_SLOT_NAME
;
1851 if (hc_reset (&gohci
) < 0) {
1852 hc_release_ohci (&gohci
);
1853 err ("can't reset usb-%s", gohci
.slot_name
);
1854 #ifdef CFG_USB_OHCI_BOARD_INIT
1855 /* board dependant cleanup */
1856 usb_board_init_fail();
1859 #ifdef CFG_USB_OHCI_CPU_INIT
1860 /* cpu dependant cleanup */
1861 usb_cpu_init_fail();
1866 /* FIXME this is a second HC reset; why?? */
1867 /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1869 if (hc_start (&gohci
) < 0) {
1870 err ("can't start usb-%s", gohci
.slot_name
);
1871 hc_release_ohci (&gohci
);
1872 /* Initialization failed */
1873 #ifdef CFG_USB_OHCI_BOARD_INIT
1874 /* board dependant cleanup */
1878 #ifdef CFG_USB_OHCI_CPU_INIT
1879 /* cpu dependant cleanup */
1886 ohci_dump (&gohci
, 1);
1894 int usb_lowlevel_stop(void)
1896 /* this gets called really early - before the controller has */
1897 /* even been initialized! */
1900 /* TODO release any interrupts, etc. */
1901 /* call hc_release_ohci() here ? */
1904 #ifdef CFG_USB_OHCI_BOARD_INIT
1905 /* board dependant cleanup */
1906 if(usb_board_stop())
1910 #ifdef CFG_USB_OHCI_CPU_INIT
1911 /* cpu dependant cleanup */
1918 #endif /* CONFIG_USB_OHCI_NEW */