1 // SPDX-License-Identifier: GPL-2.0
3 * From coreboot src/soc/intel/broadwell/igd.c
5 * Copyright (C) 2016 Google, Inc
10 #include <bootstage.h>
17 #include <asm/global_data.h>
18 #include <asm/intel_regs.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/iomap.h>
23 #include <asm/arch/pch.h>
24 #include <linux/delay.h>
27 struct broadwell_igd_priv
{
31 struct broadwell_igd_plat
{
36 int power_backlight_on_delay
;
38 int power_backlight_off_delay
;
39 int power_cycle_delay
;
43 int pre_graphics_delay
;
47 #define GT_CDCLK_337 0
48 #define GT_CDCLK_450 1
49 #define GT_CDCLK_540 2
50 #define GT_CDCLK_675 3
52 u32
board_map_oprom_vendev(u32 vendev
)
54 return SA_IGD_OPROM_VENDEV
;
57 static int poll32(u8
*addr
, uint mask
, uint value
)
62 debug("%s: addr %p = %x\n", __func__
, addr
, readl(addr
));
63 while ((readl(addr
) & mask
) != value
) {
64 if (get_timer(start
) > GT_RETRY
) {
65 debug("poll32: timeout: %x\n", readl(addr
));
73 static int haswell_early_init(struct udevice
*dev
)
75 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
76 u8
*regs
= priv
->regs
;
79 /* Enable Force Wake */
80 writel(0x00000020, regs
+ 0xa180);
81 writel(0x00010001, regs
+ 0xa188);
82 ret
= poll32(regs
+ 0x130044, 1, 1);
87 setbits_le32(regs
+ 0xa248, 0x00000016);
89 /* GFXPAUSE settings */
90 writel(0x00070020, regs
+ 0xa000);
93 clrsetbits_le32(regs
+ 0xa180, ~0xff3fffff, 0x15000000);
95 /* Enable DOP Clock Gating */
96 writel(0x000003fd, regs
+ 0x9424);
98 /* Enable Unit Level Clock Gating */
99 writel(0x00000080, regs
+ 0x9400);
100 writel(0x40401000, regs
+ 0x9404);
101 writel(0x00000000, regs
+ 0x9408);
102 writel(0x02000001, regs
+ 0x940c);
108 /* Wake Rate Limits */
109 setbits_le32(regs
+ 0xa090, 0x00000000);
110 setbits_le32(regs
+ 0xa098, 0x03e80000);
111 setbits_le32(regs
+ 0xa09c, 0x00280000);
112 setbits_le32(regs
+ 0xa0a8, 0x0001e848);
113 setbits_le32(regs
+ 0xa0ac, 0x00000019);
115 /* Render/Video/Blitter Idle Max Count */
116 writel(0x0000000a, regs
+ 0x02054);
117 writel(0x0000000a, regs
+ 0x12054);
118 writel(0x0000000a, regs
+ 0x22054);
119 writel(0x0000000a, regs
+ 0x1a054);
121 /* RC Sleep / RCx Thresholds */
122 setbits_le32(regs
+ 0xa0b0, 0x00000000);
123 setbits_le32(regs
+ 0xa0b4, 0x000003e8);
124 setbits_le32(regs
+ 0xa0b8, 0x0000c350);
127 setbits_le32(regs
+ 0xa010, 0x000f4240);
128 setbits_le32(regs
+ 0xa014, 0x12060000);
129 setbits_le32(regs
+ 0xa02c, 0x0000e808);
130 setbits_le32(regs
+ 0xa030, 0x0003bd08);
131 setbits_le32(regs
+ 0xa068, 0x000101d0);
132 setbits_le32(regs
+ 0xa06c, 0x00055730);
133 setbits_le32(regs
+ 0xa070, 0x0000000a);
136 writel(0x00000b92, regs
+ 0xa024);
139 writel(0x88040000, regs
+ 0xa090);
141 /* Video Frequency Request */
142 writel(0x08000000, regs
+ 0xa00c);
145 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
148 writel(0, regs
+ 0x138128);
149 writel(0x80000004, regs
+ 0x138124);
150 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
154 /* Enable PM Interrupts */
155 writel(0x03000076, regs
+ 0x4402c);
157 /* Enable RC6 in idle */
158 writel(0x00040000, regs
+ 0xa094);
162 debug("%s: ret=%d\n", __func__
, ret
);
166 static int haswell_late_init(struct udevice
*dev
)
168 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
169 u8
*regs
= priv
->regs
;
173 setbits_le32(regs
+ 0x0a248, (1 << 31));
174 setbits_le32(regs
+ 0x0a004, (1 << 4));
175 setbits_le32(regs
+ 0x0a080, (1 << 2));
176 setbits_le32(regs
+ 0x0a180, (1 << 31));
178 /* Disable Force Wake */
179 writel(0x00010000, regs
+ 0xa188);
180 ret
= poll32(regs
+ 0x130044, 1, 0);
183 writel(0x00000001, regs
+ 0xa188);
185 /* Enable power well for DP and Audio */
186 setbits_le32(regs
+ 0x45400, (1 << 31));
187 ret
= poll32(regs
+ 0x45400, 1 << 30, 1 << 30);
193 debug("%s: ret=%d\n", __func__
, ret
);
197 static int broadwell_early_init(struct udevice
*dev
)
199 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
200 u8
*regs
= priv
->regs
;
203 /* Enable Force Wake */
204 writel(0x00010001, regs
+ 0xa188);
205 ret
= poll32(regs
+ 0x130044, 1, 1);
209 /* Enable push bus metric control and shift */
210 writel(0x00000004, regs
+ 0xa248);
211 writel(0x000000ff, regs
+ 0xa250);
212 writel(0x00000010, regs
+ 0xa25c);
214 /* GFXPAUSE settings (set based on stepping) */
217 writel(0x45200000, regs
+ 0xa180);
219 /* Enable DOP Clock Gating */
220 writel(0x000000fd, regs
+ 0x9424);
222 /* Enable Unit Level Clock Gating */
223 writel(0x00000000, regs
+ 0x9400);
224 writel(0x40401000, regs
+ 0x9404);
225 writel(0x00000000, regs
+ 0x9408);
226 writel(0x02000001, regs
+ 0x940c);
227 writel(0x0000000a, regs
+ 0x1a054);
229 /* Video Frequency Request */
230 writel(0x08000000, regs
+ 0xa00c);
232 writel(0x00000009, regs
+ 0x138158);
233 writel(0x0000000d, regs
+ 0x13815c);
239 /* Wake Rate Limits */
240 clrsetbits_le32(regs
+ 0x0a090, ~0, 0);
241 setbits_le32(regs
+ 0x0a098, 0x03e80000);
242 setbits_le32(regs
+ 0x0a09c, 0x00280000);
243 setbits_le32(regs
+ 0x0a0a8, 0x0001e848);
244 setbits_le32(regs
+ 0x0a0ac, 0x00000019);
246 /* Render/Video/Blitter Idle Max Count */
247 writel(0x0000000a, regs
+ 0x02054);
248 writel(0x0000000a, regs
+ 0x12054);
249 writel(0x0000000a, regs
+ 0x22054);
251 /* RC Sleep / RCx Thresholds */
252 setbits_le32(regs
+ 0x0a0b0, 0x00000000);
253 setbits_le32(regs
+ 0x0a0b8, 0x00000271);
256 setbits_le32(regs
+ 0x0a010, 0x000f4240);
257 setbits_le32(regs
+ 0x0a014, 0x12060000);
258 setbits_le32(regs
+ 0x0a02c, 0x0000e808);
259 setbits_le32(regs
+ 0x0a030, 0x0003bd08);
260 setbits_le32(regs
+ 0x0a068, 0x000101d0);
261 setbits_le32(regs
+ 0x0a06c, 0x00055730);
262 setbits_le32(regs
+ 0x0a070, 0x0000000a);
263 setbits_le32(regs
+ 0x0a168, 0x00000006);
266 writel(0x00000b92, regs
+ 0xa024);
269 writel(0x90040000, regs
+ 0xa090);
272 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
275 writel(0, regs
+ 0x138128);
276 writel(0x80000004, regs
+ 0x138124);
277 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
281 /* Enable PM Interrupts */
282 writel(0x03000076, regs
+ 0x4402c);
284 /* Enable RC6 in idle */
285 writel(0x00040000, regs
+ 0xa094);
289 debug("%s: ret=%d\n", __func__
, ret
);
293 static int broadwell_late_init(struct udevice
*dev
)
295 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
296 u8
*regs
= priv
->regs
;
300 setbits_le32(regs
+ 0x0a248, 1 << 31);
301 setbits_le32(regs
+ 0x0a000, 1 << 18);
302 setbits_le32(regs
+ 0x0a180, 1 << 31);
304 /* Disable Force Wake */
305 writel(0x00010000, regs
+ 0xa188);
306 ret
= poll32(regs
+ 0x130044, 1, 0);
310 /* Enable power well for DP and Audio */
311 setbits_le32(regs
+ 0x45400, 1 << 31);
312 ret
= poll32(regs
+ 0x45400, 1 << 30, 1 << 30);
318 debug("%s: ret=%d\n", __func__
, ret
);
323 static unsigned long gtt_read(struct broadwell_igd_priv
*priv
,
326 return readl(priv
->regs
+ reg
);
329 static void gtt_write(struct broadwell_igd_priv
*priv
, unsigned long reg
,
332 writel(data
, priv
->regs
+ reg
);
335 static inline void gtt_clrsetbits(struct broadwell_igd_priv
*priv
, u32 reg
,
338 clrsetbits_le32(priv
->regs
+ reg
, bic
, or);
341 static int gtt_poll(struct broadwell_igd_priv
*priv
, u32 reg
, u32 mask
,
344 unsigned try = GT_RETRY
;
348 data
= gtt_read(priv
, reg
);
349 if ((data
& mask
) == value
)
354 debug("GT init timeout\n");
358 static void igd_setup_panel(struct udevice
*dev
)
360 struct broadwell_igd_plat
*plat
= dev_get_plat(dev
);
361 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
364 /* Setup Digital Port Hotplug */
365 reg32
= (plat
->dp_hotplug
[0] & 0x7) << 2;
366 reg32
|= (plat
->dp_hotplug
[1] & 0x7) << 10;
367 reg32
|= (plat
->dp_hotplug
[2] & 0x7) << 18;
368 gtt_write(priv
, PCH_PORT_HOTPLUG
, reg32
);
370 /* Setup Panel Power On Delays */
371 reg32
= (plat
->port_select
& 0x3) << 30;
372 reg32
|= (plat
->power_up_delay
& 0x1fff) << 16;
373 reg32
|= (plat
->power_backlight_on_delay
& 0x1fff);
374 gtt_write(priv
, PCH_PP_ON_DELAYS
, reg32
);
376 /* Setup Panel Power Off Delays */
377 reg32
= (plat
->power_down_delay
& 0x1fff) << 16;
378 reg32
|= (plat
->power_backlight_off_delay
& 0x1fff);
379 gtt_write(priv
, PCH_PP_OFF_DELAYS
, reg32
);
381 /* Setup Panel Power Cycle Delay */
382 if (plat
->power_cycle_delay
) {
383 reg32
= gtt_read(priv
, PCH_PP_DIVISOR
);
385 reg32
|= plat
->power_cycle_delay
& 0xff;
386 gtt_write(priv
, PCH_PP_DIVISOR
, reg32
);
389 /* Enable Backlight if needed */
390 if (plat
->cpu_backlight
) {
391 gtt_write(priv
, BLC_PWM_CPU_CTL2
, BLC_PWM2_ENABLE
);
392 gtt_write(priv
, BLC_PWM_CPU_CTL
, plat
->cpu_backlight
);
394 if (plat
->pch_backlight
) {
395 gtt_write(priv
, BLC_PWM_PCH_CTL1
, BLM_PCH_PWM_ENABLE
);
396 gtt_write(priv
, BLC_PWM_PCH_CTL2
, plat
->pch_backlight
);
400 static int igd_cdclk_init_haswell(struct udevice
*dev
)
402 struct broadwell_igd_plat
*plat
= dev_get_plat(dev
);
403 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
404 int cdclk
= plat
->cdclk
;
410 dm_pci_read_config16(dev
, PCI_DEVICE_ID
, &devid
);
412 /* Check for ULX GT1 or GT2 */
413 if (devid
== 0x0a0e || devid
== 0x0a1e)
416 /* 675MHz is not supported on haswell */
417 if (cdclk
== GT_CDCLK_675
)
418 cdclk
= GT_CDCLK_337
;
420 /* If CD clock is fixed or ULT then set to 450MHz */
421 if ((gtt_read(priv
, 0x42014) & 0x1000000) || cpu_is_ult())
422 cdclk
= GT_CDCLK_450
;
424 /* 540MHz is not supported on ULX */
425 if (gpu_is_ulx
&& cdclk
== GT_CDCLK_540
)
426 cdclk
= GT_CDCLK_337
;
428 /* 337.5MHz is not supported on non-ULT/ULX */
429 if (!gpu_is_ulx
&& !cpu_is_ult() && cdclk
== GT_CDCLK_337
)
430 cdclk
= GT_CDCLK_450
;
432 /* Set variables based on CD Clock setting */
451 /* Set LPCLL_CTL CD Clock Frequency Select */
452 gtt_clrsetbits(priv
, 0x130040, ~0xf3ffffff, lpcll
);
454 /* ULX: Inform power controller of selected frequency */
456 if (cdclk
== GT_CDCLK_450
)
457 gtt_write(priv
, 0x138128, 0x00000000); /* 450MHz */
459 gtt_write(priv
, 0x138128, 0x00000001); /* 337.5MHz */
460 gtt_write(priv
, 0x13812c, 0x00000000);
461 gtt_write(priv
, 0x138124, 0x80000017);
464 /* Set CPU DP AUX 2X bit clock dividers */
465 gtt_clrsetbits(priv
, 0x64010, ~0xfffff800, dpdiv
);
466 gtt_clrsetbits(priv
, 0x64810, ~0xfffff800, dpdiv
);
470 debug("%s: ret=%d\n", __func__
, ret
);
474 static int igd_cdclk_init_broadwell(struct udevice
*dev
)
476 struct broadwell_igd_plat
*plat
= dev_get_plat(dev
);
477 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
478 int cdclk
= plat
->cdclk
;
479 u32 dpdiv
, lpcll
, pwctl
, cdset
;
482 /* Inform power controller of upcoming frequency change */
483 gtt_write(priv
, 0x138128, 0);
484 gtt_write(priv
, 0x13812c, 0);
485 gtt_write(priv
, 0x138124, 0x80000018);
487 /* Poll GT driver mailbox for run/busy clear */
488 if (gtt_poll(priv
, 0x138124, 1 << 31, 0 << 31))
489 cdclk
= GT_CDCLK_450
;
491 if (gtt_read(priv
, 0x42014) & 0x1000000) {
492 /* If CD clock is fixed then set to 450MHz */
493 cdclk
= GT_CDCLK_450
;
495 /* Program CD clock to highest supported freq */
497 cdclk
= GT_CDCLK_540
;
499 cdclk
= GT_CDCLK_675
;
502 /* CD clock frequency 675MHz not supported on ULT */
503 if (cpu_is_ult() && cdclk
== GT_CDCLK_675
)
504 cdclk
= GT_CDCLK_540
;
506 /* Set variables based on CD Clock setting */
528 lpcll
= (1 << 26) | (1 << 27);
536 debug("%s: frequency = %d\n", __func__
, cdclk
);
538 /* Set LPCLL_CTL CD Clock Frequency Select */
539 gtt_clrsetbits(priv
, 0x130040, ~0xf3ffffff, lpcll
);
541 /* Inform power controller of selected frequency */
542 gtt_write(priv
, 0x138128, pwctl
);
543 gtt_write(priv
, 0x13812c, 0);
544 gtt_write(priv
, 0x138124, 0x80000017);
546 /* Program CD Clock Frequency */
547 gtt_clrsetbits(priv
, 0x46200, ~0xfffffc00, cdset
);
549 /* Set CPU DP AUX 2X bit clock dividers */
550 gtt_clrsetbits(priv
, 0x64010, ~0xfffff800, dpdiv
);
551 gtt_clrsetbits(priv
, 0x64810, ~0xfffff800, dpdiv
);
555 debug("%s: ret=%d\n", __func__
, ret
);
559 u8
systemagent_revision(struct udevice
*bus
)
563 pci_bus_read_config(bus
, PCI_BDF(0, 0, 0), PCI_REVISION_ID
, &val
,
569 static int igd_pre_init(struct udevice
*dev
, bool is_broadwell
)
571 struct broadwell_igd_plat
*plat
= dev_get_plat(dev
);
572 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
576 mdelay(plat
->pre_graphics_delay
);
578 /* Early init steps */
580 ret
= broadwell_early_init(dev
);
584 /* Set GFXPAUSE based on stepping */
585 if (cpu_get_stepping() <= (CPUID_BROADWELL_E0
& 0xf) &&
586 systemagent_revision(pci_get_controller(dev
)) <= 9) {
587 gtt_write(priv
, 0xa000, 0x300ff);
589 gtt_write(priv
, 0xa000, 0x30020);
592 ret
= haswell_early_init(dev
);
597 /* Set RP1 graphics frequency */
598 rp1_gfx_freq
= (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
599 gtt_write(priv
, 0xa008, rp1_gfx_freq
<< 24);
601 /* Post VBIOS panel setup */
602 igd_setup_panel(dev
);
606 debug("%s: ret=%d\n", __func__
, ret
);
610 static int igd_post_init(struct udevice
*dev
, bool is_broadwell
)
614 /* Late init steps */
616 ret
= igd_cdclk_init_broadwell(dev
);
619 ret
= broadwell_late_init(dev
);
623 igd_cdclk_init_haswell(dev
);
624 ret
= haswell_late_init(dev
);
632 static int broadwell_igd_int15_handler(void)
636 debug("%s: INT15 function %04x!\n", __func__
, M
.x86
.R_AX
);
638 switch (M
.x86
.R_AX
) {
641 * Boot Display Device Hook:
652 M
.x86
.R_CX
= 0x0000; /* Use video bios default */
656 debug("Unknown INT15 function %04x!\n", M
.x86
.R_AX
);
663 static int broadwell_igd_probe(struct udevice
*dev
)
665 struct video_uc_plat
*plat
= dev_get_uclass_plat(dev
);
666 struct video_priv
*uc_priv
= dev_get_uclass_priv(dev
);
671 if (!ll_boot_init()) {
673 * If we are running from EFI or coreboot, this driver can't
676 printf("Not available (previous bootloader prevents it)\n");
679 is_broadwell
= cpu_get_family_model() == BROADWELL_FAMILY_ULT
;
680 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD
, "vesa display");
681 debug("%s: is_broadwell=%d\n", __func__
, is_broadwell
);
682 ret
= igd_pre_init(dev
, is_broadwell
);
684 ret
= vesa_setup_video(dev
, broadwell_igd_int15_handler
);
686 debug("failed to run video BIOS: %d\n", ret
);
689 ret
= igd_post_init(dev
, is_broadwell
);
690 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD
);
694 /* Use write-combining for the graphics memory, 256MB */
695 fbbase
= IS_ENABLED(CONFIG_VIDEO_COPY
) ? plat
->copy_base
: plat
->base
;
696 ret
= mtrr_set_next_var(MTRR_TYPE_WRCOMB
, fbbase
, 256 << 20);
698 printf("Failed to add MTRR: Display will be slow (err %d)\n", ret
);
700 debug("fb=%lx, size %x, display size=%d %d %d\n", plat
->base
,
701 plat
->size
, uc_priv
->xsize
, uc_priv
->ysize
, uc_priv
->bpix
);
706 static int broadwell_igd_of_to_plat(struct udevice
*dev
)
708 struct broadwell_igd_plat
*plat
= dev_get_plat(dev
);
709 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
710 int node
= dev_of_offset(dev
);
711 const void *blob
= gd
->fdt_blob
;
713 if (fdtdec_get_int_array(blob
, node
, "intel,dp-hotplug",
715 ARRAY_SIZE(plat
->dp_hotplug
)))
717 plat
->port_select
= fdtdec_get_int(blob
, node
, "intel,port-select", 0);
718 plat
->power_cycle_delay
= fdtdec_get_int(blob
, node
,
719 "intel,power-cycle-delay", 0);
720 plat
->power_up_delay
= fdtdec_get_int(blob
, node
,
721 "intel,power-up-delay", 0);
722 plat
->power_down_delay
= fdtdec_get_int(blob
, node
,
723 "intel,power-down-delay", 0);
724 plat
->power_backlight_on_delay
= fdtdec_get_int(blob
, node
,
725 "intel,power-backlight-on-delay", 0);
726 plat
->power_backlight_off_delay
= fdtdec_get_int(blob
, node
,
727 "intel,power-backlight-off-delay", 0);
728 plat
->cpu_backlight
= fdtdec_get_int(blob
, node
,
729 "intel,cpu-backlight", 0);
730 plat
->pch_backlight
= fdtdec_get_int(blob
, node
,
731 "intel,pch-backlight", 0);
732 plat
->pre_graphics_delay
= fdtdec_get_int(blob
, node
,
733 "intel,pre-graphics-delay", 0);
734 priv
->regs
= (u8
*)dm_pci_read_bar32(dev
, 0);
735 debug("%s: regs at %p\n", __func__
, priv
->regs
);
736 debug("dp_hotplug %d %d %d\n", plat
->dp_hotplug
[0], plat
->dp_hotplug
[1],
737 plat
->dp_hotplug
[2]);
738 debug("port_select = %d\n", plat
->port_select
);
739 debug("power_up_delay = %d\n", plat
->power_up_delay
);
740 debug("power_backlight_on_delay = %d\n",
741 plat
->power_backlight_on_delay
);
742 debug("power_down_delay = %d\n", plat
->power_down_delay
);
743 debug("power_backlight_off_delay = %d\n",
744 plat
->power_backlight_off_delay
);
745 debug("power_cycle_delay = %d\n", plat
->power_cycle_delay
);
746 debug("cpu_backlight = %x\n", plat
->cpu_backlight
);
747 debug("pch_backlight = %x\n", plat
->pch_backlight
);
748 debug("cdclk = %d\n", plat
->cdclk
);
749 debug("pre_graphics_delay = %d\n", plat
->pre_graphics_delay
);
754 static int broadwell_igd_bind(struct udevice
*dev
)
756 struct video_uc_plat
*uc_plat
= dev_get_uclass_plat(dev
);
758 /* Set the maximum supported resolution */
759 uc_plat
->size
= 2560 * 1600 * 4;
760 log_debug("%s: Frame buffer size %x\n", __func__
, uc_plat
->size
);
765 static const struct video_ops broadwell_igd_ops
= {
768 static const struct udevice_id broadwell_igd_ids
[] = {
769 { .compatible
= "intel,broadwell-igd" },
773 U_BOOT_DRIVER(broadwell_igd
) = {
774 .name
= "broadwell_igd",
776 .of_match
= broadwell_igd_ids
,
777 .ops
= &broadwell_igd_ops
,
778 .of_to_plat
= broadwell_igd_of_to_plat
,
779 .bind
= broadwell_igd_bind
,
780 .probe
= broadwell_igd_probe
,
781 .priv_auto
= sizeof(struct broadwell_igd_priv
),
782 .plat_auto
= sizeof(struct broadwell_igd_plat
),