1 /* ported from ctfb.c (linux kernel):
2 * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
5 * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include "videomodes.h"
38 #define PRINTF(fmt,args...) printf (fmt ,##args)
40 #define PRINTF(fmt,args...)
45 #define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
48 #define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
51 #error "term minmax already used."
53 #define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
54 #define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
56 /* CT Register Offsets */
57 #define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
58 #define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
59 #define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
60 #define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
61 #define CT_XR_O 0x3d6 /* Extended Register index */
62 #define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
63 #define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
64 #define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
65 #define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
66 #define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
67 #define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
69 #define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
70 #define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
72 /* defines for the memory mapped registers */
73 #define BR00_o 0x400000 /* Source and Destination Span Register */
74 #define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
75 #define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
76 #define BR03_o 0x40000C /* Monochrome Source Control Register */
77 #define BR04_o 0x400010 /* BitBLT Control Register */
78 #define BR05_o 0x400014 /* Pattern Address Registe */
79 #define BR06_o 0x400018 /* Source Address Register */
80 #define BR07_o 0x40001C /* Destination Address Register */
81 #define BR08_o 0x400020 /* Destination Width & Height Register */
82 #define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
83 #define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
85 #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
86 #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
87 #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
88 #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
90 /* Some Mode definitions */
91 #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
92 #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
93 #define FB_SYNC_EXT 4 /* external sync */
94 #define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
95 #define FB_SYNC_BROADCAST 16 /* broadcast video timings */
96 /* vtotal = 144d/288n/576i => PAL */
97 /* vtotal = 121d/242n/484i => NTSC */
98 #define FB_SYNC_ON_GREEN 32 /* sync on green */
100 #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
101 #define FB_VMODE_INTERLACED 1 /* interlaced */
102 #define FB_VMODE_DOUBLE 2 /* double scan */
103 #define FB_VMODE_MASK 255
105 #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
106 #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
107 #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
112 /* table for VGA Initialization */
114 const unsigned char reg
;
115 const unsigned char val
;
118 /* this table provides some basic initialisations such as Memory Clock etc */
119 static CT_CFG_TABLE xreg
[] = {
120 {0x09, 0x01}, /* CRT Controller Extensions Enable */
121 {0x0A, 0x02}, /* Frame Buffer Mapping */
122 {0x0B, 0x01}, /* PCI Write Burst support */
123 {0x20, 0x00}, /* BitBLT Configuration */
124 {0x40, 0x03}, /* Memory Access Control */
125 {0x60, 0x00}, /* Video Pin Control */
126 {0x61, 0x00}, /* DPMS Synch control */
127 {0x62, 0x00}, /* GPIO Pin Control */
128 {0x63, 0xBD}, /* GPIO Pin Data */
129 {0x67, 0x00}, /* Pin Tri-State */
130 {0x80, 0x80}, /* Pixel Pipeline Config 0 register */
131 {0xA0, 0x00}, /* Cursor 1 Control Reg */
132 {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
133 {0xA2, 0x00}, /* Cursor 1 Base Address Low */
134 {0xA3, 0x00}, /* Cursor 1 Base Address High */
135 {0xA4, 0x00}, /* Cursor 1 X-Position Low */
136 {0xA5, 0x00}, /* Cursor 1 X-Position High */
137 {0xA6, 0x00}, /* Cursor 1 Y-Position Low */
138 {0xA7, 0x00}, /* Cursor 1 Y-Position High */
139 {0xA8, 0x00}, /* Cursor 2 Control Reg */
140 {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
141 {0xAA, 0x00}, /* Cursor 2 Base Address Low */
142 {0xAB, 0x00}, /* Cursor 2 Base Address High */
143 {0xAC, 0x00}, /* Cursor 2 X-Position Low */
144 {0xAD, 0x00}, /* Cursor 2 X-Position High */
145 {0xAE, 0x00}, /* Cursor 2 Y-Position Low */
146 {0xAF, 0x00}, /* Cursor 2 Y-Position High */
147 {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
148 {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
149 {0xC3, 0x34}, /* Dot Clock 0 Divisor select */
150 {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
151 {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
152 {0xC7, 0x24}, /* Dot Clock 1 Divisor select */
153 {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
154 {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
155 {0xCB, 0x34}, /* Dot Clock 2 Divisor select */
156 {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
157 {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
158 {0xCE, 0x90}, /* Memory Clock 0 Divisor select */
159 {0xCF, 0x06}, /* Clock Config */
160 {0xD0, 0x0F}, /* Power Down */
161 {0xD1, 0x01}, /* Power Down BitBLT */
162 {0xFF, 0xFF} /* end of table */
169 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
170 * They are encoded as follows:
172 * +---+--------------+
173 * | 2 | Loop Divisor |
174 * +---+--------------+
176 * +---+--------------+
178 * +---+--------------+
179 * Note: The Memory Clock does not have a Loop Divisor.
180 * +---+---+---+--------------+
181 * | 6 | 5 | 4 | Post Divisor |
182 * +---+---+---+--------------+
184 * +---+---+---+--------------+
186 * +---+---+---+--------------+
188 * +---+---+---+--------------+
190 * +---+---+---+--------------+
192 * +---+---+---+--------------+
194 * +---+---+---+--------------+
195 * | 1 | 1 | X | reserved |
196 * +---+---+---+--------------+
198 * All other bits are reserved in these registers.
200 * Clock VCO M Registers:
201 * ----------------------
202 * These Registers contain the M Value -2.
204 * Clock VCO N Registers:
205 * ----------------------
206 * These Registers contain the N Value -2.
210 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
211 * Fout = Fvco / Post Divisor
213 * Dot Clk0 (default 25MHz):
214 * -------------------------
215 * Fvco = 14.318 * 127 / 9 = 202.045MHz
216 * Fout = 202.045MHz / 8 = 25.25MHz
219 * XRC0 = (M - 2) = 125 = 0x7D
220 * XRC1 = (N - 2) = 7 = 0x07
223 * Dot Clk1 (default 28MHz):
224 * -------------------------
225 * Fvco = 14.318 * 87 / 11 = 113.24MHz
226 * Fout = 113.24MHz / 4 = 28.31MHz
229 * XRC4 = (M - 2) = 85 = 0x55
230 * XRC5 = (N - 2) = 9 = 0x09
233 * Dot Clk2 (variable for extended modes set to 25MHz):
234 * ----------------------------------------------------
235 * Fvco = 14.318 * 127 / 9 = 202.045MHz
236 * Fout = 202.045MHz / 8 = 25.25MHz
239 * XRC8 = (M - 2) = 125 = 0x7D
240 * XRC9 = (N - 2) = 7 = 0x07
243 * Memory Clk for most modes >50MHz:
244 * ----------------------------------
245 * Fvco = 14.318 * 58 / 5 = 166MHz
246 * Fout = 166MHz / 2 = 83MHz
248 * XRCC = (M - 2) = 57 = 0x38
249 * XRCD = (N - 2) = 3 = 0x03
252 * Note Bit7 enables the clock source from the VCO
256 /*******************************************************************
258 *******************************************************************/
259 struct ctfb_chips_properties
{
260 int device_id
; /* PCI Device ID */
261 unsigned long max_mem
; /* memory for frame buffer */
262 int vld_set
; /* value of VLD if bit2 in clock control is set */
263 int vld_not_set
; /* value of VLD if bit2 in clock control is set */
264 int mn_diff
; /* difference between M/N Value + mn_diff = M/N Register */
265 int mn_min
; /* min value of M/N Value */
266 int mn_max
; /* max value of M/N Value */
267 int vco_min
; /* VCO Min in MHz */
268 int vco_max
; /* VCO Max in MHz */
271 static const struct ctfb_chips_properties chips
[] = {
272 {PCI_DEVICE_ID_CT_69000
, 0x200000, 1, 4, -2, 3, 257, 100, 220},
273 #ifdef CONFIG_USE_CPCIDVI
274 {PCI_DEVICE_ID_CT_69030
, 0x400000, 1, 4, -2, 3, 257, 100, 220},
276 {PCI_DEVICE_ID_CT_65555
, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
277 {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
285 /*******************************************************************************
290 /*******************************************************************************
292 * Read CT ISA register
296 ctRead (unsigned short index
)
298 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
299 if (index
== CT_AR_O
)
300 /* synch the Flip Flop */
301 in8 (pGD
->isaBase
+ CT_STATUS_REG1_O
);
303 return (in8 (pGD
->isaBase
+ index
));
306 /*******************************************************************************
308 * Write CT ISA register
311 ctWrite (unsigned short index
, unsigned char val
)
313 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
315 out8 ((pGD
->isaBase
+ index
), val
);
318 /*******************************************************************************
320 * Read CT ISA register indexed
323 ctRead_i (unsigned short index
, char reg
)
325 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
326 if (index
== CT_AR_O
)
327 /* synch the Flip Flop */
328 in8 (pGD
->isaBase
+ CT_STATUS_REG1_O
);
329 out8 ((pGD
->isaBase
+ index
), reg
);
330 return (in8 (pGD
->isaBase
+ index
+ 1));
333 /*******************************************************************************
335 * Write CT ISA register indexed
338 ctWrite_i (unsigned short index
, char reg
, char val
)
340 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
341 if (index
== CT_AR_O
) {
342 /* synch the Flip Flop */
343 in8 (pGD
->isaBase
+ CT_STATUS_REG1_O
);
344 out8 ((pGD
->isaBase
+ index
), reg
);
345 out8 ((pGD
->isaBase
+ index
), val
);
347 out8 ((pGD
->isaBase
+ index
), reg
);
348 out8 ((pGD
->isaBase
+ index
+ 1), val
);
352 /*******************************************************************************
354 * Write a table of CT ISA register
357 ctLoadRegs (unsigned short index
, CT_CFG_TABLE
* regTab
)
359 while (regTab
->reg
!= 0xFF) {
360 ctWrite_i (index
, regTab
->reg
, regTab
->val
);
365 /*****************************************************************************/
371 for (i
= 0; i
< 0x10; i
++)
372 ctWrite_i (CT_AR_O
, i
, i
);
378 ctWrite_i (CT_AR_O
, 0x10, tmp
); /* Mode Control Register */
379 ctWrite_i (CT_AR_O
, 0x11, 0x00); /* Overscan Color Register */
380 ctWrite_i (CT_AR_O
, 0x12, 0x0f); /* Memory Plane Enable Register */
385 ctWrite_i (CT_AR_O
, 0x13, tmp
); /* Horizontal Pixel Panning */
386 ctWrite_i (CT_AR_O
, 0x14, 0x00); /* Color Select Register */
387 ctWrite (CT_AR_O
, 0x20); /* enable video */
390 /*****************************************************************************/
393 { /* Set Graphics Mode */
396 for (i
= 0; i
< 0x05; i
++)
397 ctWrite_i (CT_GR_O
, i
, 0);
399 ctWrite_i (CT_GR_O
, 0x05, 0x10);
400 ctWrite_i (CT_GR_O
, 0x06, 0x02);
402 ctWrite_i (CT_GR_O
, 0x05, 0x40);
403 ctWrite_i (CT_GR_O
, 0x06, 0x05);
405 ctWrite_i (CT_GR_O
, 0x07, 0x0f);
406 ctWrite_i (CT_GR_O
, 0x08, 0xff);
409 /*****************************************************************************/
415 ctWrite_i (CT_SR_O
, 0x00, 0x00); /* reset */
416 /*rr( sr, 0x01, tmp );
417 if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
418 wr( sr, 0x01, tmp ); */
420 ctWrite_i (CT_SR_O
, 0x01, 0x01); /* Clocking Mode Register */
422 ctWrite_i (CT_SR_O
, 0x01, 0x00); /* Clocking Mode Register */
423 ctWrite_i (CT_SR_O
, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
424 ctWrite_i (CT_SR_O
, 0x03, 0x00); /* Character Map Select Register */
429 ctWrite_i (CT_SR_O
, 0x04, tmp
); /* Enable CPU accesses to the rest of the 256KB
430 total VGA memory beyond the first 64KB and set
432 ctWrite_i (CT_SR_O
, 0x00, 0x03); /* enable */
435 /*****************************************************************************/
437 SetBitsPerPixelIntoXrRegs (int bpp
)
439 unsigned int n
= (bpp
>> 3), tmp
; /* only for 15, 8, 16, 24 bpp */
440 static char md
[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
441 static char off
[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
442 static char on
[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
445 tmp
= ctRead_i (CT_XR_O
, 0x20);
448 ctWrite_i (CT_XR_O
, 0x20, tmp
); /* BitBLT Configuration */
449 ctWrite_i (CT_XR_O
, 0x81, md
[n
]);
452 /*****************************************************************************/
454 SetCrRegs (struct ctfb_res_modes
*var
, int bits_per_pixel
)
455 { /* he -le- ht|0 hd -ri- hs -h- he */
456 unsigned char cr
[0x7a];
458 unsigned int hd
, hs
, he
, ht
, hbe
; /* Horizontal. */
459 unsigned int vd
, vs
, ve
, vt
; /* vertical */
460 unsigned int bpp
, wd
, dblscan
, interlaced
, bcast
, CrtHalfLine
;
461 unsigned int CompSyncCharClkDelay
, CompSyncPixelClkDelay
;
462 unsigned int NTSC_PAL_HorizontalPulseWidth
, BlDelayCtrl
;
463 unsigned int HorizontalEqualizationPulses
;
464 unsigned int HorizontalSerration1Start
, HorizontalSerration2Start
;
466 const int LineCompare
= 0x3ff;
467 unsigned int TextScanLines
= 1; /* this is in fact a vertical zoom factor */
468 unsigned int RAMDAC_BlankPedestalEnable
= 0; /* 1=en-, 0=disable, see XR82 */
470 hd
= (var
->xres
) / 8; /* HDisp. */
471 hs
= (var
->xres
+ var
->right_margin
) / 8; /* HsStrt */
472 he
= (var
->xres
+ var
->right_margin
+ var
->hsync_len
) / 8; /* HsEnd */
473 ht
= (var
->left_margin
+ var
->xres
+ var
->right_margin
+ var
->hsync_len
) / 8; /* HTotal */
474 hbe
= ht
- 1; /* HBlankEnable todo docu wants ht here, but it does not work */
475 /* ve -up- vt|0 vd -lo- vs -v- ve */
476 vd
= var
->yres
; /* VDisplay */
477 vs
= var
->yres
+ var
->lower_margin
; /* VSyncStart */
478 ve
= var
->yres
+ var
->lower_margin
+ var
->vsync_len
; /* VSyncEnd */
479 vt
= var
->upper_margin
+ var
->yres
+ var
->lower_margin
+ var
->vsync_len
; /* VTotal */
480 bpp
= bits_per_pixel
;
481 dblscan
= (var
->vmode
& FB_VMODE_DOUBLE
) ? 1 : 0;
482 interlaced
= var
->vmode
& FB_VMODE_INTERLACED
;
483 bcast
= var
->sync
& FB_SYNC_BROADCAST
;
484 CrtHalfLine
= bcast
? (hd
>> 1) : 0;
485 BlDelayCtrl
= bcast
? 1 : 0;
486 CompSyncCharClkDelay
= 0; /* 2 bit */
487 CompSyncPixelClkDelay
= 0; /* 3 bit */
489 NTSC_PAL_HorizontalPulseWidth
= 7; /*( var->hsync_len >> 1 ) + 1 */
490 HorizontalEqualizationPulses
= 0; /* inverse value */
491 HorizontalSerration1Start
= 31; /* ( ht >> 1 ) */
492 HorizontalSerration2Start
= 89; /* ( ht >> 1 ) */
494 NTSC_PAL_HorizontalPulseWidth
= 0;
495 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
496 * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
497 HorizontalEqualizationPulses
= 1; /* inverse value */
498 HorizontalSerration1Start
= 0; /* ( ht >> 1 ) */
499 HorizontalSerration2Start
= 0; /* ( ht >> 1 ) */
504 wd
= var
->xres
* bpp
/ 64; /* double words per line */
505 if (interlaced
) { /* we divide all vertical timings, exept vd */
510 memset (cr
, 0, sizeof (cr
));
511 cr
[0x00] = 0xff & (ht
- 5);
512 cr
[0x01] = hd
- 1; /* soll:4f ist 59 */
514 cr
[0x03] = (hbe
& 0x1F) | 0x80; /* hd + ht - hd */
516 cr
[0x05] = ((hbe
& 0x20) << 2) | (he
& 0x1f);
517 cr
[0x06] = (vt
- 2) & 0xFF;
518 cr
[0x30] = (vt
- 2) >> 8;
519 cr
[0x07] = ((vt
& 0x100) >> 8)
520 | ((vd
& 0x100) >> 7)
521 | ((vs
& 0x100) >> 6)
522 | ((vs
& 0x100) >> 5)
523 | ((LineCompare
& 0x100) >> 4)
524 | ((vt
& 0x200) >> 4)
525 | ((vd
& 0x200) >> 3)
526 | ((vs
& 0x200) >> 2);
528 cr
[0x09] = (dblscan
<< 7)
529 | ((LineCompare
& 0x200) >> 3)
530 | ((vs
& 0x200) >> 4)
531 | (TextScanLines
- 1);
532 cr
[0x10] = vs
& 0xff; /* VSyncPulseStart */
533 cr
[0x32] = (vs
& 0xf00) >> 8; /* VSyncPulseStart */
534 cr
[0x11] = (ve
& 0x0f); /* | 0x20; */
535 cr
[0x12] = (vd
- 1) & 0xff; /* LineCount */
536 cr
[0x31] = ((vd
- 1) & 0xf00) >> 8; /* LineCount */
537 cr
[0x13] = wd
& 0xff;
538 cr
[0x41] = (wd
& 0xf00) >> 8;
539 cr
[0x15] = vs
& 0xff;
540 cr
[0x33] = (vs
& 0xf00) >> 8;
541 cr
[0x38] = (0x100 & (ht
- 5)) >> 8;
542 cr
[0x3C] = 0xc0 & hbe
;
543 cr
[0x16] = (vt
- 1) & 0xff; /* vbe - docu wants vt here, */
544 cr
[0x17] = 0xe3; /* but it does not work */
545 cr
[0x18] = 0xff & LineCompare
;
546 cr
[0x22] = 0xff; /* todo? */
547 cr
[0x70] = interlaced
? (0x80 | CrtHalfLine
) : 0x00; /* check:0xa6 */
548 cr
[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable
<< 6)
550 | ((0x03 & CompSyncCharClkDelay
) << 3)
551 | (0x07 & CompSyncPixelClkDelay
); /* todo: see XR82 */
552 cr
[0x72] = HorizontalSerration1Start
;
553 cr
[0x73] = HorizontalSerration2Start
;
554 cr
[0x74] = (HorizontalEqualizationPulses
<< 5)
555 | NTSC_PAL_HorizontalPulseWidth
;
556 /* todo: ct69000 has also 0x75-79 */
557 /* now set the registers */
558 for (i
= 0; i
<= 0x0d; i
++) { /*CR00 .. CR0D */
559 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
561 for (i
= 0x10; i
<= 0x18; i
++) { /*CR10 .. CR18 */
562 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
565 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
566 for (i
= 0x30; i
<= 0x33; i
++) { /*CR30 .. CR33 */
567 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
570 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
572 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
573 for (i
= 0x40; i
<= 0x41; i
++) { /*CR40 .. CR41 */
574 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
576 for (i
= 0x70; i
<= 0x74; i
++) { /*CR70 .. CR74 */
577 ctWrite_i (CT_CR_O
, i
, cr
[i
]);
579 tmp
= ctRead_i (CT_CR_O
, 0x40);
582 ctWrite_i (CT_CR_O
, 0x40, tmp
); /* StartAddressEnable */
585 /* pixelclock control */
587 /*****************************************************************************
588 We have a rational number p/q and need an m/n which is very close to p/q
589 but has m and n within mnmin and mnmax. We have no floating point in the
590 kernel. We can use long long without divide. And we have time to compute...
591 ******************************************************************************/
593 FindBestPQFittingMN (unsigned int p
, unsigned int q
, unsigned int mnmin
,
594 unsigned int mnmax
, unsigned int *pm
, unsigned int *pn
)
596 /* this code is not for general purpose usable but good for our number ranges */
597 unsigned int n
= mnmin
, m
= 0;
598 long long int L
= 0, P
= p
, Q
= q
, H
= P
>> 1;
599 long long int D
= 0x7ffffffffffffffLL
;
600 for (n
= mnmin
; n
<= mnmax
; n
++) {
601 m
= mnmin
; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
602 L
= P
* n
- m
* Q
; /* n * vco - m * fref should be near 0 */
603 while (L
> 0 && m
< mnmax
) {
604 L
-= q
; /* difference is greater as 0 subtract fref */
605 m
++; /* and increment m */
607 /* difference is less or equal than 0 or m > maximum */
609 break; /* no solution: if we increase n we get the same situation */
611 if (-L
> H
&& m
> mnmin
) { /* if difference > the half fref */
612 L
+= q
; /* we take the situation before */
613 m
--; /* because its closer to 0 */
615 L
= (L
< 0) ? -L
: +L
; /* absolute value */
616 if (D
< L
) /* if last difference was better take next n */
620 *pn
= n
; /* keep improved data */
622 break; /* best result we can get */
624 return (unsigned int) (0xffffffff & D
);
627 /* that is the hardware < 69000 we have to manage
628 +---------+ +-------------------+ +----------------------+ +--+
629 | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
630 | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
631 +---------+ +-------------------+ +----------------------+ +--+ |
632 ___________________________________________________________________|
635 | +--------+ +------------+ +-----+ +-------------------+ +----+
636 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
637 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
638 | +--------+ +------------+ +-----+ | +-------------------+ +----+
640 | +--+ +---------------+ |
641 |____|÷M|___|VCO Loop Divide|__________|
642 | | |(VLD)(÷4, ÷16) |
643 +--+ +---------------+
644 ****************************************************************************
645 that is the hardware >= 69000 we have to manage
653 | +--------+ +------------+ +-----+ +-------------------+ +----+
654 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
655 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
656 | +--------+ +------------+ +-----+ | +-------------------+ +----+
658 | +--+ +---------------+ |
659 |____|÷M|___|VCO Loop Divide|__________|
661 +--+ +---------------+
666 #define VIDEO_FREF 14318180; /* Hz */
667 /*****************************************************************************/
669 ReadPixClckFromXrRegsBack (struct ctfb_chips_properties
*param
)
671 unsigned int m
, n
, vld
, pd
, PD
, fref
, xr_cb
, i
, pixclock
;
675 m
= ctRead_i (CT_XR_O
, 0xc8);
676 n
= ctRead_i (CT_XR_O
, 0xc9);
679 xr_cb
= ctRead_i (CT_XR_O
, 0xcb);
680 PD
= (0x70 & xr_cb
) >> 4;
682 for (i
= 0; i
< PD
; i
++) {
685 vld
= (0x04 & xr_cb
) ? param
->vld_set
: param
->vld_not_set
;
687 unsigned long long p
= 1000000000000LL * pd
* n
;
688 unsigned long long q
= (long long) fref
* vld
* m
;
689 while ((p
> 0xffffffffLL
) || (q
> 0xffffffffLL
)) {
690 p
>>= 1; /* can't divide with long long so we scale down */
693 pixclock
= (unsigned) p
/ (unsigned) q
;
695 printf ("Invalid data in xr regs.\n");
699 /*****************************************************************************/
701 FindAndSetPllParamIntoXrRegs (unsigned int pixelclock
,
702 struct ctfb_chips_properties
*param
)
704 unsigned int m
, n
, vld
, pd
, PD
, fref
, xr_cb
;
705 unsigned int fvcomin
, fvcomax
, pclckmin
, pclckmax
, pclk
;
706 unsigned int pfreq
, fvco
, new_pixclock
;
707 unsigned int D
,nback
,mback
;
712 fvcomin
= param
->vco_min
;
713 fvcomax
= param
->vco_max
; /* MHz */
714 pclckmin
= 1000000 / fvcomax
+ 1; /* 4546 */
715 pclckmax
= 32000000 / fvcomin
- 1; /* 666665 */
716 pclk
= minmax (pclckmin
, pixelclock
, pclckmax
); /* ps pp */
717 pfreq
= 250 * (4000000000U / pclk
);
718 fvco
= pfreq
; /* Hz */
720 while (fvco
< fvcomin
* 1000000) {
721 /* double VCO starting with the pixelclock frequency
722 * as long as it is lower than the minimal VCO frequency */
727 /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
729 vld
= param
->vld_set
;
730 D
=FindBestPQFittingMN (fvco
/ vld
, fref
, param
->mn_min
, param
->mn_max
, &m
, &n
); /* rds = 1 */
734 vld
= param
->vld_not_set
;
735 if(D
<FindBestPQFittingMN (fvco
/ vld
, fref
, param
->mn_min
, param
->mn_max
, &m
, &n
)) { /* rds = 1 */
736 /* first try was better */
739 vld
= param
->vld_set
;
743 PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco
, pd
, m
, n
, vld
);
744 xr_cb
= ((0x7 & PD
) << 4) | (vld
== param
->vld_set
? 0x04 : 0);
745 /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
746 * written, and in order from XRC8 to XRCB, before the hardware will
747 * update the synthesizer s settings.
749 ctWrite_i (CT_XR_O
, 0xc8, m
);
750 ctWrite_i (CT_XR_O
, 0xc9, n
); /* xrca does not exist in CT69000 and CT69030 */
751 ctWrite_i (CT_XR_O
, 0xca, 0); /* because of a hw bug I guess, but we write */
752 ctWrite_i (CT_XR_O
, 0xcb, xr_cb
); /* 0 to it for savety */
753 new_pixclock
= ReadPixClckFromXrRegsBack (param
);
754 PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
755 pixelclock
, new_pixclock
);
758 /*****************************************************************************/
760 SetMsrRegs (struct ctfb_res_modes
*mode
)
762 unsigned char h_synch_high
, v_synch_high
;
764 h_synch_high
= (mode
->sync
& FB_SYNC_HOR_HIGH_ACT
) ? 0 : 0x40; /* horizontal Synch High active */
765 v_synch_high
= (mode
->sync
& FB_SYNC_VERT_HIGH_ACT
) ? 0 : 0x80; /* vertical Synch High active */
766 ctWrite (CT_MSR_W_O
, (h_synch_high
| v_synch_high
| 0x29));
767 /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
768 * Selects the upper 64KB page.Bit5=1
769 * CLK2 (left reserved in standard VGA) Bit3|2=1|0
770 * Disables CPU access to frame buffer. Bit1=0
771 * Sets the I/O address decode for ST01, FCR, and all CR registers
772 * to the 3Dx I/O address range (CGA emulation). Bit0=1
776 /************************************************************************************/
780 ctDispRegs (unsigned short index
, int from
, int to
)
782 unsigned char status
;
785 for (i
= from
; i
< to
; i
++) {
786 status
= ctRead_i (index
, i
);
787 printf ("%02X: is %02X\n", i
, status
);
792 video_dump_reg (void)
796 printf ("Extended Regs:\n");
797 ctDispRegs (CT_XR_O
, 0, 0xC);
798 ctDispRegs (CT_XR_O
, 0xe, 0xf);
799 ctDispRegs (CT_XR_O
, 0x20, 0x21);
800 ctDispRegs (CT_XR_O
, 0x40, 0x50);
801 ctDispRegs (CT_XR_O
, 0x60, 0x64);
802 ctDispRegs (CT_XR_O
, 0x67, 0x68);
803 ctDispRegs (CT_XR_O
, 0x70, 0x72);
804 ctDispRegs (CT_XR_O
, 0x80, 0x83);
805 ctDispRegs (CT_XR_O
, 0xA0, 0xB0);
806 ctDispRegs (CT_XR_O
, 0xC0, 0xD3);
807 printf ("Sequencer Regs:\n");
808 ctDispRegs (CT_SR_O
, 0, 0x8);
809 printf ("Graphic Regs:\n");
810 ctDispRegs (CT_GR_O
, 0, 0x9);
811 printf ("CRT Regs:\n");
812 ctDispRegs (CT_CR_O
, 0, 0x19);
813 ctDispRegs (CT_CR_O
, 0x22, 0x23);
814 ctDispRegs (CT_CR_O
, 0x30, 0x34);
815 ctDispRegs (CT_CR_O
, 0x38, 0x39);
816 ctDispRegs (CT_CR_O
, 0x3C, 0x3D);
817 ctDispRegs (CT_CR_O
, 0x40, 0x42);
818 ctDispRegs (CT_CR_O
, 0x70, 0x80);
819 /* don't display the attributes */
824 #ifdef CONFIG_VIDEO_HW_CURSOR
825 /***************************************************************
826 * Set Hardware Cursor in Pixel
829 video_set_hw_cursor (int x
, int y
)
831 int sig_x
= 0, sig_y
= 0;
840 ctWrite_i (CT_XR_O
, 0xa4, x
& 0xff);
841 ctWrite_i (CT_XR_O
, 0xa5, (x
>> 8) & 0x7);
842 ctWrite_i (CT_XR_O
, 0xa6, y
& 0xff);
843 ctWrite_i (CT_XR_O
, 0xa7, (y
>> 8) & 0x7);
846 /***************************************************************
847 * Init Hardware Cursor. To know the size of the Cursor,
848 * we have to know the Font size.
851 video_init_hw_cursor (int font_width
, int font_height
)
854 unsigned long *curs
, pattern
;
857 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
859 cursor_start
= pGD
->dprBase
;
860 xr_80
= ctRead_i (CT_XR_O
, 0x80);
861 /* set start address */
862 ctWrite_i (CT_XR_O
, 0xa2, (cursor_start
>> 8) & 0xf0);
863 ctWrite_i (CT_XR_O
, 0xa3, (cursor_start
>> 16) & 0x3f);
864 /* set cursor shape */
865 curs
= (unsigned long *) cursor_start
;
868 curs
[i
++] = 0xffffffff; /* AND mask */
869 curs
[i
++] = 0xffffffff; /* AND mask */
870 curs
[i
++] = 0; /* XOR mask */
871 curs
[i
++] = 0; /* XOR mask */
874 pattern
= 0xffffffff >> font_width
;
876 while (i
< (font_height
* 2)) {
877 curs
[i
++] = pattern
; /* AND mask */
878 curs
[i
++] = pattern
; /* AND mask */
879 curs
[i
++] = 0; /* XOR mask */
880 curs
[i
++] = 0; /* XOR mask */
884 ctWrite_i (CT_FP_O
, 0x19, 0xf);
886 /* set cursors colors */
887 xr_80
= ctRead_i (CT_XR_O
, 0x80);
888 xr_80
|= 0x1; /* alternate palette select */
889 ctWrite_i (CT_XR_O
, 0x80, xr_80
);
890 video_set_lut (4, CONSOLE_FG_COL
, CONSOLE_FG_COL
, CONSOLE_FG_COL
);
891 /* position 4 is color 0 cursor 0 */
892 xr_80
&= 0xfe; /* normal palette select */
893 ctWrite_i (CT_XR_O
, 0x80, xr_80
);
895 ctWrite_i (CT_XR_O
, 0xa0, 0x91);
896 xr_80
|= 0x10; /* enable hwcursor */
897 ctWrite_i (CT_XR_O
, 0x80, xr_80
);
898 video_set_hw_cursor (0, 0);
900 #endif /* CONFIG_VIDEO_HW_CURSOR */
902 /***************************************************************
903 * Wait for BitBlt ready
906 video_wait_bitblt (unsigned long addr
)
911 while (br04
& 0x80000000) {
915 printf ("ERROR Timeout %lx\n", br04
);
922 /***************************************************************
923 * Set up BitBlt Registrs
926 SetDrawingEngine (int bits_per_pixel
)
928 unsigned long br04
, br00
;
931 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
933 tmp
= ctRead_i (CT_XR_O
, 0x20); /* BitBLT Configuration */
934 tmp
|= 0x02; /* reset BitBLT */
935 ctWrite_i (CT_XR_O
, 0x20, tmp
); /* BitBLT Configuration */
937 tmp
&= 0xfd; /* release reset BitBLT */
938 ctWrite_i (CT_XR_O
, 0x20, tmp
); /* BitBLT Configuration */
939 video_wait_bitblt (pGD
->pciBase
+ BR04_o
);
941 /* set pattern Address */
942 out32r (pGD
->pciBase
+ BR05_o
, PATTERN_ADR
& 0x003ffff8);
944 if (bits_per_pixel
== 1) {
945 br04
|= 0x00040000; /* monochome Pattern */
946 br04
|= 0x00001000; /* monochome source */
948 br00
= ((pGD
->winSizeX
* pGD
->gdfBytesPP
) << 16) + (pGD
->winSizeX
* pGD
->gdfBytesPP
); /* bytes per scanline */
949 out32r (pGD
->pciBase
+ BR00_o
, br00
); /* */
950 out32r (pGD
->pciBase
+ BR08_o
, (10 << 16) + 10); /* dummy */
951 out32r (pGD
->pciBase
+ BR04_o
, br04
); /* write all 0 */
952 out32r (pGD
->pciBase
+ BR07_o
, 0); /* destination */
953 video_wait_bitblt (pGD
->pciBase
+ BR04_o
);
956 /****************************************************************************
957 * supported Video Chips
959 static struct pci_device_id supported
[] = {
960 {PCI_VENDOR_ID_CT
, PCI_DEVICE_ID_CT_69000
},
961 #ifdef CONFIG_USE_CPCIDVI
962 {PCI_VENDOR_ID_CT
, PCI_DEVICE_ID_CT_69030
},
967 /*******************************************************************************
974 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
975 unsigned short device_id
;
978 unsigned long t1
, hsynch
, vsynch
;
979 unsigned int pci_mem_base
, *vm
;
980 int tmp
, i
, bits_per_pixel
;
982 struct ctfb_res_modes
*res_mode
;
983 struct ctfb_res_modes var_mode
;
984 struct ctfb_chips_properties
*chips_param
;
985 /* Search for video chip */
987 if ((devbusfn
= pci_find_devices (supported
, 0)) < 0) {
988 #ifdef CONFIG_VIDEO_ONBOARD
989 printf ("Video: Controller not found !\n");
995 pci_write_config_dword (devbusfn
, PCI_COMMAND
,
996 (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
));
997 pci_read_config_word (devbusfn
, PCI_DEVICE_ID
, &device_id
);
998 pci_read_config_dword (devbusfn
, PCI_BASE_ADDRESS_0
, &pci_mem_base
);
999 pci_mem_base
= pci_mem_to_phys (devbusfn
, pci_mem_base
);
1001 /* get chips params */
1002 for (chips_param
= (struct ctfb_chips_properties
*) &chips
[0];
1003 chips_param
->device_id
!= 0; chips_param
++) {
1004 if (chips_param
->device_id
== device_id
)
1007 if (chips_param
->device_id
== 0) {
1008 #ifdef CONFIG_VIDEO_ONBOARD
1009 printf ("Video: controller 0x%X not supported\n", device_id
);
1013 /* supported Video controller found */
1018 /* get video mode via environment */
1019 if ((penv
= getenv ("videomode")) != NULL
) {
1020 /* deceide if it is a string */
1021 if (penv
[0] <= '9') {
1022 videomode
= (int) simple_strtoul (penv
, NULL
, 16);
1029 /* parameter are vesa modes */
1031 for (i
= 0; i
< VESA_MODES_COUNT
; i
++) {
1032 if (vesa_modes
[i
].vesanr
== videomode
)
1035 if (i
== VESA_MODES_COUNT
) {
1036 printf ("no VESA Mode found, switching to mode 0x301 ");
1040 (struct ctfb_res_modes
*) &res_mode_init
[vesa_modes
[i
].
1042 bits_per_pixel
= vesa_modes
[i
].bits_per_pixel
;
1045 res_mode
= (struct ctfb_res_modes
*) &var_mode
;
1046 bits_per_pixel
= video_get_params (res_mode
, penv
);
1049 /* calculate available color depth for controller memory */
1050 if (bits_per_pixel
== 15)
1053 tmp
= bits_per_pixel
>> 3; /* /8 */
1054 if (((chips_param
->max_mem
-
1055 ACCELMEMORY
) / (res_mode
->xres
* res_mode
->yres
)) < tmp
) {
1057 ((chips_param
->max_mem
-
1058 ACCELMEMORY
) / (res_mode
->xres
* res_mode
->yres
));
1061 ("No matching videomode found .-> reduce resolution\n");
1064 printf ("Switching back to %d Bits per Pixel ",
1066 bits_per_pixel
= tmp
<< 3;
1070 /* calculate hsynch and vsynch freq (info only) */
1071 t1
= (res_mode
->left_margin
+ res_mode
->xres
+
1072 res_mode
->right_margin
+ res_mode
->hsync_len
) / 8;
1074 t1
*= res_mode
->pixclock
;
1076 hsynch
= 1000000000L / t1
;
1078 (res_mode
->upper_margin
+ res_mode
->yres
+
1079 res_mode
->lower_margin
+ res_mode
->vsync_len
);
1081 vsynch
= 1000000000L / t1
;
1083 /* fill in Graphic device struct */
1084 sprintf (pGD
->modeIdent
, "%dx%dx%d %ldkHz %ldHz", res_mode
->xres
,
1085 res_mode
->yres
, bits_per_pixel
, (hsynch
/ 1000),
1087 printf ("%s\n", pGD
->modeIdent
);
1088 pGD
->winSizeX
= res_mode
->xres
;
1089 pGD
->winSizeY
= res_mode
->yres
;
1090 pGD
->plnSizeX
= res_mode
->xres
;
1091 pGD
->plnSizeY
= res_mode
->yres
;
1092 switch (bits_per_pixel
) {
1094 pGD
->gdfBytesPP
= 1;
1095 pGD
->gdfIndex
= GDF__8BIT_INDEX
;
1098 pGD
->gdfBytesPP
= 2;
1099 pGD
->gdfIndex
= GDF_15BIT_555RGB
;
1102 pGD
->gdfBytesPP
= 2;
1103 pGD
->gdfIndex
= GDF_16BIT_565RGB
;
1106 pGD
->gdfBytesPP
= 3;
1107 pGD
->gdfIndex
= GDF_24BIT_888RGB
;
1110 pGD
->isaBase
= CONFIG_SYS_ISA_IO_BASE_ADDRESS
;
1111 pGD
->pciBase
= pci_mem_base
;
1112 pGD
->frameAdrs
= pci_mem_base
;
1113 pGD
->memSize
= chips_param
->max_mem
;
1114 /* Cursor Start Address */
1116 (pGD
->winSizeX
* pGD
->winSizeY
* pGD
->gdfBytesPP
) + pci_mem_base
;
1117 if ((pGD
->dprBase
& 0x0fff) != 0) {
1119 pGD
->dprBase
&= 0xfffff000;
1120 pGD
->dprBase
+= 0x00001000;
1122 PRINTF ("Cursor Start %x Pattern Start %x\n", pGD
->dprBase
,
1124 pGD
->vprBase
= pci_mem_base
; /* Dummy */
1125 pGD
->cprBase
= pci_mem_base
; /* Dummy */
1126 /* set up Hardware */
1128 #ifdef CONFIG_USE_CPCIDVI
1129 if (device_id
== PCI_DEVICE_ID_CT_69030
) {
1130 ctWrite (CT_MSR_W_O
, 0x0b);
1131 ctWrite (0x3cd, 0x13);
1132 ctWrite_i (CT_FP_O
, 0x02, 0x00);
1133 ctWrite_i (CT_FP_O
, 0x05, 0x00);
1134 ctWrite_i (CT_FP_O
, 0x06, 0x00);
1135 ctWrite (0x3c2, 0x0b);
1136 ctWrite_i (CT_FP_O
, 0x02, 0x10);
1137 ctWrite_i (CT_FP_O
, 0x01, 0x09);
1139 ctWrite (CT_MSR_W_O
, 0x01);
1142 ctWrite (CT_MSR_W_O
, 0x01);
1145 /* set the extended Registers */
1146 ctLoadRegs (CT_XR_O
, xreg
);
1147 /* set atribute registers */
1149 /* set Graphics register */
1155 SetMsrRegs (res_mode
);
1157 /* set CRT Registers */
1158 SetCrRegs (res_mode
, bits_per_pixel
);
1159 /* set color mode */
1160 SetBitsPerPixelIntoXrRegs (bits_per_pixel
);
1163 FindAndSetPllParamIntoXrRegs (res_mode
->pixclock
, chips_param
);
1165 ctWrite_i (CT_SR_O
, 0, 0x03); /* clear synchronous reset */
1166 /* Clear video memory */
1167 i
= pGD
->memSize
/ 4;
1168 vm
= (unsigned int *) pGD
->pciBase
;
1171 SetDrawingEngine (bits_per_pixel
);
1176 return ((void *) &ctfb
);
1179 /*******************************************************************************
1181 * Set a RGB color in the LUT (8 bit index)
1184 video_set_lut (unsigned int index
, /* color number */
1185 unsigned char r
, /* red */
1186 unsigned char g
, /* green */
1187 unsigned char b
/* blue */
1191 ctWrite (CT_LUT_MASK_O
, 0xff);
1193 ctWrite (CT_LUT_START_O
, (char) index
);
1195 ctWrite (CT_LUT_RGB_O
, r
); /* red */
1196 ctWrite (CT_LUT_RGB_O
, g
); /* green */
1197 ctWrite (CT_LUT_RGB_O
, b
); /* blue */
1199 ctWrite (CT_LUT_MASK_O
, 0xff);
1202 /*******************************************************************************
1204 * Drawing engine fill on screen region
1207 video_hw_rectfill (unsigned int bpp
, /* bytes per pixel */
1208 unsigned int dst_x
, /* dest pos x */
1209 unsigned int dst_y
, /* dest pos y */
1210 unsigned int dim_x
, /* frame width */
1211 unsigned int dim_y
, /* frame height */
1212 unsigned int color
/* fill color */
1215 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
1216 unsigned long *p
, br04
;
1218 video_wait_bitblt (pGD
->pciBase
+ BR04_o
);
1220 p
= (unsigned long *) PATTERN_ADR
;
1223 bpp
++; /* 24Bit needs a 32bit pattern */
1224 memset (p
, color
, (bpp
* sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
1225 out32r (pGD
->pciBase
+ BR07_o
, ((pGD
->winSizeX
* dst_y
) + dst_x
) * pGD
->gdfBytesPP
); /* destination */
1226 br04
= in32r (pGD
->pciBase
+ BR04_o
) & 0xffffff00;
1227 br04
|= 0xF0; /* write Pattern P -> D */
1228 out32r (pGD
->pciBase
+ BR04_o
, br04
); /* */
1229 out32r (pGD
->pciBase
+ BR08_o
, (dim_y
<< 16) + dim_x
); /* starts the BITBlt */
1230 video_wait_bitblt (pGD
->pciBase
+ BR04_o
);
1233 /*******************************************************************************
1235 * Drawing engine bitblt with screen region
1238 video_hw_bitblt (unsigned int bpp
, /* bytes per pixel */
1239 unsigned int src_x
, /* source pos x */
1240 unsigned int src_y
, /* source pos y */
1241 unsigned int dst_x
, /* dest pos x */
1242 unsigned int dst_y
, /* dest pos y */
1243 unsigned int dim_x
, /* frame width */
1244 unsigned int dim_y
/* frame height */
1247 GraphicDevice
*pGD
= (GraphicDevice
*) & ctfb
;
1250 br04
= in32r (pGD
->pciBase
+ BR04_o
);
1252 /* to prevent data corruption due to overlap, we have to
1253 * find out if, and how the frames overlaps */
1254 if (src_x
< dst_x
) {
1255 /* src is more left than dest
1256 * the frame may overlap -> start from right to left */
1257 br04
|= 0x00000100; /* set bit 8 */
1261 br04
&= 0xfffffeff; /* clear bit 8 left to right */
1263 if (src_y
< dst_y
) {
1264 /* src is higher than dst
1265 * the frame may overlap => start from bottom */
1266 br04
|= 0x00000200; /* set bit 9 */
1270 br04
&= 0xfffffdff; /* clear bit 9 top to bottom */
1273 out32r (pGD
->pciBase
+ BR06_o
, ((pGD
->winSizeX
* src_y
) + src_x
) * pGD
->gdfBytesPP
); /* source */
1274 out32r (pGD
->pciBase
+ BR07_o
, ((pGD
->winSizeX
* dst_y
) + dst_x
) * pGD
->gdfBytesPP
); /* destination */
1276 br04
|= 0x000000CC; /* S -> D */
1277 out32r (pGD
->pciBase
+ BR04_o
, br04
); /* */
1278 out32r (pGD
->pciBase
+ BR08_o
, (dim_y
<< 16) + dim_x
); /* start the BITBlt */
1279 video_wait_bitblt (pGD
->pciBase
+ BR04_o
);
1281 #endif /* CONFIG_VIDEO */