2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compat.h>
13 #include <linux/err.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/dp_info.h>
17 #include <asm/arch/dp.h>
21 #include "exynos_dp_lowlevel.h"
23 DECLARE_GLOBAL_DATA_PTR
;
25 static struct exynos_dp_platform_data
*dp_pd
;
27 void __exynos_set_dp_phy(unsigned int onoff
)
30 void exynos_set_dp_phy(unsigned int onoff
)
31 __attribute__((weak
, alias("__exynos_set_dp_phy")));
33 static void exynos_dp_disp_info(struct edp_disp_info
*disp_info
)
35 disp_info
->h_total
= disp_info
->h_res
+ disp_info
->h_sync_width
+
36 disp_info
->h_back_porch
+ disp_info
->h_front_porch
;
37 disp_info
->v_total
= disp_info
->v_res
+ disp_info
->v_sync_width
+
38 disp_info
->v_back_porch
+ disp_info
->v_front_porch
;
43 static int exynos_dp_init_dp(void)
48 /* SW defined function Normal operation */
49 exynos_dp_enable_sw_func(DP_ENABLE
);
51 ret
= exynos_dp_init_analog_func();
52 if (ret
!= EXYNOS_DP_SUCCESS
)
61 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data
)
64 unsigned char sum
= 0;
66 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
67 sum
= sum
+ edid_data
[i
];
72 static unsigned int exynos_dp_read_edid(void)
74 unsigned char edid
[EDID_BLOCK_LENGTH
* 2];
75 unsigned int extend_block
= 0;
77 unsigned char test_vector
;
81 * EDID device address is 0x50.
82 * However, if necessary, you must have set upper address
83 * into E-EDID in I2C device, 0x30.
86 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
87 exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR
, EDID_EXTENSION_FLAG
,
90 if (extend_block
> 0) {
91 printf("DP EDID data includes a single extension!\n");
94 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
97 &edid
[EDID_HEADER_PATTERN
]);
99 printf("DP EDID Read failed!\n");
102 sum
= exynos_dp_calc_edid_check_sum(edid
);
104 printf("DP EDID bad checksum!\n");
108 /* Read additional EDID data */
109 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
112 &edid
[EDID_BLOCK_LENGTH
]);
114 printf("DP EDID Read failed!\n");
117 sum
= exynos_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
119 printf("DP EDID bad checksum!\n");
123 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST
,
125 if (test_vector
& DPCD_TEST_EDID_READ
) {
126 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM
,
127 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
128 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE
,
129 DPCD_TEST_EDID_CHECKSUM_WRITE
);
132 debug("DP EDID data does not include any extensions.\n");
135 retval
= exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR
,
138 &edid
[EDID_HEADER_PATTERN
]);
141 printf("DP EDID Read failed!\n");
144 sum
= exynos_dp_calc_edid_check_sum(edid
);
146 printf("DP EDID bad checksum!\n");
150 exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST
,
152 if (test_vector
& DPCD_TEST_EDID_READ
) {
153 exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM
,
154 edid
[EDID_CHECKSUM
]);
155 exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE
,
156 DPCD_TEST_EDID_CHECKSUM_WRITE
);
160 debug("DP EDID Read success!\n");
165 static unsigned int exynos_dp_handle_edid(struct edp_device_info
*edp_info
)
167 unsigned char buf
[12];
170 unsigned char retry_cnt
;
171 unsigned char dpcd_rev
[16];
172 unsigned char lane_bw
[16];
173 unsigned char lane_cnt
[16];
175 memset(dpcd_rev
, 0, 16);
176 memset(lane_bw
, 0, 16);
177 memset(lane_cnt
, 0, 16);
182 /* Read DPCD 0x0000-0x000b */
183 ret
= exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV
, 12,
185 if (ret
!= EXYNOS_DP_SUCCESS
) {
186 if (retry_cnt
== 0) {
187 printf("DP read_byte_from_dpcd() failed\n");
196 temp
= buf
[DPCD_DPCD_REV
];
197 if (temp
== DP_DPCD_REV_10
|| temp
== DP_DPCD_REV_11
)
198 edp_info
->dpcd_rev
= temp
;
200 printf("DP Wrong DPCD Rev : %x\n", temp
);
204 temp
= buf
[DPCD_MAX_LINK_RATE
];
205 if (temp
== DP_LANE_BW_1_62
|| temp
== DP_LANE_BW_2_70
)
206 edp_info
->lane_bw
= temp
;
208 printf("DP Wrong MAX LINK RATE : %x\n", temp
);
212 /*Refer VESA Display Port Stnadard Ver1.1a Page 120 */
213 if (edp_info
->dpcd_rev
== DP_DPCD_REV_11
) {
214 temp
= buf
[DPCD_MAX_LANE_COUNT
] & 0x1f;
215 if (buf
[DPCD_MAX_LANE_COUNT
] & 0x80)
216 edp_info
->dpcd_efc
= 1;
218 edp_info
->dpcd_efc
= 0;
220 temp
= buf
[DPCD_MAX_LANE_COUNT
];
221 edp_info
->dpcd_efc
= 0;
224 if (temp
== DP_LANE_CNT_1
|| temp
== DP_LANE_CNT_2
||
225 temp
== DP_LANE_CNT_4
) {
226 edp_info
->lane_cnt
= temp
;
228 printf("DP Wrong MAX LANE COUNT : %x\n", temp
);
232 ret
= exynos_dp_read_edid();
233 if (ret
!= EXYNOS_DP_SUCCESS
) {
234 printf("DP exynos_dp_read_edid() failed\n");
241 static void exynos_dp_init_training(void)
244 * MACRO_RST must be applied after the PLL_LOCK to avoid
245 * the DP inter pair skew issue for at least 10 us
247 exynos_dp_reset_macro();
249 /* All DP analog module power up */
250 exynos_dp_set_analog_power_down(POWER_ALL
, 0);
253 static unsigned int exynos_dp_link_start(struct edp_device_info
*edp_info
)
255 unsigned char buf
[5];
256 unsigned int ret
= 0;
258 debug("DP: %s was called\n", __func__
);
260 edp_info
->lt_info
.lt_status
= DP_LT_CR
;
261 edp_info
->lt_info
.ep_loop
= 0;
262 edp_info
->lt_info
.cr_loop
[0] = 0;
263 edp_info
->lt_info
.cr_loop
[1] = 0;
264 edp_info
->lt_info
.cr_loop
[2] = 0;
265 edp_info
->lt_info
.cr_loop
[3] = 0;
267 /* Set sink to D0 (Sink Not Ready) mode. */
268 ret
= exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE
,
269 DPCD_SET_POWER_STATE_D0
);
270 if (ret
!= EXYNOS_DP_SUCCESS
) {
271 printf("DP write_dpcd_byte failed\n");
275 /* Set link rate and count as you want to establish*/
276 exynos_dp_set_link_bandwidth(edp_info
->lane_bw
);
277 exynos_dp_set_lane_count(edp_info
->lane_cnt
);
279 /* Setup RX configuration */
280 buf
[0] = edp_info
->lane_bw
;
281 buf
[1] = edp_info
->lane_cnt
;
283 ret
= exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET
, 2,
285 if (ret
!= EXYNOS_DP_SUCCESS
) {
286 printf("DP write_dpcd_byte failed\n");
290 exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0
,
293 /* Set training pattern 1 */
294 exynos_dp_set_training_pattern(TRAINING_PTN1
);
296 /* Set RX training pattern */
297 buf
[0] = DPCD_SCRAMBLING_DISABLED
| DPCD_TRAINING_PATTERN_1
;
299 buf
[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
300 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
301 buf
[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
302 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
303 buf
[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
304 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
305 buf
[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0
|
306 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0
;
308 ret
= exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
310 if (ret
!= EXYNOS_DP_SUCCESS
) {
311 printf("DP write_dpcd_byte failed\n");
318 static unsigned int exynos_dp_training_pattern_dis(void)
320 unsigned int ret
= EXYNOS_DP_SUCCESS
;
322 exynos_dp_set_training_pattern(DP_NONE
);
324 ret
= exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
325 DPCD_TRAINING_PATTERN_DISABLED
);
326 if (ret
!= EXYNOS_DP_SUCCESS
) {
327 printf("DP requst_link_traninig_req failed\n");
334 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable
)
337 unsigned int ret
= EXYNOS_DP_SUCCESS
;
339 ret
= exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET
,
341 if (ret
!= EXYNOS_DP_SUCCESS
) {
342 printf("DP read_from_dpcd failed\n");
347 data
= DPCD_ENHANCED_FRAME_EN
| DPCD_LN_COUNT_SET(data
);
349 data
= DPCD_LN_COUNT_SET(data
);
351 ret
= exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET
,
353 if (ret
!= EXYNOS_DP_SUCCESS
) {
354 printf("DP write_to_dpcd failed\n");
362 static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode
)
364 unsigned int ret
= EXYNOS_DP_SUCCESS
;
366 ret
= exynos_dp_enable_rx_to_enhanced_mode(enhance_mode
);
367 if (ret
!= EXYNOS_DP_SUCCESS
) {
368 printf("DP rx_enhance_mode failed\n");
372 exynos_dp_enable_enhanced_mode(enhance_mode
);
377 static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info
*edp_info
,
378 unsigned char *status
)
381 unsigned char buf
[2];
382 unsigned char lane_stat
[DP_LANE_CNT_4
] = {0,};
383 unsigned char shift_val
[DP_LANE_CNT_4
] = {0,};
390 ret
= exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS
, 2, buf
);
391 if (ret
!= EXYNOS_DP_SUCCESS
) {
392 printf("DP read lane status failed\n");
396 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
397 lane_stat
[i
] = (buf
[(i
/ 2)] >> shift_val
[i
]) & 0x0f;
398 if (lane_stat
[0] != lane_stat
[i
]) {
399 printf("Wrong lane status\n");
404 *status
= lane_stat
[0];
409 static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num
,
410 unsigned char *sw
, unsigned char *em
)
412 unsigned int ret
= EXYNOS_DP_SUCCESS
;
414 unsigned int dpcd_addr
;
415 unsigned char shift_val
[DP_LANE_CNT_4
] = {0, 4, 0, 4};
417 /*lane_num value is used as arry index, so this range 0 ~ 3 */
418 dpcd_addr
= DPCD_ADJUST_REQUEST_LANE0_1
+ (lane_num
/ 2);
420 ret
= exynos_dp_read_byte_from_dpcd(dpcd_addr
, &buf
);
421 if (ret
!= EXYNOS_DP_SUCCESS
) {
422 printf("DP read adjust request failed\n");
426 *sw
= ((buf
>> shift_val
[lane_num
]) & 0x03);
427 *em
= ((buf
>> shift_val
[lane_num
]) & 0x0c) >> 2;
432 static int exynos_dp_equalizer_err_link(struct edp_device_info
*edp_info
)
436 ret
= exynos_dp_training_pattern_dis();
437 if (ret
!= EXYNOS_DP_SUCCESS
) {
438 printf("DP training_patter_disable() failed\n");
439 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
442 ret
= exynos_dp_set_enhanced_mode(edp_info
->dpcd_efc
);
443 if (ret
!= EXYNOS_DP_SUCCESS
) {
444 printf("DP set_enhanced_mode() failed\n");
445 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
451 static int exynos_dp_reduce_link_rate(struct edp_device_info
*edp_info
)
455 if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
456 edp_info
->lane_bw
= DP_LANE_BW_1_62
;
457 printf("DP Change lane bw to 1.62Gbps\n");
458 edp_info
->lt_info
.lt_status
= DP_LT_START
;
459 ret
= EXYNOS_DP_SUCCESS
;
461 ret
= exynos_dp_training_pattern_dis();
462 if (ret
!= EXYNOS_DP_SUCCESS
)
463 printf("DP training_patter_disable() failed\n");
465 ret
= exynos_dp_set_enhanced_mode(edp_info
->dpcd_efc
);
466 if (ret
!= EXYNOS_DP_SUCCESS
)
467 printf("DP set_enhanced_mode() failed\n");
469 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
475 static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
478 unsigned int ret
= EXYNOS_DP_SUCCESS
;
479 unsigned char lane_stat
;
480 unsigned char lt_ctl_val
[DP_LANE_CNT_4
] = {0, };
482 unsigned char adj_req_sw
;
483 unsigned char adj_req_em
;
484 unsigned char buf
[5];
486 debug("DP: %s was called\n", __func__
);
489 ret
= exynos_dp_read_dpcd_lane_stat(edp_info
, &lane_stat
);
490 if (ret
!= EXYNOS_DP_SUCCESS
) {
491 printf("DP read lane status failed\n");
492 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
496 if (lane_stat
& DP_LANE_STAT_CR_DONE
) {
497 debug("DP clock Recovery training succeed\n");
498 exynos_dp_set_training_pattern(TRAINING_PTN2
);
500 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
501 ret
= exynos_dp_read_dpcd_adj_req(i
, &adj_req_sw
,
503 if (ret
!= EXYNOS_DP_SUCCESS
) {
504 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
509 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
511 if ((adj_req_sw
== VOLTAGE_LEVEL_3
)
512 || (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
513 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
|
514 MAX_PRE_EMPHASIS_REACH_3
;
516 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val
[i
], i
);
519 buf
[0] = DPCD_SCRAMBLING_DISABLED
| DPCD_TRAINING_PATTERN_2
;
520 buf
[1] = lt_ctl_val
[0];
521 buf
[2] = lt_ctl_val
[1];
522 buf
[3] = lt_ctl_val
[2];
523 buf
[4] = lt_ctl_val
[3];
525 ret
= exynos_dp_write_bytes_to_dpcd(
526 DPCD_TRAINING_PATTERN_SET
, 5, buf
);
527 if (ret
!= EXYNOS_DP_SUCCESS
) {
528 printf("DP write traning pattern1 failed\n");
529 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
532 edp_info
->lt_info
.lt_status
= DP_LT_ET
;
534 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
535 lt_ctl_val
[i
] = exynos_dp_get_lanex_pre_emphasis(i
);
536 ret
= exynos_dp_read_dpcd_adj_req(i
,
537 &adj_req_sw
, &adj_req_em
);
538 if (ret
!= EXYNOS_DP_SUCCESS
) {
539 printf("DP read adj req failed\n");
540 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
544 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
545 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
))
546 ret
= exynos_dp_reduce_link_rate(edp_info
);
548 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val
[i
]) ==
550 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val
[i
]) ==
552 edp_info
->lt_info
.cr_loop
[i
]++;
553 if (edp_info
->lt_info
.cr_loop
[i
] == MAX_CR_LOOP
)
554 ret
= exynos_dp_reduce_link_rate(
559 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
561 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
562 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
563 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
|
564 MAX_PRE_EMPHASIS_REACH_3
;
566 exynos_dp_set_lanex_pre_emphasis(lt_ctl_val
[i
], i
);
569 ret
= exynos_dp_write_bytes_to_dpcd(
570 DPCD_TRAINING_LANE0_SET
, 4, lt_ctl_val
);
571 if (ret
!= EXYNOS_DP_SUCCESS
) {
572 printf("DP write traning pattern2 failed\n");
573 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
581 static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
584 unsigned int ret
= EXYNOS_DP_SUCCESS
;
585 unsigned char lane_stat
, adj_req_sw
, adj_req_em
, i
;
586 unsigned char lt_ctl_val
[DP_LANE_CNT_4
] = {0,};
587 unsigned char interlane_aligned
= 0;
589 unsigned char f_lane_cnt
;
590 unsigned char sink_stat
;
594 ret
= exynos_dp_read_dpcd_lane_stat(edp_info
, &lane_stat
);
595 if (ret
!= EXYNOS_DP_SUCCESS
) {
596 printf("DP read lane status failed\n");
597 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
601 debug("DP lane stat : %x\n", lane_stat
);
603 if (lane_stat
& DP_LANE_STAT_CR_DONE
) {
604 ret
= exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED
,
606 if (ret
!= EXYNOS_DP_SUCCESS
) {
607 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
612 interlane_aligned
= (sink_stat
& DPCD_INTERLANE_ALIGN_DONE
);
614 for (i
= 0; i
< edp_info
->lane_cnt
; i
++) {
615 ret
= exynos_dp_read_dpcd_adj_req(i
,
616 &adj_req_sw
, &adj_req_em
);
617 if (ret
!= EXYNOS_DP_SUCCESS
) {
618 printf("DP read adj req 1 failed\n");
619 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
625 lt_ctl_val
[i
] = adj_req_em
<< 3 | adj_req_sw
;
627 if ((adj_req_sw
== VOLTAGE_LEVEL_3
) ||
628 (adj_req_em
== PRE_EMPHASIS_LEVEL_3
)) {
629 lt_ctl_val
[i
] |= MAX_DRIVE_CURRENT_REACH_3
;
630 lt_ctl_val
[i
] |= MAX_PRE_EMPHASIS_REACH_3
;
634 if (((lane_stat
&DP_LANE_STAT_CE_DONE
) &&
635 (lane_stat
&DP_LANE_STAT_SYM_LOCK
))
636 && (interlane_aligned
== DPCD_INTERLANE_ALIGN_DONE
)) {
637 debug("DP Equalizer training succeed\n");
639 f_bw
= exynos_dp_get_link_bandwidth();
640 f_lane_cnt
= exynos_dp_get_lane_count();
642 debug("DP final BandWidth : %x\n", f_bw
);
643 debug("DP final Lane Count : %x\n", f_lane_cnt
);
645 edp_info
->lt_info
.lt_status
= DP_LT_FINISHED
;
647 exynos_dp_equalizer_err_link(edp_info
);
650 edp_info
->lt_info
.ep_loop
++;
652 if (edp_info
->lt_info
.ep_loop
> MAX_EQ_LOOP
) {
653 if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
654 ret
= exynos_dp_reduce_link_rate(
657 edp_info
->lt_info
.lt_status
=
659 exynos_dp_equalizer_err_link(edp_info
);
662 for (i
= 0; i
< edp_info
->lane_cnt
; i
++)
663 exynos_dp_set_lanex_pre_emphasis(
666 ret
= exynos_dp_write_bytes_to_dpcd(
667 DPCD_TRAINING_LANE0_SET
,
669 if (ret
!= EXYNOS_DP_SUCCESS
) {
670 printf("DP set lt pattern failed\n");
671 edp_info
->lt_info
.lt_status
=
673 exynos_dp_equalizer_err_link(edp_info
);
677 } else if (edp_info
->lane_bw
== DP_LANE_BW_2_70
) {
678 ret
= exynos_dp_reduce_link_rate(edp_info
);
680 edp_info
->lt_info
.lt_status
= DP_LT_FAIL
;
681 exynos_dp_equalizer_err_link(edp_info
);
687 static unsigned int exynos_dp_sw_link_training(struct edp_device_info
*edp_info
)
689 unsigned int ret
= 0;
690 int training_finished
;
692 /* Turn off unnecessary lane */
693 if (edp_info
->lane_cnt
== 1)
694 exynos_dp_set_analog_power_down(CH1_BLOCK
, 1);
696 training_finished
= 0;
698 edp_info
->lt_info
.lt_status
= DP_LT_START
;
701 while (!training_finished
) {
702 switch (edp_info
->lt_info
.lt_status
) {
704 ret
= exynos_dp_link_start(edp_info
);
705 if (ret
!= EXYNOS_DP_SUCCESS
) {
706 printf("DP LT:link start failed\n");
711 ret
= exynos_dp_process_clock_recovery(edp_info
);
712 if (ret
!= EXYNOS_DP_SUCCESS
) {
713 printf("DP LT:clock recovery failed\n");
718 ret
= exynos_dp_process_equalizer_training(edp_info
);
719 if (ret
!= EXYNOS_DP_SUCCESS
) {
720 printf("DP LT:equalizer training failed\n");
725 training_finished
= 1;
735 static unsigned int exynos_dp_set_link_train(struct edp_device_info
*edp_info
)
739 exynos_dp_init_training();
741 ret
= exynos_dp_sw_link_training(edp_info
);
742 if (ret
!= EXYNOS_DP_SUCCESS
)
743 printf("DP dp_sw_link_traning() failed\n");
748 static void exynos_dp_enable_scramble(unsigned int enable
)
753 exynos_dp_enable_scrambling(DP_ENABLE
);
755 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET
,
757 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
758 (u8
)(data
& ~DPCD_SCRAMBLING_DISABLED
));
760 exynos_dp_enable_scrambling(DP_DISABLE
);
761 exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET
,
763 exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET
,
764 (u8
)(data
| DPCD_SCRAMBLING_DISABLED
));
768 static unsigned int exynos_dp_config_video(struct edp_device_info
*edp_info
)
770 unsigned int ret
= 0;
771 unsigned int retry_cnt
;
775 if (edp_info
->video_info
.master_mode
) {
776 printf("DP does not support master mode\n");
780 exynos_dp_config_video_slave_mode(&edp_info
->video_info
);
783 exynos_dp_set_video_color_format(&edp_info
->video_info
);
785 if (edp_info
->video_info
.bist_mode
) {
786 if (exynos_dp_config_video_bist(edp_info
) != 0)
790 ret
= exynos_dp_get_pll_lock_status();
791 if (ret
!= PLL_LOCKED
) {
792 printf("DP PLL is not locked yet\n");
796 if (edp_info
->video_info
.master_mode
== 0) {
799 ret
= exynos_dp_is_slave_video_stream_clock_on();
800 if (ret
!= EXYNOS_DP_SUCCESS
) {
801 if (retry_cnt
== 0) {
802 printf("DP stream_clock_on failed\n");
812 /* Set to use the register calculated M/N video */
813 exynos_dp_set_video_cr_mn(CALCULATED_M
, 0, 0);
815 /* For video bist, Video timing must be generated by register */
816 exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE
);
818 /* Enable video bist */
819 if (edp_info
->video_info
.bist_pattern
!= COLOR_RAMP
&&
820 edp_info
->video_info
.bist_pattern
!= BALCK_WHITE_V_LINES
&&
821 edp_info
->video_info
.bist_pattern
!= COLOR_SQUARE
)
822 exynos_dp_enable_video_bist(edp_info
->video_info
.bist_mode
);
824 exynos_dp_enable_video_bist(DP_DISABLE
);
826 /* Disable video mute */
827 exynos_dp_enable_video_mute(DP_DISABLE
);
829 /* Configure video Master or Slave mode */
830 exynos_dp_enable_video_master(edp_info
->video_info
.master_mode
);
833 exynos_dp_start_video();
835 if (edp_info
->video_info
.master_mode
== 0) {
838 ret
= exynos_dp_is_video_stream_on();
839 if (ret
!= EXYNOS_DP_SUCCESS
) {
840 if (retry_cnt
== 0) {
841 printf("DP Timeout of video stream\n");
854 #ifdef CONFIG_OF_CONTROL
855 int exynos_dp_parse_dt(const void *blob
, struct edp_device_info
*edp_info
)
857 unsigned int node
= fdtdec_next_compatible(blob
, 0,
858 COMPAT_SAMSUNG_EXYNOS5_DP
);
860 debug("exynos_dp: Can't get device node for dp\n");
864 edp_info
->disp_info
.h_res
= fdtdec_get_int(blob
, node
,
866 edp_info
->disp_info
.h_sync_width
= fdtdec_get_int(blob
, node
,
867 "samsung,h-sync-width", 0);
868 edp_info
->disp_info
.h_back_porch
= fdtdec_get_int(blob
, node
,
869 "samsung,h-back-porch", 0);
870 edp_info
->disp_info
.h_front_porch
= fdtdec_get_int(blob
, node
,
871 "samsung,h-front-porch", 0);
872 edp_info
->disp_info
.v_res
= fdtdec_get_int(blob
, node
,
874 edp_info
->disp_info
.v_sync_width
= fdtdec_get_int(blob
, node
,
875 "samsung,v-sync-width", 0);
876 edp_info
->disp_info
.v_back_porch
= fdtdec_get_int(blob
, node
,
877 "samsung,v-back-porch", 0);
878 edp_info
->disp_info
.v_front_porch
= fdtdec_get_int(blob
, node
,
879 "samsung,v-front-porch", 0);
880 edp_info
->disp_info
.v_sync_rate
= fdtdec_get_int(blob
, node
,
881 "samsung,v-sync-rate", 0);
883 edp_info
->lt_info
.lt_status
= fdtdec_get_int(blob
, node
,
884 "samsung,lt-status", 0);
886 edp_info
->video_info
.master_mode
= fdtdec_get_int(blob
, node
,
887 "samsung,master-mode", 0);
888 edp_info
->video_info
.bist_mode
= fdtdec_get_int(blob
, node
,
889 "samsung,bist-mode", 0);
890 edp_info
->video_info
.bist_pattern
= fdtdec_get_int(blob
, node
,
891 "samsung,bist-pattern", 0);
892 edp_info
->video_info
.h_sync_polarity
= fdtdec_get_int(blob
, node
,
893 "samsung,h-sync-polarity", 0);
894 edp_info
->video_info
.v_sync_polarity
= fdtdec_get_int(blob
, node
,
895 "samsung,v-sync-polarity", 0);
896 edp_info
->video_info
.interlaced
= fdtdec_get_int(blob
, node
,
897 "samsung,interlaced", 0);
898 edp_info
->video_info
.color_space
= fdtdec_get_int(blob
, node
,
899 "samsung,color-space", 0);
900 edp_info
->video_info
.dynamic_range
= fdtdec_get_int(blob
, node
,
901 "samsung,dynamic-range", 0);
902 edp_info
->video_info
.ycbcr_coeff
= fdtdec_get_int(blob
, node
,
903 "samsung,ycbcr-coeff", 0);
904 edp_info
->video_info
.color_depth
= fdtdec_get_int(blob
, node
,
905 "samsung,color-depth", 0);
910 unsigned int exynos_init_dp(void)
913 struct edp_device_info
*edp_info
;
915 edp_info
= kzalloc(sizeof(struct edp_device_info
), GFP_KERNEL
);
917 debug("failed to allocate edp device object.\n");
921 #ifdef CONFIG_OF_CONTROL
922 if (exynos_dp_parse_dt(gd
->fdt_blob
, edp_info
))
923 debug("unable to parse DP DT node\n");
925 edp_info
= dp_pd
->edp_dev_info
;
926 if (edp_info
== NULL
) {
927 debug("failed to get edp_info data.\n");
932 exynos_dp_set_base_addr();
934 exynos_dp_disp_info(&edp_info
->disp_info
);
936 exynos_set_dp_phy(1);
938 ret
= exynos_dp_init_dp();
939 if (ret
!= EXYNOS_DP_SUCCESS
) {
940 printf("DP exynos_dp_init_dp() failed\n");
944 ret
= exynos_dp_handle_edid(edp_info
);
945 if (ret
!= EXYNOS_DP_SUCCESS
) {
946 printf("EDP handle_edid fail\n");
950 ret
= exynos_dp_set_link_train(edp_info
);
951 if (ret
!= EXYNOS_DP_SUCCESS
) {
952 printf("DP link training fail\n");
956 exynos_dp_enable_scramble(DP_ENABLE
);
957 exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE
);
958 exynos_dp_enable_enhanced_mode(DP_ENABLE
);
960 exynos_dp_set_link_bandwidth(edp_info
->lane_bw
);
961 exynos_dp_set_lane_count(edp_info
->lane_cnt
);
963 exynos_dp_init_video();
964 ret
= exynos_dp_config_video(edp_info
);
965 if (ret
!= EXYNOS_DP_SUCCESS
) {
966 printf("Exynos DP init failed\n");
970 printf("Exynos DP init done\n");
975 void exynos_set_dp_platform_data(struct exynos_dp_platform_data
*pd
)
978 debug("pd is NULL\n");